1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
1
Pin Assignment
Pin# Pin# Pin# Pin#
1Vss 37 DQ8 73 OE* 109 A9
2Vss 38 DQ40 74 RFU 110 A12
3DQ0 39 DQ9 75 Vss 111 A10/AP
4DQ32 40 DQ41 76 Vss 112 A13
5DQ1 41 DQ10 77 RSVD 113 Vcc
6DQ33 42 DQ42 78 RSVD 114 Vcc
7DQ2 43 DQ11 79 RSVD 115 CAS2*
8DQ34 44 DQ43 80 RSVD 116 CAS6*
9DQ3 45 Vcc 81 Vcc 117 CAS3*
10 DQ35 46 Vcc 82 Vcc 118 CAS7*
11 Vcc 47 DQ12 83 DQ16 119 Vss
12 Vcc 48 DQ44 84 DQ48 120 Vss
13 DQ4 49 DQ13 85 DQ17 121 DQ24
14 DQ36 50 DQ45 86 DQ49 122 DQ56
15 DQ5 51 DQ14 87 DQ18 123 DQ25
16 DQ37 52 DQ46 88 DQ50 124 DQ57
17 DQ6 53 DQ15 89 DQ19 125 DQ26
18 DQ38 54 DQ47 90 DQ51 126 DQ58
19 DQ7 55 Vss 91 Vss 127 DQ27
20 DQ39 56 Vss 92 Vss 128 DQ59
21 Vss 57 RSVD 93 DQ20 129 Vcc
22 Vss 58 RSVD 94 DQ52 130 Vcc
23 CAS0* 59 RSVD 95 DQ21 131 DQ28
24 CAS4* 60 RSVD 96 DQ53 132 DQ60
25 CAS1* 61 RFU 97 DQ22 133 DQ29
26 CAS5* 62 RFU 98 DQ54 134 DQ61
27 Vcc 63 Vcc 99 DQ23 135 DQ30
28 Vcc 64 Vcc 100 DQ55 136 DQ62
29 A0 65 RFU 101 Vcc 137 DQ31
30 A3 66 RFU 102 Vcc 138 DQ63
31 A1 67 WE* 103 A6 139 Vss
32 A4 68 RFU 104 A7 140 Vss
33 A2 69 RAS0* 105 A8 141 SDA
34 A5 70 RFU 106 BA0 142 SCL
35 Vss 71 NC 107 Vss 143 Vcc
36 Vss 72 RFU 108 Vss 144 Vcc
* Active Low
Extended Data Out (EDO) DRAM SMALL OUTLINE DIMM
641006EWS1G05TC 144 Pin 1Mx64 EDO SODIMM
Unbuffered, 1k Self Refresh, 3.3V with SPD
Features
• JEDEC-Standard 144-pin Small Outline Dual Inline
Memory Module (SODIMM)
• Unbuffered
• Supports Extended Data-out (EDO) access cycles
• Based on 1Mx16 DRAM
• Power Supply: 3.3V ± 0.3V
• 64ms, 1024-cycle refresh
• Supports Self Refresh, RAS-Only-Refresh (ROR),
CAS-before-RAS (CBR) refresh and Hidden refresh
cycles
• Serial Presence Detect (SPD)
• LVTTL Compatible Inputs and Outputs
• One External Bank
• Gold PCB connector
General Description
The 641006EWS1G05TC is a 1Mx64 bit, 5 chip,
3.3V, 144 Pin DIMM module consisting of (4) 1Mx16
(TSOP) DRAM and (1) 256x8 EEPROM for serial
presence detect. The module is unbuffered and supports
Extended Data Out (EDO) page mode access.
Valid Part Numbers
Part Number Access
Time Supply
Voltage
641006EWS1G05TC 60ns 3.3V
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
2
Block Diagram
A0 A2A1
SERIAL PD
SA0 SA2
SA1
SDA
SCL
VCC
VSS
U1 - U4
U1 - U4
Bypass:
One 0.22uF capacitor per DRAM device.
U1 U3
U2 U4
DQ(0:7)
DQ(8:15)
DQ(32:39)
DQ(40:16)
DQ(16:23)
DQ(24:31)
DQ(48:55)
DQ(56:63)
CAS0
CAS1
CAS2
CAS3
CAS4
CAS5
CAS7
CAS6
RAS0
A0 - AN A0 - AN : DRAMs U1 - U4
WE WE : DRAMs U1 - U4
CE CE : DRAMs U1 - U4
X64 DRAM SODIMM, 1BANK with X16 DRAMs
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
3
Pin Descriptions
Pin Name Function
RAS# Row Address Strobe RAS# is used to strobe the row address.
CAS# Column Address Strobe CAS# is used to strobe the column address.
WE# Write Enable WE# is used to control read/write cycles.
OE# Output Enable OE# is the input/output control for the DQ lines.
A# Address Lines Address lines are multiplexed to specify the row and column address.
DQ0-DQ63 Data Lines Data input/output lines.
Vdd Power Supply Power Supply 3.3V±0.3V
Vss Ground Ground
SDA, SCL SPD Data/Clock Lines Serial Presence Detect (SPD) EEPROM bus lines. These line provides
bi-directional data transfer over an I2C bus.
RFU Reserved for Future
Use Line is not connected in DIMM.
RSVD Reserved Line is not connected in DIMM.
NC No Connection Line is not connected in DIMM.
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
4
Serial Presence Detect Matrix Binary HexByte # Function
76543210 MS-LS
Description
0Define # of bytes written into EEPROM 10000000 80 128
1Total # of bytes of SPD memory device 00001000 08 256
2Fundamental memory type (EDO,SDRAM...) 00000010 02 EDO
3# of row addresses 00001010 0A 10
4# of column addresses 00001010 0A 10
5# of module rows 00000001 01 1
6Data width... 01000000 40 64
7...Data width continued 00000000 00 00
8Voltage interface 00000011 03 3.3V
9tRAC (-60) 00111100 3C 60ns
9tRAC (-50) 00110010 32 50ns
10 tCAC (-60) 00001111 0F 15ns
10 tCAC (-50) 00001101 0D 13ns
11 DIMM configuration type (non-parity,ECC…) 00000000 00 non-parity
12 Refresh rate/type 10000000 80 Self Refresh (15.6µs)
13 Primary DRAM width 00010000 10 16
14 Error checking DRAM width 00000000 00 0
15-127 Reserved 00000000 00 0
128-255 Not Used 00000000 00 0
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
5
Absolute Maximum Ratings
Parameter Symbol Value Units
Voltage on any pin relative to Vss Vin -0.5 to 4.6 V
Short circuit output current Iout 50 mA
Power dissipation Pt 5W
Operating temperature Topr 0 to +70 °C
Storage temperature Tst -55 to +125 °C
NOTE: Permanent damage may occur if absolute maximum ratings are exceeded.
Device should be operated within recommended operating conditions only.
DC Characteristics (TA = 0 to 70C, Vcc = 3.3V ±± 0.3V)
Parameter Symbol Min Typ Max Units Note
Supply voltage Vss 0 0 0 V
Supply voltage Vcc 3.0 3.3 3.6 V16
Input high voltage Vih 2.0 -Vcc+0.3 V16
Input low voltage Vil -0.5 -0.8 V16
Output high voltage Voh 2.4 - - V
Output low voltage Vol - - 0.8 V
DC Current Consumption (TA = 0 to 70C, Vcc = 3.3V ±± 0.3V)
Parameter Symbol Test Condition -50 -60 Unit Note
Standby Current (TTL) ICC1 (RAS# = CAS# = VIH)8 8 mA 17
Standby Current (CMOS) ICC2 All inputs = Vcc - 0.2V 4 4 mA 17
Operating Current Random Read/Write ICC3 RAS#, CAS#, address cycling. tRC = tRC[MIN] 770 720 mA 17, 18
Operating Current Fast Page Mode ICC4 RAS# = VIL, CAS#, Address cycling. tPC = tPC[MIN] N/A N/A mA 17, 18
Operating Current EDO Page Mode ICC5 RAS# = VIL, CAS#, Address cycling. tPC = tPC[MIN] 580 530 mA 17, 18
Refresh Current: RAS#-Only ICC6 RAS# cycling, CAS#=VIH; tRC = tRC[MIN] 770 720 mA 17
Refresh Current: CAS# before RAS# ICC7 RAS#, CAS#, address cycling tRC = tRC[MIN]960 960 mA 17
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
6
Capacitance (TA = 0 to 70C, Vcc = 3.3V ±± 0.3V, Vss = 0V)
Parameter Symbol Typ Max Units Note
Input capacitance (Address) CI1 -20 pF
Input capacitance (WE#, OE#) CI2 -28 pF
Input/Output capacitance (Data) CI/O -7pF
Input capacitance (CAS#) CI3 -7pF
Input/Output capacitance (SDA,SCL,SAm) -10 pF
Input capacitance (RAS#) C14 -28 pF
AC Characteristics (TA = 0 to 70C, Vcc = 3.3V ±± 0.3V, Vss = 0V)
-50 -60Parameter Symbol Min Max Min Max Units Note
Access time from column address tAA 25 30 ns 3, 5, 14
Column address setup to CAS# precharge tACH 12 15 ns
Column address hold time (from RAS#) tAR 40 50 ns
Column address setup time tASC 0 0 ns
Row address setup time tASR 0 0 ns
Access time from CAS# tCAC 15 17 ns 3, 4, 14
Column address hold time tCAH 8 10 ns
CAS# pulse width tCAS 810 000 10 10 000 ns
CAS# to output in Low-Z tCLZ 3 3 ns
Data output hold after CAS# LOW tCOH 3 3 ns
CAS# precharge time tCP 8 10 ns
Access time from CAS# precharge tCPA 28 35 ns
CAS# to RAS# precharge time tCRP 5 5 ns
CAS# hold time tCSH 40 50 ns
WRITE command to CAS# lead time tCWL 8 10 ns
Data-in hold time tDH 8 10 ns 11
Data-in setup time tDS 0 0 ns 11
Output buffer turn-off delay tOFF 0 12 0 15 ns
EDO Page-mode read or write cycle time tPC 20 25 ns
Access time from RAS# tRAC 50 60 ns 2, 3
RAS# to column address delay time tRAD 15 25 15 30 ns 9
Row-address hold time tRAH 10 10 ns
RAS# pulse width tRAS, tRASP 50 10 000 60 10 000 ns
Random read/write cycle time tRC 84 104 ns
RAS# to CAS# delay time tRCD 20 35 20 43 ns 8
Read command hold time tRCH 0 0 ns
Read command setup time tRCS 0 0 ns
Refresh Period (1024 cycles) tREF 64 64 ms 15
RAS# precharge time tRP 30 40 ns
RAS# to CAS# precharge time tRPC 5 5 ns
READ command hold time tRRH 0 0 ns
RAS# hold time tRSH 13 17 ns
WRITE command to RAS# lead time tRWL 13 15 ns
Transition Time tτ2 50 2 50 ns 7
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
7
AC Characteristics (TA = 0 to 70C, Vcc = 3.3V ±± 0.3V, Vss = 0V)
-50 -60Parameter Symbol Min Max Min Max Units Note
WRITE command hold time tWCH 8 10 ns
WRITE command hold time (RAS# referenced) tWCR 38 45 ns
WE# command setup time tWCS 0 0 ns 10
Output disable delay from WE# tWHZ 0 12 0 15 ns
Write command pulse width tWP 5 5 ns
Notes
1. AC measurements assume tT = 5ns
2. Assumes that tRCD ≤ tRCD (max.) and tRAD ≥ tRAD (max.). If tRCD or tRAD is greater that the maximum recommended value shown in this table, tRAC
exceeds the value shown.
3. Measured with a load circuit equivilaent to 1 TTL load and 100pF.
4. Assumes that tRCD ≥ tRCD (max.), tRAD ≤ tRAD (max.).
5. Assumes that tRCD ≤ tRCD (max.), tRAD ≥ tRAD (max.).
6. tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
7. Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vih and Vil.
8. Operation with the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference point only, if tRCD is greater that the
specified tRCD (max.) limit, then the access time is controlled exclusively by tCAC.
9. Operation with the tRAD (max.) limit insures that tRAC (max.) can be met, tRAD (max.) is specified as a reference point only, if tRAD is greater that the
specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
10. Early write cycle only (tWCS ≥ tWCS (min.))
11. These parameters are referenced to CAS* leading edge in an early write cycle.
12. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS*
clock such as RAS* only refresh)
13. tRASC defines RAS* pulse width in fast page mode cycles.
14. Access time is determined by the longer of tAA or tCAC or tACP
15. tREF defined is 1,024 refresh cycle.
16. All voltages referenced to Vss
17. Typical maximum current consumption levels
18. Column address changed once per cycle
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
8
t
RP
t
RAS
t
RC
t
CRP
t
RCD
t
CAS
t
RSH
t
CSH
t
RRH
t
ASR
t
RAH
t
RAD
t
ACH
t
CAH
t
ASC
t
AR
t
RCS
t
RCH
t
CLZ
t
CAC
t
RAC
t
AA
t
OFF
ADDR
WE
DQ
CAS
RAS
ROW COLUMN ROW
VALID DATA
OPEN OPEN
READ CYCLE
DON'T CARE
UNDEFINED
tRP
tRAS
tRC
tCRP tRCD tCAS
tRSH
tCSH
tASR tRAH
tRAD tACH
tCAH
tASC
tAR
tWP
tWCH
tWCR
tRWL
ADDR
WE
DQ
CAS
RAS
ROW COLUMN ROW
VALID DATA
DON'T CARE
UNDEFINED
tWCS
tCWL
tDH
tDS
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
9
t
RP
t
RASP
t
CRP
t
RCD
t
CSH
t
CAS
t
CP
t
CAS
t
PC
t
CP
t
CAS
t
RSH
t
CP
t
ASR
t
RAH
t
RAD
t
AR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RCS
t
RCH
t
OFF
t
CLZ
t
CAC
t
CPA
t
AA
t
COH
t
CAC
t
CPA
t
AA
t
CLZ
t
CAC
t
RAC
t
AA
ADDR
WE
DQ
CAS
RAS
DON'T CARE
UNDEFINED
ROW ROWCOLUMNCOLUMN COLUMN
VALID
DATA VALID
DATA VALID
DATA
EDO-PAGE-MODE READ CYCLE
t
ACH
t
CAH
t
CAH
t
RRH
OPEN OPEN
tRP
tRASP
tCRP tRCD
tCSH
tCAS tCP tCAS
tPC tCP tCAS
tRSH tCP
tASR tRAH
tRAD
tAR
tASC tCAH tASC tCAH tASC tCAH
tDH
tDS
tCOH
tCAC
tCAC
tRAC
ADDR
WE
DQ
CAS
RAS
DON'T CARE
UNDEFINED
ROW ROW
COLUMN (B)COLUMN (A) COLUMN (N)
VALID Dout VALID Dout VALID Din
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
tACH
tRCH
tAA
tPC
tWCS tWCH
tRCS
tWHZ
tCPA
tAA
OPEN
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
10
tRP
tRASP
tCRP tRCD
tCSH tCAS tCP tCAS
tPC tCP tCAS
tRSH tCP
tASR tRAH
tRAD
tAR
tASC tCAH tASC tCAH tASC tCAH
tWP tWP tWP
tDH
tDS
tDH
tDS
tCAC
tWCR
ADDR
WE
DQ
CAS
RAS
DON'T CARE
UNDEFINED
ROW ROW
COLUMNCOLUMN COLUMN
VALID DATA VALID DATA VALID DATA
FAST/EDO-PAGE-MODE EARLY-WRITE CYCLE
tACH
tACH
tACH
tWCH
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tCWL
tWCS
tDS
tRWL
t
CRP
t
RCD
t
CSH
t
CAS
t
CP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
AR
t
ASC
ROW COLUMN COLUMN
t
RCS
t
RCH
t
WPZ
t
RCS
OPEN
t
CLZ
t
CAC
t
RAC
t
AA
t
WHZ
OPEN
t
CLZ
DON'T CARE
UNDEFINED
VALID DATA
EDO READ CYCLE
( with /WE-controlled disable )
ADDR
WE
DQ
CAS
RAS
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
11
tRP
tRAS
tRC
tCRP tRPC
tASR tRAH
ROW ROW
OPEN
/RAS-ONLY REFRESH CYCLE
DON'T CARE
UNDEFINED
ADDR
Q
RAS
WE
CASL / CASH
tRP
tRAS
tCP tCHR
OPEN
DON'T CARE
UNDEFINED
tRP tRAS
tRPC tCSR tRPC tCSR tCHR
tWRP tWRH tWRP tWRH
WE
DQ
CAS
RAS
CBR REFRESH CYCLE
( Addresses = DON'T CARE )
1M x 64 Bit 3.3V
UNBUFFERED EDO SODIMM
1Mx64 UNBUFFERED 3.3V EDO SODIMM
DS456-1 – 4/7/00
PNY Technologies Reserves the right to change product or specifications without notice
2000 PNY Technologies, Inc.
12
Note: Drawing is for component location only, assembly may not have all components installed.
OUTLINE DRAWING
FRONT SIDE
BACK SIDE
SIDE VIEW
.055”
.055”
.150”