2N7640-GA
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Normally OFF Silicon Carbide
Junction Transistor
Features
Package
210°C maximum operating temperature
Gate Oxide Free SiC Switch
Exceptional Safe Operating Area
Excellent Gain Linearity
Compatible with 5 V TTL Gate Drive
Temperature Independent Switching Performance
Low Output Capacitance
Positive Temperature Coefficient of RDS,ON
Suitable for Connecting an Anti-parallel Diode
RoHS Compliant
SMD0.5 / TO – 276 (Hermetic Package)
Advantages
Applications
Compatible with Si MOSFET/IGBT Gate Drive ICs
> 20 µs Short-Circuit Withstand Capability
Lowest-in-class Conduction Losses
High Circuit Efficiency
Minimal Input Signal Distortion
High Amplifier Bandwidth
Down Hole Oil Drilling
Geothermal Instrumentation
Solenoid Actuators
General Purpose High-Temperature Switching
Amplifiers
Solar Inverters
Switched-Mode Power Supply (SMPS)
Power Factor Correction (PFC)
Table of Contents
Section I: Absolute Maximum Ratings .......................................................................................................... 1
Section II: Static Electrical Characteristics ................................................................................................... 2
Section III: D ynamic Electrical Characteristics ............................................................................................ 2
Section IV: Figures .......................................................................................................................................... 3
Section V: Driving the 2N7640-GA ................................................................................................................. 6
Section VI: Packag e Di mensions: .................................................................................................................. 9
Section VII: SPICE Model Parameters ......................................................................................................... 10
Section I: Absolute Maximum Ratings
Parameter Symbol Conditions Values Unit
Drain – Source Voltage V
DS
VGS = 0 V 600 V
Continuous Drain Current
I
D
TJ = 210°C, TC = 25°C
A
Continuous Gate Current
IGM
A
Turn-Off Safe Operating Area RBSOA TVJ = 210°C, I G = 1.5 A,
Clamped Inductive Load
D,max
A
Short Circuit Safe Operating Area SCSOA
T
VJ
= 210°C, I
G
= 1.5 A, V
DS
= 400 V,
Non Repetitive
>20 µs
Reverse Gate – Source Voltage
VGS
V
Reverse Drain – Source Voltage
V
DS
V
Power Dissipation Ptot TJ = 210°C, TC = 25°C 330 W
Operating and Storage Temperature
T
j
, T
stg
°C
S
G
D
D
S
G
VDS = 600 V
RDS(ON) = 60 m
ID (Tc = 25°C) = 32 A
hFE (Tc = 25°C) = 80
2N7640-GA
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Section II: Static Electrical Characteristics
Parameter Symbol Conditions Values Unit
min. typ. max.
A: On State
Drain – Source On Resistance RDS(ON) ID = 20 A, Tj = 2 5 ° C
ID = 20 A, Tj = 125 °C
ID = 20 A, Tj = 175 °C
ID = 20 A, Tj = 210 °C
60
96
128
155
Gate – Source Saturation Voltage VGS,SAT ID = 20 A, ID/IG = 40, Tj = 25 °C
ID = 20 A, ID/IG = 30, Tj = 175 °C
3.44
3.24 V
DC Current Gain hFE VDS = 5 V, ID = 20 A, Tj = 25 °C
VDS = 5 V, ID = 20 A, Tj = 125 °C
VDS = 5 V, ID = 20 A, Tj = 175 °C
VDS = 5 V, ID = 20 A, Tj = 210 °C
80
50
43
35
B: Off State
Drain Leakage Current IDSS VR = 600 V, VGS = 0 V , Tj = 25 °C
3
100
µA
VR = 600 V, VGS = 0 V, Tj = 175 °C
10
400
V
R
= 600 V, V
GS
= 0 V, T
j
= 210 °C
50
600
C: Thermal
Thermal resistance, junction - case
RthJC
0.6
°C/W
Section III: Dynamic Electrical Characteristics
A: Capacitance and Gate Charge
Input Capacitance
Ciss
VGS = 0 V, VD = 100 V, f = 1 MHz
2500
pF
Reverse Transfer/Output Capacitance
Crss/Coss
VD = 100 V, f = 1 MHz
158
pF
Output Capacitance Stored Energy
EOSS
V
GS
= 0 V, V
D
= 100 V,
f
= 1 MHz
0.8
µJ
Effective Output Capacitance,
time related
Coss,tr ID = constant, VGS = 0 V, VDS =
0…100 V 260 pF
Effective Output Capacitance,
energy related Coss,er VGS = 0 V, VDS = 0…100 V 202 pF
Gate-Source Charge
Q
GS
VGS = -5…3 V
27
nC
Gate-Drain Charge
QGD
VGS = 0 V, VDS = 0…100 V
26
nC
Gate Charge - Total
QG
53
nC
B: Switching1
1 – All times are relative to the Drain-Source Voltage VDS
Parameter Symbol Conditions
Values
Unit
min. typ. max.
Internal Gate Resistance – zero bias RG(INT-ZERO)
f = 1 MHz, V
AC
= 50 mV, V
DS
= V
GS
= 0 V ,
T
j
= 210 ºC 2.6 Ω
Internal Gate Resistance ON
R
G(INT-ON)
VGS > 2.5 V, VDS = 0 V, Tj = 225 ºC
0.16
Ω
Turn On Delay Time
td(on)
Tj = 25 ºC, VDS = 400 V,
ID = 20 A, Inductive Load
Refer to Section V: for additional
driving information
90
ns
Fall Time, VDS
tf
80
ns
Fig. 11, 13
Turn Off Delay Time
td(off)
50
ns
Rise Time, VDS
tr
55
ns
Fig. 12, 14
Turn On Delay Time
td(on)
Tj = 210 ºC, VDS = 400 V,
ID = 20 A, Inductive Load
Refer to Section V: for additional
driving information
90
ns
Fall Time, VDS tf
85
ns Fig. 11
Turn Off Delay Time
t
d(off)
50
ns
Rise Time, VDS
tr
50
ns
Fig. 12
Turn-On Energy Per Pulse
Eon
Tj = 25 ºC, VDS = 400 V,
ID = 20 A, Inductive Load
810
µJ
Fig. 11, 13
Turn-Off Energy Per Pulse
Eoff
95
µJ
Fig. 12, 14
Total Switching Energy
Etot
905
µJ
Turn-On Energy Per Pulse
Eon
Tj = 210 ºC, VDS = 400 V,
ID = 20 A, Inductive Load
140
µJ
Fig. 11
Turn-Off Energy Per Pulse
E
off
45
µJ
Fig. 12
Total Switching Energy
E
tot
185
µJ
2N7640-GA
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Section IV: Figures
A: Static Characteristics
Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C
Figure 3: Typical Output Characteristics at 210 °C Figure 4: Drain-Source Voltage vs. Gate Current
Figure 5: DC Current Gain and Normalized On-Resistance
vs. Tempera tur e
Figure 6: Typical Gate Source Saturation Voltage
2N7640-GA
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Figure 7: Typical Blocking Characteristics
Figure 8: Forward Bias Safe Operating Area at Tc=120
o
C
B: Dynamic Characteristics
Figure 9: Capacitance Characteristics
Figure 10: Output Capacitance Stored Energy
Figure 11: Typical Turn On Energy Losses and Switching
Times vs. Temperature
Figure 12: Typical Turn Off Energy Losses and Switching
Times vs. Temperature
2N7640-GA
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Figure 13: Typical Turn On Energy Losses and Switching
Times vs. Drain Current
Figure 14: Typical Turn Off Energy Losses and Switching
Times vs. Drain Current
Figure 15: Power Derating Curve
Figure 16: Typical Hard Switched Device Power Loss vs.
Switching Fr eq uen cy
2
Figure 17: Turn-Off Safe Operating Area
2Representative values based on device switching energy loss. Actual losses will depend on gate drive conditions, device load, and circuit topology
2N7640-GA
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Section V: Driving the 2N7640-GA
The 2N7640-GA is a current controlled SiC transistor which requires a positive gate current for turn-on and to remain in on-state. It may be
driven by different drive topologies depending on the intended application.
Table 1: Estimated Power Consumption and switching frequencies for various Gate Drive topologies.
Drive Topology Gate Drive Power
Consumption Switching
Frequency
Simple TTL
High
Low
Constant Current
Medium
Medium
High Speed – Boost Capacitor
Medium
High
High Speed – Boost Inductor Low High
Proportional
Lowest
Medium
Pulsed Power
Medium
N/A
A: Simple TTL Drive
The 2N7640-GA may be driv en by 5 V TTL l ogic by using a simple current amplific ation stage. The c urrent amplifier o utput current mu st meet
or exceed the steady state gate current, IG,steady, required to operate the 2N7640-GA. An external gate resistor RG, shown in the
Figure 18 topology, sets IG,steady to the required level which is dependent on the SJT drain current ID and DC current gain hFE, RG may be
calculated from the equation below. The v alue of VEC,sat c an be taken from the PNP datasheet, a partial list of high-temperatu re PNP and NPN
transistors options is given below. High-temperature MOSFETs may also be used in the topology.
, =5.0 , () , () (,)
1.5
Figure 18: Simple TTL Gate Drive Topology
Table 2: Partial List of High-Temperature BJTs for TTL Gate Driving
BJT Part Number Type Tj,max (°C)
PHPT60603PY
PNP
175
PHPT60603NY NPN 175
2N2222
NPN
200
2N6730
PNP
200
2N2905
PNP
200
2N5883
PNP
200
2N5885
NPN
200
SiC SJT
D
S
G
TTL
Gate Signal
0 / 5 V
TTL i/p
inverted
I
G,steady
5 V
PNP
NPN
Inverting
Current
Boost
Stage
0 / 5 V
TTL o/p R
G
2N7640-GA
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B: High Speed Driving
For ultra high speed 2N7640-GA switching (tr, tf < 20 ns) while maintaining low gate drive losses the supplied gate current should include a
positive current peak during turn-on, a negative voltage peak during turn-off, and continuous gate current IG to remain on.
An SJT is rapidly switched from its bloc king state to on-state, when the necessary gate charge for turn-on, QG, is supplied by a burst of high
gate current until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. Ideally, the burst should terminate
when the drain voltage has fallen to its on-s tate value in order to av oid unnec ess ary drive los ses . A negative voltage peak is recommended for
the turn-off transition i n order to ensure that the gate current is not being s upplied under high dV/dt due to t he Miller effect. Whil e satisfactory
turn off can be achieved with VGS = 0 V, a negative VGS value may be used in order to speed up the turn-off transition.
B:1: High Speed, Low Loss Drive with Boost Capacitor
The 2N7640-GA may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate
resistor, and a gate capacitor are used to provi de current peaks at turn-on and turn -off for fas t switchi ng and a continuous gate current while in
on-state. As shown in Figure 19, in this topology two gate driver ICs are utilized. An external gate resis tor RG is driven by a low voltage driver
to supply the continuous gate current throughout on-state.and a gate capaci tor CG is driven at a higher voltage level to supply a high current
peak at turn-on and turn-off. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) from GeneSiC Semiconductor utilizing this
topology is commercially available for high and low-side driving, its datasheet provides additional details about this drive topology.
Figure 19: High Speed, Low Loss Drive with Boost Capacitor Topology
B:2: High Speed, Low Loss Drive with Boost Inductor
A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the 2N7640-GA at high-speed. It utilizes a gate drive inductor
instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a speci fied IG,on
current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 20. After turn on,
while the device remains on the neces sary steady s tate gate current IG,steady is supplied from s ource VCC through RG. Please refer to t he article
“A current-sourc e concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this
driving topology.3
Figure 20: High Speed, Low-Loss Driver with Boost Inductor Topology
3Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013
Gate
RG
CGIG
SiC SJT
D
S
G
VGH
VGL
Gate Signal
SiC SJT D
S
G
L
R
G
V
EE
V
CC
V
CC
V
EE
S
1
S
2
S
3
S
4
2N7640-GA
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C: Proportional Gate Current Driving
A proportional gate drive topology may be benefi cial for applications in which the 2N7640-GA will operate over a wide range of drain current
conditions to lower the gate drive power consumption. A proportion al gate driver relies on instantaneous drain current I D feedback to vary the
steady state gate current IG,steady supplied to the 2N7640-GA.
C:1: Voltage Controlled Proportional Driver
A voltage controlled proportional driver relies on a gate drive integrated circuit to detect the 2N7640-GA drain-source voltage VDS during on-
state to sense ID. The integrated circuit will then increase or decrease IG in respons e to ID. This allows IG and gate drive power consumption to
reduce while ID is low or for IG to increase when ID increases. A high voltage diode connected between the drain and sense protects the
integrated circuit from high-voltage when blocking. A simplified version of this topology is shown in Figure 21. Additional information will be
available in the future at http://www.genesicsemi.com/references/product-notes/.
Figure 21: Simplified Voltage Controlled Proportional Driver
C:2: Current Controlled Proportional Driver
The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback of the
2N7640-GA drain current during on-state to supply IG,steady into the gate. IG,steady will increase or decrease in response to ID at a fixed forced
current gain which is set be the turns rati o of the t ransformer, hforce = ID / IG = N2 / N1. 2N7640-GA is initi ally tuned-on us ing a gate current pul se
supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady and the gate drive power consumption to
reduce while ID is relatively low or for IG,steady to increase when ID increases. A simplified version of this topology is shown in Figure 22.
Additional information will be available in the future at http://www.genesicsemi.com/references/product-notes/.
Figure 22: Simplified Current Controlled Proportional Driver
SiC SJT
Proportional
Gate Current
Driver D
S
G
Gate Signal
I
G,steady
HV Diode
Sense
Signal Output
SiC SJT D
S
G
N
2
N
2
N
1
N
3
Gate Signal
2N7640-GA
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Section VI: Package Dimensions:
SMD-0.5/TO-276 PACKAGE OUTLINE
NOTE
1. CONTROLLED DIMENSI O N IS MILLIMETER. DIMENSION IN BRACKET I S INCH.
2. DIMENSIONS DO NOT INCLUDE END FLAS H, MOLD FLASH, MATERIAL PROTRUSIO NS
Revision History
Date Revision Comments Supersedes
2014/12/12 6 Updated Electrical Characteristics
2014/08/25 5 Updated Electrical Characteristics
2014/03/19 4 Updated Gate Drive Section
2014/02/14 3 Updated Electrical Characteristics
2013/12/19 2 Updated Gate Drive Section
2013/11/18 1 Updated Electrical Characteristics
2012/08/24 0 Initial release
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
2N7640-GA
Dec 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg1 of 1
Section VII: SPICE Model Parameters
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/hit_sic/sjt/2N7640-GA_SPICE.pdf) into LTSPICE (version 4)
software for simulation of the 2N7640-GA.
* MODEL OF GeneSiC Semiconductor Inc.
*
* $Revision: 1.3 $
* $Date: 12-DEC-2014 $
*
* GeneSiC Semiconductor Inc.
* 43670 Trade Center Place Ste. 155
* Dulles, VA 20166
*
* COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc.
* ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model 2N7640 NPN
+ IS 9.8338E-48
+ ISE 1.0733E-26
+ EG 3.23
+ BF 110
+ BR 0.55
+ IKF 200
+ NF 1.02
+ NE 2.0
+ RB 2.6
+ IRB 0.002
+ RBM 0.16
+ RE 0.01
+ RC 0.045
+ CJC 8.2281E-10
+ VJC 3.31126
+ MJC 0.48117
+ CJE 2.33957E-9
+ VJE 2.91486
+ MJE 0.48211
+ XTI 3
+ XTB -1.2
+ TRC1 6.20E-03
+ VCEO 600
+ ICRATING 32
+ MFG GeneSiC_Semiconductor
*
* End of 2N7640-GA SPICE Model
Mouser Electronics
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