MAX1286ETA+ - Hytronics - Datasheet.Live

General Description

The MAX1286–MAX1289 are low-cost, micropower, seri-

al output 12-bit analog-to-digital converters (ADCs)

available in a tiny 8-pin SOT23 and an 8-pin TDFN. The

MAX1286/MAX1288 operate with a single +5V supply.

The MAX1287/MAX1289 operate with a single +3V sup-

ply. The devices feature a successive-approximation

ADC, automatic shutdown, fast wakeup (1.4µs), and a

high-speed 3-wire interface. Power consumption is only

0.5mW (VDD = +2.7V) at the maximum sampling rate of

150ksps. AutoShutdown™ (0.2µA) between conversions

results in reduced power consumption at slower

throughput rates. The MAX1286/MAX1287 provide

2-channel, single-ended operations and accept input

signals from 0 to VREF. The MAX1288/MAX1289 accept

true-differential inputs ranging from 0 to VREF. Data is

accessed using an external clock through the 3-wire

SPI™-/QSPI™-/MICROWIRE™-compatible serial inter-

face. Excellent dynamic performance, low power, ease

of use, and small package size make these converters

ideal for portable battery-powered data-acquisition

applications, and for other applications that demand low

power consumption and minimal space.

Applications

Low-Power Data Acquisition

Portable Temperature Monitors

Flowmeters

Touch Screens

Features

♦Single-Supply Operation

+3V (MAX1287/MAX1289)

+5V (MAX1286/MAX1288)

♦Autoshutdown Between Conversions

♦Low Power

245µA at 150ksps

150µA at 100ksps

15µA at 10ksps

2µA at 1ksps

0.2µA in Shutdown

♦True-Differential Track/Hold, 150kHz Sampling Rate

♦Software-Configurable Unipolar/Bipolar

Conversion (MAX1288/MAX1289 Only)

♦SPI-/QSPI-/MICROWIRE-Compatible Interface for

DSPs and Processors

♦Internal Conversion Clock

♦8-Pin SOT23 and 8-Pin TDFN Packages

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

________________________________________________________________ Maxim Integrated Products 1

CNVST

REFGND

SCLK

DOUTAIN1 (AIN+)

AIN2 (AIN-)

VDD

SOT23

TOP VIEW

( ) ARE FOR THE MAX1288/MAX1289

MAX1286–

MAX1289

CNVST

GND

678

DOUT

SCLK

REF

421

AIN1 (AIN+)

VDD

TDFN

MAX1286–

MAX1289

AIN2 (AIN-)

Pin Configurations

19-2231; Rev 2; 12/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

PART PIN-PACKAGE TOP MARK PKG

CODE

MAX1286EKA-T 8 SOT23-8 AAFA K8F-4

MAX1286ETA+T 8 TDFN-8 +AFR T833-1

MAX1287EKA-T 8 SOT23-8 AAEW K8F-4

MAX1287ETA+T 8 TDFN-8 +AFN T833-1

MAX1288EKA-T 8 SOT23-8 AAFC K8F-4

MAX1288ETA+T 8 TDFN-8 +AFT T833-1

MAX1289EKA-T 8 SOT23-8 AAEY K8F-4

MAX1289ETA+T 8 TDFN-8 +AFP T833-1

EVALUATION KIT

AVAILABLE

+Indicates lead-free packaging.

Note: All devices specified over the -40°C to +85°C operating

range.

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1286/MAX1288,

0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. TA= TMIN to TMAX, unless otherwise

noted. Typical values at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND..............................................................-0.3V to +6V

CNVST, SCLK, DOUT to GND....................-0.3V to (VDD + 0.3V)

REF, AIN1 (AIN+), AIN2 (AIN-) to GND......-0.3V to (VDD + 0.3V)

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (TA= +70°C)

8-Pin SOT23 (derate 9.70mW/°C above TA= +70°C) ...696mW

8-Pin TDFN (derate 18.5mW/°C above TA= +70°C) ...1481mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 1)

Resolution 12 Bits

Relative Accuracy (Note 2) INL ±1.0 LSB

Differential Nonlinearity DNL No missing codes over temperature ±1.0 LSB

Offset Error ±2±4 LSB

Gain Error (Note 3) ±2±4 LSB

Gain Temperature Coefficient ±0.4 ppm/°C

Offset Tem p er atur e C oeffi ci ent ±0.4 p p m/°C

Channel-to-Channel Offset Matching ±0.1 LSB

Channel-to-Channel Gain Matching ±0.1 LSB

Input Common-Mode Rejection CMR VCM = 0V to VDD; zero scale input ±0.1 mV

DYNAMIC SPECIFICATIONS: (fIN (sine-wave) = 10kHz, VIN = 4.096Vp-p for MAX1286/MAX1288 or VIN = 2.5V

for MAX1287/MAX1289, 150ksps, fSCLK = 8MHz, (50% duty cycle) AIN- = GND for MAX1288/MAX1289)

Signal to Noise Plus Distortion SINAD 70 dB

Total Harmonic Distortion

(up to the 5th harmonic) THD -82 dB

Spurious-Free Dynamic Range SFDR 86 dB

Full-Power Bandwidth -3dB point 1 MHz

Full-Linear Bandwidth SINAD > 68dB 100 kHz

CONVERSION RATE

Conversion Time tCONV Does not include tACQ 3.7 µs

T/H Acquisition Time tACQ 1.4 µs

Aperture Delay 30 ns

Aperture Jitter <50 ps

Maximum Serial Clock Frequency fSCLK 8 MHz

Duty Cycle 30 70 %

ANALOG INPUT

Unipolar 0 VREF

Input Voltage Range (Note 4) Bipolar -VREF /2 VREF/2 V

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1286/MAX1288,

0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. TA= TMIN to TMAX, unless otherwise

noted. Typical values at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage Current C hannel not sel ected or conver si on stop p ed ±0.01 ±1µA

Input Capacitance 34 pF

EXTERNAL REFERENCE INPUT

Input Voltage Range VREF 1.0 VDD

+50mV V

VREF = +2.5V at 150ksps 16 30

VREF = +4.096V at 150ksps 26 45Input Current IREF

Acquisition/Between conversions ±0.01 ±1

µA

DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT)

Input Low Voltage VIL 0.8 V

Input High Voltage VIH VDD -1 V

Input Leakage Current IL±0.01 ±1.0 µA

Input Capacitance CIN 15 pF

ISINK = 2mA 0.4 V

Output Low Voltage VOL ISINK = 4mA 0.8 V

Output High Voltage VOH ISOURCE = 1.5mA VDD

-0.5 V

Three-State Leakage Current CNVST = GND ±0.05 ±10 µA

Three-State Output Capacitance COUT CNVST = GND 15 pF

POWER REQUIREMENTS

MAX1286/MAX1288 4.75 5.0 5.25

Positive Supply Voltage VDD MAX1287/MAX1289 2.7 3.0 3.6 V

fSAMPLE =150ksps 245 350

fSAMPLE =100ksps 150

fSAMPLE =10ksps 15

VDD = +3V

fSAMPLE =1ksps 2

fSAMPLE =150ksps 320 400

fSAMPLE =100ksps 215

fSAMPLE =10ksps 22

VDD = +5V

fSAMPLE =1ksps 2.5

Positive Supply Current IDD

Shutdown 0.2 5

µA

VDD = 5V ±5%; full-scale input ±0.3 ±1.0

Positive Supply Rejection PSR VDD = +2.7V to +3.6V; full-scale input ±0.4 ±1.2 mV

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS (Figures 1, 2, and 5)

(VDD = +2.7V to +3.6V, VREF = +2.5V, 0.1µF capacitor at REF, or VDD = +4.75V to +5.25V for MAX1286/MAX1288, VREF = +4.096V,

0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. TA= TMIN to TMAX, unless otherwise

noted. Typical values at TA= +25°C.)

PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Pulse Width High tCH 38 ns

SCLK Pulse Width Low tCL 38 ns

SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 60 ns

SCLK Rise to DOUT Disable tDOD CLOAD = 30pF 100 500 ns

CNVST Rise to DOUT Enable tDOE CLOAD = 30pF 80 ns

CNVST Fall to MSB Valid tCONV CLOAD = 30pF 3.7 µs

CNVST Pulse Width tCSW 30 ns

Note 1: Unipolar mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Offset nulled.

Note 4: The absolute input voltage range for the analog inputs is from GND to VDD.

• • •

CNVST

SCLK

DOUT

tDOE

HIGH-Z HIGH-Z

tCSW

tCL

tCH

tDOD

tDOT

DOUT

6kΩ

GND

DOUT

GND

VDD

a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z b) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z

Figure 1. Detailed Serial-Interface Timing Sequence

Figure 2. Load Circuits for Enable/Disable Times

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

_______________________________________________________________________________________ 5

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 1000 1500 2000500 2500 3000 3500 4000 4500

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX1286-9 toc01

OUTPUT CODE

INL (LSB)

MAX1287/MAX1289

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 1000 1500 2000500 2500 3000 3500 4000 4500

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX1286-9 toc02

OUTPUT CODE

INL (LSB)

MAX1286/MAX1288

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 1000 1500 2000500 2500 3000 3500 4000 4500

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX1286-9 toc03

OUTPUT CODE

DNL (LSB)

MAX1287/MAX1289

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 1000 1500 2000500 2500 3000 3500 4000 4500

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX1286-9 toc04

OUTPUT CODE

DNL (LSB)

MAX1286/MAX1288

1000

010

100 1000

SUPPLY CURRENT

vs. SAMPLING RATE

100

MAX1286-9 toc05

SAMPLING RATE (ksps)

SUPPLY CURRENT (µA)

0.1

MAX1287/MAX1289

1000

SUPPLY CURRENT

vs. SAMPLING RATE

100

MAX1286-9 toc06

SAMPLING RATE (ksps)

SUPPLY CURRENT (µA)

0.1

010

100 10000.1 1

MAX1286/MAX1288

Typical Operating Characteristics

(VDD = +3V, VREF = +2.5V for MAX1287/MAX1289. VDD = +5V, VREF = +4.096V for MAX1286/MAX1288; 0.1µF capacitor at REF,

fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, TA= +25°C, unless otherwise noted.)

100

200

250

150

300

2.7 3.7 4.23.2 4.7 5.2

SHUTDOWN CURRENT

vs. SUPPLY VOLTAGE

MAX1286-9 toc08

VDD (V)

SHUTDOWN CURRENT (nA)

180

220

200

260

240

300

320

340

360

280

380

2.7 3.7 4.23.2 4.7 5.2

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1286-9 toc07

VDD (V)

SUPPLY CURRENT (µA)

180

230

380

330

280

430

-40 0 20-20 40 60 80

SUPPLY CURRENT

vs. TEMPERATURE

MAX1286-9 toc09

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

MAX1286

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD = +3V, VREF = +2.5V for MAX1287/MAX1284. VDD = +5V, VREF = +4.096V for MAX1286/MAX1288; 0.1µF capacitor at REF,

fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, TA= +25°C, unless otherwise noted.)

100

250

200

150

300

-40 0 20-20 40 60 80

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX1286-9 toc10

TEMPERATURE (°C)

SHUTDOWN CURRENT (nA)

-1.00

-0.40

-0.60

-0.80

0.00

-0.20

0.80

0.60

0.40

0.20

1.00

-40 -20 0 20 40 60 80

OFFSET ERROR

vs. TEMPERATURE

MAX1286-9 toc11

TEMPERATURE (°C)

OFFSET ERROR (LSB)

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.6

0.8

1.0

2.7 3.7 4.23.2 4.7 5.2

OFFSET ERROR

vs. SUPPLY VOLTAGE

MAX1286-9 toc12

VDD (V)

OFFSET ERROR (LSB)

-40 0 20-20 40 60 80

GAIN ERROR

vs. TEMPERATURE

MAX1286-9 toc13

TEMPERATURE (°C)

GAIN ERROR (LSB)

-2.0

-1.2

-1.6

-0.4

-0.8

0.4

0.8

1.2

1.6

2.0

-2.0

-1.2

-1.6

-0.4

-0.8

0.4

0.8

1.2

1.6

2.0

2.7 3.7 4.23.2 4.7 5.2

GAIN ERROR

vs. SUPPLY VOLTAGE

MAX1286-9 toc14

VDD (V)

GAIN ERROR (LSB)

-140

-120

-100

-80

-60

-40

-20

0 15k 30k 45k 60k

FFT PLOT (SINAD)

MAX1286-9 toc15

FREQUENCY (Hz)

AMPLITUDE (dB)

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

_______________________________________________________________________________________ 7

Detailed Description

The MAX1286–MAX1289 ADCs use a successive-

approximation conversion (SAR) technique and an on-

chip track-and-hold (T/H) structure to convert an

analog signal into a 12-bit digital result.

The serial interface provides easy interfacing to micro-

processors (µPs). Figure 3 shows the simplified internal

structure for the MAX1286/MAX1287 (2 channels, sin-

gle ended) and the MAX1288/MAX1289 (1 channel,

true differential).

True-Differential Analog Input T/H

The equivalent circuit of Figure 4 shows the

MAX1286–MAX1289s’ input architecture, which is com-

posed of a T/H, input multiplexer, comparator, and

switched-capacitor DAC. The T/H enters its tracking

mode on the rising edge of CNVST. The positive input

capacitor is connected to AIN1 or AIN2 (MAX1286/

MAX1287) or AIN+ (MAX1288/MAX1289). The negative

input capacitor is connected to GND (MAX1286/

MAX1287) or AIN- (MAX1288/MAX1289). The T/H

enters its hold mode on the falling edge of CNVST and

the difference between the sampled positive and nega-

tive input voltages is converted. The time required for

the T/H to acquire an input signal is determined by how

quickly its input capacitance is charged. If the input

signal’s source impedance is high, the acquisition time

lengthens, and CNVST must be held high for a longer

period of time. The acquisition time, tACQ, is the maxi-

mum time needed for the signal to be acquired, plus

the power-up time. It is calculated by the following

equation:

tACQ = 9 x (RS+ RIN) x 24pF + tPWR

12-BIT

SAR

ADC

CONTROL

OSCILLATOR

INPUT SHIFT

T/H

REF

CNVST

SCLK

DOUT

AIN2

(AIN-)

AIN1

(AIN+)

MAX1286–MAX1289

( ) ARE FOR MAX1288/MAX1289

Figure 3. Simplified Functional Diagram

NAME

PIN MAX1286

MAX1287

MAX1288

MAX1289

FUNCTION

DD VDD Positive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V

(MAX1286/MAX1288). Bypass with a 0.1µF capacitor to GND.

2 AIN1 AIN+ Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289)

3 AIN2 AIN- Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289)

4 GND GND Ground

5 REF REF External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF

capacitor to GND.

6 CNVST CNVST

Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling

edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the

input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289).

7 DOUT DOUT

Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a

conversion and presents the MSB at the completion of a conversion. DOUT goes high

impedance once data has been fully clocked out.

8 SCLK SCLK Serial Clock Input. Clocks out data at DOUT MSB first.

Pin Description

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

8 _______________________________________________________________________________________

where RIN = 1.5kΩ, RSis the source impedance of the

input signal, and tPWR = 1µs is the power-up time of the

device.

Note: tACQ is never less than 1.4µs and any source

impedance below 300Ωdoes not significantly affect the

ADC’s AC performance. A high-impedance source can

be accommodated either by lengthening tACQ or by

placing a 1µF capacitor between the positive and neg-

ative analog inputs.

Selecting AIN1 or AIN2

(MAX1286/MAX1287)

Select one of the MAX1286/MAX1287s’ two positive

input channels using the CNVST pin. If AIN1 is desired

(Figure 5a), drive CNVST high to power up the ADC

and place the T/H in track mode with AIN1 connected

to the positive input capacitor. Hold CNVST high for

tACQ to fully acquire the signal. Drive CNVST low to

place the T/H in hold mode. The ADC then performs a

conversion and shutdown automatically. The MSB is

available at DOUT after 3.7µs. Data can then be

clocked out using SCLK. Clock out all 12 bits of data

before driving CNVST high for the next conversion. If all

12 bits of data are not clocked out before CNVST is dri-

ven high, AIN2 is selected for the next conversion.

If AIN2 is desired (Figure 5b), drive CNVST high for at

least 30ns. Next, drive it low for at least 30ns, and then

high again. This powers up the ADC and places the

T/H in track mode with AIN2 connected to the positive

input capacitor. Now hold CNVST high for tACQ to fully

acquire the signal. Drive CNVST low to place the T/H in

hold mode. The ADC then performs a conversion and

shutdown automatically. The MSB is available at DOUT

after 3.7µs. Data can then be clocked out using SCLK.

If all 12 bits of data are not clocked out before CNVST

is driven high, AIN2 is selected for the next conversion.

Selecting Unipolar or Bipolar Conversions

(MAX1288/MAX1289)

Initiate true-differential conversions with the

MAX1288/MAX1289s’ unipolar and bipolar modes,

using the CNVST pin. AIN+ and AIN- are sampled at

the falling edge of CNVST. In unipolar mode, AIN+ can

exceed AIN- by up to VREF. The output format is

straight binary. In bipolar mode, either input can

exceed the other by up to VREF/2. The output format is

two’s complement.

Note: In both modes, AIN+ and AIN- must not exceed

VDD by more than 50mV or be lower than GND by more

than 50mV.

If unipolar mode is desired (Figure 5a), drive CNVST

high to power up the ADC and place the T/H in track

mode with AIN+ and AIN- connected to the input

capacitors. Hold CNVST high for tACQ to fully acquire

the signal. Drive CNVST low to place the T/H in hold

mode. The ADC then performs a conversion and shut-

down automatically. The MSB is available at DOUT

after 3.7µs. Data can then be clocked out using SCLK.

Clock out all 12 bits of data before driving CNVST high

for the next conversion. If all 12 bits of data are not

clocked out before CNVST is driven high, bipolar mode

is selected for the next conversion.

If bipolar mode is desired (Figure 5b), drive CNVST

high for at least 30ns. Next, drive it low for at least 30ns

and then high again. This places the T/H in track mode

with AIN+ and AIN- connected to the input capacitors.

Now hold CNVST high for tACQ to fully acquire the sig-

nal. Drive CNVST low to place the T/H in hold mode.

The ADC then performs a conversion and shutdown

automatically. The MSB is available at DOUT after

3.7µs. Data can then be clocked out using SCLK. If all

12 bits of data are not clocked out before CNVST is dri-

ven high, bipolar mode is selected for the next conver-

sion.

Input Bandwidth

The ADC’s input tracking circuitry has a 1MHz small-

signal bandwidth, so it is possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid high-fre-

quency signals being aliased into the frequency band

of interest, anti-alias filtering is recommended.

RIN+

HOLD

RIN-

CIN+

REF

GND DAC

CIN-

TRACK

VDD/2

COMPARATOR

GND (AIN-)

AIN2

AIN1 (AIN+)

HOLD

( ) ARE FOR MAX1288/MAX1289

Figure 4. Equivalent Input Circuit

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

_______________________________________________________________________________________ 9

Analog Input Protection

Internal protection diodes that clamp the analog input to

VDD and GND allow the analog input pins to swing from

GND - 0.3V to VDD + 0.3V without damage. Both inputs

must not exceed VDD by more than 50mV or be lower

than GND by more than 50mV for accurate conversions.

If an off-channel analog input voltage exceeds the

supplies, limit the input current to 2mA.

Internal Clock

The MAX1286–MAX1289 operate from an internal oscilla-

tor, which is accurate within 10% of the 4MHz specified

clock rate. This results in a worst-case conversion time of

3.7µs. The internal clock releases the system micro-

processor from running the SAR conversion clock and

allows the conversion results to be read back at the

processor’s convenience, at any clock rate from 0 to

8MHz.

CNVST

SCLK

DOUT

tACQ

tCONV

SAMPLING INSTANT

41812

B11

MSB B10 B9 B8 B7

B5 B4 B3 B2 B1 B0

LSB

HIGH-Z

CNVST

SCLK

DOUT

tACQ

tCONV

SAMPLING INSTANT

41812

B11

MSB B10 B9 B8 B7

B5 B4 B3 B2 B1 B0

LSB

HIGH-Z

Figure 5b. Single Conversion AIN2 vs. GND (MAX1286/MAX1287), Bipolar Mode AIN+ vs. AIN- (MAX1288/MAX1289)

Figure 5a. Single Conversion AIN1 vs. GND (MAX1286/MAX1287), Unipolar Mode AIN+ vs. AIN- (MAX1288/MAX1289)

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

10 ______________________________________________________________________________________

Output Data Format

Figures 5a and 5b illustrate the conversion timing for the

MAX1286–MAX1289. The 12-bit conversion result is out-

put in MSB-first format. Data on DOUT transitions

on the falling edge of SCLK. All 12 bits must be clocked

out before CNVST transitions again. For the MAX1288/

MAX1289, data is straight binary for unipolar mode and

two’s complement for bipolar mode. For the MAX1286/

MAX1287, data is always straight binary.

Transfer Function

Figure 6 shows the unipolar transfer function for the

MAX1286–MAX1289. Figure 7 shows the bipolar transfer

function for the MAX1288/MAX1289. Code transitions

occur halfway between successive-integer LSB values.

Applications Information

Automatic Shutdown Mode

With CNVST low, the MAX1286–MAX1289 default to an

AutoShutdown state (< 0.2µA) after power-up and

between conversions. After detecting a rising edge on

CNVST, the part powers up, sets DOUT low, and enters

track mode. After detecting a falling edge on CNVST, the

device enters hold mode and begins the conversion. A

maximum of 3.7µs later, the device completes conver-

sion, enters shutdown, and MSB is available at DOUT.

External Reference

An external reference is required for the MAX1286–

MAX1289. Use a 0.1µF bypass capacitor for best per-

formance. The reference input structure allows a volt-

age range of +1V to VDD + 50mV.

Connection to Standard Interfaces

The MAX1286–MAX1289 feature a serial interface that is

fully compatible with SPI, QSPI, and MICROWIRE. If a

serial interface is available, establish the CPU’s serial

interface as a master, so that the CPU generates the seri-

al clock for the ADCs. Select a clock frequency up to

8MHz.

How to Perform a Conversion

1) Use a general-purpose I/O line on the CPU to hold

CNVST low between conversions.

2) Drive CNVST high to acquire AIN1(MAX1286/

MAX1287) or unipolar mode (MAX1288/MAX1289).

To acquire AIN2 (MAX1286/MAX1287) or bipolar

mode (MAX1288/MAX1289), drive CNVST low and

high again.

3) Hold CNVST high for 1.4µs.

4) Drive CNVST low and wait approximately 3.7µs for

conversion to complete. After 3.7µs, the MSB is

available at DOUT.

5) Activate SCLK for a minimum of 12 rising clock

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

123

0FS

FS - 3/2 LSB

FS = VREF

ZS = GND

INPUT VOLTAGE (LSB)

MAX1286–

MAX1289

1 LSB = VREF

4096

Figure 6. Unipolar Transfer Function

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

- FS 0

INPUT VOLTAGE (LSB)

OUTPUT CODE

ZS = 0

+FS - 1 LSB

*VCOM VREF / 2 *VIN = (AIN+) - (AIN-)

FS = VREF

-FS = -VREF

≤

MAX1288/MAX1289

1 LSB = VREF

4096

Figure 7. Bipolar Transfer Function

edges. DOUT transitions on SCLK’s falling edge

and is available in MSB-first format. Observe the

SCLK to DOUT valid timing characteristic. Clock

data into the µP on SCLK’s rising edge.

SPI and MICROWIRE Interface

When using an SPI (Figure 8a) or MICROWIRE inter-

face (Figures 8a and 8b), set CPOL = CPHA = 0. Two

8-bit readings are necessary to obtain the entire 12-bit

result from the ADC. DOUT data transitions on the seri-

al clock’s falling edge and is clocked into the µP on

SCLK’s rising edge. The first 8-bit data stream contains

the first 8-bits of DOUT starting with the MSB. The sec-

ond 8-bit data stream contains the remaining four result

bits. DOUT then goes high impedance.

QSPI Interface

Using the high-speed QSPI interface (Figure 9a) with

CPOL = 0 and CPHA = 0, the MAX1286–MAX1289

support a maximum fSCLK of 8MHz. One 12- to 16-bit

reading is necessary to obtain the entire 12-bit result

from the ADC. DOUT data transitions on the serial

clock’s falling edge and is clocked into the µP on

SCLK’s rising edge. The first 12 bits are the data.

DOUT then goes high impedance (Figure 9b).

PIC16 and SSP Module and

PIC17 Interface

The MAX1286–MAX1289 are compatible with a

PIC16/PIC17 µC, using the synchronous serial port

(SSP) module

To establish SPI communication, connect the controller

as shown in Figure 10a and configure the PIC16/PIC17

as system master. This is done by initializing its syn-

chronous serial port control register (SSPCON) and

synchronous serial port status register (SSPSTAT) to

the bit patterns shown in Tables 1 and 2.

In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data

to be synchronously transmitted and received simulta-

neously. Two consecutive 8-bit readings (Figure 10b)

are necessary to obtain the entire 12-bit result from the

ADC. DOUT data transitions on the serial clock’s falling

edge and is clocked into the µC on SCLK’s rising edge.

The first 8-bit data stream contains the first 8 data bits

starting with the MSB. The second data stream con-

tains the remaining bits, D3 through D0.

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

______________________________________________________________________________________ 11

Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections

CNVST

SCLK

DOUT

I/O

SCK

MISO VDD

SPI

MAX1286–

MAX1289

MAX1286–

MAX1289

CNVST

SCLK

DOUT

I/O

MICROWIRE

Table 1. Detailed SSPCON Register Content

CONTROL BIT MAX1286–MAX1289

SETTINGS SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)

WCOL Bit 7 X Write Collision Detection Bit

SSPOV Bit 6 X Receive Overflow Detect Bit

SSPEN Bit 5 1

Synchronous Serial Port Enable Bit:

0: Disables serial port and configures these pins as I/O port pins.

1: E nab l es ser i al p or t and confi g ur es S C K, S D O, and S C I p i ns as ser i al p or t p i ns.

CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.

SSPM3 Bit 3 0

SSPM2 Bit 2 0

SSPM1 Bit 1 0

SSPM0 Bit 0 1

Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects

FCLK = fOSC / 16.

MAX1286–MAX1289

Layout, Grounding, and Bypassing

For best performance, use printed circuit (PC) boards.

Wire-wrap configurations are not recommended since

the layout should ensure proper separation of analog

and digital traces. Do not run analog and digital lines

parallel to each other, and do not lay out digital signal

paths underneath the ADC package. Use separate

analog and digital PC board ground sections with only

one starpoint (Figure 11), connecting the two ground

systems (analog and digital). For lowest-noise opera-

tion, ensure the ground return to the star ground’s

power supply is low impedance and as short as possi-

ble. Route digital signals far away from sensitive analog

and reference inputs.

High-frequency noise in the power supply (VDD) may

degrade the performance of the ADC’s fast comparator.

Bypass VDD to the star ground with a 0.1µF capacitor,

located as close as possible to the MAX1286–MAX1289s’

power-supply pin. Minimize capacitor lead length for best

supply-noise rejection. Add an attenuation resistor (5Ω) if

the power supply is extremely noisy.

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

12 ______________________________________________________________________________________

CNVST

SCLK

DOUT

SCK

MISO VDD

QSPI

MAX1286–

MAX1289

Figure 9a. QSPI Connections

Table 2. Detailed SSPSTAT Register Content

CONTROL BIT MAX1286–MAX1289

SETTINGS SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)

SMP Bit 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data

output time.

CKE Bit 6 1 SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial

clock.

D/A Bit 5 X Data Address Bit

P Bit 4 X Stop Bit

S Bit 3 X Start Bit

R/W Bit 2 X Read/Write Bit Information

UA Bit 1 X Update Address

BF Bit 0 X Buffer Full Status Bit

Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)

CNVST

1ST BYTE READ

SCLK

DOUT

2ND BYTE READ

SAMPLING INSTANT

418

B11

MSB B10 B9 B8 B7

B5 B4 B3 B2 B1 B0

LSB

HIGH-Z

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nullified. The sta-

tic linearity parameters for the MAX1286–MAX1289 are

measured using the end-point method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1 LSB. A

DNL error specification of less than 1 LSB guarantees

no missing codes and a monotonic transfer function.

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

______________________________________________________________________________________ 13

CNVST

SCLK

DOUT

SAMPLING INSTANT

418

B11

MSB B10 B9 B8 B7

B5 B4 B3 B2 B1 B0

LSB

HIGH-Z

Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)

SCK

SDI

GND GND

I/O

SCLK

DOUT

CNVST

VDD VDD

MAX1286–

MAX1289

PIC16/PIC17

Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller

CNVST

1ST BYTE READ

SCLK

DOUT

2ND BYTE READ

SAMPLING INSTANT

418

B11

MSB B10 B9 B8 B7

B5 B4 B3 B2 B1 B0

LSB

HIGH-Z

Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

14 ______________________________________________________________________________________

Aperture Definitions

Aperture jitter (tAJ) is the sample-to-sample variation in

the time between the samples. Aperture delay (tAD) is

the time between the rising edge of the sampling clock

and the instant when an actual sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam-

ples, signal-to-noise ratio (SNR) is the ratio of full-scale

analog input (RMS value) to the RMS quantization error

(residual error). The ideal, theoretical minimum analog-to-

digital noise is caused by quantization error only and

results directly from the ADC’s resolution (N bits):

SNR = (6.02 ✕N + 1.76)dB

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter,

etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise, which includes all spectral

components minus the fundamental, the first five har-

monics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to RMS

equivalent of all other ADC output signals.

SINAD (dB) = 20 ✕log (SignalRMS / NoiseRMS)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the full-

scale range of the ADC, calculate the effective number

of bits as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through

V5are the amplitudes of the 2nd- through 5th-order har-

monics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest distortion

component.

Chip Information

TRANSISTOR COUNT: 6922

PROCESS: BiCMOS

THD VVVV

=× +++

⎛

⎝

⎜

⎞

⎠

⎟

20 2345

2222

log

VLOGIC = +5V

OR +3V GND

SUPPLIES

DGND+5V OR

+3V

GND

0.1µF

VDD

DIGITAL

CIRCUITRY

MAX1286–

MAX1289

R* = 5Ω

*OPTIONAL

+5V OR

+3V

Figure 11. Power-Supply and Grounding Connections

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

______________________________________________________________________________________ 15

SOT23, 8L .EPS

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

3.002.60E

BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP.

8. MEETS JEDEC MO178.

8∞

0.60

1.75

0.30

0∞

1.50E1

0.65 BSC.

1.95 REF.

0.25 BSC.

GAUGE PLANE

SEATING PLANE C

PIN 1

I.D. DOT

(SEE NOTE 6)

DETAIL "A"

5. COPLANARITY 4 MILS. MAX.

NOTE:

7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD

6. PIN 1 I.D. DOT IS 0.3 MM ÿ MIN. LOCATED ABOVE PIN 1.

4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING.

3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR.

HEEL OF THE LEAD PARALLEL TO SEATING PLANE C.

2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF

1. ALL DIMENSIONS ARE IN MILLIMETERS.

0.45

1.30

0.15

1.45

MAX

0.28b

0.90A2

0.00A1

0.90

MIN

SYMBOL

3.00

0.20

2.80D

0.09

SEE DETAIL "A"

21-0078

PACKAGE OUTLINE, SOT-23, 8L BODY

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

MAX1286–MAX1289

150ksps, 12-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

6, 8, &10L, DFN THIN.EPS

PIN 1

INDEX

AREA

21-0137

PACKAGE OUTLINE, 6,8,10 & 14L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

-DRAWING NOT TO SCALE-

[(N/2)-1] x e

REF.

PIN 1 ID

0.35x0.35

DETAIL A

COMMON DIMENSIONS

SYMBOL MIN. MAX.

A0.70 0.80

D2.90 3.10

E2.90 3.10

A1 0.00 0.05

L0.20 0.40

PKG. CODE ND2 E2 eJEDEC SPEC b[(N/2)-1] x e

PACKAGE VARIATIONS

0.25 MIN.k

A2 0.20 REF.

2.30±0.101.50±0.106T633-1 0.95 BSC MO229 / WEEA 1.90 REF0.40±0.05

1.95 REF0.30±0.05

0.65 BSC

2.30±0.108T833-1

2.00 REF0.25±0.05

0.50 BSC

2.30±0.1010T1033-1

2.40 REF0.20±0.05- - - -

0.40 BSC

1.70±0.10 2.30±0.1014T1433-1

1.50±0.10

MO229 / WEEC

MO229 / WEED-3

0.40 BSC - - - - 0.20±0.05 2.40 REFT1433-2 14 2.30±0.101.70±0.10

T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF

T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF

T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF

-DRAWING NOT TO SCALE-

21-0137

PACKAGE OUTLINE, 6,8,10 & 14L,

TDFN, EXPOSED PAD, 3x3x0.80 mm

DOWNBONDS

ALLOWED

YES

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)