ee February 1990 FAIRCHILD Revised November 1999 SEMICONDUCTOR 100314 Low Power Quint Differential Line Receiver General Description Features The 100314 is a monolithic quint differential line receiver i 35% power reduction of the 100114 with emitter-follower outputs. An internal reference supply _ 2000V ESD protection (Vpp) is available for single-ended reception. When used in Pin/function compatible with 100114 single-ended operation the apparent input threshold of the . rue inputs is 35 mV to 30 nV higher (positive) than the M Voltage compensated operating range =4.2V to -5.7V threshold of the complementary inputs. Unlike other F100K Ml Available to industrial grade temperature range ECL devices, the inputs do not have input pull-down resis- (PLCC package only) tors. Active current sources provide common-mode rejection of 1.0V in either the positive or negative direction. A defined output state exists if both inverting and non-inverting inputs are at the same potential between Vee and Voc. The defined state is logic HIGH on the 0,-0.2 outputs. Ordering Code: Order Number | Package Number Package Description 100314SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 10031 4PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide 10031 4QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 10031 4Ql V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C) Devices also available in Tape and Reel. Specify by appending the suffix letter Xx to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC Pa Le Oe _ wy, Da Oa 0.4! 24FD, 0,742 23;D, Dp Op o.-43 22;-Dg Dp Ob Ou 4 21D, Oy-5 20;D, De Oc Veo 6 197-Vep De Oe Veca]7 187-Vee 6,48 17;-5, Da Ou 0.49 16D, Ds Ou Op 10 15F=D, Ott 14FD, De Oe 0-412 13-0, De Oe 28-Pin PLCC > Ves = ~ = 2 Pa OaVeEs Om O OD : sgt & @ Pin Descriptions Pin Names Description DzDe Data Inputs DzDe Inverting Data Inputs O,-O, Data Outputs O,-O, Complementary Data Outputs Dg Dg DeVeesdy O, Oe 1999 Fairchild Semiconductor Corporation DS010260 www.fairchildsemi.com JBVAIBIOY BU! [EHUDIBJJIG JUINH AOMOd MO] FLEOOL100314 Storage Temperature (Tst@) Input Voltage (DC) ESD (Note 2) Commercial Version Maximum Junction Temperature (Ty) Pin Potential to Ground Pin (Vee) Output Current (DC Output HIGH) Absolute Maximum Ratingsinote 1) 65C to +150C +150C -7.0V to +0.5V Veg to +0.5V 50 mA 22000V DC Electrical Characteristics (note 3) Veg =-4.2V to -8.7V, Voo = Voca = GND, Ty = 0C to +85C Recommended Operating Conditions Case Temperature (Tc) Commercial OC to +85C Industrial 40C to +85C Supply Voltage (Veg) -5.7V to -4.2V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The Recommended Operating Conditions table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage 1025 955 -870 mv Vin = Vin (Max) Loading with VoL Output LOW Voltage 1830 1705 1620 mV or Vi, (Min) 502 to 2.0V Vouc Output HIGH Voltage 1035 mv Vin=Vin Loading with Voice Output LOW Voltage 1610 mv or Vi_ (Max) 50. to -2.0V Vep Output Reference Voltage 1380 1320 1260 mv yep =250 pA VDIFF Input Voltage Differential 150 mv Required for Full Qutput Swing Vom Common Mode Voltage Voc - 2.0 Voc - 0.5 Vv Vin Single-Ended Guaranteed HIGH Signal for All Input HIGH Voltage 1110 -870 mv Inputs (with one input tied to Vgp) Vee (Max) + Vpire Vit Single-Ended Guaranteed LOW Signal for All Input LOW Voltage 1830 1530 mv Inputs (with one input tied to Vgp) Vee (Min) VpiFr lit Input LOW Current 0.50 HA Vin = Vit (Min) lin Input HIGH Current 240 HA Vin = VIH (Max), Da-De = Vp, D,-D, = ViLemin) IcBo Input Leakage Current -10 HA Vin = Vee, Da-De = Ves, D.-Dg = Vit (tiny lee Power Supply Current 60 -30 mA D,-D, = Vep, D,-D, = Vib (tiny Note 3: The specified limits represent the worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under worst case conditions. www. fairchildsemi.comCommercial Version (continued) DIP AC Electrical Characteristics Veg =4.2V to-5.7V, Voc = Veca = GND Te =0C Te = +25C Te = +85C Symbol Parameter Units Conditions Min Max Min Max Min Max f Toggle Frequenc MAXFS gale Frequency 250 250 250 MHz | (Note 2) (Full Swing) fMAXRS Toggle Frequency / 700 700 700 MHz | (Note 3) (Reduced Swing) t Propagation Dela PLH Pag 0.65 4.90 0.65 2.00 0.70 2.00 ns teu Data to Output . - Figures 1, 2 ttLy Transition Time 0.35 1.20 0.35 1.20 0.35 1.20 ns tTHL 20% to 80%, 80% to 20% SOIC and PLCC AC Electrical Characteristics Veg =4.2V to5.7V, Veo = Voca = GND Te = 0C Te = 425C Te = +85C Symbol Parameter Units Conditions Min Max Min Max Min Max f Toggle Frequenc MAXFS gale Frequency 250 250 250 MHz | (Note 4) (Full Swing) f Toggle Frequenc MAXRS gale Frequency 700 700 700 MHz | (Note 5) (Reduced Swing) t Propagation Dela PLH Pag 0.65 4.70 0.65 4.80 0.70 4.80 ns tPHL Data to Output ; - Figures 1, 2 toy Transition Time 0,35 1.10 0,35 1.10 0,35 1.10 ns tTHL 20% to 80%, 80% to 20% tPLH Propagation Delay 0.70 1.50 0,80 1.60 0,80 1.80 ns PLCC only teu Data to Output tosHL Maximum Skew Common Edge PLCC only Output-to-Output Variation 280 280 280 ps (Note 6)(Note 7) Data to Output Path tosLH Maximum Skew Common Edge PLCC only Output-to-Output Variation 330 330 330 ps (Note 6)(Note 7) Data to Output Path tost Maximum Skew Opposite Edge PLCC only Output-to-Output Variation 330 330 330 ps (Note 6)(Note 7) Data to Output Path tps Maximum Skew PLCC only Pin (Signal) Transition Variation 320 320 320 ps (Note 6)(Note 7) Data to Output Path Note 4: Maximum toggle frequency at which Voy and Vo, DC specifications are maintained. Note 5: Maximum toggle frequency at which outputs maintain 150 mV swing. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack- aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tog}1,), or LOW-to-HIGH (tog, 4), or in opposite directions both HL and LH (tog). Parameters togy and tpg guaranteed by design. Note 7: All skews calculated using input crossing point to output crossing point propagation delays. www. fairchildsemi.com VLEOOL100314 Industrial Version PLCC DC Electrical Characteristics (note ) Vee =-4.2V to-5.7V, Veco = Veca =GND, Te =-40C to +85C To = 40C Te =0C to +85C Symbol Parameter Units Conditions Min Max Min Max Vou Output HIGH Voltage 1085 870 1025 870 mv Vin = Vin (Max) Loading with Voi Output LOW Voltage 1830 1575 1830 1620 mv or Vi_ (Min) 50. to -2.0V Vouc Output HIGH Voltage 1095 1035 mV Vin = Vin Loading with Voice Output LOW Voltage 1565 1610 mv or Vi_ (Min) 50. to -2.0V Vep Output Reference Voltage 1395 1255 1380 1260 mV lyep =250 pA VbIFF Input Voltage Differential 150 150 mv Required for Full Output Swing Vom Common Mode Voltage Voo- 2.0 Vocg 0.5] Veg - 2.0 Vog-0.5 Vv Vin Single-Ended Guaranteed HIGH Signal for All Input HIGH Voltage 1115 870 1110 870 mv Inputs (with one input tied to Vga) Vpp (Max) + Voir VIL Single-Ended Guaranteed LOW Signal for All Input LOW Voltage 1830 1535 1830 1530 mv Inputs (with one input tied to Vga) Vp (Min) Voir lit Input LOW Current 0.50 0.50 HA Vin = Vib min) lin Input HIGH Current 240 240 HA Vin = Vin (Max): Pa-De = Ves: D.-Dg = VIL (Min) IcBo Input Leakage Current 10 10 HA Vin = Vee, Da-De = Ves Da-De = VIL (Min) lee Power Supply Current -60 -30 -60 -30 MA | Da-De = Vap, Da-De = Vi (Min) Note 8: The specified limits represent the worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho- sen to guarantee operation under worst case conditions. PLCC AC Electrical Characteristics Ver = 4.2V to -5.7V, Voo = Voca = GND Te = 40C Te = +25C Te = +85C Symbol Parameter Units Conditions Min Max Min Max Min Max f Toggle Frequenc MAXFS gale Frequency 250 250 250 MHz | (Note 9) (Full Swing) fMaxRs Toggle Frequency / 700 700 700 MHz | (Note 10) (Reduced Swing) t Propagation Dela PLH Pag 0.65 1.70 0.65 1.80 0.70 1.80 ns tpuL Data to Output Figures 1Figure trLy Transition Time 2 0.20 1.40 0.35 1.10 0.35 1.10 ns tTHL 20% to 80%, 80% to 20% Note 9: Maximum toggle frequency at which Vg, and Vg, DC specifications are maintained. Note 10: Maximum toggle frequency at which outputs maintain 150 mV swing. www. fairchildsemi.comTest Circuit Note: Voc: Vooa = +2V, Vee = -2.5V L1 ie SCOPE V vd CHAN A Co 0.1 nF L - " = Rr L2 PULSE i ORDER +\e--e@-| SCOPE GENERATOR V7 ; x TEST 1 | CHAN B = = Rr CL , I L1 and L2 = equal length 509 impedance lines Ry = 509 terminator internal to scope Decoupling 0.1 LF from GND to Veg and Veg + All unused outputs are loaded with 500 to GND C, = Fixture and stray capacitance < 3 pF FIGURE 1. AC Test Circuit Switching Waveforms 0.7+0.1 ns *| < [~<_ 0.7+0.1 ns + 1.05 V INPUT +0.31V tpH_] re Saal - tPpLH TRUE 50% OUTPUT tpLH _| < ten 80% 50% COMPLEMENT 20% tL J FIGURE 2. Propagation Delay and Transition Times www. fairchildsemi.com VLEOOL100314 Physical DimeNnsiONS inches (millimeters) unless otherwise noted == 0.6141 LEAD NO 1 IDENTIFICATION N~ a. 104s 0.0125 0.0926 9.0091 Typ ALL LEADS 2.65 .0 0.23 2.35 Lo O i om +UGEMEEEBEEEE tc __ NR PLANE lo. 0.0500 ae max Tye 7 0.014 ALL LEAD TIPS 0.0160 0.35 >| Taz TYP ALL LEADS 0:40 M24B (REV F) 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 1.194-1.214 [30.33-30.84] 0.202 24 [5.13] 13 DOLE CI PI pi Pa ei a 9:035-0.045 f [0.89-1.14] SD 0.337-0.347 [8.56-8.81] Q | u LICICICI CUCU Uo LI 1 12 PIN NO. 1 IDENT 0.125 [5.18] 0.125-0.135 5 0.060 0.039 - [3.18-3.43] TrR>| be 4x >| je 0.390- 0.410 [1.52] [0.99] 0.065 [9.91-10.41] [1.65] - 0.145-0.200 | | } 9 ohooe [3.68-5.08] B6-94 Le 0.380 0.020 yy} |__ 0.125-0.140 yp , 4 [el [9.65] MN [0.51] [3.18-3.56] | | ' | 9.047-0.057 +0.040 0.050 yp >| I Ph.19-1.43] PP 0.428 015 [1.27] [10.87 71-02 0.018-0.021 0.090-0.110 0.009-0.015, PP 0,38] 10.38-0.33] TYP 12.29-2.79] TYP [0.23-0.38] N24E (REV A) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide Package Number N24E www. fairchildsemi.com 6Physical DimensiON inches (millimeters) unless otherwise noted (Continued) +0.006 -0.000 40.15 -0.00 0.450 [11.43] PIN #1 IDENT 1 26 12 18 | 0.050 typ | < [1.27] 0.300 typ [7.62] 450 y 2-045 0.49040.005 TYP [12.4540.13] OUUOUOU [1.14] Oo A5e Xr] 0.02940.003 rp (0.4340. 10] [0.7440.08] | | 25 0.165-0.180 [4.19-4.57] 0.045 0.01740.004 oF 0.41040.020 [10.4140.51] q Le SEATING PLANE 0.020 [0.51] 9.10540.015 yp [2.670.38] MIN TYP TYP 0.004 [9.10] V28A (REV K) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www. fairchildsemi.com JBVAIBIOY BU! [EHUDIBJJIG JUINH AOMOd MO] FLEOOL