DATA SHEET MOS INTEGRATED CIRCUIT PD75104, 75106, 75108 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION PD75108 is a 4-bit single-chip microcomputer integrating timer/event counters, serial interface, and vector interrupt function, in addition to a CPU, ROM, RAM, and I/O ports, on a single chip. Operating at high speeds, the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog inputs, PD75108 is suitable for controlling such systems as VTRs, acoustic products, button telephones, radio communications equipment, and printers. A pin-compatible EPROM model is also available for evaluation of system development and small-scale production of application systems. Detailed functions are described in the following user's manual. Be sure to read it for designing. PD751XX Series User's Manual: IEM-922 FEATURES * Internal memory * Program memory (ROM) : 8068 x 8 bits ( PD75108) : 6016 x 8 bits ( PD75106) : 4096 x 8 bits ( PD75104) * Data memory (RAM) : 512 x 4 bits ( PD75108) : 320 x 4 bits ( PD75106, 75104) * New architecture "75X series" rivaling 8-bit microcomputers * 43 systematically organized instructions * A wealth of bit manipulation instructions * 8-bit data transfer, compare, operation, increment, and decrement instructions * 1-byte relative branch instructions * GETI instruction executing 2-/3-byte instruction with one byte * High speed. Minimum instruction execution time: 0.95 s (at 4.19 MHz), 5 V * Power-saving, instruction time change function: 0.95 s/1.91 s/15.3 s (at 4.19 MHz) * I/O port pins as many as 58 * Three channels of 8-bit timers * 8-bit serial interface * Multiplexed vector interrupt function * Model with PROM is available: PD75P108B (One-time PROM, EPROM) Unless there are differences among PD75104, 75106, and 75108 functions, PD75108 is treated as the representative model throughout this manual. The information in this document is subject to change without notice. Document No. IC-2520B (O. D. No. IC-6906B) Date Published January 1994 P Printed in Japan The mark shows major revised points. NEC Corporation 1989 PD75104, 75106, 75108 ORDERING INFORMATION Part Number Package Quality Grade PD75104CW-xxx 64-pin plastic shrink DIP (750 mil) Standard PD75104GF-xxx-3BE 64-pin plastic QFP (14 x 20 mm) Standard PD75106CW-xxx 64-pin plastic shrink DIP (750 mil) Standard PD75106GF-xxx-3BE 64-pin plastic QFP (14 x 20 mm) Standard PD75108CW-xxx 64-pin plastic shrink DIP (750 mil) Standard PD75108GF-xxx-3BE 64-pin plastic QFP (14 x 20 mm) Standard Remarks: xxx is ROM code number. Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 PD75104, 75106, 75108 FUNCTIONAL OUTLINE Item Specifications Number of Basic Instructions 43 Minimum Instruction Changeable in three steps: 0.95 s, 1.91 s, and 15.3 s at 4.19 MHz Execution Time ROM 8064 x 8 bits (PD75108), 6016 x 8 bits (PD75106), 4096 x 8 bits (PD75104) RAM 512 x 4 bits (PD75108), 320 x 4 bits (PD75106, 75104) Internal Memory General-Purpose Register 4 bits x 8 x 4 banks (memory mapped) Accumulator Three accumulators selectable according to the bit length of manipulated data: * 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA) I/O Port 58 port pins * CMOS input pins: 10 * CMOS I/O pins (can directly drive LEDs): 32 * Medium voltage N-ch open-drain I/O pins: 12 (can directly drive LEDs. Pull-up resistor can be connected to each bit) * Comparator input pins (4-bit accuracy): 4 Timer/Counter * 8-bit timer/event counter x 2 * 8-bit basic interval timer (can be used as watchdog timer) * 8 bits Serial Interface * LSB first/MSB first mode selectable * Two transfer modes (transfer/reception and reception only modes) Vector Interrupt External: 3, Internal: 4 Test Input External: 2 Standby * STOP and HALT modes Instruction Set * * * * Others * Power-ON reset circuit (mask option) * Bit manipulation memory (bit sequential buffer: 16 bits) Package * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm) Various bit manipulation instructions (set, reset, test, Boolean operation) 8-bit data transfer, compare, operation, increment, and decrement 1-byte relative branch instructions GETI instruction constituting 2 or 3-byte instruction with 1 byte 3 PD75104, 75106, 75108 CONTENTS 4 1. PIN CONFIGURATION (TOP VIEW) ............................................................................................... 6 2. BLOCK DIAGRAM ........................................................................................................................... 8 3. PIN FUNCTIONS .............................................................................................................................. 9 3.1 PORT PINS ............................................................................................................................................. 9 3.2 PINS OTHER THAN PORTS ................................................................................................................. 10 3.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... 11 3.4 RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... 12 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS ...................................................................... 13 4. MEMORY CONFIGURATION .......................................................................................................... 14 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 20 5.1 PORTS .................................................................................................................................................... 20 5.2 CLOCK GENERATOR CIRCUIT ............................................................................................................ 21 5.3 CLOCK OUTPUT CIRCUIT .................................................................................................................... 22 5.4 BASIC INTERVAL TIMER ..................................................................................................................... 23 5.5 TIMER/EVENT COUNTER ..................................................................................................................... 23 5.6 SERIAL INTERFACE .............................................................................................................................. 25 5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) .................................................... 27 5.8 BIT SEQUENTIAL BUFFER .... 16 BITS ............................................................................................... 28 5.9 POWER-ON FLAG (MASK OPTION) .................................................................................................... 28 6. INTERRUPT FUNCTIONS ................................................................................................................ 28 7. STANDBY FUNCTIONS .................................................................................................................. 30 8. RESET FUNCTION ........................................................................................................................... 31 9. INSTRUCTION SET ......................................................................................................................... 34 PD75104, 75106, 75108 10. APPLICATION EXAMPLES .............................................................................................................. 43 10.1 VTR SYSTEM CONTROLLER ............................................................................................................... 43 10.2 VTR CAMERA ........................................................................................................................................ 43 10.3 COMPACT DISC PLAYER ..................................................................................................................... 44 10.4 AUTOMOBILE APPLICATIONS (TRIP COMPUTER) ............................................................................ 44 10.5 PUSHBUTTON TELEPHONE ................................................................................................................ 45 10.6 DISPLAY PAGER ................................................................................................................................... 45 10.7 PLAIN PAPER COPIER (PPC) ............................................................................................................... 46 10.8 PRINTER CONTROLLER ....................................................................................................................... 46 11. MASK OPTION SELECTION ........................................................................................................... 47 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48 13. CHARACTERISTIC DATA ................................................................................................................ 57 14. PACKAGE DRAWINGS ................................................................................................................... 62 15. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 65 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PRODUCTS IN PD751XX SERIES ......... 66 APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 67 APPENDIX C. 68 RELATED DOCUMENTS .............................................................................................. 5 PD75104, 75106, 75108 1. PIN CONFIGURATION (Top View) * 64-Pin Plastic Shrink DIP (750 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PD75104CW- xxx PD75106CW- xxx PD75108CW- xxx P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 PTH00 TI0 TI1 P23 P22/PCL P21 PTO1 P20 PTO0 P03/SI P02/SO P01/SCK P00/INT4 P123 P122 P121 P120 P133 P132 P131 P130 P143 P142 P141 P140 NC V DD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 V SS P90 P91 P92 P93 P80 P81 P82 P83 P70 P71 P72 P73 P60 P61 P62 P63 X1 X2 RESET P50 P51 P52 P53 P40 P41 P42 P43 P30 P31 P32 P33 P42 P43 P30 P31 P32 P33 V DD NC P140 P141 P142 P143 P130 * 64-Pin Plastic QFP (14 x 20 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 20 21 22 23 24 25 26 27 28 29 30 31 32 P81 P80 P93 P92 P91 P90 V SS P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PD75104GF- xxx -3BE PD75106GF- xxx -3BE PD75108GF- xxx -3BE P41 P40 P53 P52 P51 P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82 6 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P131 P132 P133 P120 P121 P122 P123 P00/INT4 P01/SCK P02/SO P03/SI P20/PTO0 P21/PTO1 P22/PCL P23 TI1 TI0 PTH00 PTH01 PD75104, 75106, 75108 Pin names P00-P03 : Port 0 SCK : Serial Clock Input/Output P10-P13 : Port 1 SO : Serial Output P20-P23 : Port 2 SI : Serial Input P30-P33 : Port 3 PTO0, PTO1 : Timer Output P40-P43 : Port 4 PCL : Clock Output P50-P53 : Port 5 PTH00-PTH03 : Comparator Input P60-P63 : Port 6 INT0, INT1, INT4 : External Vector Interrupt Input P70-P73 : Port 7 INT2, INT3 : External Test Input P80-P83 : Port 8 TI0, TI1 : Timer Input P90-P93 : Port 9 X1, X2 : Clock Oscillation Pin P120-P123 : Port 12 RESET : Reset Input P130-P133 : Port 13 NC : No Connection P140-P143 : Port 14 7 8 2. PROGRAM COUNTER* INTBT TI0 CY ALU SP (8) TIMER/EVENT COUNTER #0 PTO0/P20 TIMER/EVENT COUNTER #1 PTO1/P21 INTT1 SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE ROM PROGRAM MEMORY 8064 x 8BITS : PD75108 6016 x 8BITS : PD75106 4096 x 8BITS : PD75104 DECODE AND CONTROL PORT 1 4 P10 - P13 PORT 2 4 P20 - P23 PORT 3 4 P30 - P33 PORT 4 4 P40 - P43 PORT 5 4 P50 - P53 PORT 6 4 P60 - P63 PORT 7 4 P70 - P73 PORT 8 4 P80 - P83 PORT 9 4 P90 - P93 PORT 12 4 P120 - P123 PORT 13 4 P130 - P133 PORT 14 4 P140 - P143 f XX /2 N 4 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL PCL/P22 *: 13 bits: PD75106, 75108 12 bits: PD75104 CLOCK DIVIDER CLOCK GENERATOR X1 X2 STAND BY CONTROL CPU CLOCK V DD V SS RESET PD75104, 75106, 75108 INT4/P00 PTH00-PTH03 RAM DATA MEMORY x 512 4BITS : PD75108 320 x 4BITS : PD75106, 75104 INTERRUPT CONTROL INT3/P13 P00 - P03 GENERAL REG. INTSIO INT0/P10 INT1/P11 INT2/P12 4 BANK INTT0 TI1 PORT 0 BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER PD75104, 75106, 75108 3. PIN FUNCTIONS 3.1 PORT PINS Pin Name I/O Shared with: P00 Input INT4 P01 I/O SCK Function 8-Bit I/O P02 I/O SO Input SI I/O Circuit TYPE*1 B F 4-bit input port (PORT 0) P03 At Reset Input E B x P10 INT0 P11 INT1 Input P12 4-bit input port (PORT 1) Input B 4-bit I/O port (PORT 2) Input E Input E Input E Input E Input E Input E Input E Input E Input*2 M Input*2 M Input*2 M INT2 P13 INT3 P20* 3 P21* 3 P22* 3 PTO0 PTO1 I/O PCL x P23*3 -- 4-bit programmable I/O port (PORT 3) P30-P33*3 I/O -- Can be specified for input or output bitwise. P40-P43*3 I/O -- 4-bit I/O port (PORT 4) o P50-P53*3 I/O -- P60-P63*3 I/O -- 4-bit I/O port (PORT 5) 4-bit programmable I/O port (PORT 6) Can be specified for input or output bitwise. P70-P73*3 I/O P80-P83* 3 I/O P90-P93* 3 o 4-bit I/O port (PORT 7) -- 4-bit I/O port (PORT 8) o I/O -- 4-bit I/O port (PORT 9) 4-bit N-ch open-drain I/O port (PORT 12) Built-in pull-up resistors can be specified in bit P120-P123* 3 I/O -- units by mask option. Open-drain withstanding voltage: 12 V o 4-bit N-ch open-drain I/O port (PORT 13) P130-P133*3 Built-in pull-up resistors can be specified in bit I/O -- units by mask option. Open-drain withstanding voltage: 12 V 4-bit N-ch open-drain I/O port (PORT 14) P140-P143*3 Built-in pull-up resistors can be specified in bit I/O -- - units by mask option. Open-drain withstanding voltage: 12 V *1: Circles indicate Schmitt trigger input pins. 2: With drain open: high impedance With pull-up resistor connected: high level 3: Can directly drive LEDs. 9 PD75104, 75106, 75108 3.2 PINS OTHER THAN PORTS Pin Name I/O Shared with: PTH00-PTH03 Input -- TI0 At Reset I/O Circuit TYPE*1 -- N -- B Outputs for timer/event counter Input E Function 4-bit variable threshold voltage analog input port External event pulse inputs for timer/event counter. Input -- Also serves as edge-detected vector interrupt input. TI1 1-bit input also possible. PTO0 P20 I/O PTO1 P21 SCK I/O P01 Serial clock I/O Input F SO I/O P02 Serial data output Input E SI Input P03 Serial data input Input B INT4 Input P00 Input B Input B Edge-detected testable inputs (rising edge detected) Input B Clock output Input E -- -- Edge-detected vectored interrupt input (both rising and falling edges detected) INT0 P10 Edge-detected vectored interrupt inputs (valid P11 edge selectable) Input INT1 INT2 P12 Input INT3 PCL P13 I/O P22 Crystal/ceramic system clock oscillator connections. X1, X2 -- -- Input external clock to X1, and signal in reverse phase with X1 to X2. Input -- System reset input (low level active type) -- B -- -- No Connection -- -- VDD -- -- Positive power supply -- -- VSS -- -- GND -- -- RESET NC* 2 *1: Circles indicate Schmitt trigger input pins. 2: Connect the NC pin directly to the VDD pin when PD75P108B and a printed circuit board are shared. 10 PD75104, 75106, 75108 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the PD75108. TYPE E TYPE A VDD data P-ch IN/OUT Type D IN output disable N-ch Type A Input buffer of CMOS standard I/O circuit consisting of Type D push-pull output circuit and Type A input buffer TYPE F TYPE B data IN/OUT IN Type D output disable Type B Schmitt trigger input with hysteresis characteristics TYPE D I/O circuit consisting of Type D push-pull output and Type B Schmitt trigger input TYPE M V DD P.U.R. (mask option) IN/OUT VDD data P-ch OUT output disable N-ch Push - pull output that can be set in a output high- impedance state (both P -ch and N -ch are off) N-ch (+12 V withstand) data output disable Medium-voltage input buffer (+12 V withstand) P.U.R.: Pull-Up Resistor 11 PD75104, 75106, 75108 TYPE N Comparator IN + - V REF (threshold voltage) 3.4 RECOMMENDED PROCESSING OF UNUSED PINS Pin PTH00-PTH03 TI0 Recommended connections Connect to V SS or VDD TI1 P00 Connect to V SS P01-P03 Connect to V SS or VDD P10-P13 Connect to V SS P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 P120-P123 P130-P133 Input: Connect to VSS or VDD Output: Open P140-P143 RESET*1 Connect to V DD NC*2 Open *1: Connect this pin to the VDD pin only when a power-ON reset circuit is provided as a mask option. 2: Connect the NC pin to the VDD pin when PD75P108 and a printed circuit board are shared. 12 PD75104, 75106, 75108 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the PD75108 are tested (solely used for IC tests), is provided to the P00/INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the PD75108 is put into test mode. Therefore, even when the PD75108 is in normal operation, if noise exceeding the VDD is input into any of these pins, the PD75108 will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. * Connect a diode across P00/INT4 and RESET , and VDD . * Connect a capacitor across P00/INT4 and RESET , and VDD . VDD VDD VDD VDD P00/INT4, RESET P00/INT4, RESET 13 PD75104, 75106, 75108 4. MEMORY CONFIGURATION * Program memory (ROM) ... 8064 x 8 bits (0000H-1F7FH) : PD75108 ... 6016 x 8 bits (0000H-177FH) : PD75106 ... 4096 x 8 bits (0000H-0FFFH) : PD75104 * 0000H, 0001H : Vector table to which address from which program is started is written after reset * 0002H-000BH: Vector table to which address from which program is started is written after interrupt * 0020H-007FH : Table area referenced by GETI instruction * Data memory (RAM) * Data area ....512 x 4 bits (000H-1FFH) : PD75108 320 x 4 bits (000H-13FH) : PD75106, 75104 * Peripheral hardware area .... 128 x 4 bits (F80H-FFFH) 14 PD75104, 75106, 75108 (a) PD75108 Address 7 0000H 6 MBE RBE 5 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 INT0/INT1 start address (upper 5 bits) INT0/INT1 start address (lower 8 bits) 0006H MBE RBE 0 INTSIO start address (upper 5 bits) INTSIO start address (lower 8 bits) 0008H MBE RBE 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 000AH MBE RBE 0 CALLF ! faddr instruction entry address INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) CALL ! addr instruction subroutine entry address BRCB ! caddr BR ! addr instruction instruction branch branch address address 0020H BR $addr instruction relational branch address (-15 to -1, +2 to +16) GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH Fig. 4-1 Program Memory Map (1/3) Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. 15 PD75104, 75106, 75108 (b) PD75106 Address 7 0000H 6 MBE RBE 5 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 INT0/INT1 start address (upper 5 bits) INT0/INT1 start address (lower 8 bits) 0006H MBE RBE 0 INTSIO start address (upper 5 bits) INTSIO start address (lower 8 bits) 0008H MBE RBE 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 000AH MBE RBE 0 CALLF ! faddr instruction entry address INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) CALL ! addr instruction subroutine entry address BRCB ! caddr BR ! addr instruction instruction branch branch address address 0020H BR $addr instruction relational branch address (-15 to +16) GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 177FH Fig. 4-1 Program Memory Map (2/3) Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. 16 PD75104, 75106, 75108 (c) PD75106 Address 7 000H 6 MBE RBE 5 4 0 0 0 Internal reset start address (upper 4 bits) Internal reset start address (lower 8 bits) 002H MBE RBE 0 0 INTBT/INT4 start address (upper 4 bits) INTBT/INT4 start address (lower 8 bits) 004H MBE RBE 0 0 INT0/INT1 start address (upper 4 bits) INT0/INT1 start address (lower 8 bits) 006H MBE RBE 0 0 INTSIO start address (upper 4 bits) INTSIO start address (lower 8 bits) 008H MBE RBE 0 0 INTT0 start address (upper 4 bits) INTT0 start address (lower 8 bits) 00AH MBE RBE 0 0 CALLF ! faddr instruction entry address BRCB ! caddr instruction branch address INTT1 start address (upper 4 bits) INTT1 start address (lower 8 bits) CALL ! addr instruction subroutine entry address Branch destination address and subroutine entry address for GETI instruction 020H GETI instruction reference table BR $addr instruction relational branch address (-15 to +16) 07FH 080H 7FFH 800H FFFH Fig. 4-1 Program Memory Map (3/3) Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. 17 PD75104, 75106, 75108 (a) PD75108 Data memory General-purpose register area 000H Memory bank (32 x 4) 01FH Stack area Bank 0 256x 4 Data memory Static RAM (512 x 4) 0FFH 100H 256x 4 Bank 1 1FFH Not provided F80H 128x 4 Peripheral hardware area FFFH Fig. 4-2 Data Memory Map(1/2) 18 Bank 15 PD75104, 75106, 75108 (b) PD75106, 75104 Data memory General-purpose register area 000H Memory bank (32 x 4) 01FH Stack area Bank 0 Generalpurpose Static RAM (320 x 4) 256x 4 0FFH 100H 64 x 4 Bank 1 13FH Not provided F80H 128x 4 Peripheral hardware area Bank 15 FFFH Fig. 4-2 Data Memory Map(2/2) 19 PD75104, 75106, 75108 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 3 kinds: * CMOS input (PORT0, 1) : 8 * CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32 * N-ch open-drain input/output (PORT12, 13, 14) : 12 Total : 52 Table 5-1 Port Function Port (Symbol) PORT0 Function 4-bit input PORT1 PORT3 Operation and Features Can always be read or tested regardless of operation mode of shared pin Can be set in input or output mode bitwise Remarks Shared with SI, SO, SCK, and INT0 to 4 pins -- PORT6 PORT2 PORT4 4-bit I/O* PORT5 PORT7 Can be set in input or output mode in units of 4 bits. Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs to input or output 8-bit data Port 2 pins are shared with PTO0, PTO1, and PCL pins Can be set in input or output mode in units of 4 bits. Ports 12 and 13 can be used in pairs to input or output 8-bit data Each bit can be connected to pull-up resistor by mask option PORT8 PORT9 PORT12 PORT13 4-bit I/O* (N-ch open- drain. 12V) PORT14 *: Can directly drive LED. 20 PD75104, 75106, 75108 5.2 CLOCK GENERATOR CIRCUIT The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and peripheral hardware. In addition, this circuit can change the instruction execution time. * 0.95 s/1.91 s/15.3 s (operating at 4.19 MHz) * Basic interval timer (BT) * Clock output circuit * Timer/event counter * Serial interface X1 1/8 to 1/4096 System clock generator circuit f XX or Frequency civider fX 1/2 1/16 X2 Oscillation stops Selector Frequency divider 1/4 * CPU * Clock output circuit PCC Internal bus PCC0 PCC1 4 HALT F/F PCC2 S HALT* PCC3 STOP* R Clears PCC2, PCC3 Q STOP F/F Q Wait release signal from BT S RES (internal reset) signal R Standby release signal from interrupt control circuit *: Execution of the instruction Remarks 1: f XX = Crystal/ceramic oscillator 2: f X = External clock frequency 3: PCC: Processor clock control register 4: One clock cycle (t CY) of is one machine cycle of an instruction. For tCY, refer to AC characteristics in 12. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram 21 PD75104, 75106, 75108 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output clock pulses to the remote control output, peripheral LSIs, etc. * Clock output (PCL) : , 524, 262 kHz (operating at 4.19 MHz) From the clock generator f XX/23 Output buffer Selector PCL/P22 f XX/24 PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 output latch 4 Internal bus Fig. 5-2 Clock Output Circuit Configuration 22 Bit 2 of PMGB Port 2 input/ output mode specification bit PD75104, 75106, 75108 5.4 BASIC INTERVAL TIMER The basic interval timer has these functions: * Interval timer operation which generates a reference time interrupt * Watchdog timer application which detects a program runaway * Selects the wait time for releasing the standby mode and counts the wait time * Reads out the count value From the clock generator Clear Clear fXX/25 fXX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fXX/29 BT f XX/212 3 BTM3 SET1* BT interrupt request flag BTM2 Vector interrupt request IRQBT signal Wait release signal for standby release BTM1 BTM0 BTM 8 4 Internal bus Remarks : *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration 5.5 TIMER/EVENT COUNTER PD75108 contains two channels of timer/event counters. These two channels are almost identical in terms of configuration and function except the count pulse (CP) that can be selected and the function to supply clocks to the serial interface. The functions of the timer/event counter include: * Programmable interval timer operation * Output of square wave at an arbitrary frequency to PTOn pin * Event counter operation * Input of TIn pin signal as external interrupt input signal * Dividing TIn pin input by N to output to PTOn pin (frequency divider operation) * Supply of serial shift clock to serial interface circuit (channel 0 only) * Reading counting status 23 24 Internal bus 8 SET1* TMn 8 8 TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 TMODn TOEn To enable flag Modulo register (8) TOFn TIn 8 Coincidence TOUT F/F Comparator (8) 8 Input buffer TOn PORT2.n Bit 2 of PGMB P2n Port 2 output I/O latch mode To serial interface (channel 0 only) P2n/PTOn To selector Output buffer Tn TIn From clock generator circuit CP MPX Edge detector circuit Count register (8) Clear TMn1 Timer operation start Remarks: * indicates the instruction execution. Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1) TMn0 IRQTn clear signal PD75104, 75106, 75108 RES IRQTn set signal PD75104, 75106, 75108 5.6 SERIAL INTERFACE The PD75108 is equipped with clock 8-bit serial interface that operates in the following two modes: * Operation stop mode * Three-line serial I/O mode 25 26 Internal bus 8 SET1* 8 8 SIO0 SIO7 SIOM SIO P03/SI Shift register (8) SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 P02/SO Serial clock counter (3) Overflow IRQSIO set signal Clear IRQSIO clear signal Serial start P01/SCK R S f XX /2 4 MPX f XX /2 10 TOF0 (from timer channel 0) *: "SET1" indicates execution of the instruction. Fig. 5-5 Serial Interface Block Diagram PD75104, 75106, 75108 Q PD75104, 75106, 75108 5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) PD75108 is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold voltage is programmable. This programmable threshold port is configured as shown in Figure 5-6. The threshold voltage (VREF) can be changed in 16 steps (VDD x 0.5/16 - VDD x 15.5/16), and analog signals can be directly input. When VREF is set to VDD x 7.5/16, the programmable threshold port can also be used as a digital signal input port. Input buffer + PTH00 Programmable threshold port input latch (4) - + PTH01 - + PTH02 - PTH03 - Operates /stops Internal bus + PTH0 V DD PTHM7 1 2R PTHM6 R PTHM5 R MPX V REF PTHM4 8 PTHM3 PTHM2 1 2R 4 PTHM1 PTHM0 PTHM Fig. 5-6 Programmable Threshold Port Configuration 27 PD75104, 75106, 75108 5.8 BIT SEQUENTIAL BUFFER .... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. FC3H Address bit 3 Symbol L register 2 FC2H 1 0 3 BSB3 L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-7 Bit Sequential Buffer Format 5.9 POWER-ON FLAG (MASK OPTION) The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal has been generated (see Fig. 8-1). The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation instruction. However, it cannot be set by the SET1 instruction. 6. INTERRUPT FUNCTIONS The PD75108 has 7 different interrupt sources and can perform multiplexed interrupt processing with priority assigned. In addition to that, the PD75108 is also provided with two types of edge detection testable inputs. The interrupt control circuit of the PD75108 has these functions: * Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * The interrupt start address can be arbitrarily set. * Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS). * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). * Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 28 Internal bus 2 2 IM1 IM0 9 INT BT Both edge detection circuit Edge detection circuit Edge detection circuit INT4 /P00 INT0 /P10 INT1 /P11 INT3 /P13 IPS IST Decoder IRQBT IRQ4 IRQ0 IRQ1 INTSIO IRQSIO INTT0 IRQT0 INTT1 IRQT1 Rising edge detection circuit Falling edge detection circuit IME 2 Priority control circuit Vector table address generator IRQ2 Standby release signal IRQ3 Interrupt request flag Fig. 6-1 Interrupt Control Block Diagram 29 PD75104, 75106, 75108 INT2 /P12 Interrupt enable flag (IE xxx ) 4 PD75104, 75106, 75108 7. STANDBY FUNCTIONS The PD75108 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption of the microcomputer chip while waiting for program execution. Table 7-1 Each Status in Standby Mode STOP Mode Setting Instruction STOP instruction HALT instruction Clock Generator circuit Clock oscillation stops Only CPU clock is stopped Basic Interval Timer Stops Operates (sets IRQBT at reference time intervals) Operates only when input of external Serial Interface Operation Status SCK or output of TO0 is selected as Operates when serial clock other than is specified serial clock (where external TI0 is input to timer/event counter 0) Timer/Event Counter Operates only when TIn pin input signal is specified as count clock Operates Clock output circuit Stops Operates when clock other than CPU clock is used CPU Stops Release Signal 30 HALT Mode Stops Interrupt request signal enabled by interrupt enable flag, or RESET input PD75104, 75106, 75108 8. RESET FUNCTION The reset ( RES ) signal generator circuit is configured as shown in Figure 8-1. RESET Internal reset signal (RES) Power-ON reset generator circuit SWA Power-ON flag (PONF) Execution of bit manipulation instruction* Internal bus SWB *: PONF cannot be set to 1 by SET1 instruction. Fig. 8-1 Reset Signal Generator Circuit The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK OPTION SELECTION.) The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs. 8-2 and 8-3, respectively. Supply voltage 0V Wait* (approx. 31.3 ms: 4.19 MHz) Internal reset signal (RES) HALT mode Operation mode Internal reset operation *: The wait time does not include the time required after the RES signal has been generated until the oscillation starts. Fig. 8-2 Reset by Power-ON Reset Circuit 31 PD75104, 75106, 75108 Wait* (31.3 ms: 4.19 MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation *: The wait time does not include the time required after the RES signal has been generated until the oscillation starts. Fig. 8-3 Reset by RESET Signal The status of each internal hardware device after the reset operation has been performed is shown in Table 81. 32 PD75104, 75106, 75108 Table 8-1 Hardware Device Status After Reset Hardware Program Counter (PC) Carry Flag (CY) Skip Flags (SK0-SK2) PSW RESET input during standby mode Power-ON Reset or RESET Input during Operation Lower 4 bits of program memory address 000H are set to PC12-8,* 1 and contents of address 001H are set to PC7-0. Lower 4 bits of program memory address 000H are set to PC12-8,* 1 and contents of address 001H are set to PC7-0. Retained Undefined 0 0 Interrupt Status Flags (IST0, 1) 0 0 Bank Enable Flags (MBE, RBE) Bit 6 of program memory address 000H is set in RBE, and bit 7 is set in MBE. Bit 6 of program memory address 000H is set in RBE, and bit 7 is set in MBE. Undefined Undefined 2 Undefined Stack Pointer (SP) Data Memory (RAM) Retained* General-Purpose Registers (X,A,H,L,D,E,B,C) Bank Selector Registers (MBS, RBS) Basic interval timer Counter (BT) Mode Register (BTM) Counter (Tn) Timer/Event Counter (n = 0, 1) Modulo Register (TMODn) Mode Register (TMn) TOEn, TOFn Serial Interface Clock Generator Circuit, Clock Output Circuit Shift Register (SIO) Undefined Undefined 0 0 0 0 FFH FFH 0 0 0, 0 0, 0 Undefined 0 0 Processor Clock Control Register (PCC) 0 0 Clock Output Mode Register (CLOM) 0 0 Reset (0) Reset (0) 0 0 Priority Selector Register (IPS) 0 0 INT0, 1 Mode Registers (IM0, IM1) 0, 0 0, 0 Output Buffer OFF OFF Output Latch Cleared (0) Cleared (0) 0 0 Undefined Undefined 0 0 Retained 1 or undefined*2 0 0 I/O Mode Registers (PMGA, PMGB, PMGC) PTH00-PTH03 Input Latches Analog Port 0, 0 Retained Interrupt Enable Flags (IExxx) Digital Port Undefined 0, 0 Mode Register (SIOM) Interrupt Request Rlags (IRQxxx) Interrupt Retained Mode Register (PTHM) Power-ON Flag (PONF) Bit Sequential Buffer (BSB0-BSB3) *1: PC11-8 for PD75104 2: Power-ON reset: 1 RESET input during operation: undefined Note: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input. 33 PD75104, 75106, 75108 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to PD751XX Series User`s Manual (IEM-922)). However, fmem and pmem restricts the label that can be described. Representation Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' rpa rpa1 HL, HL+, HL-, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label* 2-bit immediate data or label fmem pmem FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr PD75104 0000H to 0FFFH immediate data or label PD75106 0000H to 177FH immediate data or label PD75108 0000H to 1F7FH immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx RBn MBn PORT0 - PORT9, PORT12 - PORT14 IEBT, IESIO, IET0, IET1, IE0 - IE4 RB0 - RB3 MB0, MB1, MB15 *: Only even address can be described as mem for 8-bit data processing. 34 PD75104, 75106, 75108 (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator XA' : Expansion register pair (XA') BC' : Expansion register pair (BC') DE' : Expansion register pair (DE') HL' : Expansion register pair (HL') PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 - 9, 12 - 14) IME : Interrupt mask enable flag IPS : Interrupt priority selection register IExxx : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC . : Processor clock control register (xx) : Contents addressed by xx xxH : Hexadecimal data : Delimiter of address and bit 35 PD75104, 75106, 75108 (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 PD75104 addr = 0000H-0FFFH PD75106 addr = 0000H-177FH PD75108 addr = 0000H-1F7FH *7 *8 Data memory addressing addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 Program memory PD75104 caddr = 0000H-0FFFH (PC 11 = 0) addressing PD75106 caddr = 0000H-0FFFH (PC 12 = 0) or 1000H-177FH (PC12 = 1) PD75108 caddr = 0000H-0FFFH (PC 12 = 0) or 1000H-1F7FH (PC12 = 1) *9 faddr = 000H-7FFH *10 taddr = 020H-07FH Remarks * MB indicates memory bank that can be accessed. * In *2, MB = 0 regardless of MBE and MBS. * In *4 and *5, MB = 15 regardless of MBE and MBS. * *6 to *10 indicate areas that can be addressed. (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: * When no instruction is skipped ........................................................................ S=0 * When 1-byte or 2-byte instruction is skipped ................................................. S=1 * When 3-byte instruction (BR ! adder or CALL ! adder) is skipped .............. S=2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock , (= tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 36 PD75104, 75106, 75108 Instructions Mnemonics Transfer MOV XCH Table MOVT Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions A, #n4 1 1 A n4 reg1, #n4 2 2 reg1 n4 XA, #n8 2 2 XA n8 String effect A HL, #n8 2 2 HL n8 String effect B rp2, #n8 2 2 rp2 n8 A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL- 1 2+S A (HL), then L L-1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 @HL, A 1 1 (HL) A *1 @HL, XA 2 2 (HL) XA *1 A,mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 mem, A 2 2 (mem) A *3 mem, XA 2 2 (mem) XA *3 A, reg 2 2 A reg XA, rp' 2 2 XA rp' reg1, A 2 2 reg1 A rp'1, XA 2 2 rp'1 XA A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL- 1 2+S A (HL), then L L-1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 A, reg1 1 1 A reg1 XA, rp' 2 2 XA rp' XA, @PCDE 1 3 String effect A * PD75104 Refer- XA (PC11-8+DE)ROM ence * PD75106, 75108 XA (PC12-8+DE)ROM XA, @PCXA 1 3 * PD75104 XA (PC11-8+XA)ROM * PD75106, 75108 XA (PC12-8+XA)ROM 37 PD75104, 75106, 75108 Instructions Mnemonics Operand Bytes Machine Cycles Bit MOV1 CY,fmem.bit 2 2 CY (fmem.bit) *4 CY,pmem.@L 2 2 CY (pmem7-2+L3-2.bit(L1-0)) *5 CY,@H+mem. 2 2 CY (H+mem3-0.bit) *1 transfer Operation Addressing Area Skip Conditions bit fmem.bit,CY 2 2 (fmem.bit) CY *4 pmem.@L,CY 2 2 (pmem7-2+L 3-2.bit(L1-0)) CY *5 @H+mem.bit, 2 2 (H+mem3-0.bit) CY *1 A, #n4 1 1+S A A+n4 carry XA, #n8 2 2+S XA XA+n8 carry CY Arith- ADDS metic opera- A, @HL 1 1+S A A+(HL) tion XA, rp' 2 2+S XA XA+rp' carry rp'1, XA 2 2+S rp'1 rp'1+XA carry A, @HL 1 1 A, CY A+(HL)+CY XA, rp' 2 2 XA, CY XA+rp'+CY rp'1, XA 2 2 A, @HL 1 1+S A A-(HL). XA, rp' 2 2+S XA XA-rp' borrow rp'1, XA 2 2+S rp'1 rp'1-XA borrow ADDC SUBS SUBC carry *1 rp'1,CY rp'1+XA+CY A, @HL 1 1 A, CY A-(HL)-CY XA, rp' 2 2 XA, CY XA-rp'-CY rp'1, XA 2 2 rp'1,CY rp'1-XA-CY A, #n4 2 2 A, @HL 1 1 XA, rp' 2 2 rp'1, XA 2 2 A, #n4 2 2 A, @HL 1 1 XA, rp' 2 2 rp'1, XA 2 2 A, #n4 2 2 A, @HL 1 1 XA, rp' 2 2 *1 borrow *1 rp'1, XA 2 2 n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA Accumulator RORC A 1 1 CY A0, A3 CY, An-1 An Manipulation NOT A 2 2 AA INCS reg 1 1+S reg reg+1 reg = 0 ment/ rp1 1 1+S rp1 rp1+1 rp1 = 00H decre- @HL 2 2+S (HL) (HL)+1 *1 (HL) = 0 ment mem 2 2+S (mem) (mem)+1 *3 (mem) = 0 reg 1 1+S reg reg-1 reg = FH rp' 2 2+S rp' rp'-1 rp' = FFH AND OR XOR Incre- DECS 38 *1 AA *1 *1 *1 PD75104, 75106, 75108 Instructions Mnemonics Com- SKE pare Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' Carry SET1 CY 1 1 CY 1 flag CLR1 CY 1 1 CY 0 Manipu- SKT CY 1 1+S lation CY 1 1 CY CY mem.bit 2 2 (mem.bit) 1 *3 Bit fmem.bit 2 2 (fmem.bit) 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L 3-2.bit(L1-0)) 1 *5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) 1 *1 mem.bit 2 2 (mem.bit) 0 *3 fmem.bit 2 2 (fmem.bit) 0 *4 pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0 )) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 2 2+S Skip if (pmem 7-2+L 3-2.bit *5 (pmem.@L) = 1 *1 (@H+mem.bit) = 1 NOT1 Memory/ SET1 CLR1 SKT SKF SKTCLR fmem.bit pmem.@L Skip if CY = 1 CY = 1 (L 1-0)) = 1 and clear AND1 OR1 XOR1 @H+mem.bit 2 2+S Skip if (H+mem 3-0.bit) = 1 and clear CY,fmem.bit 2 2 CY,pmem.@L 2 2 CY,@H+mem.bit 2 2 CY,fmem.bit 2 2 (fmem.bit) CY CY (pmem 7-2+L 3-2.bit(L1-0)) CY CY (H+mem 3-0.bit) CY CY (fmem.bit) CY,pmem.@L 2 2 CY CY (pmem7-2+L3-2.bit (L 1-0)) CY,@H+mem.bit 2 2 CY CY CY,fmem.bit 2 CY,pmem.@L CY,@H+mem.bit CY CY *4 *5 *1 *4 *5 2 (H+mem 3-0.bit) CY CY (fmem.bit) *4 2 2 CY CY (pmem 7-2+L 3-2.bit (L 1-0)) *5 2 2 CY CY (H+mem 3-0.bit) *1 *1 39 PD75104, 75106, 75108 Instructions Mnemonics Branch BR Operand addr Machine Bytes Cycles -- Addressing Area Operation * PD75104 -- *6 PC11-0 addr The most suitable instruction is selectable from among BRCB ! caddr, and BR $ addr depending on the assembler. * PD75106, 75108 PC12-0 addr The most suitable instruction is selectable from among BR ! addr, BRCB ! caddr, and BR $ addr depending on the assembler. ! addr 3 3 * PD75106, 75108 *6 PC12-0 addr $ addr 1 2 * PD75104 *7 PC11-0 addr * PD75106, 75108 PC12-0 addr BRCB ! caddr 2 2 * PD75104 *8 PC11-0 caddr 11-0 * PD75106, 75108 PC12-0 PC12 + caddr11-0 BR PCDE 2 3 * PD75104 PC11-0 PC11-8 + DE * PD75106, 75108 PC12-0 PC12-8 + DE PCXA 2 3 * PD75104 PC11-0 PC11-8 + XA * PD75106, 75108 PC12-0 PC12-8 + XA Subrou- CALL ! addr 3 3 * PD75104 tine/ (SP-4)(SP-1)(SP-2) PC11-0 Stack (SP-3) MBE, RBE, 0, 0 Control PC11-0 addr, SP SP-4 * PD75106, 75108 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 addr, SP SP-4 40 *6 Skip Conditions PD75104, 75106, 75108 Instructions Mnemonics Subrou- CALLF Operand ! faddr Machine Bytes Cycles 2 2 Operation * PD75104 tine/ (SP-4)(SP-1)(SP-2) PC11-0 Stack (SP-3) MBE, RBE, 0, 0 Control PC11-0 0, faddr, SP SP-4 (Cont`d) Addressing Area Skip Conditions *9 * PD75106, 75108 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 00, faddr, SP SP-4 RET 1 3 * PD75104 MBE, RBE, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4 * PD75106, 75108 MBE, RBE, x, PC 12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4 RETS 1 3+S * PD75104 Unconditioned MBE, RBE, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally * PD75106, 75108 MBE, RBE, x, PC 12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally RETI 1 3 * PD75104 MBE, RBE, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 * PD75106, 75108 MBE, RBE, x, PC 12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 PUSH rp 1 1 BS 2 2 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 POP rp 1 1 BS 2 2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 41 PD75104, 75106, 75108 Instructions Mnemonics Inter- EI rupt Control I/O Operand 2 IME (IPS.3) 1 2 2 IExxx 1 2 2 IME (IPS.3) 0 IExxx 2 2 IExxx 0 A, PORTn 2 2 A PORTn XA, PORTn 2 2 XA PORTn+1,PORTn (n = 4, 6, 8, 12) PORTn, A 2 2 PORTn A PORTn, XA 2 2 PORTn+1 , PORTn XA(n = 4, 6, 8, 12) DI OUT* Operation 2 IExxx IN* Machine Bytes Cycles (n = 2-9, 12-14) HALT 2 2 Set HALT Mode (PCC.2 1) Control STOP 2 2 Set STOP Mode (PCC.3 1) NOP 1 1 No Operation RBn 2 2 RBS n (n = 0-3) MBn 2 2 MBS n (n = 0, 1, 15) taddr 1 3 SEL GETI Skip Conditions (n = 0-9, 12-14) CPU Special Addressing Area * PD75104 *10 * Where TBR instruction, PC11-0 (taddr)3-0+(taddr+1) ......................................................... * Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr)3-0+(taddr+1) SP SP-4 ......................................................... * Except for TBR and TCALL ............................. Depends on instructions, referenced Instruction execution of instruction (taddr)(taddr+1) * PD75106, 75108 * Where TBR instruction, PC12-0 (taddr)4-0+(taddr+1) ......................................................... * Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0 (taddr)4-0+(taddr+1) SP SP-4 ......................................................... * Except for TBR and TCALL ............................. Depends on instructions, referenced Instruction execution of instruction (taddr)(taddr+1) *: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition. 42 PD75104, 75106, 75108 10. APPLICATION EXAMPLES 10.1 VTR SYSTEM CONTROLLER Remote controller signal receiver Operation mode LED indicator PD75108 Highcurrent output Key matrix System controller/ tape counter/ remote controller/ remaining tape computation INT Take-up reel pulse INT Servo system control circuit Supply reel pulse Sensor circuit Exposure sensor Tape start/end sensor Comparator input Motor driver circuit, etc. INT SIO On-screen display controller MNOS PD6252 PD6253 PD6254 PD752 xx timer/tuner/OSD 12 V PWM output Audio video system control circuit 10.2 FIP Tuner VTR CAMERA PD75108 Highcurrent output Operation mode LED indicator Key matrix (including message input) System control/ editing function Reel pulse INT Servo system control circuit Battery sensor Comparator input Sensor circuit Exposure sensor Tape start/end sensor Motor plunger driver circuit, etc. Powerdown detector INT On-screen display controller 12 V Audio video system control circuit 43 PD75104, 75106, 75108 10.3 COMPACT DISC PLAYER PD75108 Servo control IC Key matrix SIO Highcurrent output Loading control circuit LED indication Remote controller signal receiver 10.4 INT AUTOMOBILE APPLICATIONS (TRIP COMPUTER) PD75108 Vehicle speed detection Number of revolutions detection Fuel comsumption INT0 INT1 SIO TI Key position Gear position Key input Mode select Numerical input 44 TO Display driver PD6300 PD6323 PD6332 Buzzer Clock Alarm Average speed Arrival time, etc. PD75104, 75106, 75108 10.5 PUSHBUTTON TELEPHONE Transmitter/ receiver Transmitter/ receiver/ speaker selector Hook switch Highcurrent output Communication circuit Speaker amplifier Speaker Microphone amplifier Microphone MPX LED indicator Call sound TO To main equipment Filter PD75108 SIO PD7228G LCD controller/ driver Key matrix LCD indicator Data receiver circuit Data transmitter circuit 10.6 DISPLAY PAGER PD75108 Filter INT RAM PD4464 Code ROM Switch Highcurrent output TO Piezoelectric buzzer LED indicator Battery check Comparator input SIO LCD controller/ driver PD7228/7229 LCD indicator 45 PD75104, 75106, 75108 10.7 PLAIN PAPER COPIER (PPC) PD75108 Highcurrent output 12 V Motor/relay driver circuit LED indicator Switch Key matrix TO Piezoelectric buzzer Sensor circuit, heater temperature, toner drum pressure, etc. Comparator input 10.8 PRINTER CONTROLLER PD75108 Host machine 12 V PD0 to PD7 STRB INT Motor driver control circuit BUSY TxD SI Dot matrix head driver circuit High current LED Key matrix TO Piezoelectric buzzer 46 PD75104, 75106, 75108 11. MASK OPTION SELECTION PD75108 has the following mask options. Options to be built in can be selected. (1) Pin Pin Mask Option P120 - P123 P130 - P133 Pull-down resistor can be built in bitwise. P140 - P143 (2) Power-ON reset generation circuit, power-ON flag (PONF) One from the following three ways can be selected. Switching Selection (Refer to Fig. 8-1.) Power-On Reset Generation Circuit Power-On Flag (PONF) Internal Reset Signal (RES) SWA SWB ON ON Provided Provided Generates automatically ON OFF Provided Provided Not generates autoamtically OFF OFF Not provided Not provided -- 47 PD75104, 75106, 75108 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25C) Parameter Supply Voltage Symbol Ratings VDD VI1 Input Voltage Conditions VI2* 1 Other than ports 12, 13, 14 Ports 12 to 14 w/pull-up resistor Open drain Output Voltage VO High-Level Output Current IOH Low-Level Output IOL*2 Unit -0.3 to +7.0 V -0.3 to V DD+0.3 V -0.3 to V DD+0.3 -0.3 to +13 V V -0.3 to V DD+0.3 V 1 pin -15 mA All pins -30 mA 1 pin Current Peak 30 mA rms 15 mA Total of ports 0, 2 to 4, 12 to 14 Peak Total of ports 5 to 9 100 mA rms 60 mA Peak 100 mA 60 mA Operating Temperature Topt rms -40 to +85 C Storage Temperature Tstg -65 to +150 C *1: The power supply impedance (pull-up resistance) must be 50 k or higher when a voltage higher than 10 V is applied to ports 12, 13, and 14. 2: rms = Peak value x Duty 48 PD75104, 75106, 75108 OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, V DD = 2.7 to 6.0 V) Recommended Constants Oscillator Ceramic Item Oscillation frequency(fXX)* 1 X1 X2 C1 C2 Crystal Conditions VDD = Oscillation voltage range X2 C1 TYP. MAX. 5.0 * 2.0 Oscillation stabiliza- After VDD come to tion time*2 MIN. of oscillation voltage range Oscillation frequency (fXX)* 1 X1 MIN. 3 4 2.0 4.19 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 5.0 * Unit MHz ms 3 MHz 10 ms 30 ms C2 External Clock X1 input frequency (f X)*1 X1 X2 PD74HCU04 X1 input high-, low-level widths (t XH, t XL) 2.0 5.0 *3 100 250 MHz ns *1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has come to MIN. of oscillation volrage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. Note: When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the osccillator circuit at the same potential as VSS . Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 49 PD75104, 75106, 75108 RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS RECOMMENDED CERAMIC OSCILLATORS Manufacturer Product Name External Oscillation Capacitance (pF) Voltage Range (V) C1 C2 MIN. MAX. CSA 2.00MG 30 30 2.7 6.0 Murata Mfg. CSA 4.19MG 30 30 3.0 6.0 Co., Ltd. CSA 4.19MGU 30 30 2.7 6.0 CST 4.19T Provided Provided 3.0 6.0 KBR-2.0MS 100 100 3.0 6.0 Kyoto Ceramic KBR-4.0MS 33 33 3.0 6.0 Co., Ltd. KBR-4.19MS 33 33 3.0 6.0 KBR-4.9152M 33 33 3.0 6.0 RECOMMENDED CRYSTAL OSCILLATOR Manufacturer Kinseki 50 Product Name HC-49/U External Capacitance (pF) Oscillation Voltage Range (V) C1 C2 MIN. MAX. 22 22 2.7 6.0 PD75104, 75106, 75108 DC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V) Item Symbol High-Level Input Voltage Low-Level Input Voltage Conditions MIN. Low-Level Output Voltage 0.7VDD VDD V VIH2 Ports 0, 1, TI0, 1, RESET 0.8 V DD VDD V VIH3 Ports 12 to 14 Pull-up resistor 0.7 VDD VDD V Open drain 0.7 VDD 12 V VDD-0.5 VDD V VIH4 X1, X2 VIL1 Other than below 0 0.3 VDD V VIL2 Ports 0, 1, TI0, 1, RESET 0 0.2 V DD V VIL3 X1, X2 0 0.4 V VOH IOH = -100 A VDD-1.0 V VDD-0.5 V VDD = Ports 0, 2 to 9, I OL = 15 mA 0.35 2.0 V 4.5 to 6.0 V Ports 12 to 14, IOL = 10 mA 0.35 2.0 V 0.4 V 0.5 V Other than below 3 A X1,X2 20 A Ports 12 to 14 (open drain) 20 A Other than X1, X2 -3 A -20 A 3 A 20 A -3 A 70 k 80 k VOL IOL = 400 A Current ILIH1 VIN = VDD ILIH2 ILIH3 Low-Level Unit Other than below VDD = 4.5 to 6.0 V, IOL = 1.6 mA High-Level Input Leakage MAX. VIH1 VDD = 4.5 to 6.0 V,IOH = -1 mA High-Level Output Voltage TYP. VIN = 12 V ILIL1 VIN = 0 V Input Leakage Current ILIL2 X1, X2 High-Level ILOH1 VOUT = V DD Other than below Output Leakage Current ILOH2 VOUT = 12 V Ports 12 to 14 (open drain) Low-Level Output Leakage Current ILOL VOUT = 0 V Internal Pull-Up Resistor*1 RL Ports 12 to 14 VDD = 5 V10% 15 40 10 IDD1 Supply Current*1 IDD2 IDD3 4.19MHz VDD = 5 V10%* 2 3 9 mA crystal VDD = 3 V10%* 3 0.55 1.5 mA oscillator HALT VDD = 5 V10% 600 1800 A C1 = C2 = 22pF mode VDD = 310% 200 600 A 0.1 10 A STOP mode, VDD = 3 V10% *1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included. 2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011. 3: When the low-speed mode is set by setting the PCC to 0000. 51 PD75104, 75106, 75108 CAPACITANCE (Ta = 25C, VDD = 0 V) Parameter Symbol Input Capacitance CIN Output Capacitance COUT Input/Output Capacitance CIO Conditions MIN. TYP. f = 1 MHz MAX. 15 Pins other than thosemeasured are at 0 V Unit pF 15 pF 15 pF MAX. Unit 100 mV V COMPARATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 4.5 to 6.0 V) Parameter Comparison Accuracy Symbol Conditions MIN. TYP. VACOMP Threshold Voltage VTH 0 V DD PTH Input voltage VIPTH 0 V DD Comparator circuit current dissipation PTHM7 is set to "1" 1 V mA POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power-On Reset High-Level VDDH 4.5 6.0 V VDDL 0 0.2 V tr 10 *1 s toff 1 Operating Voltage Power-On Reset Low-Level Operating Voltage Supply Voltage Rise Time Supply Voltage s Off Time Power-On Reset Circuit Current Dissipation*2 IDDPR VDD = 5 V10% 10 100 A VDD = 2.5 V 2 20 A 17 *1: 2 /fXX (31.3 ms at fXX = 4.19 MHz) 2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated. V DDH V DD V DDL t off Note: Apply power gradually and smoothly. 52 tr PD75104, 75106, 75108 AC CHARACTERISTICS (Ta = -40 to +85C, V DD = 2.7 to 6.0 V) Parameter Symbol Conditions MIN. MAX. Unit 0.95 32 s 3.8 32 s VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz VDD = 4.5 to 6.0 V 0.48 s 1.8 s Input 0.8 s Output 0.95 s Input 3.2 s Output 3.8 s Input 0.4 s tKCY /2-50 ns VDD = 4.5 to 6.0 V CPU Clock Cycle Time* (Minimum Instruction Execution Time = 1 Machine Cycle) tCY TI0, TI1 Input Frequency fTI TI0, TI1 Input High-/ Low-Level Width tTIH , tTIL VDD = 4.5 to 6.0 V SCK Cycle Time tKCY VDD = 4.5 to 6.0 V SCK High-/Low-Level Width tKH, Output tKL Input Output TYP. 1.6 s tKCY /2-150 ns SI Setup Time (vs. SCK) tSIK 100 ns SI Hold Time (vs. SCK) tKSI 400 ns SCK SO Output delay Time tKSO INT0 to 4 tINTH, High-/Low-Level Width tINTL RESET Low-Level Width tRSL VDD = 4.5 to 6.0 V *: The cycle time of the CPU clock () is 300 ns 1000 ns 5 s 5 s tCY vs. VDD determined by the input frequency of 40 the ceramic or crystal oscillator circuit 32 and the set value of the processor clock 7 6 control register. The tCY vs. VDD characteristics are as shown on the right. 5 Operation guaranteed range t CY [s] 4 3 2 1 0.5 0 1 2 3 4 5 6 V DD [V] 53 PD75104, 75106, 75108 AC TIMING MEASURING POINTS (excluding Ports 0, 1, TI0, TI1, X1, X2, and RESET) 0.7 VDD 0.7 VDD Measuring points 0.3 VDD 0.3 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD -0.5 0.4 TI TIMING 1/fTI tTIL TI0, TI1 tTIH 0.8 VDD 0.2 VDD 54 PD75104, 75106, 75108 SERIAL TRANSFER TIMING tKCY tKL tKH 0.8 V DD SCK 0.2 V DD tSIK tKSI 0.8 V DD SI Input data 0.2 V DD tKSO Output data SO INTERRUPT INPUT TIMING tINTL tINTH 0.8 V DD INT0 to 4 0.2 V DD RESET INPUT TIMING tRSL RESET 0.2 V DD 55 PD75104, 75106, 75108 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -40 to +85C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current*1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization tWAIT Conditions MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 6.0 V 10 A s 0 Released by RESET Wait Time*2 Released by interrupt request 217/fX ms *3 ms *1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 - 0 0 0 2 20/fXX (approx. 250 ms) - 0 1 1 2 17/fXX (approx. 31.3 ms) - 1 0 1 2 15/fXX (approx. 7.82 ms) - 1 1 1 2 13/fXX (approx. 1.95 ms) DATA RETENTION TIMING Wait time ( ): f XX = 4.19 MHz (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 56 PD75104, 75106, 75108 CHARACTERISTIC DATA IDD vs. VDD Characteristics (crystal oscillation) (Ta = 25C) 5000 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] 1000 HALT mode [0100] Supply current IDD [ A] 500 100 50 STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. 10 5 Figure in [ ] indicate set values of PCC. X1 X2 Crystal oscillation 4.194304 MHz 22 pF 22 pF 1 0.5 0 1 2 3 4 5 Supply voltage VDD [V] 6 I DD vs. f XX Characteristics (crystal oscillation) (VDD = 5.0 V, Ta = 25C) 3.0 Figure in [ ] indicate set values of PCC. X1 X2 High-speed mode [0011] 2.5 C1 Supply current IDD [mA] 13. C2 2.0 Medium-speed mode [0010] 1.5 Low-speed mode [0000] 1.0 HALT mode [0100] 0.5 0 0 1 2 3 4 f XX [MHz] 5 57 PD75104, 75106, 75108 I DD vs. V DD Characteristics (ceramic oscillation) (Ta = 25C) 5000 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100] 1000 Supply current IDD [ A] 500 100 50 STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. 10 5 Figure in [ ] indicate set values of PCC. X1 X2 Ceramic oscillation 4.19 MHz 30 pF 30 pF 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] I DD vs. f XX Characteristics (ceramic oscillation) (VDD = 5.0 V, Ta = 25C) 3.0 Figure in [ ] indicate set values of PCC. X1 X2 High-speed mode [0011] 2.5 Supply current IDD [mA] C1 C2 Medium-speed mode [0010] 2.0 Low-speed mode [0000] 1.5 1.0 HALT mode [0100] 0.5 0 0 58 1 2 3 4 f XX [MHz] 5 PD75104, 75106, 75108 I DD vs. f X Characteristics (external clock) (VDD = 5.0 V, Ta = 25C) 3.0 Figures in [ ] indicate set values of PCC. X1 X2 2.5 Supply current IDD [ A] PD74HCU04 High-speed mode [0011] 2.0 Medium-speed mode [0010] 1.5 Low-speed mode [0000] 1.0 0.5 HALT mode [0100] 0 0 1 2 3 4 f X [MHz] 5 TIn input frequency f TI [kHz] f TI vs. V DD Characteristics 1000 500 Operation guaranteed range 100 50 0 1 2 3 4 V DD [V] 5 6 7 59 PD75104, 75106, 75108 V OL vs. I OL (Ports 0 and 2 to 9) Characteristics V DD = 6 V V DD = 5 V Low-level output current of port 0 and 2 to 9 I OL [mA] 30 V DD = 4 V V DD = 3 V 20 10 0 0 1 2 V OL [V] 3 4 VOL vs. IOL (Ports 12 to 14) Characteristics V DD = 6 V V DD = 5 V 30 Low-level output current of ports 12 to 14 I OL [mA] V DD = 4 V 20 V DD = 3 V 10 0 60 0 1 2 V OL [V] 3 4 PD75104, 75106, 75108 V OH vs. I OH (Ports 0 and 2 to 9) Characteristics V DD = 6 V -15 V DD = 5 V High-level output current of port 0 and 2 to 9 IOH [mA] V DD = 4 V -10 V DD = 3 V -5 0 0 1 2 3 4 V DD - V OH [V] Remarks: Unless otherwise specified, all the characteristic data shown are reference values. 61 PD75104, 75106, 75108 14. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE M B C ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.500.10 0.020 +0.004 -0.005 F 0.9 MIN. 0.035 MIN. G 3.20.3 0.1260.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 -0.05 0.010 +0.004 -0.003 N 0.17 0.007 R 0~15 0~15 P64C-70-750A,C-1 62 PD75104, 75106, 75108 64 PIN PLASTIC QFP (14x20) A B 51 52 detail of lead end 33 32 C D S R Q 64 1 20 19 F G H I M J K M P N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.60.4 0.9290.016 B 20.00.2 0.795 +0.008 -0.009 C 14.00.2 0.551+0.009 -0.008 D 17.60.4 0.6930.016 F 1.0 0.039 G 1.0 0.039 H 0.400.10 0.016 +0.004 -0.005 0.008 I 0.20 J 1.0 (T.P.) 0.039 (T.P) K 1.80.2 0.071 +0.008 -0.009 L 0.80.2 0.031 +0.009 -0.008 M 0.15 +0.10 -0.05 0.006 +0.004 -0.003 N P Q R S 0.10 0.004 2.7 0.106 0.10.1 0.0040.004 55 55 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2 63 PD75104, 75106, 75108 15. RECOMMENDED SOLDERING CONDITIONS It is recommended that PD75104, 75106, and 75108 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, please consult NEC. Table 15-1 Soldering Conditions of Surface Mount Type PD75108GF - xxx - 3BE: 64-pin plastic QFP (14 x 20 mm) Soldering Method Soldering Conditions Symbol for Recommended Condition Infrared Reflow Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1 IR30-00-1 VPS Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1 VP15-00-1 Wave Soldering Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120C max. (package surface temperature) WS60-00-1 Pin Partial Heating Pin temperature: 300C max., time: 3 seconds max. (per side) -- Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Table 15-2 Soldering Conditions of Through-Hole Type PD75108CW - xxx : 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave Soldering (Only for lead part) Soldering bath temperature: 260C max., Time: 10 seconds max. Pin Partial Heating Pin temperature: 260C max., Time: 10 seconds max. Caution: The wave soldering must be performed at the lead part only. Note that the solder must not be directly contacted to the package body. 65 66 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PRODUCTS IN PD751XX SERIES Item PD75104 PD75106 PD75108 PD75112 PD75116 ROM Configuration ROM (Bits) RAM (Bits) Instruction Set PD75104A PD75108F PD75112F PD75116F PD75P108B Mask ROM 000H-FFFH 4096 x 8 0000H-177FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 6016 x 8 8064 x 8 12160 x 8 16256 x 8 320 x 4 512 x 4 (Bank 0: 256 x 4) (Bank 0: 256 x 4) (Bank 1: 64 x 4) (Bank 1: 256 x 4) 000H-FFFH 4096 x 8 PD75P116 PROM 0000H-1F7FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 0000H-1F7FH 0000H-3F7FH 8064 x 8 8064 x 8 12160 x 8 16256 x 8 8064 x 8 16256 x 8 320 x 4 (Bank 0: 256 x 4) (Bank 1: 64 x 4) 512 x 4 (Bank 0: 256 x 4) (Bank 1: 256 x 4) 512 x 4 (Bank 0: 256 x 4) (Bank 1: 256 x 4) High-end (Only PD75104 and 75104A are not provided with BR!addr instruction.) Total High end 58 * CMOS I/O: 32 I/O PD75108A * +12 V open-drain output: 12 I/O (pull-up resistor as mask option) Lines LED direct drive: 44 * CMOS input: 10 Input * Comparator input: 4 Power-ON Reset Circuit * CMOS I/O: 32 (pull-up resistor as mask option: 24) * +12 V open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44 * CMOS input: 10 (pull-up resistor as mask option: 4) * Comparator input: 44 * CMOS I/O: 32 * +12 V open-drain output: 12 LED direct drive: 44 * CMOS I/O: 32 * +10 V open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44 * CMOS input: 10 * Comparator input: 4 Provided (mask option) None Power-ON Flag Operating Voltage Range 0.95 s (at 4.5 V to 5.0 V) 0.95 s (at 5 V) 3 s (at 3 V) Pin Connections 1.91 s (at 3 V) * 64-pin plastic QFP (14 x 20 mm) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm) 5 V 10% 0.95 s (at 5 V) 3 s (at 3 V) 0.95 s (at 5 V) Depends on package. Only PD75P108, and 75P116 are provided with VPP pin. Depends on package * 64-pin plastic shrink DIP (750 mil) 2.7 to 6.0 V * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic QFP (14 x 20 mm) * 64-pin * 64-pin plastic plastic shrink DIP shrink DIP (750 mil) (750 mil) * 64-pin ceramic * 64-pin shrink DIP plastic QFP (w/window) (14 x 20 * 64-pin mm) plastic QFP (14 x 20 mm) PD75104, 75106, 75108 Minimum Instruction Execution Time Package 2.7 to 5.0 V (Ta = -40 to +50C) 2.8 to 5.0 V (Ta = -40 to +60C) 2.7 to 6.0 V PD75104, 75106, 75108 APPENDIX B. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using PD75108: Hardware Software IE-75000-R* 1 IE-75001-R In-circuit emulator for 75X series IE-75000-R-EM*2 Emulation board for IE-75000-R and IE-75001-R EP-75108CW-R Emulation prove for PD75108CW EP-75108GF-R EV-9200G-64 PG-1500 Emulation prove for PD75108GF. It is provided with a 64-pin conversion socket, EV-9200G-64 PA-75P108CW PROM programmer adapter for PD75P108BCW and 75P108BDW. It is connected to PG-1500. PA-75P116GF Programmer adapter for PD75P108BGF. It is connected to PG-1500. IE Control Program Host machine PG-1500 Controller RA75X Relocatable Assembler PROM programmer PC-9800 series (MS-DOS IBM PC/AT TM (PC DOS TM TM Ver.3.30 to Ver.5.00A*3 ) Ver.3.1) *1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). 67 PD75104, 75106, 75108 APPENDIX C. 68 RELATED DOCUMENTS PD75104, 75106, 75108 GENERAL NOTES ON CMOS DEVICES 1 STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . 2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices. 3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 69 PD75104, 75106, 75108 [MEMO] No p art of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 70