SG2525A
SG3525A
REGULATING PULSE WIDTH MODULATORS
.8 TO 35 V OPERATION
.5.1V REFERENCETRIMMED TO ±1%
.100Hz TO 500 KHz OSCILLATORRANGE
.SEPARATEOSCILLATORSYNCTERMINAL
.ADJUSTABLEDEADTIMECONTROL
.INTERNALSOFT-START
.PULSE-BY-PULSESHUTDOWN
.INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
.LATCHING PWM TO PREVENT MULTIPLE
PULSES
.DUAL SOURCE/SINKOUTPUT DRIVERS
DESCRIPTION
The SG3525Aseriesof pulsewidthmodulatorinte-
grated circuits are designedto offerimproved per-
formance and lowered external parts count when
used indesigningall typesof switchingpower sup-
plies. Theon-chip+ 5.1 V referenceistrimmedto±
1 %andthe inputcommon-moderangeoftheerror
amplifierincludesthe referencevoltageeliminating
externalresistors. A sync input to the oscillator al-
lowsmultipleunitstobeslavedorasingleunittobe
synchronizedto an externalsystemclock. A single
resistorbetweentheCTandthedischargeterminals
provide a wide rangeof deadtime ad- justment.
Thesedevicesalsofeaturebuilt-insoft-startcircuitry
with only an external timing capacitor required. A
shutdownterminalcontrolsboththesoft-startcircu-
ity and the outputstages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down,as well assoft-startrecycle with longershut-
downcommands.Thesefunctionsarealsocontrol-
ledbyan undervoltagelockoutwhichkeepstheout-
puts off and the soft-start capacitor discharged for
sub-normal input voltages.This lockoutcircuitry in-
cludesapproximately500mVofhysteresisforjitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
theoutputswill remainoffforthedurationofthepe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525AoutputstagefeaturesNORlogic,givinga
LOWoutputfor anOFFstate.
DIP16 16(Narrow)
Type Plastic DIP SO16
SG2525A SG2525AN SG2525AP
SG3525A SG3525AN SG3525AP
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
June 2000 1/12
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
ViSupply Voltage 40 V
VCCollector Supply Voltage 40 V
IOSC Oscillator Charging Current 5 mA
IoOutput Current, Source or Sink 500 mA
IRReference Output Current 50 mA
ITCurrent through CTTerminal
Logic Inputs
Analog Inputs
5
– 0.3 to + 5.5
– 0.3 to Vi
mA
V
V
Ptot Total Power Dissipation at Tamb =70°C 1000 mW
TjJunction Temperature Range – 55 to 150 °C
Tstg Storage Temperature Range – 65 to 150 °C
Top Operating Ambient Temperature : SG2525A
SG3525A –25to85
0to70 °
C
°C
THERMAL DATA
Symbol Parameter SO16 DIP16 Unit
Rth j-pins
Rth j-amb
Rth j-alumina
Thermal Resistance Junction-pins Max
Thermal Resistance Junction-ambient Max
Thermal Resistance Junction-alumina (*) Max 50
50
80 °C/W
°C/W
°C/W
*Thermalresistancejunction-aluminawiththedevicesolderedonthemiddleofanaluminasupportingsubstratemeasuring15×20mm; 0.65mm
thickness with infiniteheatsink.
BLOCK DIAGRAM
SG2525A-SG3525A
2/12
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, andover operatingtemperature, unlessotherwise specified)
Symbol Parameter Test Conditions SG2525A SG3525A Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF Output Voltage Tj=25°
C 5.05 5.1 5.15 5 5.1 5.2 V
∆VREF Line Regulation Vi= 8 to 35 V 10 20 10 20 mV
∆VREF Load Regulation IL= 0 to 20 mA 20 50 20 50 mV
∆VREF/∆T* Temp. Stability Over Operating Range 20 50 20 50 mV
* Total Output Variation Line, Load and
Temperature 5 5.2 4.95 5.25 V
Short Circuit Current VREF =0T
j=25°C 80 100 80 100 mA
* Output Noise Voltage 10 Hz ≤f≤10 kHz,
Tj=25°C40 200 40 200 µVrms
∆VREF* Long Term Stability Tj= 125 °C, 1000 hrs 20 50 20 50 mV
OSCILLATOR SECTION * *
*, •Initial Accuracy Tj=25°C±2±6±2±6%
*, •Voltage Stability Vi= 8 to 35 V ±0.3 ±1±1±2%
∆f/∆T* Temperature Stability Over Operating Range ±3±6±3±6%
f
MIN Minimum Frequency RT= 200 KΩCT= 0.1 µF 120 120 Hz
fMAX Maximum Frequency RT=2K
ΩC
T= 470 pF 400 400 KHz
Current Mirror IRT = 2 mA 1.7 2 2.2 1.7 2 2.2 mA
*, •Clock Amplitude 3 3.5 3 3.5 V
*, •Clock Width Tj=25°
C 0.3 0.5 1 0.3 0.5 1 µs
Sync Threshold 1.2 2 2.8 1.2 2 2.8 V
Sync Input Current Sync Voltage = 3.5 V 1 2.5 1 2.5 mA
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
VOS Input Offset Voltage 0.5 5 2 10 mV
IbInput Bias Current 1 10 1 10 µA
Ios Input Offset Current 1 1 µA
DC Open Loop Gain RL≥10 MΩ60 75 60 75 dB
* Gain Bandwidth
Product Gv= 0 dB Tj=25°
C1 2 1 2 MHz
*, ❚DC Transconduct. 30 KΩ≤RL≤1MΩ
T
j=25°C1.1 1.5 1.1 1.5 ms
Output Low Level 0.2 0.5 0.2 0.5 V
Output High Level 3.8 5.6 3.8 5.6 V
CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB
PSR Supply Voltage
Rejection Vi= 8 to 35 V 50 60 50 60 dB
SG2525A-SG3525A
3/12
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Conditions SG2525A SG3525A Unit
Min. Typ. Max. Min. Typ. Max.
PWM COMPARATOR
Minimum Duty-cycle 0 0 %
•Maximum Duty-cycle 45 49 45 49 %
•Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V
Maximum Duty-cycle 3.3 3.6 3.3 3.6 V
* Input Bias Current 0.05 1 0.05 1 µA
SHUTDOWN SECTION
Soft Start Current VSD = 0 V, VSS =0V 255080255080 µA
Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V
Shutdown Threshold To outputs, VSS = 5.1 V
Tj=25°C0.6 0.8 1 0.6 0.8 1 V
Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 mA
* Shutdown Delay VSD = 2.5 V Tj=25°C 0.2 0.5 0.2 0.5 µs
OUTPUT DRIVERS (each output) (VC=20V)
Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V
Isink = 100 mA 1 2 1 2 V
Output High Level Isource =20mA 1819 1819 V
I
source = 100 mA 17 18 17 18 V
Under-Voltage Lockout Vcomp and Vss = High 6 7 8 6 7 8 V
ICCollector Leakage VC= 35 V 200 200 µA
tr* Rise Time CL= 1 nF, Tj=25°C 100 600 100 600 ns
tf* Fall Time CL= 1 nF, Tj=25°C 50 300 50 300 ns
TOTAL STANDBY CURRENT
IsSupply Current Vi= 35 V 14 20 14 20 mA
*These parameters, although guaranteed over therecommended operating conditions, are not 100% tested in production.
•Testedat fosc =40 KHz(RT= 3.6 KΩ,C
T=10nF,RD=0Ω). Approximate oscillator frequency is defined by :
1
f= C
T(0.7 RT+3RD)
.
DC transconductance (gM) relatesto DC open-loop voltage gain(Gv) according to thefollowingequation :Gv=g
MR
LwhereRListhe resistance
from pin 9 to ground. The minimumgMspecification is used to calculate minimum Gvwhen the error amplifieroutput is loaded.
SG2525A-SG3525A
4/12
TEST CIRCUIT
SG2525A-SG3525A
5/12
Figure 1 : Oscillator Charge Time vs. RT
and CT.Figure 2 : Oscillator Discharge Time vs. RD
and CT.
RECOMMENDED OPERATINGCONDITIONS (•)
Parameter Value
Input Voltage (Vi)8to35V
Collector Supply Voltage (VC) 4.5 to 35 V
Sink/Source Load Current (steady state) 0 to 100 mA
Sink/Source Load Current (peak) 0 to 400 mA
Reference Load Current 0to20mA
Oscillator Frequency Range 100 Hz to 400 KHz
Oscillator Timing Resistor 2 KΩto 150 KΩ
Oscillator Timing Capacitor 0.001 µF to 0.1 µF
Dead Time Resistor Range 0 to 500 Ω
•(⋅) Range over which the device is functionaland parameter limits are guaranteed.
Figure 3 : OutputSaturation
Characteristics. Figure 4 : Error AmplifierVoltageGain and
Phasevs. Frequency.
SG2525A-SG3525A
6/12
SHUTDOWN OPTIONS(see Block Diagram)
Since both the compensation and soft-start termi-
nals (Pins 9 and 8) have current source pull-ups,
either can readily accept a pull-down signal which
onlyhastosinka maximumof 100
µA
toturnoffthe
outputs.Thisissubjecttotheaddedrequirementof
dischargingwhateverexternalcapacitancemay be
attachedto thesepins.
Analternateapproachistheuseoftheshutdowncir-
cuitry of Pin 10 which has been improved to en-
hance the available shutdown options. Activating
this circuit by applying a positive signal on Pin 10
performs two functions : the PWM latch is immedi-
ately set providing the fastest turn-offsignal to the
outputs ; and a 150 µA current sink begins to dis-
chargethe externalsoft-startcapacitor.If the shut-
down command is short, the PWM signal is termi-
nated without significantdischarge of the soft-start
capacitor,thus,allowing,forexample,a convenient
implementation of pulse-by-pulse current limiting.
HoldingPin 10 highfora longerduration,however,
will ultimately discharge this external capacitor, re-
cycling slowturn-onupon release.
Pin 10 should not be left floating as noise pickup
couldconceivablyinterruptnormal operation.
Figure5 : ErrorAmplifier.
PRINCIPLES OF OPERATION
SG2525A-SG3525A
7/12
Figure7:Output Circuit (1/2 circuit shown).
Figure 6 : Oscillator Schematic.
SG2525A-SG3525A
8/12
Figure 10. Figure 11.
For single-ended supplies, the driver outputs are
grounded.TheVCterminalisswitchedto groundby
thetotem-polesourcetransistorsonalternateoscil-
latorcycles.
In conventionalpush-pull bipolar designs, forward
base drive is controlled by R1-R
3
. Rapid turn-off
times for the power devices are achieved with
speed-upcapacitorsC1andC2.
Thelowsourceimpedanceoftheoutputdriverspro-
vides rapid charging of Power Mos input capaci-
tancewhile minimizing externalcomponents.
Low power transformers can be driven directly.
Automaticresetoccursduringdeadtime,whenboth
endsof theprimarywindingareswitchedtoground.
Figure 8. Figure 9.
SG2525A-SG3525A
9/12
DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
SG2525A-SG3525A
10/12
SO16 Narrow
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004
0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45°(typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050
M 0.62 0.024
S
(1) D andF donot includemold flash or protrusions. Mold flashor potrusions shall not exceed 0.15mm(.006inch).
OUTLINE AND
MECHANICAL DATA
8°(max.)
SG2525A-SG3525A
11/12
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SG2525A-SG3525A
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