BD9528AMUV - ROHM Co., Ltd.

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High Performance Regulators for PCs

Main Power Supply

for Notebook PCs

(With Built-in Linear Regulator)

BD9528AMUV

●Description

BD9528AMUV is a 2ch switching regulator controller with high output current which can achieve low output voltage (1.0V～

5.5V) from a wide input voltage range (5.5V～28V). High efficiency for the switching regulator can be realized by utilizing an

external N-MOSFET power transistor. A new technology called H3RegTM(High speed, High efficiency, High performance) is

a Rohm proprietary control method to realize ultra high transient response against load change. SLLM (Simple Light Load

Mode) technology is also integrated to improve efficiency in light load mode, providing high efficiency over a wide load range.

For protection and ease of use, 2ch LDO (5V/3.3V (total 100mA)), the soft start function, variable frequency function, short

circuit protection function with timer latch, over voltage protection, and Power good function are all built in. This switching

regulator is specially designed for Main Power Supply of laptop PC.

●Features

1) 2ch H3REGTM DC/DC Converter controller

2) Adjustable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and Forced continuous Mode

3) Ther mal Shut Down (TSD), Under Voltage LockOut (UVLO), Over Current Protection (OCP),

Over Voltage Protection (OVP), Short circuit protection with 0.75ms timer-latch (SCP)

4) Soft start function to minimize rush current during startup

5) Switching Frequency Variable (f=150kHz～500kHz)

6) Built-in Power good circuit

7) Built-in 2ch Linear regulator (5V/3.3V (total 100mA))

8) Built in reference voltage(0.7V)

9) VQFN032-V5050 package

10) Built-in BOOT-Di

11) Built-in output discharge

12) ESD Susceptibility ( HBM (Human Body Model) : 2kV, MM (Machine Model) : 200V )

●Applications

Laptop PC, Desktop PC, LCD-TV, Digital Components

No.11030JAT46

Technical Note

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BD9528AMUV

●Maximum Absolute Ratings (Ta=25℃)

Parameter Symbol Limits Unit

Terminal Voltage

VIN, CTL, SW1, SW2 30 *1*2 V

EN1, EN2, PGOOD1, PGOOD2

Vo1, Vo2, MCTL1, MCTL2 6 *1*2 V

FS1, FS2, FB1, FB2, ILIM1, ILIM2,

SS1, SS2, LG1, LG2, REF,REG2 REG1+0.3 *1 V

BOOT1, BOOT2 35 *1*2 V

BOOT1-SW1, BOOT2-SW2,

HG1-SW1, HG2-SW2 7 *1*2 V

HG1 BOOT1+0.3 *1*2 V

HG2 BOOT2+0.3 *1*2 V

PGND1, PGND2 AGND±0.3 *1*2 V

Power Dissipation1 Pd1 0.38 *3 W

Power Dissipation2 Pd2 0.88 *4 W

Power Dissipation3 Pd3 3.26 *5 W

Power Dissipation4 Pd4 4.56 *6 W

Operating temperature Range Topr -20～+100 ℃

Storage temperature Range Tstg -55～+150 ℃

Junction Temperature Tjmax +150 ℃

*1 Do not however exceed Pd.

*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.

*3 Reduced by 3.0mW for each increase in Ta of 1℃ over 25℃ (when don’t mounted on a heat radiation board )

*4 Reduced by 7.0mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 1 layer.

(Copper foil area : 20.2mm2)

*5 Reduced by 26.1mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 4 layers.

(1

st and 4th copper foil area : 20.2mm2, 2nd and 3rd copper foil area : 5505mm2)

*6 Reduced by 36.5mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 4 layers.

(All copper foil area : 5505mm2)

●Operating Conditions (Ta=25℃)

Parameter Symbol Min. Max. Unit

Terminal Voltage

VIN 5.5 28 V

CTL -0.3 28 V

EN1, EN2, MCTL1, MCTL2 -0.3 5.5 V

BOOT1, BOOT2 4.5 33 V

SW1, SW2 -0.3 28 V

BOOT1-SW1, BOOT2-SW2,

HG1-SW1, HG2-SW2 -0.3 5.5 V

Vo1, Vo2, PGOOD1, PGOOD2 -0.3 5.5 V

MIN ON TIME TONmin - 150 nsec

★ This product should not be used in a radioactive environment.

Technical Note

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BD9528AMUV

●ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, Ta=25℃ VIN=12V, CTL=OPEN, EN1=EN2=5V, FS1=FS2=51kΩ)

Parameter Symbol Limits Unit Condition

Min. Typ. Max.

VIN standby current ISTB 70 150 250 μA EN1=EN2=0V, CTL=5V

VIN bias current IIN 60 130 230 μAVo1=5V

VIN shut down mode current ISHD 6 12 18 μA CTL=0V

CTL Low Voltage VCTLL -0.3 - 0.8 V

CTL High Voltage VCTLH 2.3 - 28 V

CTL bias current ICTL -18 -12 -6 μA CTL=0V

EN Low Voltage VENL -0.3 - 0.8 V

EN High Voltage VENH 2.3 - 5.5 V

EN bias current IEN - 3 6 μA EN=3V

[5V linear regulator](VIN)

REG1 output voltage VREG1 4.90 5.00 5.10 V IREG1=1mA

Maximum current IREG1 100 - - mA IREG2=0mA*

Line Regulation Reg.l1 - 90 180 mV VIN=5.5 to 28V

Load Regulation Reg.L1 - 30 50 mV IREG1=0 to 30mA

[3.3V linear regulator]

REG2 output voltage VREG2 3.27 3.30 3.33 V IREG2=1mA

Maximum current IREG2 100 - - mA IREG1=0mA*

Line Regulation Reg.l2 - - 20 mV VIN=5.5 to 28V

Load Regulation Reg.L2 - - 30 mV IREG2=0 to 30mA

[5V linear regulator](Vo1)

Input threshold voltage REG1th 4.1 4.4 4.7 V Vo1: Sweep up

Input delay time TREG1 1.5 3 6 ms

Switch resistance RREG1 - 1.0 3.0 Ω

[Under Voltage lock out block]

REG1 threshold voltage REG1_UVLO 3.9 4.2 4.5 V REG1: Sweep up

Hysteresis voltage dV_UVLO 50 100 200 mV REG1: Sweep down

[Output voltage sense block]

Feedback voltage1 VFB1 0.693 0.700 0.707 V

FB1 bias current IFB1 - 0 1 μA FB1=REF

Output discharge resistance1 RDISOUT1 50 100 200 Ω

Feedback voltage2 VFB2 0.693 0.700 0.707 V

FB2 bias current IFB2 - 0 1 μA FB2=REF

Output discharge resistance2 RDISOUT2 50 100 200 Ω

* IREG1+IREG2≦100mA

Technical Note

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BD9528AMUV

●ELECTRICAL CHARACTERISTICS

(unless otherwise noted, Ta = 2 5℃ VIN=12V, CTL=OPEN, EN1=EN2=5V, FS1=FS2=51kΩ)

Parameter Symbol Limits Unit Condition

Min. Typ. Max.

[H3REG block]

Ontime1 TON1 0.760 0.910 1.060 μs Vo1= 5V

Ontime2 TON2 0.470 0.620 0.770 μs Vo2= 3.3V

Maximum On time 1 TONMAX1 2.5 5 10 μs Vo1= 5V

Maximum On time 2 TONMAX2 1.65 3.3 6.6 μs Vo2= 3.3V

Minimum Off time TOFFMIN - 0.2 0.4 μs

[FET driver block]

HG higher side ON resistor HGHON - 3.0 6.0 Ω

HG lower side ON resistor HGLON - 2.0 4.0 Ω

LG higher side ON resistor LGHON - 2.0 4.0 Ω

LG lower side ON resistor LGLON - 0.5 1.0 Ω

[Over voltage protection block]

OVP threshold voltage VOVP 0.77

(+10%)

0.84

(+20%)

0.91

(+30%) V

OVP Hysteresis dV_OVP 50 150 300 mV

[Short circuit protection block]

SCP threshold voltage VSCP 0.42

(-40%)

0.49

(-30%)

0.56

(-20%) V

Delay time TSCP 0.4 0.75 1.5 ms

Current limit protection block]

Offset voltage dVSMAX 80 100 120 mV ILIM=100kΩ

[Power good block]

Power good low threshold VPGTHL 0.525

(-25%)

0.595

(-15%)

0.665

(-5%) V

Power good low voltage VPGL - 0.1 0.2 V IPGOOD=1mA

Delay time TPGOOD 0.4 0.75 1.5 ms

Power good leakage current ILEAKPG -2 0 2 μA VPGOOD=5V

[Soft start block]

Charge current ISS 1.5 2.3 3.1 μA

Standby voltage VSS_STB - - 50 mV

[Mode control block]

MCTL Low voltage VMCTL_L -0.3 - 0.3 V

MCTL High voltage VMCTL_H 2.3 - REG1

+0.3 V

MCTL bias current Imctl 8 16 24 μA MCTL=5V

Technical Note

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BD9528AMUV

●Output condition table

Input Output

CTL EN1 EN2 REG1(5V) REG2(3.3V) DC/DC1 DC/DC2

Low Low Low OFF OFF OFF OFF

Low Low High OFF OFF OFF OFF

Low High Low OFF OFF OFF OFF

Low High High OFF OFF OFF OFF

High Low Low ON ON OFF OFF

High Low High ON ON OFF ON

High High Low ON ON ON OFF

High High High ON ON ON ON

※ CTL pin is connected to VIN pin with 1MΩ resistor(pull up) internal IC.

※ EN pin is connected to AGND pin with 1MΩ resistor(pull down) internal IC.

●Block Diagram, Application circuit

3 2 1 31 32 22 23 24 26 25

11

6

8

Short through

Protection

Circuit

SLLM

TM

Block

H3RegTM

Controller

Block

Time r

Timer

14

12

17

21

Short th rou g h

Protection

Ci rcuit

SL L M

TM

Block

H3RegTM

Controller

Block

4

30 29 18

Reference

Bl oc k

5V

Reg

Thermal

Pr otection

EN1

REF

FB1

10 15

13

RFS1

FS1

A

GND

PGND1

LG1

SW1

HG1

BOOT1

PG ND2

LG 2

SW2

HG2

BOOT2

VIN

Vo 2

A

djustable

Vo1

A

djustable

REG1

REG1 REG1

CL1

SCP1

OVP 1

CL2

SCP2

OVP2

MCTL

FS2

MCT

L

FS1

EN 1

EN 2

Shor t Circuit Pr otect

SCP2

REF

Shor t Circuit Pr otect

SCP1

CL1

Over Current

Protect

CL2

Over Current

Protect

TSD

REG1

Power Good

MCTL

SLLM Mode C ontr ol

REG1

5V

REG1

MCTL1

VIN

5.5～28V

S

S2

FB2

FS2

EN2

PGOOD1

19

SS 1

Over Voltage Protect

OVP2

Over Voltage Protect

OVP1

REF

928

REG2

3.3V

CT

L

20

REG1

5

REG1

Power Good

7

Vo2

REG

2

PG OO D2

3.3V

Reg

Vo1

Timer

Ti mer

UVLO

PGND2

PGND1

27

Vo1

REF

ILIM1

I

LIM2

SW 2

SW1

16

MCTL

2

Technical Note

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BD9528AMUV

●Pin Configuration

Input Control Mode

MCTL1 MCTL2

Low Low SLLM

Low High QLLM

High Low Forced Continuous Mode

High High Forced Continuous Mode

●Pin Function Table

PIN No. PIN name PIN Function

1 SW2 Highside FET source pin 2

2 HG2 Highside FET gate drive pin 2

3 BOOT2 HG Driver power supply pin 2

4 EN2 Vo2 ON/OFF pin (High=ON, Low,OPEN=OFF)

5 PGOOD2 Vo2 Power Good Open Drain Output pin

6 SS2 Vo2 Soft start pin

7 Vo2 Vo2 Output voltage sense pin

8 ILIM2 OCP setting pin 2

9 CTL Linear regulator ON/OFF pin (High,OPEN=ON, Low=OFF)

10 FS2 Input pin for setting Vo2 frequency

11 FB2 Vo2 output voltage feedback pin

12 REF Output voltage setting pin

13 AGND Input pin Ground

14 FB1 Vo1 output voltage feedback pin

15 FS1 Input pin for setting Vo1 frequency

16 MCTL2 Mode switch pin 2 ( OPEN = L )

17 ILIM1 OCP setting pin 1

18 MCTL1 Mode switch pin 1 ( OPEN = L )

19 SS1 Vo1 Soft start pin

20 PGOOD1 Vo1 Power Good Open Drain Output pin

21 EN1

Vo1 ON/OFF pin

(High=ON, Low,OPEN=OFF)

22 BOOT1 HG Driver power supply pin

23 HG1 Highside FET gate drive pin 1

24 SW1 Highside FET source pin 1

25 PGND1 Lowside FET source pin 1

26 LG1 Lowside FET gate drive pin 1

27 Vo1 Vo1 Output voltage sense pin

28 REG2 3.3V Linear regulator output pin

29 REG1 5V Linear regulator output pin

30 VIN Power supply input pin

31 LG2 Lowside FET gate drive pin 2

32 PGND2 Lowside FET source pin 2

reverse FIN Exposed Pad1, connect to GND

3 1 2 4 5 6 7 8

9

10

11

12

13

14

15

16

24 23 22 21 20 19 18 17

32

31

30

29

28

27

26

25

PGND1

LG1

SW2

HG2

BOOT2

PGOOD2

SS2

Vo2

ILIM2

SW1

HG1

BOOT1

PGOOD1

SS1

MCTL1

REF

MCTL2

FS1

FB1

A

GND

ILIM1

FB2

FS2

CTL

REG2

REG1

VIN

LG2

PGND2

FIN

Vo1

EN1

EN2

※ MCTL pin is connected to AGND pin with 500kΩ resistor ( pull down) internal IC

Technical Note

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BD9528AMUV

●Reference data

Fig.1 Switching Waveform

(Vo=5V, Io=0A, PWM)

Fig.2 Switching Waveform

(Vo=5V, Io=8A, PWM)

Fig.3 Switching Waveform

(Vo=5V, Io=0A, QLLM)

Fig.4 Switching Waveform

(Vo=5V, Io=0A, SLLM)

Fig.5 Switching Waveform

(Vo=3.3V, Io=0A, PWM)

Fig.6 Switching Waveform

(Vo=3.3V, Io=8A, PWM)

Fig.7 Switching Waveform

(Vo=3.3V, Io=0A, QLLM)

Fig.8 Switching Waveform

(Vo=3.3V, Io=0A, SLLM)

Fig.9 Switching Waveform

(Vo=1V, Io=0A, PWM)

Fig.10 Switching Waveform

(Vo=1V, Io=8A, PWM)

Fig.11 Switching Waveform

(Vo=1V, Io=0A, QLLM)

Fig.12 Switching Waveform

(Vo=1V, Io=0A, SLLM)

HG

10V/div

SW

10V/div

LG

5V/div

2μs

HG

10V/div

SW

10V/div

LG

5V/div

10μs

HG

10V/div

SW

10V/div

LG

5V/div

2μs

HG

10V/div

SW

10V/div

LG

5V/div

2μs

HG

10V/div

SW

10V/div

LG

5V/div

2μs

HG

10V/div

SW

10V/div

LG

5V/div

10μs

HG

10V/div

SW

10V/div

LG

5V/div

2μs

HG

10V/div

SW

10V/div

LG

5V/div

10μs

HG

10V/div

SW

10V/div

LG

5V/div

10μs

HG

10V/div

SW

10V/div

LG

5V/div

2μs

HG

10V/div

SW

10V/div

LG

5V/div

10μs

HG

10V/div

SW

10V/div

LG

5V/div

10μs

Technical Note

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BD9528AMUV

●Reference data

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

0

20

40

60

80

100

1 10 100 1000 10000

Io[mA]

η[%]

Fig.13 Efficiency

(Vo=5V, PWM)

Fig.14 Efficiency

(Vo=5V, QLLM)

Fig.15 Efficiency

(Vo=5V, SLLM)

Fig.16 Efficiency

(Vo=3.3V, PWM)

Fig.17 Efficiency

(Vo=3.3V, QLLM)

Fig.18 Efficiency

(Vo=3.3V, SLLM)

Fig.19 Efficiency

(Vo=1V, PWM)

Fig.20 Efficiency

(Vo=1V, QLLM)

Fig.21 Efficiency

(Vo=1V, SLLM)

Fig.22 Transient Response

(Vo=5V, PWM, Io=0→8A)

Fig.23 Transient Response

(Vo=5V, PWM, Io=8→0A)

Fig.24 Transient Response

(Vo=3.3V, PWM, Io=0→8A)

7V 12V

21V

7V

12V

21V

7V

12V

21V

7V

12V

21V

7V

12V

21V

7V

12V

21V

7V

12V

21V

5V

7V 12V

21V

12V

7V

Vo

100mV/div

IL

5A/div

IO

5A/div

20μs

Vo

100mV/div

IL

5A/div

IO

5A/div

20μs

Vo

100mV/div

IL

5A/div

IO

5A/div

20μs

Technical Note

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BD9528AMUV

●Reference data

Fig.25 Transient Response

(Vo=3.3V, PWM, Io=8→0A)

Fig.26 Transient Response

(Vo=1V, PWM, Io=0→8A)

Fig.27 Transient Response

(Vo=1V, PWM, Io=8→0A)

Fig.28 Output Voltage

(Vo=5V, PWM, Io=0A)

Fig.29 Output Voltage

(Vo=5V, PWM, Io=8A)

Fig.30 Output Voltage

(Vo=5V, QLLM, Io=0A)

Fig.31 Output Voltage

(Vo=5V, SLLM, Io=0A)

Fig.32 Output Voltage

(Vo=3.3V, PWM, Io=0A)

Fig.33 Output Voltage

(Vo=3.3V, PWM, Io=8A)

Fig.34 Output Voltage

(Vo=3.3V, QLLM, Io=0A)

Fig.35 Output Voltage

(Vo=3.3V, SLLM, Io=0A)

Fig.36 Output Voltage

(Vo=1V, PWM, Io=0A)

Vo

100mV/div

IL

5A/div

IO

5A/div

20μs

Vo

100mV/div

IL

5A/div

IO

5A/div

20μs

Vo

50mV/div

10μs

Vo

100mV/div

IL

5A/div

IO

5A/div

20μs

Vo

50mV/div

2μs

Vo

50mV/div

2μs

Vo

50mV/div

2μs

Vo

50mV/div

2μs

Vo

50mV/div

2μs

Vo

50mV/div

10μs

Vo

50mV/div

2μs

Vo

50mV/div

2μs

Technical Note

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BD9528AMUV

●Reference data

Fig.37 Output Voltage

(Vo=1V, PWM, Io=8A)

Fig.38 Output Voltage

(Vo=1V, QLLM, Io=0A)

Fig.39 Output Voltage

(Vo=1V, SLLM, Io=0A)

Vo

50mV/div

2μs

Vo

50mV/div

10μs

Vo

50mV/div

2μs

Fig.43 Wake up waveform

(EN1/2→PGOOD1/2)

Fig.44 Io-frequency

(Vo=5V, PWM, RFS=68kΩ)

Fig.45 Io-frequency

(Vo=3.3V, PWM, RFS=68kΩ)

Fig.46 FS-ONTIME Fig.48 Ta-IOCP

(Vo=5V)

Fig.47 FS-frequency

Fig.40 Wake up waveform

(EN1=EN2)

Fig.41 Wake up waveform

(EN2→EN1)

Fig.42 Wake up waveform

(EN1→EN2)

IOUT-frequency (VOUT=5V, R(FS)=68kΩ)

300

350

400

450

500

01234567

IOUT [A]

frequency [kHz]

VIN=7.5V

VIN=12V

VIN=18V

IOUT-frequency (VOUT=5V, R(FS)=68kΩ)

300

350

400

450

500

01234567

IOUT [A]

frequency [kHz]

VIN=7.5V

VIN=12V

VIN=18V

0

0.5

1

1.5

2

2.5

050100150

RFS [kΩ]

ONTIME [usec]

VOUT=5V

VOUT=3.3V

0

100

200

300

400

500

600

700

0 50 100 150

RFS [kΩ]

frequency [kHz]

VOUT=5V

VOUT=3.3V

0.000

0.500

1.000

1.500

2.000

2.500

3.000

3.500

4.000

4.500

5.000

5.500

0246810121416

IOUT [A]

VOUT [V]

VIN=7.5V(-5℃）

VIN=21V（-5℃）

VIN=7.5V(75℃）

VIN=21V（75℃）

EN1

5V/div

Vo1

2V/div

EN2

5V/div

Vo2

2V/div

EN1

5V/div

Vo1

2V/div

EN2

5V/div

Vo2

2V/div

EN1

5V/div

Vo1

2V/div

EN2

5V/div

Vo2

2V/div

EN1

5V/div

PGOOD1

2V/div

EN2

5V/div

PGOOD2

2V/div

Technical Note

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BD9528AMUV

●Reference data

Fig.50 IREG1-REG1 Fig.51 IREG2-REG2

Fig.49 Ta-IOCP

(Vo=3.3V)

IOUT - REG2 voltage

2.8

2.9

3

3.1

3.2

3.3

3.4

0 50 100 150 200 250

IOUT [mA]

REG2 voltage [V]

IOUT - REG1 voltage

4.5

4.6

4.7

4.8

4.9

5

5.1

0 50 100 150 200 250

IOUT [mA]

REG1 voltage [V]

0.000

0.500

1.000

1.500

2.000

2.500

3.000

3.500

0246810121416

IOUT [A]

VOUT [V]

VIN=7.5V(-5℃）

VIN=21V（-5℃）

VIN=7.5V(75℃）

VIN=21V（75℃）

Technical Note

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BD9528AMUV

●Pin Descriptions

・VIN (30 pin)

This is the main power supply pin. The input supply voltage range is 5.5V to 28V. The duty cycle of BD9528AMUV is

determined by input voltage and control output voltage. Therefore, when VIN voltage fluctuated, the output voltage also

becomes unstable. Since VIN line is also the input voltage of switching regulator, stability depends on the impedance of

the voltage supply. It is recommended to establish bypass capacitor and CR filter suitable for the actual application.

・CTL (9 pin)

When CTL pin voltage is at least 2.3V, the status of the linear regulator output becomes active (REG1=5V, REG2=3.3V).

Conversely, the status switches off when CTL pin voltage goes lower than 0.8V. The switching regulator doesn’t become

active when the status of CTL pin is low, if the status of EN pin is high.

(※CTL pin is connected to VIN pin with 1MΩ resistor(pull up) intermall IC)

・EN1, 2 (21 pin, 4 pin)

When EN pin voltage is at least 2.3V, the status of the switching regulator becomes active. Conversely, the status switches

off when EN pin voltage goes lower than 0.8V.

(※EN pin is connected to AGND pin with 1MΩ resistor(pull down) intermall IC)

・REG1 (29 pin)

This is the output pin for 5V linear regulator and also active in power supply for driver and control circuit of the inside. The

standby function for REG1 is determined by CTL pin. The voltage is 5V, with 100mA current ability. It is recommended that

a 10μF capacitor (X5R or X7R) be established between REG1 and GND.

・REG2 (28 pin)

This is the output pin for 3.3V linear regulator. The standby function for REG2 is determined by CTL. The voltage is 3.3V,

with 100mA current ability. It is recommended that a 10μF capacitor (X5R or X7R) be established between REG2 and

GND.

・REF (12 pin)

This is the setting pin for output voltage of switching regulator. This IC controls the voltage in the status of REF≒FB.

・FB 1, 2 (14 pin, 11 pin)

This is the feedback pin from the output of switching regulator. This IC controls the voltage in the status of REF≒FB.

・Vo1 (27 pin)

This is the output discharge pin, and output voltage feedback pin for frequency setting. When the voltage is beyond 4.4V

from the external power supply during operation, it supplies REG1.

・Vo2 (7 pin)

This is the output discharge pin, and output voltage feedback pin for frequency setting.

・SS1, 2 (19 pin, 6 pin)

This is the setting pin for soft start. The rising time is determined by the capacitor connected between SS and GND, and

the fixed current inside IC after it is the status of low in standby mode. It controls the output voltage till SS voltage catch up

the REF pin to become the SS terminal voltage.

・FS1, 2 (15 pin, 10 pin)

This is the input pin for setting the frequency. It is available to set it in frequency range is 150kHz to 500kHz.

・ILIM1, 2 (17 pin, 8 pin)

BD9528AMUV detects voltage differential between SW and PGND, and set OCP. OCP setting current value is determined

by the resistance value of ILIM pin. FET of various Ron is available.

・PGOOD 1, 2 (20 pin, 5 pin)

This is the open drain pin for deciding the output of switching regulator.

・MCTL1, 2 (18 pin, 16 pin)

This is the switching shift pin for SLLM (Simple Light Load Mode). MCTL pin is at low level when it goes lower than 0.8V,

and at high level when it goes higher than 2.3V.

(※MCTL pin is connected to AGND pin with 500kΩ resistor(pull down) intermall IC)

・AGND (13 pin)

This is the ground pin.

・BOOT1, 2 (22 pin, 3 pin)

This is the power supply pin for high side FET driver. The maximum voltage range to GND pin is to 35V, to SW pin is to 7V.

In switching operations, the voltage swings from (VIN+REG1) to REG1 by BOOT pin operation.

・HG1, 2 (23 pin, 2 pin)

This is the highside FET gate drive pin. It is operated in switching between BOOT to SW. In case the output MOS is 3ohm

/the status of Hi, 2ohm/the status of Low, it is operated hi-side FET gate in high speed.

・SW1, 2 (24 pin, 1 pin)

This is the ground pin for high side FET drive. The maximum voltage range to GND pin is to 30V. Switching operation

swings from the status of BOOT to the status of GND.

・LG1, 2 (26 pin, 31 pin)

This is the lowside FET gate drive pin. It is operated in switching between REG1 to PGND. In case the output MOS is

2ohm /the status of Hi, 0.5ohm/the status of Low, it is operated low-side FET gate in high speed.

・PGND1, 2 (25 pin, 32 pin)

This is the ground pin for low side FET drive.

Technical Note

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BD9528AMUV

●Explanation of Operation

The BD9528AMUV is a 2ch synchronous buck regulator controller incorporating ROHM’s proprietary H3REG CONTROLLA

control system. Because controlling of output voltage by a comparator, high response is realized with not relying on the

switching frequency. And, when VOUT drops due to a rapid load change, the system quickly restores VOUT by extending the

TON time interval. Thus, it serves to improve the regulator’s transient response. Activating the Light Load Mode will also

exercise Simple Light Load Mode (SLLM) control when the load is light, to further increase efficiency.

H3RegTM control

(Normal operation)

(VOUT drops due to a rapid load change)

(when VIN drops)

If VIN voltage drops because of the battery voltage fall, ontime tON and offtime tOFF is determined by the following formula:

tON=VOUT/VIN×I/f and tOFF=(VIN-VOUT)/VIN×f so that tON lengthen and tOFF shorten to keep output voltage constant.

However, if VIN still drops and tOFF equals to tminoff (tminoff:Minimum OFF time, regulated inside IC) , because tOFF

cannot shorten any more, as a result output voltage drops. In H3RegTM system, lengthening tON time than regulated tON

(lengthen tON time until FB＞REF) enables to operate stable not to drop the output voltage even if VIN turns to be low. With

the reason above, it is suitable for 2-cell battery.

FB

REF

HG

LG

HG output is determined by the formula above.

A

fter the status of HG is OFF, LG go on outputting until

output voltage become FB=REF.

When FB falls to a reference voltage (REF),

the drop is detected, activating the H3REG CONTROLL

A

system.<Route A>

REF

FB

HG

Io

LG

tON +α

When VOUT drops due to a rapid load change, and the

voltage remains below reference voltage after the

programmed tON time interval has elapsed (Output of a

comparator for output voltage control =H), the system

quickly restores VOUT by extending the tON time,

improving the transient response.<Route B> After VOU

T

restores (FB=REF), HG turns to be OFF, and it goes back

to a normal operation.

Internal

reference

voltage

REF

FB

Vout/Vin

Circuit

Transient

Circuit

Driver

HG

SW

LG

VIN

VOUT

Comparator for

output voltage control

A

B

HG

LG

FB

REF

VIN

tON1 tON2t

ON3t

ON4

tOFF1t

OFF2tOFF3tOFF4=tOFF3

tON4+α

tOFF4=tOFF3

H3RegTM

FB=REF

Output voltage drops

tON==VOUT

VIN

× 1

f [sec]・・・(1)

Technical Note

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BD9528AMUV

Light Load Control

(SLLM)

(QLLM)

MCTL1 MCTL2 Control mode Running

L L SLLM PWM

L H QLLM PWM

H X PWM PWM

●Timing Chart

• Soft Start Function

In SLLM, when the status of LG is OFF and the coil current

is within 0A (it flows to SW from VOUT.), SLLM function is

operated to prevent output next HG. The status of HG is

ON, when FB falls below reference voltage again.

In QLLM, when the status of LG is OFF and the coil current

is within 0A (it flows to SW from VOUT.), QLLM function is

operated to prevent output next HG.

Then, FB falls below the output programmed voltage within

the programmed time (typ=40μs), the status of HG is ON.

In case FB doesn’t fall in the programmed time, the status

of LG is ON forcedly and VOUT falls. As a result, he status

of next HG is ON.

FB

REF

HG

LG

0

A

Load

COUT

*Attention: H

3

Reg

TM

CONTROLLA monitors the supplying current from

capacitor to load, using the ESR of output capacitor, and realize

the rapid response. Bypass capacitor used at each load (Ex.

Ceramic capacitor) exercises the effect with connecting to each

load side. Do not put a ceramic capacitor on COUT side o

f

power supply.

EN

SS

VOUT

IIN

Tss

Soft start time

TSS = REF×Css

2.3μA(typ)

[sec]

Incoming current

IIN = Co×VOUT

Tss

[A]

(Css: Soft start capacitor; Co: Output capacitor)

・・・(2)

・・・(3)

FB

HG

LG

0

A

The BD9528AMUV operates in PWM mode until SS pin

reaches cramp voltage (2.5V), regardless of the control

mode setting, in order to operate stable during the

operation.

Soft start is exercised with the EN pin set high. Current

control takes effect at startup, enabling a moderate

output voltage “ramping start.” Soft start timing and

incoming current are calculated with formulas (2) and

(3) below.

Technical Note

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BD9528AMUV

Notes when waking up with CTL pin or VIN pin

If EN pin is High or short (or pull up resistor) to REG1 pin, IC starts up by switching CTL pin, the IC might fail to start

up (SCP function) with the reason below, please be careful of SS pin and REF pin capacitor capacity.

CTL

(Vin)

EN

REG1(5V)

REG2(3.3V)

SCP_REF

SS

REF FB

FB

about 1.5V

SCP becomes valid from the point

SS reached 1.5V.

SCP invalid for

SS has not reached 1.5V.

SCP is valid here,

because this is SCP valid

area and also because FB

fall below SCP_REF.

SCP will be effective with

EN=ON at this section.

SW

Start up NG

EN

SW

Start up OK

SCP valid area

SCP is valid here,but with FB

exceeding SCP_REF it is normally

activate-able area.

SCP is effective at SCP_REF>FB condition.

SCP

SCP protection (function) activates when output shorts

and FB falls below the activation standard of SCP.

Inclination of REF is influenced

by the external condenser connected to REF.

※ To be accurate,Delay occurs after SCP activating.

But this shows the relationship of each signals briefly.

Delay SCP

PWM

(Switching control signal)

1ms(typ.)

SCP circuit

BG

SCP_REF

SCP

CTL

REF

SS

REG1 REG2 FB

Inner

reference

circuit

VIN

Technical Note

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BD9528AMUV

●Output Discharge

It will be available to use if connecting VOUT pin to DC/DC output.

(Total about 100Ω) . Discharge function operates when ①EN=’L’

②UVLO=ON(If input voltage is low) ③SCP Latch time ④TSD=ON.

The function at output discharge time is shown as left.

(1)during EN=’H’→‘L’

If EN pin voltage is below than EN threshold voltage, output

discharge function is operated, and discharge output capacito

r

charge.

(2) during VIN=CTL=H→0V

① IC is in normal operation until REG1 voltage becomes lower than

UVLO voltage. However, because VIN voltage also becomes low,

output voltage will drop, too.

② If REG1 voltage reaches the UVLO voltage, output discharge

function is operated, and discharge output capacitor charge.

③ In addition, if REG1 voltage drops, inner IC logic cannot operate, so

that output discharge function does not work, and becomes output

Hi-z. (In case, FB has resistor against GND, discharge at the

resistor.）

VIN,CTL

EN

VOUT

The efficiency of

VIN voltage drop

Output Discharge

Output Hi-Z

VIN, CTL

REG1

VOUT

UVLO ON

Technical Note

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BD9528AMUV

・Timer Latch Type Short Circuit Protection

・Over Voltage Protection

・Over current protection circuit

Short protection kicks in when output falls to or belo

w

REF X 0.7.

When the programmed time period elapses, output is

latched OFF to prevent destruction of the IC. (HG=Low,

LG=Low) Output voltage can be restored either b

y

reconnecting the EN pin or disabling UVLO.

FB

SCP

EN / UVLO

REF×0.7

0.75ms(typ)

FB

HG

LG

REF×1.2

Switching

When output rise to or above REF×1.2 (typ), output

over voltage protection is exercised, and low side FE

T

goes up maximum for reducing output.(LG=High,

HG=Low).When output falls, output voltage can be

restored., and go back to the normal operation.

During the normal operation, when FB becomes less

than REF, HG becomes High during the time tON, and

after HG becomes OFF, it output LG.

However, when inductor current exceeds ILIMIT

threshold, next HG pulse doesn’t pulsate until it is lowe

r

than ILIMIT level.

tON tON

HG

LG

IL

tON

Technical Note

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BD9528AMUV

●External Component Selection

1. Inductor (L) selection

※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease

system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed

the inductor rated current value.

※To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance.

2.Output Capacitor (CO) Selection

Please give due consideration to the conditions in formula (8) below for output capacity, bear in mind that output rise time

must be established within the soft start time frame. Capacitor for bypass capacitor is connected to Load side which

connect to output in output capacitor capacity (CEXT, figure above). Please set the soft start time or over current detecting

value, regarding these capacities.

Note: Improper capacitor may cause startup malfunctions.

3. Input Capacitor (Cin) Selection

A low ESR capacitor is recommended to reduce ESR loss and maximize efficiency.

The inductor value is a major influence on the output ripple current.

A

s formula (4) below indicates, the greater the inductor or the switching

frequency, the lower the ripple current.

⊿IL=

(VIN-VOUT)×VOUT

L×VIN×f

[

A

]

・・・

(

4

)

The proper output ripple current setting is about 30% of maximum

out

p

ut current.

⊿IL=0.3×IOUTmax. [A]・・・(5)

L=

(VIN-VOUT)×VOUT

⊿IL×VIN×f

[

H

]

・・・

(

6

)

(⊿IL: output ripple current; f: switch frequency)

Input Capacitor

Output ripple current

⊿IL

VIN

IL

L

Co

VOUT

VIN

L Co

VOUT

Cin

When determining the proper output capacitor, be sure to factor in the equivalent

series resistance required to smooth out ripple volume and maintain a stable

output voltage range.

Output ripple voltage is determined as in formula (7) below.

⊿VOUT=⊿IL×ESR+ESL×⊿IL/TON・・・(7)

Co+CEXT ≦ TSS×(Limit-IOUT)

VOUT ・・・

(

8

)

Tss: Soft start time

Limit: Over current detection

VIN

L

Co

VOUT

ESR

Output Capacitor

ESL

Load

CEXT

(⊿IL: Output ripple current、ESR: CO equivalent series resistance、

ESL: CO equivalent series inductance)

The input capacitor selected must have low enough ESR resistance to fully support

large ripple output, in order to prevent extreme over current. The formula for ripple

current IRMS is given in (9) below.

IRMS=IOUT×VIN

(

VIN-VOUT

)

VIN [A]・・・

(

9

)

Where VIN=2×VOUT,IRMS =

IOUT

2

※In selecting a capacitor, make sure the capacitor rating allows sufficient margin

relative to output voltage. Note that a lower ESR can minimize output ripple voltage.

Technical Note

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BD9528AMUV

4. MOSFET Selection

5. Setting output voltage

This IC is operated that output voltage is REF≒FB.

And it is operated that output voltage is feed back to FB pin.

Ex. VIN=20V,VOUT=5V,f=300kHz,L=2.5uH,ESR=20mΩ,R1=56kΩ,R2=9.1kΩ

⊿IL =(20V-5V)×5V/(2.5×10-6H×20V×300×103Hz)=5[A]

⊿VOUT=5A×20×10-3Ω=0.1[V]

V

OUT=0.7V×(56kΩ+9.1kΩ)/9.1kΩ+1/2×0.1V=5.057[V]

VIN

L

Co

VOUT

synchronous switch

main switch

VIN-VOUT

VIN

×RON×IOUT2+Ciss×f×VDD

=・・・(11)

Pmain=PRON+PGATE+PTRAN

Psyn=PRON+PGATE

＜Loss on the main MOSFET＞

(Ron: On-resistance of FET; Ciss: FET gate capacitance;

f: Switching frequency Crss: FET inverse transfer function;

IDRIVE: Gate peak current)

＜Loss on the synchronous MOSFET＞

・・・(10)

VOUT

VIN

×RON×IOUT2+Ciss×f×VDD+ VIN2×Crss×IOUT×f

IDRIVE

=

MOSFET may cause the loss as below, so please select proper FET for each.

(⊿VOUT: Output ripple voltage)

※(Notice) Please set ⊿FB more than 10mV

Output voltage

REF

FB

H

3

REG

CONTROLLA

S

RQ SLLM

Driver

Circuit

SLLM

VIN VIN

R1

R2

(⊿IL: ripple current of coil)

(L: inductance[H] f: switching frequency[Hz])

⊿VOUT =⊿IL×ESR

⊿IL =( VIN - VOUT)× VOUT

(

L×VIN×f

)

VOUT = ×REF(0.7V)+ ⊿VOUT

(R1+R2)

R2

1

2

⊿IL =(20V-5V)× =5(A)

5V

(

2.5×10-6H×20V×300×103Hz

)

⊿VOUT =5A×20×10-3Ω=0.1(V)

VOUT =0.7V× + ×0.1V=5.057(V)

1

2

(51kΩ+ 9.1kΩ)

9.1kΩ

Technical Note

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BD9528AMUV

6. Setting over current protection

(Example)

If load current 5A want to be realized with VIN=6～19V、VOUT=5V、f=400ｋHZ、L=2.5uH、RON=20mΩ, the formula would

be below.

When VIN=6V, Iocp will be minimum(this is because the ripple current is also minimum) so that if each condition is input,

the formula will be the following: RILIM＜109.1[kΩ].

※To design the actual board, please consider enough margin for FET ON resistor dispersion, Coil inductor dispersion, IC

over current reference value dispersion, frequency dispersion.

7. Relation between output voltage and TON time

The BD9528AMUV, both 1ch and 2ch, are high efficiency synchronous regulator controller with frequency variable.

TON time varies with Input voltage [VIN], output voltage [VOUT], and RFS of FS pin resistance.

TON time is calculated with the following formula:

Ton =k

From TON time above, frequency on application condition is following:

Frequency =

However, real-life considerations (such as the external MOSFET gate capacitor and switching speed) must be factored in

as they affect the overall switching rise and fall time, so please confirm in reality by the instrument.

RFS – ontime(VOUT=5V) RFS – ontime(VOUT=3.3V) RFS – ontime(VOUT=1V)

Detecting the ON resistance (between SW and PGND voltage) of MOSFET a

t

low side, it set the over current voltage protection.

Over current reference voltage (ILIM_ref) is determined as in formula(12) below.

10k

RILIM[kΩ] ×RON[mΩ]

ILIM_ref=

(RILIM: Resistance for setting of over current voltage protection value[kΩ]

RON: Low side ON resistance value of FET[mΩ])

[A]・・・(12)

[nsec]・・・(14)

VOUT

VIN ×1

Ton [kHz]・・・(15)

0

0.5

1

1.5

2

2.5

0 20 40 60 80 100 120

RFS[kΩ]

ontime[us]

VIN=7V

VIN=12V

VIN=21V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 20 40 60 80 100 120

RFS[kΩ]

ontime[us]

VIN=7V

VIN=12V

VIN=21V

0

0.5

1

1.5

2

2.5

3

3.5

0 20 40 60 80 100 120

RFS[kΩ]

ontime[us]

VIN=7V

VIN=12V

VIN=21V

VOUT・RFS

VIN

However, the value, which set the over current protection actually, is

determined by the formula (13) below.

ILIM_ref +

Iocp=⊿IL

1

2

ILIM_ref +

=×

1

2

I

f

VIN - Vo

L

×Vo

VIN

× ・・・(13)

VIN

L

Co

VOUT

PGND

SW

RILIM

Coil current

Iocp

ILIM_re

f

(⊿IL:Coil ripple current[A]、VIN:Input voltage[V]、Vo:Output voltage [V]

f:Switching frequency [HZ]、L:Coil inductance [H])

10k

RILIM[kΩ] ×RON[mΩ]

Iocp=+ ×

1

2

I

f

VIN - Vo

L

×Vo

VIN

× ＞ 5

Technical Note

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BD9528AMUV

8. Relation between output voltage and frequency

Because the BD9528AMUV is TON time focused regulator controller, if output current is up, switching loss of Coil,

MOSFET and output capacitor will increase, and frequency will be fast.

Loss of each Coil, MOSFET and output capacitor are below.

Regarding those loss above and frequency formula, it is determined below.

However, real-life considerations (such as parasitic resistance element of Layout pattern) must be factored in as they

affect the loss, please confirm in reality by the instrument.

VOUT

VIN

① Coil loss = IOUT2 × DCR

② MOSFET(High Side) loss = IOUT2 × Ronh ×

VIN

③ MOSFET(Low Side) loss = IOUT2 × RonL × (1- VOUT )

VIN × IOUT × Ton

VOUT × IOUT + ① + ② + ③

T (=1/Freq) = ・・・(17)

(Ronh : ON resistance of high side MOSFET, Ronl : ON resistance of low side MOSFET,

ESR : Output capacitor equivalent cascade resistance)

Technical Note

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BD9528AMUV

●I/O Equivalent Circuit

1, 24pin (SW2, SW1) 2, 23pin (HG2, HG1) 3, 22pin (BOOT2, BOOT1)

4, 21pin (EN2, EN1) 5, 20pin (PGOOD2, PGOOD1) 6, 19pin (SS2, SS1)

12pin (REF) 11, 14pin (FB2, FB1) 10, 15pin (FS2, FS1)

16, 18pin (MCTL2, MCTL 1) 9pin (CTL) 26, 31pin (LG1, LG2)

BOOT BOOT

SW

REG1

HG

SW

REG1

HG

BOOT

REG1

VIN

Technical Note

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BD9528AMUV

●I/O Equivalent Circuit

7, 27pin (Vo2, Vo1) 28pin (REG2) 29pin (REG1)

30pin (VIN) 8, 17pin (ILIM2, ILIM1)

REG1 VIN VIN

Technical Note

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BD9528AMUV

●Evaluation Board Circuit (Vo1=5V/8A, f1=300kHz Vo2=3.3V/8A f2=300kHz)

DESIGNATION RATING PART No. COMPANY DESIGNATION RATING PART No. COMPANY

R1 0Ω - - C4 0.1uF(6.3V) GRM21BB10J104KD MURATA

R5 68kΩ MCR03 ROHM C5 2200pF GRM188B11H102KD MURATA

R6 68kΩ MCR03 ROHM C6 2200pF GRM188B11H102KD MURATA

R7 75kΩ MCR03 ROHM C7 0.47uF GRM188B11A474KD MURATA

R8 75kΩ MCR03 ROHM C8 0.47uF GRM188B11A474KD MURATA

R9 0Ω - - C9 10uF(25V) GRM31CB31E106KA75 MURATA

R10 0Ω - - C12 10uF(25V) GRM31CB31E106KA75 MURATA

R11 0Ω - - C14 330uF 6TPE330MI SANYO

R12 0Ω - - C18 330uF 6TPE330MI SANYO

R13 0Ω - - C30 1000pF GRM1882C1H102JA01 MURATA

R14 0Ω - - C31 1000pF GRM1882C1H102JA01 MURATA

R15 100kΩ MCR03 ROHM (D1) (Diode) (RSX501L-20) (ROHM)

R16 100kΩ MCR03 ROHM (D2) (Diode) (RSX501L-20) (ROHM)

R17 56kΩ MCR03 ROHM L1 2.2uH FDVE1040-2R2M TOKO

R18 9.1kΩ MCR03 ROHM L2 2.2uH FDVE1040-2R2M TOKO

R19 30kΩ MCR03 ROHM Q1 FET RMW130N03 ROHM

R20 8.2kΩ MCR03 ROHM Q2 FET RMW130N03 ROHM

C1 10uF(25V) GRM31CB31E106KA75 MURATA Q3 FET RMW130N03 ROHM

C2 10uF(10V) GRM21BB10J106KD MURATA Q4 FET RMW130N03 ROHM

C3 10uF(6.3V) GRM21BB10J106KD MURATA U1 - BD9528AMUV ROHM

note) Without any value of ripple(about 10mV), there is a possibility of FB signal not acting stable switching due to the

adoption of comparator control method. Please use in condition with enough ripple voltage either by ①reducing the

L-value of coil, or ②using big output capacitor of ESR. Ripple voltage can be generated in FB terminal by adding

capacitor in parallel to resistor (R17, R19) of FB terminal, but because it becomes delicate to noise from output

(Vo1/Vo2) line it is not recommended. Also condition of stable action gets effected by layout of board, etc., so please

give full attention.

VIN

CTL

EN1

EN2

REG1

REG2

REF

SS1

FS1

BOOT1

HG1

SW1

LG1

PGND1

FB1

BOOT2

HG2

SW2

LG2

PGND2

VIN

12V

C1

CTL

EN1

EN2

CTL

EN1

EN2

VIN

REG1

5V

REG2

3.3

V

C2

C3

C4

C5 C6

Q3

Q4

VIN VIN

C12

SW2

D2

Q1

Q2

C7

VIN VIN

C9

SW1

D1

30

9

21

4

29

28

12

19

6

15

22

23

24

26

25

14

3

2

1

31

32

BD9528AMUV

R1

R12

R13

R14

R10

R9

R11

L2

R19

VO2

C18

L1

R17

VO1

C14

FS2

10

MCTL1

A

GND

FB2

PGOOD1

PGOOD2

C8

REG1

REG1 PGOOD2

PGOOD1

18

13

MCTL1

11

20

5

R15

R16

SS2

Vo1

Vo2

ILIM2

8

ILIM1

17

27

7

R5

R6

R7

R8

R20

R18

MCTL2

16

Power Ground

A

nalog Ground

C30

C31

Technical Note

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BD9528AMUV

●Handling method of unused pin during using only DC/DC 1ch

If using only 1ch DC/DC and 2ch pin is set to be off at all times, please manage the unused pin as diagram below.

PIN No, PIN name Management

1 SW2 GND

2 HG2 Open

3 BOOT2 Open

4 EN2 GND

5 PGOOD2 GND

6 SS2 GND

7 Vo2 GND

8 ILIM2 GND

10 FS2 GND

11 FB2 GND

31 LG2 Open

VIN

CTL

EN1

EN2

REG1

REG2

REF

SS1

FS1

BOOT1

HG1

SW1

LG1

PGND1

FB1

BOOT2

HG2

SW2

LG2

PGND2

VIN

12V

C1

CTL

EN1

CTL

EN1

VIN

REG1

5V

REG2

3.3

V

C2

C3

C4

C5

Q1

Q2

C7

VIN VIN

C9 C10

SW1

D1

30

9

21

4

29

28

12

19

6

15

22

23

24

26

25

14

3

2

1

32

BD9528AMUV

R1

R10

R9

R11

L1

R17

VO1

C14

FS2

10

MCTL1

A

GND

FB2

PGOOD1

PGOOD2

REG1 PGOOD1

18

13

MCTL1

11

20

5

R15

SS2

Vo1

Vo2

ILIM2

8

ILIM1

17

27

7

R5

R7

R18

MCTL2

16

Technical Note

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BD9528AMUV

●Example of PCB layout

SW2

HG2

BOOT2

EN2

PGOOD2

SS2

Vo2

ILIM2

CTL

FS2

FB2

REF

AGND

FB1

FS1

MCTL2

ILMI1

MCTL1

SS1

PGOOD1

EN1

BOOT1

SW1

PGND1

LG1

Vo1

REG2

REG1

VIN

LG2

PGND2

HG1

L-FET

(CH2)

Vo2

Vo1

L-FET

(CH1)

L

Co

Cin

R

C

R

C

High current GND

‘Silent’GND

H-FET

(CH2)

VIN

H-FET

(CH1)

① Because high pulse current rush into power loop, consisted of input capacitor Cin, output inductor L and output

capacitor Co, this part layout should be built at parts side (upper side) including GND pattern.

Also, drawing via formation in power loop line should be avoided.

(The reason is that it will be a factor of noise because via oneself holds some nH parasitic inductance)

② FB pin has comparatively high impedance, so floating capacity should be minimum as possible.

And feedback wiring from output should be taken properly, and shielding, not going through around L (because of

magnetic). Please be careful in drawing.

③ Trace from SW node pin to inductor should be cut short. And both inductor element pattern should be kept away.

(Closer wiring has SW node noise influence Vo by parasitic capacity between wiring). This layout example shows that

SW node is outside, but if the application board will be like that, SW node should be shielded.

Please consider the influence to other circuit.

④ Input capacitor Cin should be placed close to IC with low inductance.

If that is difficult, please place a capacitor for high frequency removal with PKG size small like 0.1uF (ESL small).

⑤ 2nd layer and 3rd layer are plain GND, so connect from parts side GND to plain GND by low impedance with many via as

possible. Inner GND is only for shielding, so that no to form loop for high current.

⑥ Please take GND pattern space widely, and design layout to be able to increase radiation efficiency.

⑦ FS pin and ILIM pin has high impedance. External resistor should be connected to “Silent GND”.

Technical Note

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BD9528AMUV

●Operation Notes and Precautions

1. This integrated circuit is a monolithic IC, which (as shown in the figure below), has P+ isolation in the P substrate and

between the various pins. A P-N junction is formed from this P layer and N layer of each pin, with the type of junction

depending on the relation between each potential, as follows:

・When GND＞ element A＞ element B, the P-N junction is a diode.

・When element B＞GND element A, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, as well as operating malfunctions and physical damage. Therefore, be careful to avoid

methods by which parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an

input pin.

2. In some modes of operation, power supply voltage and pin voltage are reversed, giving rise to possible internal circuit

damage. For example, when the external capacitor is charged, the electric charge can cause a VCC short circuit to the

GND. In order to avoid these problems, inserting a VCC series countercurrent prevention diode or bypass diode

between the various pins and the VCC is recommended.

3. Absolute maximum rating

Although the quality of this IC is rigorously controlled, the IC may be destroyed when applied voltage or operating

temperature exceeds its absolute maximum rating. Because short mode or open mode cannot be specified when the IC

is destroyed, it is important to take physical safety measures such as fusing if a special mode in excess of absolute

rating limits is to be implemented.

4. GND potential

Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the

operating mode.

5. Thermal design

In order to build sufficient margin into the thermal design, give proper consideration to the allowable loss (Power

Dissipation) in actual operation.

6. Short-circuits between pins and incorrect mounting position

When mounting the IC onto the circuit board, be extremely careful about the orientation and position of the IC. The IC

may be destroyed if it is incorrectly positioned for mounting. Do not short-circuit between any output pin and supply pin

or ground, or between the output pins themselves. Accidental attachment of small objects on these pins will cause

shorts and may damage the IC.

7. Operation in strong electromagnetic fields

Use in strong electromagnetic fields may cause malfunctions. Use extreme caution with electromagnetic fields.

8. Thermal shutdown circuit

This IC is provided with a built-in thermal shutdown (TSD) circuit, which is activated when the operating temperature

reaches 175℃ (standard value), and has a hysteresis range of -15℃ (standard value). When the IC chip temperature

rises to the threshold, all the inputs automatically turn OFF. Note that the TSD circuit is provided for the exclusive

purpose shutting down the IC in the presence of extreme heat, and is not designed to protect the IC per se or guarantee

performance when or after extreme heat conditions occur. Therefore, do not operate the IC with the expectation of

continued use or subsequent operation once the TSD is activated.

Resistor Transistor (NPN)

N

N P+ P+

P

P substrate

GND

Parasitic element

Pin A

N

N P+ P+

P

P substrate

GND

Parasitic element

Pin B C B

E

N

GND

Pin A

P

aras

iti

c

element

Pin B

Other adjacent elements

E

B C

GND

P

aras

iti

c

element

VCC

Counter current prevention diode

Bypass diode

Technical Note

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BD9528AMUV

9. Capacitor between output and GND

When a larger capacitor is connected between the output and GND, Vcc or VIN shorted with the GND or 0V line – for

any reason – may cause the charged capacitor current to flow to the output, possibly destroying the IC. Do not connect

a capacitor larger than 1000uF between the output and GND.

10. Precautions for board inspection

Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be

certain to use proper discharge procedure before each process of the operation. To prevent electrostatic accumulation

and discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage,

and continue observing ESD-prevention procedures in all handling, transfer and storage operations. Before attempting

to connect components to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply

is OFF before removing any component connected to the test setup.

11. GND wiring pattern

When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is

recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change

stemming from the wiring resistance and high current does not cause any voltage change in the small-signal GND. In

the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND.

●Heat Dissipation Characteristics

Ambient Temperature [Ta]

Power Dissipation [Pd]

150125100755025 0

200

400

600

800

1000

[℃]

[mW]

880mW

380mW

74.2mm×74.2mm×1.6mm Glass-epoxy PCB

θj-a=142.0℃/W

IC Only θj-a=328.9℃/W

Technical Note

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BD9528AMUV

●Ordering Part Number

B D 9 5 2 8 A MU V -E 2

Package

MUV : VQFN032V5050

Packaging and forming specification

E2: Embossed tape and reel

(Unit : mm)

VQFN032V5050

0.08 S

S

1.0MAX

(0.22)

0.02+0.03

-

0.02

24

81

9

32

16

25 17

0.5

0.75

0.4±0.1

3.4±0.1

0.25 +0.05

-

0.04

C0.2

5.0±0.1

1PIN MARK

∗

Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

2500pcs

E2

()

Direction of feed

Reel 1pin

R1120

A

www.rohm.com

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Examples of application circuits, circuit constants and any other information contained herein

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