50 mA/500 mA, Ultralow Power Step-Down Regulator with Battery Voltage Monitor ADP5302 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT VIN = 2.15V TO 6.50V 2.2H SW PVIN 10F ADP5302 10F (LFCSP-10) ON PGND EN OFF PWM HYS VOUT SYNC/ MODE FB STOP VINOK AGND VID STOP SW EPAD VID0: 1.2V VID1: 1.5V VID2: 1.8V VID3: 2.0V R0 VID4: 2.1V VID5: 2.2V VID6: 2.3V VID7: 2.4V VID8: 2.5V VID9: 2.6V VID10: 2.7V VID11: 2.8V VID12: 2.9V VID13: 3.0V VID14: 3.3V VID15: 3.6V 13443-001 Input supply voltage range: 2.15 V to 6.50 V Operates down to 2.00 V Ultralow 240 nA quiescent current with no load Selectable output voltages of 1.2 V to 3.6 V, or 0.8 V to 5.0 V 1.5% output accuracy over the full temperature range in pulse-width modulation (PWM) mode Selectable hysteresis mode or PWM operation mode Output current Up to 50 mA in hysteresis mode Up to 500 mA in PWM mode VINOK flag to monitor input battery voltage Ultrafast stop switching control 100% duty cycle operation mode 2 MHz switching frequency with optional synchronization input from 1.5 MHz to 2.5 MHz Quick output discharge (QOD) option UVLO, OCP, and TSD protection 10-lead, 3 mm x 3 mm LFCSP package Junction temperature: -40C to +125C Figure 1. APPLICATIONS Energy (gas, water) metering Portable and battery-powered equipment Medical applications Keep-alive power supplies GENERAL DESCRIPTION The ADP5302 is a high efficiency, ultralow quiescent current step-down regulator that draws only 240 nA quiescent current to regulate the output at no load. The ADP5302 runs from an input voltage of 2.15 V to 6.50 V, allowing the use of multiple alkaline or NiMH cells, Li-Ion cells, or other power sources. The output voltage is selectable from 0.8 V to 5.0 V by an external, dynamic voltage identification (VID) resistor and a factory fuse. The total solution requires only four tiny external components. The ADP5302 can operate between hysteresis mode and PWM mode via the SYNC/MODE pin. In hysteresis mode, the regulator achieves excellent efficiency at less than 1 mW and provides up to 50 mA of output current. In PWM mode, the regulator produces a lower output ripple and supplies up to 500 mA of output current. The flexible configuration capability during operation of the device enables very efficient power management to meet both long battery life and low system noise requirements. Rev. B The ADP5302 integrates an ultralow power comparator with a factory programmable voltage reference to monitor the input battery voltage. The regulator runs at a 2 MHz switching frequency in PWM mode, and the SYNC/MODE pin can be synchronized to an external clock from 1.5 MHz to 2.5 MHz. The ADP5302 includes an extra STOP pin that can temporarily disable the regulator switching; in this way, a quiet system environment can be achieved to benefit the noise sensitive circuitry, which includes data conversion, RF data transmission, and analog sensors. Other key features in the ADP5302 include separate enabling, QOD, and safety features, such as overcurrent protection (OCP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5302 is available in a 10-lead, 3 mm x 3 mm LFCSP package rated for the -40C to +125C junction temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2015-2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5302 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Short-Circuit Protection............................................................ 15 Applications ....................................................................................... 1 Soft Start ...................................................................................... 15 Typical Application Circuit ............................................................. 1 Startup with Precharged Output .............................................. 15 General Description ......................................................................... 1 100% Duty Operation ................................................................ 15 Revision History ............................................................................... 2 Active Discharge ......................................................................... 15 Detailed Functional Block Diagram .............................................. 3 VINOK Function........................................................................ 15 Specifications..................................................................................... 4 STOP Switching .......................................................................... 16 Absolute Maximum Ratings............................................................ 6 Thermal Shutdown .................................................................... 16 Thermal Resistance ...................................................................... 6 Applications Information .............................................................. 17 ESD Caution .................................................................................. 6 External Component Selection ................................................ 17 Pin Configuration and Function Descriptions ............................. 7 Selecting the Inductor ................................................................ 17 Typical Performance Characteristics ............................................. 8 Output Capacitor........................................................................ 17 Theory of Operation ...................................................................... 14 Input Capacitor ........................................................................... 18 Buck Regulator Operational Modes......................................... 14 Efficiency ..................................................................................... 18 Oscillator and Synchronization ................................................ 14 Printed Circuit Board Layout Recommendations ................. 19 Adjustable and Fixed Output Voltages .................................... 14 Typical Application Circuits ......................................................... 20 Undervoltage Lockout (UVLO) ............................................... 15 Factory Programmable Options ................................................... 21 Enable/Disable ............................................................................ 15 Outline Dimensions ....................................................................... 22 Current Limit .............................................................................. 15 Ordering Guide .......................................................................... 22 REVISION HISTORY 9/2019--Rev. A to Rev. B Changes to Adjustable and Fixed Output Voltages Section ........... 15 Changes to Table 8, Table 9, Table 10, and Table 11 .................. 21 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 6/2016--Rev. 0 to Rev. A Changes to Features Section and General Description Section....... 1 Change to SYNC Clock Range Parameter, Table 1 ...................... 4 Change to Table 4 ............................................................................. 7 Change to Oscillator and Synchronization Section ................... 14 9/2015--Revision 0: Initial Version Rev. B | Page 2 of 22 Data Sheet ADP5302 DETAILED FUNCTIONAL BLOCK DIAGRAM VINOK PVIN PVIN VINOK_TH DRIVER ILIM_PWM PVIN SW ILIM_HYS 1.2V STOP -0.6A (PWM) 0A (HYS) CONTROL LOGIC FORCE SLEEP 0.4V PVIN PWM DRIVER SLOPE COMPENSATION PGND STANDBY 0.808V 0.8V FB INTERNAL FEEDBACK RESISTOR DIVIDE 0.8V V TO I VID MODE 1.2V 0.4V SOFT START EN PVIN UVLO AGND BAND GAP BIAS AND HOUSEKEEPING 1.2V 0.4V SYNC/ MODE SYNC KEEP ALIVE BLOCK 2MHz OSC MODE Figure 2. Detailed Functional Block Diagram Rev. B | Page 3 of 22 ADP5302 13443-002 2.06V 2.00V ADP5302 Data Sheet SPECIFICATIONS VIN = 3.6 V, VOUT = 2.5 V, TJ = -40C to +125C for minimum and maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1. Parameter INPUT SUPPLY VOLTAGE RANGE SHUTDOWN CURRENT Symbol VIN ISHUTDOWN QUIESCENT CURRENT Operating Quiescent Current in Hysteresis Mode IQ_HYS Operating Quiescent Current in Hysteresis Mode Operating Quiescent Current in PWM Mode UNDERVOLTAGE LOCKOUT UVLO Threshold Rising Falling OSCILLATOR CIRCUIT Switching Frequency in PWM Mode Feedback (FB) Threshold of Frequency Fold SYNCHRONIZATION THRESHOLD1 SYNC Clock Range SYNC High Level Threshold SYNC Low Level Threshold SYNC Duty Cycle Range SYNC/MODE Leakage Current MODE TRANSITION Transition Delay from Hysteresis Mode to PWM Mode EN PIN Input Voltage Threshold High Low Input Leakage Current STOP SWITCHING PWM Switching Stop Delay PWM Switching Resume Delay FB PIN Output Options by VID Resistor PWM Mode Fixed VID Code Voltage Accuracy Adjustable VID Code Voltage Accuracy Min 2.15 Unit V nA nA Test Conditions/Comments 18 18 Max 6.50 40 130 240 360 nA -40C TJ +85C 240 640 520 1500 nA nA IQ_HYS2 2.4 3.2 A -40C TJ +125C 100% duty cycle operation, VIN = 3.0 V, VOUT set to 3.3 V STOP = high; VIN = 3.6 V, VSTOP = 3.6 V IQ_PWM UVLO 425 630 A VUVLO_RISING VUVLO_FALLING 2.06 2.00 2.14 V V 2.0 0.3 2.3 MHz V 2.5 MHz V V ns 1.90 fSW VOSC_FOLD 1.7 SYNCCLOCK SYNCHIGH SYNCLOW SYNCDUTY 1.5 1.2 Typ 100 ISYNC_LEAKAGE 50 tHYS_TO_PWM 20 VIH VIL IEN_LEAKAGE 0.4 1/fSW - 150 150 1.2 0.4 25 tSTOP_RISE_DELAY tSTOP_FALL_DELAY 10 20 VEN = 0 V, -40C TJ +85C VEN = 0 V, -40C TJ +125C nA VSYNC/MODE = 3.6 V Clock cycles SYNC/MODE goes logic high from logic low V V nA ns ns STOP goes logic high from logic low STOP goes logic low from logic high VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in various factory options VFB_PWM_FIX -0.6 +0.6 % VFB_PWM_ADJ -1.2 -1.5 +1.2 +1.5 % % TJ = 25C, output voltage setting via factory fuse -40C TJ +125C Output voltage setting via the VID resistor Rev. B | Page 4 of 22 Data Sheet Parameter Hysteresis Mode Fixed VID Code Threshold Accuracy from Active Mode to Standby Mode Adjustable VID Code Threshold Accuracy from Active Mode to Standby Mode Hysteresis of Threshold Accuracy from Active Mode to Standby Mode Feedback Bias Current SW PIN High-Side Power FET On Resistance Low-Side Power FET On Resistance Current-Limit in PWM Mode Peak Current in Hysteresis Mode Minimum On Time VINOK PIN VINOK Monitor Threshold Range VINOK Monitor Accuracy ADP5302 Symbol Min VFB_HYS_FIX VFB_HYS_ADJ Typ Max Unit Test Conditions/Comments -0.75 +0.75 % TJ = 25C -2.5 -3 +2.5 +3 % % -40C TJ +125C -40C TJ +125C VFB_HYS (HYS) 1 IFB 66 25 95 45 nA nA Output Option 0, VOUT = 2.5 V Output Option 1, VOUT = 1.3 V RDS (ON) H RDS (ON) L ILIM_PWM ILIM_HYS tMIN_ON 386 299 1000 265 40 520 470 1200 m m mA mA ns Pin to pin measurement Pin to pin measurement SYNC/MODE = high SYNC/MODE = low V % % % s s A mV Factory programmable TJ = 25C -40C TJ +125C Factory trim, 1 bit (350 s, 2800 s) Delay from the EN pin being pulled high VVINOK (RISE) 800 2.05 -1.5 -3 % 70 5.15 +1.5 +3 VINOK Monitor Threshold Hysteresis VINOK Rising Delay VINOK Falling Delay Leakage Current for VINOK Pin Output Low Voltage for VINOK Pin SOFT START Default Soft Start Time Start-Up Delay VVINOK (HYS) tVINOK_RISE tVINOK_FALL IVINOK_LEAKAGE VVINOK_LOW 1.5 190 130 0.1 50 tSS tSTART_DELAY 350 2 s ms COUT DISCHARGE SWITCH ON RESISTANCE THERMAL SHUTDOWN Threshold Hysteresis RDIS 290 TSHDN THYS 142 127 C C 1 SYNC refers to the synchronization function of the multifunction SYNC/MODE pin only. Rev. B | Page 5 of 22 1 100 IVINOK = 100 A ADP5302 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter PVIN to PGND SW to PGND FB to AGND VID to AGND EN to AGND VINOK to AGND SYNC/MODE to AGND STOP to AGND PGND to AGND Storage Temperate Range Operational Junction Temperature Range Rating -0.3 V to +7 V -0.3 V to PVIN + 0.3 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +0.3 V -65C to +150C -40C to +125C JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. JC is the thermal resistance from the operating portion of the device to the outside surface of the package (case) closest to the device mounting area. Table 3. Thermal Resistance Package Type 10-Lead, 3 mm x 3 mm LFCSP ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 6 of 22 JA 57 JC 0.86 Unit C/W Data Sheet ADP5302 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 10 PVIN EN 1 SYNC/MODE 3 VID 4 FB 5 ADP5302 TOP VIEW (Not to Scale) 9 SW 8 PGND 7 AGND 6 VINOK NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION. 13443-003 STOP 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic EN STOP 3 SYNC/MODE 4 VID 5 6 7 8 9 10 EPAD FB VINOK AGND PGND SW PVIN EPAD Description Enable Input for the Regulator. A logic low on this pin disables the regulator. Stop Switching Input Signal. When this pin is logic high, the regulator stops switching. When this pin is logic low, the regulator resumes switching. Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz. PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode. Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the output voltage of the regulator (see Table 5). Feedback Sensing Input for the Regulator. Input Power-Good Signal. This open-drain output is the power-good signal for the input voltage. Analog Ground. Power Ground. Switching Node Output for the Regulator. Power Input for the Regulator. Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal dissipation. Rev. B | Page 7 of 22 ADP5302 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN =3.6 V, VOUT = 2.5 V, L1 = 2.2 H, CIN = COUT = 10 F, fSW = 2 MHz, TA = 25C, unless otherwise noted. 100 100 90 90 60 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 50 40 0.01 0.1 1 LOAD CURRENT (mA) 10 40 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V 100 100 90 90 EFFICIENCY (%) 80 70 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 0.01 0.1 1 LOAD CURRENT (mA) 10 80 70 VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 0.001 13443-005 EFFICIENCY (%) VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V 40 0.001 70 Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V 0.01 0.1 1 LOAD CURRENT (mA) 13443-008 30 0.001 80 13443-007 EFFICIENCY (%) 70 13443-004 EFFICIENCY (%) 80 10 Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V 100 100 90 80 90 70 60 50 40 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 30 VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 60 50 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 20 10 0 0 100 200 300 LOAD CURRENT (mA) 400 Figure 9. PWM Efficiency vs. Load Current, VOUT = 1.2 V Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V Rev. B | Page 8 of 22 500 13443-009 EFFICIENCY (%) 80 13443-006 EFFICIENCY (%) 70 ADP5302 100 90 90 80 80 70 70 60 50 40 VIN = 2.5V VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 20 10 0 100 200 300 LOAD CURRENT (mA) 400 40 VIN = 2.5V 30 VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 20 10 500 0 0 100 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 30 10 0 0 100 200 300 LOAD CURRENT (mA) 400 50 40 VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 20 10 500 0 0 QUIESCENT CURRENT (nA) 600 80 60 40 400 500 -40C +25C +85C +125C 500 400 300 200 20 2.9 3.5 4.1 4.7 5.3 5.9 VIN (V) 6.5 13443-012 SHUTDOWN CURRENT (nA) 200 300 LOAD CURRENT (mA) 700 -40C +25C +85C +125C 100 0 2.3 100 Figure 14. PWM Efficiency vs. Load Current, VOUT = 3.3 V 160 120 500 60 Figure 11. PWM Efficiency vs. Load Current, VOUT = 2.5 V 140 400 30 VIN = 3.0V VIN = 3.6V VIN = 4.2V VIN = 5.0V VIN = 6.0V 20 200 300 LOAD CURRENT (mA) Figure 13. PWM Efficiency vs. Load Current, VOUT = 1.8 V 13443-011 EFFICIENCY (%) Figure 10. PWM Efficiency vs. Load Current, VOUT = 1.5 V 100 100 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 VIN (V) Figure 15. Hysteresis Quiescent Current vs. VIN, SYNC/MODE = Low Figure 12. Shutdown Current vs. VIN, EN = Low Rev. B | Page 9 of 22 13443-015 0 50 13443-014 30 60 13443-013 EFFICIENCY (%) 100 13443-010 EFFICIENCY (%) Data Sheet ADP5302 Data Sheet 810 801 FEEDBACK VOLTAGE (mV) FEEDBACK VOLTAGE (mV) 808 800 799 798 ACTIVE TO STANDBY 806 804 STANDBY TO ACTIVE 802 800 798 796 -40 25 85 TEMPERATURE (C) 792 13443-016 125 Figure 16. Feedback Voltage vs. Temperature, PWM Mode -40C +25C +125C -40C +25C +125C LOW-SIDE RDS (ON) L (m) 450 600 500 400 300 400 350 300 2.9 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 13443-017 250 200 2.3 2.9 3.5 Figure 17. High-Side RDS (ON) H vs. VIN 4.1 4.7 VIN (V) 5.3 5.9 6.5 Figure 20. Low-Side RDS (ON) L vs. VIN 1200 1090 1150 PEAK CURRENT LIMIT (mA) 1040 990 940 890 -40C +25C +125C 1100 1050 1000 950 900 840 -40 25 85 TEMPERATURE (C) 125 Figure 18. Peak Current Limit vs. Temperature 800 2.3 2.9 3.5 4.1 4.7 5.3 VIN (V) Figure 21. Peak Current Limit vs. VIN Rev. B | Page 10 of 22 5.9 6.5 13443-021 850 13443-018 PEAK CURRENT LIMIT (mA) 125 500 700 HIGH-SIDE RDS (ON) H (m) 25 85 TEMPERATURE (C) Figure 19. Feedback Voltage vs. Temperature, Hysteresis Mode 800 200 2.3 -40 13443-020 797 13443-019 794 Data Sheet ADP5302 2.10 2.3 2.04 2.02 FALLING 2.00 1.96 -40 25 85 TEMPERATURE (C) 13443-022 1.98 125 2.1 2.0 1.9 1.8 1.7 2.3 2.9 3.5 4.1 4.7 VIN (V) 5.3 5.9 6.5 Figure 25. Switching Frequency vs. VIN Figure 22. UVLO Threshold, Rising and Falling vs. Temperature VOUT 1 VOUT (AC) 1 SW 4 IL 2 IL 2 4 M 200s A CH4 T 39.60% 140mA CH1 10.0mV Figure 23. Steady Waveform of Hysteresis Mode, ILOAD = 1 mA 1.52V VIN VOUT 3 VOUT 1 IL IL 4 SW SW 2 2 CH1 1.00V CH3 2.00V B B W W CH2 5.00V M 200s A CH1 CH4 500mA BW T 50.60% 1.22V CH1 500mV CH3 2.00V B W B W CH2 5.00V M 100s A CH1 CH4 500mA BW T 40.00% Figure 27. Soft Start with Precharge Function Figure 24. Soft Start, ILOAD = 300 mA (IL is the Inductor Current) Rev. B | Page 11 of 22 1.05V 13443-027 4 CH2 2.00V M 1.00s A CH2 CH4 200mA BW T 45.20% Figure 26. Steady Waveform of PWM Mode, ILOAD = 300 mA VIN 1 B W 13443-026 CH2 2.00V CH4 500mA 13443-023 SW CH1 100mV 13443-024 UVLO THRESHOLD (V) RISING 2.06 -40C +25C +125C 2.2 13443-025 SWITCHING FREQUENCY (kHz) 2.08 ADP5302 Data Sheet VOUT (AC) 1 1 VOUT (AC) IOUT IOUT B CH1 50.0mV M 200s A CH4 CH4 50.0mA BW T 20.80% W 111mA CH1 50.0mV Figure 28. Load Transient of Hysteresis Mode, ILOAD from 0 mA to 50 mA B W M 200s A CH4 CH4 200mA BW T 20.40% 308mA 13443-031 4 13443-028 4 Figure 31. Load Transient of PWM Mode, ILOAD from 125 mA to 375 mA 1 1 VOUT (AC) VOUT (AC) VIN VIN IL 4 3 IL 4 2 SW 2 CH2 5.00V M 2.00ms A CH3 CH4 500mA BW T 30.00% 4.72V CH1 10.0mV CH3 2.00V Figure 29. Line Transient of Hysteresis Mode, ILOAD = 10 A, VIN from 2.5 V to 6 V B W B W CH2 5.00V M 2.00ms A CH3 CH4 500mA BW T 30.20% 4.28V 13443-032 B W B W CH1 50.0mV CH3 2.00V 13443-029 SW Figure 32. Line Transient of PWM Mode, ILOAD = 500 mA, VIN from 2.5 V to 6 V VOUT VIN 1 VOUT VIN 2 1 IL VIN_OK B B W W M 10.0ms A CH3 CH4 200mA BW T 40.20% 4.80V 13443-030 CH1 1.00V CH3 1.00V CH1 2.00V CH3 1.00V Figure 30. Input Voltage Ramp-Up and Ramp-Down in Hysteresis Mode Rev. B | Page 12 of 22 B W B W CH2 1.00V B W M 4.00ms A CH3 T 20.20% 980mV Figure 33. VINOK Function at VINOK Threshold = 3.0 V 13443-033 3 4 Data Sheet ADP5302 VOUT VOUT 1 1 IL IL 4 4 SW SW CH1 2.00V B W CH2 2.00V CH4 500mA M 10.0s A CH1 T 40.20% 1.44V CH1 2.00V CH2 2.00V CH4 500mA B W Figure 34. Output Short M 1.00ms A CH1 T 40.20% 1.44V 13443-037 2 13443-034 2 Figure 37. Output Short Recovery EN 1 SYNC/ MODE 3 VOUT SW 2 1 2 CH2 2.00V M 400ns A CH2 T 50.00% 1.40V CH1 1.00V CH3 2.00V Figure 35. Synchronized to 2.5 MHz B W B W CH2 2.00V B W M 4.00ms A CH3 T 40.00% 1.64V 13443-038 B W 520mV 13443-039 CH1 2.00V 13443-035 SW Figure 38. Quick Output Discharge Function 1 VOUT (AC) VOUT 1 VSTOP SYNC/MODE 3 3 SW 2 2 CH1 100mV CH3 2.00V CH2 2.00V M 20.0s A CH3 T 39.80% 1.56V 13443-036 SW B W B W CH1 2.00V CH3 2.00V Figure 36. Hysteresis Mode to PWM Mode with 10 mA Load Current B B W CH2 2.00V M 100ms A CH3 W Figure 39. Stop Switching Function Rev. B | Page 13 of 22 ADP5302 Data Sheet THEORY OF OPERATION The ADP5302 is a high efficiency, ultralow quiescent current step-down regulator in a 10-lead LFCSP package, designed to meet demanding performance and board space requirements. The device enables direct connection to a wide input voltage range of 2.15 V to 6.50 V, allowing the use of multiple alkaline/NiMH or Li-Ion cells and other power sources. BUCK REGULATOR OPERATIONAL MODES The user can alternate between hysteresis mode and PWM mode during operation. The flexible configuration capability during operation of the device enables efficient power management to meet high efficiency and low output ripple requirements when the system switches between active mode and standby mode. OSCILLATOR AND SYNCHRONIZATION The ADP5302 operates at a typical 2 MHz switching frequency in PWM operation mode. PWM Mode In PWM mode, the buck regulator in the ADP5302 operates at a fixed frequency set by an internal oscillator. At the start of each oscillator cycle, the high-side MOSFET switch turns on and sends a positive voltage across the inductor. The inductor current increases until the current sense signal exceeds the peak inductor current threshold, which turns off the high-side MOSFET switch. This threshold is set by the error amplifier output. During the high-side MOSFET off time, the inductor current decreases through the low-side MOSFET until the next oscillator clock pulse starts a new cycle. Hysteresis Mode In hysteresis mode, the buck regulator in the ADP5302 charges the output voltage slightly higher than its nominal output voltage with PWM pulses by regulating the constant peak inductor current. When the output voltage increases until the output sense signal exceeds the hysteresis upper threshold, the regulator enters standby mode. In standby mode, the high-side and low-side MOSFETs and a majority of the circuitry are disabled to allow a low quiescent current, as well as high efficiency performance. During standby mode, the output capacitor supplies energy into the load and the output voltage decreases until it falls below the hysteresis comparator lower threshold. The buck regulator wakes up and generates the PWM pulses to charge the output again. Because the output voltage occasionally enters standby mode and then recovers, the output voltage ripple in hysteresis mode is larger than the ripple in PWM mode. Mode Selection The ADP5302 includes the SYNC/MODE pin to allow flexible configuration in hysteresis mode or PWM mode. When a logic high level is applied to the SYNC/MODE pin, the buck regulator is forced to operate in PWM mode. In PWM mode, the regulator can supply up to 500 mA of output current. The regulator can provide lower output ripple and output noise in PWM mode, which is useful for noise sensitive applications. When a logic low level is applied to the SYNC/MODE pin, the buck regulator is forced to operate in hysteresis mode. In hysteresis mode, the regulator draws only 240 nA of quiescent current (typical) to regulate the output under zero load, which allows the regulator to act as a keep-alive power supply in a battery-powered system. In hysteresis mode, the regulator supplies up to 50 mA of output current with a relatively large output ripple compared to PWM mode. The switching frequency of the ADP5302 can be synchronized to an external clock with a frequency range from 1.5 MHz to 2.5 MHz. The ADP5302 automatically detects the presence of an external clock applied to the SYNC/MODE pin, and the switching frequency transitions to the frequency of the external clock. When the external clock signal stops, the device automatically switches back to the internal clock. ADJUSTABLE AND FIXED OUTPUT VOLTAGES The ADP5302 provides adjustable output voltage settings by connecting one resistor through the VID pin to AGND. The VID detection circuitry works in the start-up period, and the voltage ID code is sampled and held in the internal register and does not change until the next power recycle. Furthermore, the ADP5302 provides a fixed output voltage programmed via the factory fuse. In this condition, connect the VID pin to the PVIN pin. For the output voltage settings, the feedback resistor divider is built into the ADP5302, and the feedback pin (FB) must be tied directly to the output. An ultralow power voltage reference and an integrated high impedance feedback divider network contribute to the low quiescent current. Table 5 lists the output voltage options by the VID pin configurations. A 1% accuracy resistor through VID to ground is recommended. Table 5. Output Voltage (VOUT) Options Using the VID Pin VID Configuration Short to ground Short to PVIN RVID = 499 k RVID = 316 k RVID = 226 k RVID = 174 k RVID = 127 k RVID = 97.6 k RVID = 76.8 k RVID = 56.2 k RVID = 43 k RVID = 32.4 k RVID = 25.5 k RVID = 19.6 k RVID = 15 k RVID = 11.8 k Rev. B | Page 14 of 22 Factory Option 0 (V) 3.0 2.5 3.6 3.3 2.9 2.8 2.7 2.6 2.4 2.3 2.2 2.1 2.0 1.8 1.5 1.2 VOUT Factory Option 1 (V) 3.1 1.3 5.0 4.5 4.2 3.9 3.4 3.2 1.9 1.7 1.6 1.4 1.1 1.0 0.9 0.8 Data Sheet ADP5302 All individual VID settings are available as internally fixed options. Contact your local Analog Devices, Inc., sales or distribution representative for more information on generating new models. UNDERVOLTAGE LOCKOUT (UVLO) The UVLO circuitry monitors the input voltage level on the PVIN pin. If the input voltage falls below 2.00 V (typical), the regulator turns off. After the input voltage rises above 2.06 V (typical), the soft start period initiates, and the regulator is enabled when the EN pin is high. ENABLE/DISABLE STARTUP WITH PRECHARGED OUTPUT The buck regulators in the ADP5302 include a precharged start-up feature to protect the low-side MOSFET from damage during startup. If the output voltage is precharged before the regulator turns on, the regulator prevents reverse inductor current-- which discharges the output capacitor--until the internal soft start reference voltage exceeds the precharged voltage on the feedback pin. 100% DUTY OPERATION A logic low on the enable pin immediately disables the regulator and brings the regulator into an extremely low current consumption state. When the input voltage approaches the output voltage, the ADP5302 stops switching and enters 100% duty cycle operation. The device connects the output via the inductor and the internal high-side power switch to the input. When the input voltage is charged again and the required duty cycle falls to 95% (typical), the buck regulator immediately restarts switching and regulation without allowing overshoot on the output voltage. In hysteresis mode, the ADP5302 draws an ultralow quiescent current of only 640 nA (typical) during 100% duty cycle operation. CURRENT LIMIT ACTIVE DISCHARGE The buck regulators in the ADP5302 have protection circuitry that limits the direction and the amount of current to a certain level that flows through the high-side MOSFET and the lowside MOSFET in cycle by cycle mode. The positive current limit on the high-side MOSFET limits the amount of current that can flow from the input to the output. The negative current limit on the low-side MOSFET prevents the inductor current from reversing direction and flowing out of the load. The regulator in the ADP5302 integrates an optional, factory programmable discharge switch from the switching node to ground. This switch turns on when its associated regulator is disabled, which helps discharge the output capacitor quickly. The typical value of the discharge switch is 290 for the regulator. The ADP5302 includes a separate enable pin. A logic high in the enable pin starts the regulator. Due to the low quiescent current design, it is typical for the regulator to start switching after a delay of few milliseconds from the enable pin (EN) being pulled high. SHORT-CIRCUIT PROTECTION The buck regulators in ADP5302 includes frequency foldback to prevent current runaway on a hard short. When the output voltage at the feedback pin falls below 0.3 V (typical), indicating the possibility of a hard short at the output, the switching frequency in PWM mode is reduced to one-fourth of the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. SOFT START The ADP5302 has an internal soft start function that ramps up the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This control prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the device. The typical default soft start time for the regulator is 350 s. By default, the discharge function is not enabled. The active discharge function can be enabled by the factory fuse. VINOK FUNCTION The ADP5302 includes an open-drain VINOK output that indicates the battery voltage status. The VINOK output becomes active high when the input voltage on the PVIN pin is above the reference threshold. When the input voltage falls below the reference threshold, the VINOK pin goes low. Note that a relatively typical long validation time 130 s exists for the status of the VINOK output to change due to the ultralow power comparator design. Different VINOK thresholds can be factory programmable from 2.05 V to 5.15 V in 50 mV steps. To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. A different soft start time (2800 s) can be programmed for the ADP5302 via the factory fuse. Rev. B | Page 15 of 22 ADP5302 Data Sheet STOP SWITCHING 2.54V The ADP5302 includes the STOP input pin, allowing the user to temporarily stop the regulator switching in hysteresis mode. 2.50V DC TO DC OUTPUT When a logic high level is applied to the STOP pin, the buck regulator is forced to stop the switching immediately. When a logic low level is applied to the STOP pin, the buck regulator resumes the switching. Note that a delay time in tens of nanoseconds exists from when the STOP signal goes high to when the signal fully stops switching. Figure 40 shows the STOP switching functionality in ADP5302. The STOP signal control is valid only when the regulator is enabled with the EN pin pulled high. Otherwise, the STOP signal is ignored if the EN pin is logic low. 2A OUTPUT LOAD STOP SIGNAL 13443-040 In some battery-powered systems, the microcontroller unit (MCU) commands the regulator to stop switching via the STOP signal. Then, the regulator relies on the output capacitor to supply the load. In this period, a quiet system environment can be achieved to benefit noise sensitive circuitry, such as data conversion, RF data transmission, and analog sensors. After the noise sensitive circuitry completes its task, the MCU controls the regulator as it resumes the switching regulation mode. DC TO DC SWITCHING 10ms OF mA Figure 40. STOP Switching Operation Status THERMAL SHUTDOWN If the ADP5302 junction temperature exceeds 142C, the thermal shutdown circuit turns off the IC except for the internal linear regulator. Extreme junction temperatures may be the result of high current operation, poor circuit board design, or high ambient temperature. A 15C hysteresis is included so that the ADP5302 does not return to operation after thermal shutdown until the junction temperature falls below 127C. When the device exits thermal shutdown, a soft start is initiated for each enabled channel. Rev. B | Page 16 of 22 Data Sheet ADP5302 APPLICATIONS INFORMATION This section describes the external components selection for the ADP5302. The typical application circuit is shown in Figure 41. 2.2H PVIN SW 10F MLCC VOUT = 1.8V 10F MLCC ADP5302 EN PGND (LFCSP-10) SYNC/ MODE FB STOP VINOK AGND VID EPAD I L VOUT R2 1M 1 - VOUT VIN L f SW I I PK I LOAD ( MAX ) L 2 where IPK is the peak inductor current. R1 19.6k 13443-041 VIN = 2.15V TO 6.50V A minimum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple (IL), as shown by the following equations: Figure 41. Typical Application Circuit EXTERNAL COMPONENT SELECTION The ADP5302 is optimized for operation with a 2.2 H inductor and 10 F output capacitors for various output voltages using the closed-loop compensation and adaptive slope compensation circuits. The selection of components depends on the efficiency, the load current transient, and other application requirements. The trade-offs among performance parameters, such as efficiency and transient response, are made by varying the choice of external components. Use the inductor series from different vendors shown in Table 6. OUTPUT CAPACITOR Output capacitance is required to minimize the voltage overshoot, the voltage undershoot, and the ripple voltage present on the output. Capacitors with low equivalent series resistance (ESR) values produce the lowest output ripple. Furthermore, use capacitors such as X5R and X7R dielectric capacitors. Do not use Y5V and Z5U capacitors, which are unsuitable choices due to their large capacitance variation over temperature and their dc bias voltage changes. Because ESR is important, select the capacitor using the following equation: ESRCOUT SELECTING THE INDUCTOR The high frequency switching of the ADP5302 allows the use of small surface-mount power inductors. The dc resistance (DCR) value of the selected inductor affects efficiency. In addition, it is recommended to select a multilayer inductor rather than a magnetic iron inductor because the high switching frequency increases the core temperature rise and enlarges the core loss. VRIPPLE I L where: ESRCOUT is the ESR of the chosen capacitor. VRIPPLE is the peak-to-peak output voltage ripple. Increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. When choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. Use the capacitor series from different vendors shown in Table 7. Table 6. Recommended Inductors Vendor TDK Wurth Coilcraft 1 Model MLP2016V2R2MT0S1 74479889222 LPS3314-222MR Inductance (H) 2.2 2.2 2.2 Dimensions (mm) 2.0 x 1.6 x 0.85 2.5 x 2.0 x 1.2 3.3 x 3.3 x 1.3 DCR (m) 280 250 100 ISAT1 (A) 1.0 1.7 1.5 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current. Table 7. Input and Output Capacitors Vendor Murata Murata Murata Model GRM188D71A106MA73 GRM21BR71A106KE51 GRM31CR71A106KA01 Capacitance (F) 10 10 10 Rev. B | Page 17 of 22 Size 0603 0805 1206 ADP5302 Data Sheet INPUT CAPACITOR An input capacitor is required to reduce the input voltage ripple, input ripple current, and source impedance. Place the input capacitor as close as possible to the PVIN pin. A low ESR X7R or X5R capacitor is highly recommended to minimize the input voltage ripple. Use the following equation to determine the rms input current: I RMS I LOAD( MAX) VOUT VIN VOUT VIN To estimate the total amount of power lost in the inductor (PL), use the following equation: PL = DCR x IOUT2 + Core Losses Driver Losses For most applications, a 10 F capacitor is sufficient. The input capacitor can be increased without any limit for better input voltage filtering. EFFICIENCY Driver losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. Estimate driver losses (PDRIVER) using the following equation: Efficiency is the ratio of output power to input power. The high efficiency of the ADP5302 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package, which in turn reduces thermal constraints. Second, the high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. Power Switch Conduction Losses Power switch dc conduction losses are caused by the flow of output current through the high-side P-channel power switch and the low-side N-channel synchronous rectifier, which have internal resistances (RDS (ON)) associated with them. The amount of power loss is approximated by PSW_COND = (RDS (ON) H x D + RDS (ON) L x (1 - D)) x IOUT2 where D = magnetic permeability of the core material. Because the ADP5302 is a high switching frequency, dc-to-dc regulator, shielded ferrite core material is recommended because of its low core losses and low electromagnetic interference (EMI). VOUT . V IN PDRIVER = (CGATE_H + CGATE_L) x VIN2 x fSW where: CGATE_H is the gate capacitance of the internal high-side switch. CGATE_L is the gate capacitance of the internal low-side switch. fSW is the switching frequency in PWM mode. The typical values for the gate capacitances are 69 pF for CGATE_H and 31 pF for CGATE_L. Transition Losses Transition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of a switch node transition, the power switch provides all of the inductor current. The source to drain voltage of the power switch is half of the input voltage, resulting in power loss. Transition losses increase with both load current and input voltage and occur twice for each switching cycle. Use the following equation to estimate transition losses (PTRAN): The internal resistance of the power switches increases with temperature and with the input voltage decrease. PTRAN = VIN/2 x IOUT x (tR + tF) x fSW Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal DCR. Larger inductors have a smaller DCR, which can decrease inductor conduction losses. Inductor core losses relate to the where: tR is the rise time of the SW node. tF is the fall time of the SW node. The typical value for the rise and fall times, tR and tF, is 2 ns. Rev. B | Page 18 of 22 Data Sheet ADP5302 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 42 shows the typical printed circuit board (PCB) layout for the ADP5302. 10F 10V/XR5 0603 EN 1 10 PVIN STOP 2 9 SW ADP5302 8 PGND TOP VIEW VID 4 7 AGND FB 5 6 VINOK L1 - 2.2H 0603 5.7 10F 6.3V/XR5 0603 100k 0201 4.6 Figure 42. Typical PCB Layout for the ADP5302 Rev. B | Page 19 of 22 13443-042 SYNC3 ADP5302 Data Sheet TYPICAL APPLICATION CIRCUITS The ADP5302 can be used as a keep-alive, ultralow power stepdown regulator to extend battery life (see Figure 43) and as a battery-powered equipment or wireless sensor network VIN = 3.0V TO 4.2V Li-Ion BATTERY controlled by a microcontroller or a processor (see Figure 44). The stop switching function achieves a quiet system environment for noise sensitive applications. 2.2H ADC/RF/AFE ADP5302 10F VOUT = 3.0V SW PVIN 10F R2 1M PGND EN FB VID VINOK MCU (ALWAYS-ON) STOP SYNC/MODE 13343-043 AGND Figure 43. Typical Application Circuit with STOP Switching Functionality VIN = 2.0V TO 3.0V ADP5302 10F ADC/RF/AFE 10F PGND EN VOUT = 1.8V R2 1M FB VID R1 19.6k 1% VINOK STOP MCU (ALWAYS-ON) SYNC/MODE AGND 13343-044 TWO ALKALINE OR Ni-MH BATTERIES 2.2H SW PVIN Figure 44. Typical Application Circuit with 2 Alkaline or NiMH Batteries Rev. B | Page 20 of 22 Data Sheet ADP5302 FACTORY PROGRAMMABLE OPTIONS To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 8. Output Voltage VID Setting Options Option Option 0 Option 1 Option2 Description VID resistor to set the output voltage as follows: 1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.3 V, 3.6 V, or 3.3 V (ADP5302ACPZ-1-R7 and ADP5302ACPZ-2-R7 default) VID resistor to set the output voltage as follows: 0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V, 3.1 V, 3.2V, 3.4 V, 3.9 V, 4.2 V, 4.5 V, 5.0 V 3.9 V fixed output voltage without VID setting (ADP5302ACPZ-3-R7 default) Table 9. VINOK Monitor Threshold Options Option Option 0 Option 1 Option 2 Option 3 ... Option 20 ... Option 62 Option 63 VINOK Monitor Threshold Setting (V) 2.05 2.10 2.15 2.20 ... 3.00 (ADP5302ACPZ-1-R7, ADP5302ACPZ-2-R7, and ADP5302ACPZ-3-R7 default) ... 5.10 5.15 Table 10. Output Discharge Functionality Options Option Option 0 Option 1 Description Output discharge function disabled for the buck regulator (ADP5302ACPZ-2-R7 and ADP5302ACPZ-3-R7 default) Output discharge function enabled for the buck regulator (ADP5302ACPZ-1-R7 default) Table 11. Soft Start Timer Options Option Option 0 Option 1 Description 350 s (ADP5302ACPZ-1-R7, ADP5302ACPZ-2-R7, and ADP5302ACPZ-3-R7 default) 2800 s Rev. B | Page 21 of 22 ADP5302 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 PIN 1 INDICATOR AREA 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 SEATING PLANE SIDE VIEW 0.30 0.25 0.20 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) BOTTOM VIE W 0.05 MAX 0.02 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 08-20-2018-C PKG-004362 0.80 0.75 0.70 0.20 MIN 1 5 TOP VIEW 0.20 REF Figure 45. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5302ACPZ-1-R7 ADP5302ACPZ-2-R7 ADP5302ACPZ-3-R7 ADP5302-EVALZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 10-Lead LFCSP Package 10-Lead LFCSP Package 10-Lead LFCSP Package Evaluation Board Z = RoHS Compliant Part. (c)2015-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13443-0-9/19(B) Rev. B | Page 22 of 22 Package Option CP-10-9 CP-10-9 CP-10-9 Marking Code LT7 LT8 LTD