HM5283206 Series
8M LVTTL interface SGRAM
125 MHz/100 MHz/83 MHz
128-kword × 32-bit × 2-bank
ADE-203-223F (Z)
Rev. 6.0
Oct. 2, 1998
Description
All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2
banks to realize better performance. 8 column block write function and write per bit function are provided
for graphic applications.
Features
• 3.3V Power supply
• Clock frequency: 125 MHz/100 MHz/83 MHz (max)
• LVTTL interface
• 2 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/ single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 1/2/3
• Byte control by DQM
• 8 column block write function with column address mask
• Write per bit function (old mask)
• Refresh cycles: 1024 refresh cycle/16 ms
• 2 variations of refresh
Auto refresh
Self refresh
HM5283206 Series
2
Ordering Information
Type No. Frequency Package
HM5283206FP-8*1
HM5283206FP-10
HM5283206FP-12
125 MHz*1
100 MHz
83 MHz
100-pin plastic QFP (FP-100J)
Note: 1. Under development
Pin Arrangement
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ29
VSSQ
DQ30
DQ31
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
DQ0
DQ1
VSSQ
DQ2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE
CAS
RAS
CS
A9
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC(Vref)
DQM3
DQM1
CLK
CKE
DSF
NC
A8
HM5283206FP Series
(Top view)
HM5283206 Series
3
Pin Description
Pin name Function
A0 to A9 Address input
Row address A0 to A8
Column address A0 to A7
Bank select address (BS) A9
DQ0 to DQ31 Data-input/output
CS Chip select
RAS Row address asserted bank enable
CAS Column address asserted
WE Write enable
DQM0 to DQM3 Byte input/output mask
CLK Clock input
CKE Clock enable
VDD Power for internal circuit
VSS Ground for internal circuit
VDDQ Power for DQ internal circuit
VSSQ Ground for DQ internal circuit
DSF Special function input flag
NC No connection
HM5283206 Series
4
Block Diagram
Column address
counter
Column address
buffer Row address
buffer Refresh
counter
A0 to A9
A0 to A9
DQ0 to DQ31
Input
buffer Output
buffer Control logic &
timing generator
Row decoder Row decoder
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Column decoder
Memory array Memory array
CLK
CKE
CS
RAS
CAS
WE
DQM3
A0 to A7
Bank 0 Bank 1
DQM2
512 row X 256 column X 32 bit 512 row X 256 column X 32 bit
DQM1
DQM0
DSF
Color register
Mask register
HM5283206 Series
5
Pin Functions
CLK (input pin): CLK is the master clock input pin. The other input signals are referred at CLK rising
edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): These pins define operation commands (read, write, etc.) depending on
the combination of their voltage levels. For details, refer to the command operation section.
DSF (input pin): DSF is a part of inputs of graphic commands of the HM5283206. If DSF is LOW, the
HM5283206 operates as standard synchronous DRAM.
A0 to A8 (input pins): Row address (AX0 to AX8) is determined by A0 to A8 pins at the CLK rising
edge when a bank active command is input. Column address (AY0 to AY7) is determined by levels on A0
to A7 pins at the CLK rising edge when a read or write command is input. A8 determines precharge mode.
When A8 is low, only the bank selected by A9 (BS) is precharged by a precharge command. When A8 is
high, both banks are precharged by a precharge command.
A9 (input pin): A9 is the bank select signal (BS). The memory array of the HM5283206 is divided into
the bank 0 and the bank 1, both contain 512 row × 256 column × 32 bits. If A9 is Low, the bank 0 is
selected, and if A9 is High, the bank 1 is selected.
CKE (input pin): By referring low level on CKE pin, HM5283206 determines to go into clock suspend
modes or power down modes. In self refresh mode, low level on this pin is also referred to turn on refresh
process.
DQM0, DQM1, DQM2 and DQM3 (input pins): DQM0 applies to DQ0 to DQ7. DQM1 applies to DQ8
to DQ15. DQM2 applies to DQ16 to DQ23. DQM3 applies to DQ24 to DQ31. In read mode, referring
high level on DQM pins, HM5283206 floats related DQ pins. In write mode, referring high level on DQM
pins, HM5283206 ignores input data through related DQ pins.
DQ0 to DQ31 (input/output): These are the data line for the HM5283206.
VDD and VDDQ (power supply pins): 3.3 V is applied. (VDD is for the internal circuit and VDDQ is power
supply pin for DQ output buffer.)
VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for
DQ output buffer.)
HM5283206 Series
6
Simplified State Diagram
PRECHARGE
WRITE/
BWRITE
SUSPEND
WRITE/
BWRITEA
SUSPEND
READ
SUSPEND
ROW
ACTIVE
IDLE
IDLE
POWER
DOWN
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
ON
READA READA
SUSPEND
SPECIAL
MODE
REGISTER
SET
SR ENTRY
SR EXIT
Active
Suspend
CKE_
CKE
MRS REFRESH
CKE
CKE_
ACTIVM
SMRS
ACTIV
WRITE READ
WRITE
WITH AP READ
WITH AP
POWER
APPLIED
SMRS
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
PRECHARGE
AP
READ WRITE/
BWRITE
WRITE/
BWRITE
WITH AP
READ
WITH
READ
WITH AP WRITE/
BWRITE
WITH AP
PRECHARGE
PRECHARGE PRECHARGE
BST
BST
*1
READ
Read
WRITE/
BWRITE
WRITE/
BWRITEA
Write
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
HM5283206 Series
7
Commands Operation
Commands Explanation
Every operations of HM5283206 are executed by input commands. A command is input, at the rising edge
of CLK, by setting the levels on CS, RAS, CAS, WE, A8 (auto precharge) and DSF pins, HIGH (VIH) or
LOW (VIL).
Note: The setup and hold condition should be obeyed when command, address or data is input.
Setup and Hold Condition of Command, Address and Data Input
tCMS tCMH
CLK
Command
tAS tAH
Address
tDS tDH
Data
HM5283206 Series
8
Precharge command [PRE, PALL]: At the CLK rising edge, by setting
CS, RAS, WE, DSF are LOW,
CAS is HIGH
bank can be precharged to idle state.
A8 = LOW: the bank selected by A9 is precharged.
A8 = HIGH: both banks are precharged.
[State transition]
power on — (precharge) -> Idle
Row active — (precharge) -> Idle
Precharge Command
CS
RAS
CAS
WE
A8
DSF
A9
A0 to A7
DQ High-Z
CLK
CKE VIH
HM5283206 Series
9
Mode register set command [MRS]: If both banks have been precharged or are in idle state, at the CLK
rising edge, by setting
CS, RAS, CAS, WE, DSF; LOW
an internal register (the mode register; MRS) are set.
The data through address pins, at the cycle when this command is input, are stored in the mode register.
A8, A9 bits determine burst write or single write. A6 to A4 bits determine CAS latency. A3 bit determines
burst type, sequential or interleave. A2 to A0 bits determine burst length. A7 bit should be set to low. See
table below for details.
[State transition]
Idle — (Mode resister set) ->Idle
Mode Register Set Command
A8, A9
DSF
A6 to A4
DQ
OP CODE
CAS Latency
A3 Burst type
A2 to A0 Burst length
High-Z
A7
CLK
CKE V
CS
RAS
CAS
WE
IH
HM5283206 Series
10
Mode Register Configuration
A9 A8 Operation CODE
0 0 Burst read and burst write
01R
1 0 Burst read and single write
11R
A6 A5 A4 CAS latency
000R
0011
0102
0113
1×× R
A3 Burst type
0 Sequential
1 Interleave
Burst length
A2 A1 A0 BT = 0 BT = 1
0001 1
0012 2
0104 4
0118 8
100R R
101R R
110R R
1 1 1 Full page R
Note: R: Reserved
HM5283206 Series
11
Bank and row active command [ACTV, ACTVM]: If a bank has been precharged or is in idle state. At
the CLK rising edge, by setting
CS, RAS; LOW,
CAS, WE: HIGH
a row of the bank is activated. The bank is selected by setting the level on A9 pin HIGH (bank 1) or LOW
(bank 0) at this timing. A0 to A8 determine the row address.
[Option]
DSF = LOW; write per bit function disable (ACTV)
DSF = HIGH; write per bit function enable (ACTVM)
[State transition]
Idle — (row active) ->Row active
Bank and Row Active Command
DSF
A9
A0 to A8
DQ High-Z
CLK
CKE VIH
CS
RAS
CAS
WE
HM5283206 Series
12
Column address and read command: For a row of one of two banks activated by ACTV or ACTVM, at
the CLK rising edge, by setting
CS, CAS, DSF; LOW,
RAS, WE; HIGH,
data is output through DQ pins.
A9 determines the bank address.
A0 to A7 determine the column address.
CAS latency stored in MRS determines the timing when data are driven.
In case, CL (CAS latency) = 1, 1 clock cycle after the command input, data start to be output.
In case CL = 2, 2 clock cycle after the command input, data start to be output.
In case CL = 3, 3 clock cycle after the command input, data start to be output.
Burst Length (BL) stored in MRS determines data length of output .
[Option]
A8 = HIGH; auto precharge mode or execute precharge automatically after finishing data output.
A8 = LOW; Read mode without auto precharge.
[State transition]
Row active — (Column address and read command) ->Row active
Row active — (Column address and read command) ->Idle (auto precharge)
Column Address and Read Command CL = 1, BL = 1.
High-Z
CS
RAS
CAS
WE
A8
DSF
A9
A0 to A7
DQ (out)
CLK
CKE VIH
HM5283206 Series
13
Column address and write command: For a row of one of two banks activated by ACTV or ACTVM, at
the CLK rising edge, by setting
CS, CAS, DSF, WE; LOW,
RAS; HIGH,
the data on DQ pins are input.
A9 determines the bank address.
A0 to A7 determine the column address.
For write, data should start to be input at the same cycle of the command input.
Burst length stored in MRS determines the expected data length to be input.
If the bank, for which command is input, is activated by ACTVM, then I/O bit mask function or write per
bit is available.
[Option]
A8 = HIGH; auto precharge mode or execute precharge automatically after finishing data input.
A8 = LOW; write mode without auto precharge.
[State transition]
Row active — (Column address and write command) ->Row active
Row active — (Column address and write command) ->Idle (auto precharge case)
Column Address and Write Command (BL = 2)
High-Z
CS
RAS
CAS
WE
A8
DSF
A9
A0 to A7
DQ (in)
CLK
CKE VIH
HM5283206 Series
14
Burst stop command (BST): At the CLK rising edge, by setting
CS, WE, DSF: LOW,
RAS, CAS; HIGH,
full page burst (BL = 256) read/write is interrupted.
If BL is set to 1, 2, 4, 8, to try to execute this command is illegal.
[State transition]
Row active — (Burst stop command) -> Row active
Burst Stop Command
A0 to A9
CS
RAS
CAS
WE
DSF
CLK
CKE VIH
HM5283206 Series
15
Auto refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting
CS, RAS, CAS, DSF; LOW,
WE; HIGH,
the HM5283206 starts auto-refresh (CBR type) operation. Refresh address is internally generated.
No precharge commands are required after autorefresh, since precharge is automatically performed for both
banks.
[State transition]
Idle — (Auto refresh command) -> Idle
Auto Refresh Command
High-Z
DQ
CS
RAS
CAS
WE
DSF
CLK
CKE VIH
A0 to A9
HM5283206 Series
16
Self refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting
CS, RAS, CAS, DSF; LOW,
WE; HIGH,
and if CKE's falling edge is detected, the HM5283206 starts self-refresh operation. Self-refresh operation is
kept while CKE is LOW.
[State transition]
Idle — (Self refresh command) -> Self refresh mode
Self Refresh Command
High-Z
A0 to A9
DQ
CS
RAS
CAS
WE
DSF
CLK
CKE
HM5283206 Series
17
No operation command (NOP): At the CLK rising edge, by setting
CS; LOW,
WE, RAS, CAS; HIGH,
[State transition]
No transition
No Operation Command
High-Z
A0 to A9
DQ
CS
RAS
CAS
WE
DSF
CLK
CKE VIH
Ignore command (DESL): At the CLK rising edge, by setting
CS; HIGH, any input is ignored.
HM5283206 Series
18
Graphic Commands
Special mode register set command (SMRS): If each banks is in idle state or activated, at the CLK rising
edge, by setting
CS, RAS, CAS, WE; LOW,
DSF; HIGH,
an internal register (the special mode register; SMRS) are set.
The data through address pins, at the cycle when this command is input, are stored in the special mode
register.
A0 to A4: reserved. should be LOW when SMRS is issued.
A5: determines whether loading mask data or not when SMRS is issued.
A6: determines whether loading color data or not when SMRS is issued.
A7 to A9: reserved. should be set LOW when SMRS is issued.
In case A5 bit of the mode register = HIGH, the data through DQ pins, at the cycle this command is issued,
are stored in the MASK register (32 bits). If write per bit function is available*, and DQi (i = 0,..,31) bit of
the MASK register = LOW, DQi data path to memory array is masked.
In case A6 bit of the mode register HIGH, the data through DQ pins, at the cycle when this command is
issued, are stored in the COLOR register (32 bits). This specific data is written to 8 columns in one clock
cycle by block write command.
Note: When bank active command is issued and DSF set to HIGH, write per bit function is enabled.
Special Mode Register Set Command
A0 to A4
A5 Load mask
A6
A7 to A9
High-Z
Load color
DQ
CS
RAS
CAS
WE
DSF
CLK
CKE VIH
HM5283206 Series
19
Special Mode Register Configuration
A5 A6 Function
0×Disable Load Mask
1 0 Enable
×0 Disable Load Color
0 1 Enable
1 1 ILLEGAL
Note: ×: VIH or VIL
Reserved Bits
A0 A1 A2 A3 A4 A7 A8 A9
00000000
HM5283206 Series
20
Graphic Function Block Diagram
DQ 1
DQ 0
DQ 31
DQ 30
31
30
1
0
1
0
31
30
Memory
Array
COLOR register
MASK register
I1
I2 O
I1
I2 O
When block write command is issued, data I1 stored in the COLOR register is loaded
into column block (8 columns) of memory array. For burst and single write, the data I2
from DQ pins are loaded into a single column.
When write per bit function is available, if mask data I1 stored in the MASK register is
LOW then the data path from I2 to O is cut.
HM5283206 Series
21
Column address and block write command: For a row of one of two banks activated by ACTV or
ACTVM, at the CLK rising edge, by setting
CS, CAS, WE; LOW,
RAS, DSF; HIGH,
a block write *2 is executed.
A9 determines the bank address.
A0 to A2 HIGH or LOW (ignored).
A3 to A7 determine the column block address.
The data through DQ pins, at the cycle when the block write command input, are referred to stop the color
data to be written onto the specific column. (Column mask)
[Option]
A8 = HIGH; Auto precharge mode or execute precharge automatically after finishing a block write
execution.
A8 = LOW; Write mode without auto precharge.
[State transition]
Row active — (Block write command) ->Row active
Row active — (Block write command) ->Idle(auto precharge case)
Column Address and Block Write Command
A8
A9
A0 to A7
DQ High-Z
CS
RAS
CAS
WE
DSF
CLK
CKE VIH
HM5283206 Series
22
Column Block
Column location Column block location
A0 A1 A2 A3 A4 A5 A6 A7
000a3a4a5a6a7
100a3a4a5a6a7
010a3a4a5a6a7
110a3a4a5a6a7
001a3a4a5a6a7
101a3a4a5a6a7
011a3a4a5a6a7
111a3a4a5a6a7
Note: 1. a3, a4, a5, a6, a7; VIH or VIL.
HM5283206 Series
23
DQ Input at the Block Write Cycle and Column Mask Location
Column location Column mask
DQ pin NO. DQ group*1A0 A1 A2 No mask Mask
DQ0 00 0 0 0 High Low
DQ1 00 1 0 0 High Low
DQ2 00 0 1 0 High Low
DQ3 00 1 1 0 High Low
DQ4 00 0 0 1 High Low
DQ5 00 1 0 1 High Low
DQ6 00 0 1 1 High Low
DQ7 00 1 1 1 High Low
DQ8 01 0 0 0 High Low
DQ9 01 1 0 0 High Low
DQ10 01 0 1 0 High Low
DQ11 01 1 1 0 High Low
DQ12 01 0 0 1 High Low
DQ13 01 1 0 1 High Low
DQ14 01 0 1 1 High Low
DQ15 01 1 1 1 High Low
DQ16 10 0 0 0 High Low
DQ17 10 1 0 0 High Low
DQ18 10 0 1 0 High Low
DQ19 10 1 1 0 High Low
DQ20 10 0 0 1 High Low
DQ21 10 1 0 1 High Low
DQ22 10 0 1 1 High Low
DQ23 10 1 1 1 High Low
DQ24 11 0 0 0 High Low
DQ25 11 1 0 0 High Low
DQ26 11 0 1 0 High Low
DQ27 11 1 1 0 High Low
DQ28 11 0 0 1 High Low
DQ29 11 1 0 1 High Low
DQ30 11 0 1 1 High Low
DQ31 11 1 1 1 High Low
Note: DQ group: 00; DQ0 to DQ7, 01; DQ8 to DQ15, 10; DQ16 to DQ23, 11; DQ24 to DQ31
HM5283206 Series
24
Command Truth Table
The HM5283206 recognizes the following commands specified by the CS, RAS, CAS, WE, DSF and
address pins. All other combinations than those in the table bellow are illegal.
CKE
Function Symbol n – 1 n CS RAS CAS WE DSF A9 A8 A0 to A7
Ignore command DESL*2H×H×× ×××××
No operation NOP H ×LH H H××××
Burst stop in full page BST*3H×LH H LL ×××
Column address and read
command READ H ×LHL HLVLV
Read with auto precharge READ A H ×LHL HLVHV
Column address and write
command WRIT H ×LHL LLVLV
Write with auto precharge WRIT A H ×LHL LLVHV
Row address strobe and bank
active ACTV H ×LL H HLVVV
Precharge select bank PRE H ×LL H LLVL×
Precharge all bank PALL H ×LL H LL ×H×
Refresh (auto, self) REF,
SELF H×LL L HL ×××
Mode register set MRS H ×LL L LLVVV
Row address strobe and bank
active and Masked write enable ACTVM H ×LL H HHVVV
Column address and block write
command BWRIT H ×LH L LHV L V
Block write with auto precharge BWRITA H ×LH L LHV H V
Special mode register set SMRS H ×LLL LHLLV
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.
2. When CS is high, the HM5283206 ignores command input. Internal operation is held.
3. Illegal if the burst length is 1, 2, 4 or 8.
HM5283206 Series
25
DQM Truth Table
CKE
Function Symbol n – 1 n DQM i
Ith byte write enable/output enable ENB i H ×L
Ith byte write input/output disable MASK i H ×H
Note: H: VIH. L: VIL. ×: VIH or VIL. i = 0, 1, 2, 3.
DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to
DQ31
CKE Truth Table
CKE
Current state Function n – 1 n CS RAS CAS WE DSF Address
Active Clock suspend mode entry H L ××××××
Any Clock suspend L L ××××××
Clock suspend Clock suspend mode exit L H ××××××
Idle Auto refresh command REF H H LLLHL×
Idle Self refresh entry SELF H LLLLHL×
Idle Power down entry H L ××××××
Self refresh Self refresh exit L H L H H H ××
LHH×××××
Power down Power down exit L H L H H H ××
LHH×××××
Note: H: VIH. L: VIL. ×: VIH or VIL.
HM5283206 Series
26
Function Truth Table
The following tables show how each command works and what command can be executed in the state
given.
Current state CS RAS CAS WE DSF Address Command Operation
Precharge H ××××× DESL NOP -> Idle after tRP
LHHH×× NOP NOP -> Idle after tRP
LHHLL×BST ILLEGAL*2, *6
L H L H L BA, CA, A8 READ/READ A ILLEGAL*2
L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL NOP*3
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
Idle H ××××× DESL NOP
LHHH×× NOP NOP
LHHLL×BST NOP*6
L H L H L BA, CA, A8 READ/READ A ILLEGAL*2
L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2
L L H H L BA, RA ACTV Bank and row active
L L H L L BA, A8 PRE, PALL NOP*3
LLLHL×REF, SELF Auto self refresh*4
LLLLLMODE MRS Mode register set*4
L L H H H BA, RA ACTVM Bank and row active and
write per bit enable
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
LLLLHSpecial MODESMRS Special mode register set*5
HM5283206 Series
27
Current state CS RAS CAS WE DSF Address Command Operation
Row active H ××××× DESL NOP
LHHH×× NOP NOP
LHHLL×BST NOP*6
L H L H L BA, CA, A8 READ/READ A Start read
L H L L L BA, CA, A8 WRIT/WRIT A Start write
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL Precharge
LLL×L ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A Start block write
LLLLHSpecial MODESMRS Special mode register set*5
Read H ××××× DESL NOP -> Burst end -> Row
active
LHHH×× NOP NOP -> Burst end -> Row
active
LHHLL×BST Burst stop -> Row active*6
L H L H L BA, CA, A8 READ/READ A Term burst -> Start new read
L H L L L BA, CA, A8 WRIT/WRIT A Term burst -> Start write
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL Term burst -> Precharge
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A Term burst -> Start block
write
Read with auto
precharge H××××× DESL NOP -> Burst end ->
Precharge
LHHH×× NOP NOP -> Burst end ->
Precharge
LHHLL×BST ILLEGAL
L H L H L BA, CA, A8 READ/READ A ILLEGAL*2
L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL ILLEGAL*2
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
HM5283206 Series
28
Current state CS RAS CAS WE DSF Address Command Operation
Write/BWrite H ××××× DESL NOP -> Burst end -> Write
recovering
LHHH×× NOP NOP -> Burst end -> Write
recovering
LHHLL×BST Burst stop -> Row active*6
L H L H L BA, CA, A8 READ/READ A Term burst -> Start read
L H L L L BA, CA, A8 WRIT/WRIT A Term burst -> Start new write
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL Term burst -> Precharge
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A Term burst -> Start block
write
Write/Bwrite
with auto
precharge
H××××× DESL NOP -> Burst end -> Write
recovering with precharge
LHHH×× NOP NOP -> Burst end -> Write
recovering with precharge
LHHLL×BST ILLEGAL
L H L H L BA, CA, A8 READ/READ A ILLEGAL*2
L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL ILLEGAL*2
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
Write/Bwrite
recovering H××××× DESL NOP -> Row active after
tWR/tBWR
LHHH×× NOP NOP -> Row active after
tWR/tBWR
LHHLL×BST NOP -> Row active after
tWR/tBWR*6
L H L H L BA, CA, A8 READ/READ A Start read*2
L H L L L BA, CA, A8 WRIT/WRIT A Start new write*2
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL ILLEGAL*2
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
HM5283206 Series
29
Current state CS RAS CAS WE DSF Address Command Operation
Write/Bwrite
recovering with
precharge
H××××× DESL NOP -> Precharge after
tWR/tBWR
LHHH×× NOP NOP -> Precharge after
tWR/tBWR
LHHLL×BST ILLEGAL
L H L H L BA, CA, A8 READ/READ A ILLEGAL*2
L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL ILLEGAL*2
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
Row activating H ××××× DESL NOP -> Row active after tRCD
LHHH×× NOP NOP -> Row active after tRCD
LHHLL×BST NOP -> Row active after
tRCD*6
L H L H L BA, CA, A8 READ/READ A ILLEGAL*2
L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2
L L H H L BA, RA ACTV ILLEGAL*2
L L H L L BA, A8 PRE, PALL ILLEGAL*2
LLL××× ILLEGAL
L L H H H BA, RA ACTVM ILLEGAL*2
L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2
Refresh (auto
precharge) H××××× DESL NOP -> Idle after tRC
LHHH×× NOP NOP -> Idle after tRC
LHHLL×BST NOP -> Idle after tRC*6
LHL××BA, CA, A8 ILLEGAL
LL×××× ILLEGAL
Mode register
set H××××× DESL NOP -> Idle after tRSC
LHHH×× NOP NOP -> Idle after tRSC
LHHLL×BST ILLEGAL
LHL××BA, CA, A8 ILLEGAL
LL×××× ILLEGAL
HM5283206 Series
30
Current state CS RAS CAS WE DSF Address Command Operation
Special Mode
register set H××××× DESL NOP -> Idle after tRSC or row
active after tSBW
LHHH×× NOP NOP -> Idle after tRSC or row
active after tSBW
LHHLL×BST ILLEGAL
LHL××BA, CA, A8 ILLEGAL
LL×××× ILLEGAL
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
2. To execute this command for the current bank is illegal. However this command can be
executed for another bank depends on the state of another bank.
3. NOP for the current bank or the bank in idle state. Precharge for the bank in other state.
4. Illegal, if both banks are not in idle state.
5. Illegal, if another bank is not in active or idle state.
6. In burst read/write, if BL is set to 1, 2, 4, 8, to try to execute BST command is illegal.
HM5283206 Series
31
Operations of HM5283206 Series
Power on sequence: In order to get rid of data contention of I/O bus when power on, the following power
on sequence recommended to be performed before any operation.
1. Apply power and start clock. Keep a NOP condition.
2. Maintain stable power, stable clock, and NOP condition for 200 µs.
3. Execute precharge command (PALL: A8 = HIGH).
4. Execute 8 or more auto refresh commands (REF) tRP after the precharge command as dummy. An
interval tRC is necessary between two consecutive auto refresh commands.
5. Execute a mode register set command (MRS) tRC after the last auto refresh command input.
Power on Sequence
PALL
CLK
Command
Address
t
A8='H'
MRS
OP
CODE
REF REF ACTV
NOP
RP
tRC tRC tRSA
Repeat this auto-refresh cycle 8 times or more
Read/Write Operations
Bank active: A read/write operation begins with a bank active command (ACTV or ACTVM). The bank
active command determines a bank (A9) and a row address (AX0 to AX8). For the bank and the row, a
read/write command can be applied. An interval not less than t RCD, after an ACTV/ ACTVM command to a
read/write command, is required.
Read operation: Burst length (BL), CAS latency (CL) and burst type (BT) of the mode register are
referred when read command is executed. Burst length (BL) determines the length of a sequential data by a
single read command, which can be set to 1, 2, 4, 8 or 256 (full-page). Starting address of a burst data is
defined by column address (AY0 to AY7) and bank select address (A9) loaded through A0 to A9 in the
cycle when the read command is issued. CAS latency (CL) determines the delay of data output after read
command input. When burst length is 1, 2, 4 or 8, DQ buffers automatically become High-Z at the next
cycle after completion of burst read. When burst length is full-page (256), data are repeatedly output until
a burst stop command, a read/write command or a precharge command is input.
HM5283206 Series
32
Burst Length
DQout
t
row column
BL=1
BL=2
BL=4
BL=8
BL=Full page
0
0
0
0
0
1
1
1
1
2
2
2
3
3
3
4
4
56 7
56 7 256 0 1
BL: Burst Length
CAS Latency = 2
BT: sequential
CLK
Command
Address
read
ACT
RCD
CAS Latency
ACT read
row
CL= 1
CL= 2
CL= 3 0 123
Burst Length = 4
CL = CAS Latency
BT: sequential
0 123
0123
DQ out
CLK
Command
Address
tRCD
column
Burst operation (on read or write): One burst data output/input by one read/write command are included
in a column block determined by A1 to A7 in case BL (Burst Length) = 2, by A2 to A7 in case BL = 4 and
by A3 to A7 in case BL = 8. Burst type (BT) determines the order how data of the column block are
output/input. There are two burst types, sequential (wrap around) or interleave. The order of the burst data
depends also on the start column location of the burst data. See tables below for details.
HM5283206 Series
33
Column Block
BL = 2
Column location Column block location
A0 A1 A2 A3 A4 A5 A6 A7
0 a1a2a3a4a5a6a7
1 a1a2a3a4a5a6a7
Note: a1, a2, a3, a4, a5, a6, a7; VIH or VIL.
BL = 4
Column location Column block location
A0 A1 A2 A3 A4 A5 A6 A7
0 0 a2a3a4a5a6a7
1 0 a2a3a4a5a6a7
0 1 a2a3a4a5a6a7
1 1 a2a3a4a5a6a7
Note: a2, a3, a4, a5, a6, a7; VIH or VIL.
BL = 8
Column location Column block location
A0 A1 A2 A3 A4 A5 A6 A7
000a3a4a5a6a7
100a3a4a5a6a7
010a3a4a5a6a7
110a3a4a5a6a7
001a3a4a5a6a7
101a3a4a5a6a7
011a3a4a5a6a7
111a3a4a5a6a7
Note: a3, a4, a5, a6, a7; VIH or VIL.
HM5283206 Series
34
The Order of Burst Operation
BL = 2
Start column location Order in decimal BL = 2
A0 Sequential Interleave
0 0101
1 1010
BL = 4
Start column location Order in decimal BL = 4
A0 A1 Sequential Interleave
0 0 01230123
1 0 12301032
0 1 23012301
1 1 30123210
BL = 8
Start column location Order in decimal BL = 8
A0 A1 A2 Sequential Interleave
0 0 0 0123456701234567
1 0 0 1234567010325476
0 1 0 2345670123016745
1 1 0 3456701232107654
0 0 1 4567012345670123
1 0 1 5670123454761032
0 1 1 6701234567452301
1 1 1 7012345676543210
HM5283206 Series
35
Write operation: OPCODE (A9, A8) of the mode register is referred when a write command is executed
as well as BL (Burst Length) and BT (Burst Type). CL (CAS Latency) is ignored and CL is fixed to 0 for
write operation, that is, write data input starts on the same cycle when the write command is issued.
Burst write: Before executing a burst write operation, OPCODE (A9, A8) should be set to (0, 0). Burst
length (BL) determines the length of a sequential data by the burst write command, which can be set to 1, 2,
4, 8 or 256 (full-page). Starting address of a burst data is defined by column address (AY0 to AY7) and
bank select address (A9) loaded through A0 to A9 in the cycle when the burst write command is issued.
BL=1
BL=2
BL=4
BL=8
BL=Full page 256 0 1
BL:Burst Length
CAS Latency = 1, 2, 3
0
0
0
0
0
1
1
1
1
2
2
2
3
3
3
4567
56 74
DQ in
CLK
Command
Address
tRCD
write
ACT
row column
Single write: Before executing a single write operation, OPCODE (A9, A8) should be set to (1, 0). In the
single write operation, data are only written to the single column defined by the column address and the
bank select address loaded at the write command set cycle regardless of the defined burst length. (The
latency of data input is 0).
row
0BL: Burst Length = 1,
2, 4, 8, full page
tRCD
DQ in
CLK
Command
Address
write
ACT
column
HM5283206 Series
36
Write per bit: To use write per bit function,
1. Set mask data in advance, which define DQ paths to be masked, to the MASK register by SMRS
command. An interval not less than tRSC after a SMRS command to an ACTVM command is
necessary.
2. Use ACTVM command to activate the bank for which write per bit operation is performed. An interval
not less than tRCD, after an ACTVM command to a write or a block write command, is necessary.
3. Execute a write or a block write command. In this write operation, DQ paths defined by mask register
are masked to preserve the previous data. (See the example below)
Special Mode Register Set (Load Mask) in Idle State and Write Per Bit
write
ACTM
row
BL: Burst Length = 2
t
SMRS
mask
data
A5=1
A6=0
01
DQ in
CLK
Command
Address
tRCD
RSC
column
Special Mode Register Set (Load Mask) in Active State and Write Per Bit
write
col
BL: Burst Length = 2
SMRS
mask
data
A5=1
A6=0
01
DQ in
CLK
Command
Address
tSBW
HM5283206 Series
37
Write Per Bit Example
A
B
C
D
E
F
G
H
DQ input data
0
1
1
0
1
1
0
0
MASK data
stored in the MASK register
B
C
E
G
Data to be written
DQ 0
DQ 1
DQ 2
DQ 3
DQ 31
DQ 30
DQ 29
DQ 28
data through
this bit will not
be written.
Block write: Before executing a block write command, a color data (32 bit) should be set in advance,
which is allowed to be written in 8 columns at one write cycle, to the color register by SMRS command.
An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. If a SMRS
command is executed in active state to set the color register, an interval not less than t SBW is required before
executing a block write command after the SMRS command. If a block write command is applied to the
bank which is activated by ACTVM command, write per bit function is also available. DQ inputs at the
cycle, when a block write command is executed, are referred to mask the specific columns. See the
example below.
Special Mode Register Set (Load Mask) in Idle State and Block Write
Bwrite
ACTM
row
BL: Burst Length = 2
SMRS
Color
data
A5=0
A6=1
Column
MASK
DQ in
CLK
Command
Address
tRCD
tRSC
column
HM5283206 Series
38
Block Write Example with Write Per Bit
H
D
H
A
B
Color data
0
1
0
1
1
0
MASK data
Data to be written
(Column block)
0
1
7
31
30
24
data through
this bit will not
be written.
A
B
D
E
G
H
A
B
E
G
D
E
G
DQ input
DQ 0
DQ 1
DQ 7
DQ 31
DQ 25
DQ 24
1
0
1
1
0
A
B
D
E
G
H
01 7
1
Column mask
Column mask
Column
location
HM5283206 Series
39
Auto Precharge
Read with auto precharge: In this operation, since precharge is automatically performed after completing
a read operation, so no precharge commands are necessary after each read operation. The command next to
this command must be a bank active (ACTV, ACTVM) command. In addition, an interval defined by l APR
is required prior to the next command.
Note: In executing read with auto precharge command, every command to another bank is ignored until
internal precharge completed.
CAS latency Precharge start cycle
3 2 cycle before the last data out
2 1 cycle before the last data out
1 0 cycle before the last data out
ACT
CLK
DQ out
CL=1
0123
t
read
Command
CL=2
0 123
Command
DQ out
CL=3
01 23
Command
DQ out
Internal precharge starts here
I
ACT
read
ACT
read
ACT
ACT
ACT
RCD
APR
IAPR
IAPR
HM5283206 Series
40
Write with auto precharge: In this operation, since precharge is automatically performed after
completion of a burst write or a single write operation, so no precharge commands are necessary after the
write operation. The command next to this command must be a bank active command (ACTV, ACTVM).
In addition, an interval of lAPW is required between the last valid data and the following command.
Note: In executing write with auto precharge command, every command to another bank is ignored until
internal precharge completed.
Burst Write (Burst Length = 4)
write
ACT
row
CLK
Command
Address
DQ in 0123
row
I
ACT
APW
column
Single Write
CLK
Command
Address
DQ in I
writeACT
row
ACT
row
0APW
column
HM5283206 Series
41
Block write with auto-precharge: In this operation, since precharge is automatically performed after
completion of a block write operation, so no need to execute precharge command. The following
command must be a bank active command (ACTV, ACTVM). In addition, an interval of lAPBW is required
between the last valid data input and the following command.
Block Write with Auto Precharge
ACT
row
CLK
Command
Address
ACT
I
row
Bwrite
APBW
column
Full Page B urst S top
Burst stop command during burst read: Burst stop command is used to stop data output during a full-
page burst read. This command sets the output buffer to High-Z and stops the full-page burst read. The
timing, from command input to the last data, depends on CAS latency. BST command is legitimate only in
case full page burst mode, and is illegal in case burst length 1, 2, 4 or 8.
CAS latency BST to valid data BST to high impedance
101
212
323
HM5283206 Series
42
CAS Latency = 1, Burst Length = Full Page
BST
CLK
DQ out
Command
I = 0 BSH
I = 1
BSR
CAS Latency = 2, Burst Length = Full Page
CLK
DQ out
BST
Command
I = 1
BSH
I = 2
BSR
CAS Latency = 3, Burst Length = Full Page
BST
CLK
DQ out
Command
I = 2
BSH
I = 3
BSR
HM5283206 Series
43
Burst stop command at burst write: For full page burst write cycle, when a burst stop command is
issued, the write data at that cycle and the following write data input are ignored. The BST command is
legitimate only in case full page burst mode, and is illegal for burst length 1, 2, 4 or 8.
Burst Length = Full Page
Burst stop Precharge
in in
CLK
Command
DQ input
tWR
HM5283206 Series
44
DQM Control
The DQM i (i=0, 1, 2, 3) controls the ith byte of DQ data. DQM control operation for read and for write are
different in terms of latency.
Reading: When data are read, output buffer can be controlled by DQMi. By setting DQMi to LOW, the
corresponding DQ output buffers become active. By setting DQMi to HIGH, the corresponding DQ output
buffers are made floated so that the ith byte of data are not driven out. The latency of DQM operation for
read operation is 2.
CLK
01 3
I = 2 Latency
DQM
DQout
DOD
Writing: Input data can be controlled by DQMi. While DQMi is LOW, data is driven into the
HM5283206. By setting DQMi to HIGH, corresponding ith byte of DQ input data are kept from being
written to the HM5283206 and the previous data are protected. The latency of DQM control operation is 0.
CLK
I = 0 Latency
DQM
DQin
01 3
DID
HM5283206 Series
45
Refresh
Auto Refresh: All the banks must be precharged before executing an auto-refresh command. Auto refresh
command increments the internal counter every time when it is executed. This command also determines
the row to be refreshed. Therefore external address specification is not necessary. Refresh cycle is 1024
cycles/16 ms. (1024 cycles are required to refresh all the row addresses.) All output buffers become High-
Z after auto-refresh start. No precharge commands are necessary after this operation.
Self Refresh: When issuing a self refresh command, by changing the level on CKE pin from HIGH to
LOW simultaneously, a self refresh operation starts and is kept while CKE is LOW. During the self-
refresh operation, all data schedule to be refreshed internally. This operation managed by an internal
refresh timer. After exiting from the self refresh, since the last row refreshed cannot be determined, auto-
refresh commands should immediately be performed for all addresses. Change the level on the CKE pin
from LOW to HIGH to exit from Self refresh mode.
Others
Power Down Mode: Power down mode is a state in which all input buffers except the CKE input buffer
are made inactive and clock signal is masked to cut power dissipation. To enter into power down mode,
CKE should be set to low. Power down mode is kept as long as CKE is low. Change the level on the CKE
pin from LOW to HIGH to exit from Power down mode. In this mode, internal refresh is not performed.
Clock Suspend: The HM5283206 enters into clock suspend mode from active mode by setting CKE to
low. There are several types of clock suspend mode depends on the state when CKE level is changed from
HIGH to LOW.
ACTIVE clock suspend: If CKE-transition (1 to 0) happens during a bank active state, the bank active
status is kept. Any input signals are ignored during this mode.
READ and READ A suspend: If CKE transition (1 to 0) happens during a read operation, the read
operation is kept or DQ output data is driven out until completion. Any input signals are ignored during
this mode.
WRITE (BLOCK WRITE) and WRITE A (BLOCK WRITE A) suspend: If CKE-transition (1 to 0)
happens during a write operation, though any input signals include DQ input data ignored, the write
operation is kept until completion. Any input signals are ignored during this mode.
Change the level on the CKE pin from LOW to HIGH to exit from Clock suspend mode.
HM5283206 Series
46
Command Intervals
Read Command to Read Command Interval:
1. Operation for a column in the same row: Read command can be issued every cycle. Note that the latest
read command has the priority to the preceding read command, that is, any read command can interrupt the
preceding burst read operation to get valid data aimed by this interruption.
read
row A
A0 B0 B1 B2 B3
read
B
Bank 0
Active Column A
read read Dout Dout
CAS Latency = 3
Burst Length = 4
Bank 0
Command
Address
DQ out
t
CLK
A9(BS)
RCD
ACT
Column AColumn B Column B
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command
and a bank-active command before executing the new read command.
3. Operation for another bank: For another bank in active state, the new read command can be executed in
the next cycle after the preceding read command is issued. If another bank is in idle state, a bank active
command should be executed before executing the new read command.
Command
Address
DQ out
t
0
CLK
Bank 0
Active read read Bank0
Dout
CAS Latency = 3
Burst Length = 4
1
A9(BS)
A0 B0 B1 B2 B3
Bank1
Dout
Bank1
Active
ACT readACT
RRD
Column A Column B
AB
read
HM5283206 Series
47
Write Command to Write Command Interval:
1. Operation for a column in the same row : Write command can be issued every cycle. Note that the latest
write command has the priority to the preceding write command, that is, any write command can interrupt
the preceding burst write operation to get valid data
ACT
t
row A
B0 B1 B2 B3
write
B
Bank 0
Active write write
Burst Write Mode
CAS Latency = 3
Burst Length = 4
Command
Address
DQ in
CLK
A9(BS)
RCD
write
A0
Column A Column B
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command
and a bank active command before executing the following write command.
3. Operation for another bank: For another bank in active state, the following burst write command can be
executed in the next cycle after the preceding write command is issued. If another bank is in the idle state,
bank active command should be executed.
Command
Address
DQ in
t
0
CLK
Bank 0
Active Bank0
write Bank 1
write
Burst Write Mode
CAS Latency = 3
1
A9(BS)
A0 B0 B1 B2 B3
Bank1
Active
ACT ACT
RRD
write
Burst Length = 4
AB
write
HM5283206 Series
48
Block Write Command to Write or Block Write Command Interval:
1. Operation for a column in the same row: It is necessary to take no less than tBWC internal between a
block write and another block write or the following write. If tCK is less than tBWC, NOP command should
be issued for the cycle between a block write command and the following write or another block write
command.
Bwrite
CLK
Command
Address row A
Bwrite
/Write
B
Bank 0
Active Block write
/Write
Block write
tRCD tBWC
ACT
Column A Column B
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command
and a bank active command before the following write or another block write operation.
3. Operation for another bank: To execute the following write command or another block write command
for another bank in active state, tBWC interval to the next command is necessary. If another bank is in the
idle state, bank active command should be executed. If tCK is less than tBWC, NOP command should be
issued for the cycle between block write command and the following write or another block write
command.
Bwrite
Command
Address
t
0A
CLK
B
Bank 0
Active
1
A9(BS)
Bank1
Active
Bwrite
/Write
Block write
/Write
Block write
RRD tBWC
ACT ACT
Column A Column B
HM5283206 Series
49
Read Command to Write or Block Write Command Interval:
1. Operation for a column in the same row: The write or the block write command following the preceding
read command can be performed after an interval of no less than 1 cycle. To set DQ output High-Z when
data are driven in, DQM must be used depending on CAS latency as the timing shown below. Note that the
latest write or block write command has the priority to the preceding read command, that is, any write or
block write command can interrupt the preceding burst read operation to get valid data.
0123
readCommand write
CLK
DQM
CL= 1
CL= 2
CL= 3
DQ in
DQ out High-Z
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command
and a bank active command before executing the next write or another block write command.
3. Operation for another bank: For another bank in active state, the following write or block write
command can be executed from the next cycle after the preceding write command is issued. If another
bank is in idle state, bank active command should be executed, prior to execute the following write or block
write command.
HM5283206 Series
50
Write Command to Read Command Interval:
1. Operation for a column in the same row: The read command following the preceding write command
can be performed after an interval of no less than 1 cycle. Note that the latest read command has the
priority to the preceding writing command, that is, any read command can interrupt the preceding write
operation to get valid data.
WRITE to READ Command Interval (1)
read
B0 B1 B2 B3
Command
CLK
DQM
DQ in
DQ out
A0
write
read Dout
CAS Latency Burst Write Mode
CAS Latency = 1
Burst Length = 4
Bank 0
write
Column B Column B
Column A
WRITE to READ Command Interval (2)
B0 B1 B2 B3
A0
write
read Dout
CAS Latency Burst Write Mode
Burst Length = 4
Bank 0
Command
CLK
DQM
DQ in
DQ out
CAS Latency = 1
write read
A0
Column A
Column B Column B
2. Operation for a column in other row of the same bank: To execute the following read command, it is
necessary to execute a precharge command and a bank active command.
3. Operation for another bank: For another bank in active state, the following read command can be
executed from the next cycle after the preceding write command is issued. If another bank is in idle state, a
bank active command should be executed prior to execute the following read command.
HM5283206 Series
51
Block Write Command to Read Command Interval:
1. Operation for a column in the same row : Within the same row, it is necessary to take no less than t BWC
between a block write and the following read command. If tCK is less than tBWC, NOP command should be
issued for the cycle between a block write command and the following read command.
Block Write Command to Read Command Interval
B0 B1 B2 B3
Command
CLK
DQM
DQ out
Block write
read Dout
Bwrite
CAS Latency = 1
Burst Length = 4
t
read
CAS Latency
BWC
Column A
Column B Column B
2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command
and a bank active command before the following write or another block write operation.
3. Operation for another bank: To execute a read command for another bank in active state, tBWC interval to
the next command is necessary. If another bank is in idle state, bank active command should be executed.
If t CK is less than tBWC, NOP command should be issued for the cycle between a block write command and
the following read command.
HM5283206 Series
52
Read Command to Precharge Command: The minimum interval between read command and precharge
command is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by
lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input
during burst read. To read all data by burst read, the cycles defined by l EP must be assured as an interval
from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (Same Bank): Output All Data.
CAS Latency = 1, Burst Length = 4
0123
Command
CLK
DQout
Pre.
CL = 1 I = 0 cycle
read
EP
CAS Latency = 2, Burst Length = 4
Command
CLK
DQout
Pre.
CL = 2 I = -1cycle
EP
0123
read
CAS Latency = 3, Burst Length = 4
0123
Command
CLK
DQout
Pre.
CL = 3
read
I = -2cycle
EP
HM5283206 Series
53
READ to PRECHARGE Command Interval (Same Bank): Stop Output Data.
CAS Latency = 1, Burst Length = 4
0
Command
CLK
DQout
Pre.
I = 1
High-Z
read
HZP
CAS Latency = 2, Burst Length = 4
0
Command
CLK
DQout
Pre.
High-Z
I = 2
HZP
read
CAS Latency = 3, Burst Length = 4
0
read
Command
CLK
DQout
Pre.
I = 3
High-Z
HZP
HM5283206 Series
54
Write Command to Precharge Command: The minimum interval between a write command and the
following precharge command is 1 cycle. However, if the burst write operation is not finished, input must
be masked by means of DQM for the cycle defined by tWR, for assurance.
WRITE to Precharge Command Interval (Same Bank)
Burst Length = 4 (To Stop Write Operation)
write
Command
CLK
DQM
DQin A0
Pre.
t
A1
WR
Burst Length = 4 (To Write All Data)
write
Command
CLK
DQM
DQin A0
Pre.
t
A1 A2 A3
WR
HM5283206 Series
55
Block Write Command to Precharge Command Interval: The minimum interval between block write
command and the following precharge command is tBWR.
Block Write to Precharge Command Interval (Same Bank)
BwriteCommand
CLK
Pre.
tBWR
Register set to register set interval: The minimum interval between two successive register set
commands (mode/special mode) is lRR.
Mode register set to special mode register interval
CLK
Command
Address
SMRS
A5,A6
DQ in color
/mask
MRS
A0-A9
IRR
Special Mode Register Set to Block Write/Write Interval: The minimum interval between a special
mode register set and a block write/write is tSBW.
Special Mode Register Set to Burst Write Interval
SMRS
A5,A6
tSBW
write
column
color
/mask
Burst length = 2
CLK
Command
Address
DQ in 01
HM5283206 Series
56
Bank Active Command Interval:
1. Operation for the same bank: The interval between two bank-active commands must be no less than tRC.
2. Operation for another bank: The interval between two bank-active commands must be no less than tRRD.
Bank Active to Bank Active for the Same Bank
Command
CLK
t
ACT
row row
Address
A9(BS)
RAS
Pre ACT
tRC
tRP
Bank Active to Bank Active for Another Bank
t
A9(BS)
CLK
Command ACT ACT
Address row row
RRD
HM5283206 Series
57
Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to VSS VT–1.0 to +4.6 V 1
Supply voltage relative to VSS VDD –1.0 to +4.6 V
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Note: 1. VIH (max) = 5.75 V for pulse width ≤ 5 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Max Unit Notes
Supply voltage VDD, VDDQ 3.0 3.6 V 1
VSS, VSSQ0 0 V
Input high voltage VIH 2.0 4.6 V 1, 2
Input low voltage VIL –0.3 0.8 V 1, 3
Notes: 1. All voltage referred to VSS
2. VIH (max) = 5.5 V for pulse width ≤ 5 ns
3. VIL (min) = –1.0 V for pulse width ≤ 5 ns
HM5283206 Series
58
DC Characteristics (Ta = 0 to 70°C, VDD, VDDQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HM5283206
-8 -10 -12
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Note
Operating current ICC1 — 210 — 180 — 150 mA Burst length = 1
tRC = min, CL = 3
tCK = min
1
Standby current
(Bank Disable) ICC2 — 5 — 5 — 5 mA CKE = VIL, tCK = min
— 3 — 3 — 3 mA CKE = VIL
CLK = VIL
or V
IH Fi x ed
— 95 — 75 — 60 mA CKE = VIH, tCK = min
NOP command
Active standby current
(Bank active) ICC3 — 15 — 10 — 10 mA CKE = VIL, tCK = min,
DQ = High-Z 1
— 100 — 80 — 65 mA CKE = VIH, tCK = min,
NOP command
DQ = High-Z
Burst operating current
(CL = 1) ICC4 — 220 — 170 — 140 mA tCK = min, BL = 4,
2 bank operation 1
(CL = 2) ICC4 — 280 — 240 — 200 mA
(CL = 3) ICC4 — 330 — 280 — 240 mA
Refresh current ICC5 — 190 — 150 — 120 mA tRC = min, CL = 3
tCK = min
Self refresh current ICC6 —4 —4 —4 mAV
IH ≥ VDD – 0.2
VIL ≤ 0.2 V
Block write operating
current ICC7 — 200 — 160 — 130 mA tCK = min, CL = 3
1 bank operation,
tRC = 150 ns
Input leakage current ILI –10 10 –10 10 –10 10 µA0 ≤ Vin ≤ VDD
Output leakage current ILO –10 10 –10 10 –10 10 µA0 ≤ Vout ≤ VDD
DQ = disable
Output high voltage VOH 2.4 — 2.4 — 2.4 — V IOH = –2 mA
Output low voltage VOL — 0.4 — 0.4 — 0.4 V IOL = 2 mA
Note: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified on
condition that all output pins are floated.
HM5283206 Series
59
Capacitance (Ta = 25°C, VDD, VDDQ = 3.3 V ± 0.3 V)
Parameter Symbol Typ Max Unit Notes
Input capacitance (Address) CI1 — 5 pF 1
Input capacitance (Signals) CI2 — 5 pF 1
Output capacitance (DQ) CO— 7 pF 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. DQM = VIH to disable Dout.
HM5283206 Series
60
AC Characteristics (Ta = 0 to 70°C, VDD, VDDQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HM5283206
-8 -10 -12
Parameter Symbol Min Max Min Max Min Max Unit Notes
System clock cycle time
(CL = 1) tCK 24 — 30 — 36 — ns 1
(CL = 2) tCK 12 — 15 — 18 — ns
(CL = 3) tCK 8 — 10 — 12 — ns
CLK high pulse width tCH 3— 3— 4— ns1
CLK low pulse width tCL 3— 3— 4— ns1
Access time from CLK
(CL = 1) tAC — 23 — 28 — 32 ns 1, 2
(CL = 2) tAC —11 —13 —15 ns
(CL = 3) tAC —7 —8 —10 ns
Access time from CAS tCAC — 23 — 28 — 32 ns 1, 2
Data-out hold time tOH 3— 3— 3— ns1
CLK to data-out low impedance tLZ 0— 0— 0— ns1
CLK to data-out high impedance
(CL = 1) tHZ — 11 — 13 — 15 ns 1, 3
(CL = 2,3) tHZ —6 —7 —9 ns
Data-in setup time tDS 2.5 — 3 — 3.5 — ns 1
Data-in hold time tDH 1— 1— 1.5— ns1
Address setup time tAS 2.5 — 3 — 3.5 — ns 1
Address hold time tAH 1— 1— 1.5— ns1
CKE setup time tCKS 2.5 — 3 — 3.5 — ns 1, 4
CKE hold time tCKH 1 — 1 — 1.5 — ns 1, 4
Command (CS, RAS, CAS, WE,
DQM, DSF) setup time tCMS 2.5 — 3 — 3.5 — ns 1
Command (CS, RAS, CAS, WE,
DQM, DSF) hold time tCMH 1— 1— 1.5— ns1
Refresh/active to refresh/active
command period tRC 72 — 90 — 108 — ns 1
Active to precharge on full page
mode tRASC — 120000 — 120000 — 120000 ns 1
Active to precharge command
period tRAS 48 120000 60 120000 72 120000 ns 1
Active command to column
command tRCD 24 — 30 — 36 — ns 1
HM5283206 Series
61
AC Characteristics (Ta = 0 to 70°C, VDD, V DDQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
(cont)
HM5283206
-8 -10 -12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Precharge to active command period tRP 24 — 30 — 36 — ns 1
The last data-in to precharge lead time
(CL = 1) tWR 12 — 15 — 18 — ns 1
(CL = 2) tWR 12 — 15 — 18 — ns
(CL = 3) tWR 16 — 20 — 24 — ns
Block write to precharge lead time
(CL = 1) tBWR 24 — 30 — 34 — ns 1
(CL = 2) tBWR 24 — 30 — 34 — ns
(CL = 3) tBWR 24 — 30 — 36 — ns
Active (a) to active (b) command period tRRD 16 — 20 — 24 — ns 1
Register set to active command tRSC 16 — 20 — 24 — ns 1
Block write cycle time tBWC 16 — 20 — 24 — ns 1
Special mode register set to column
command tSBW 16 — 20 — 24 — ns 1
Transition time (rise to fall) tT151515ns
Refresh period tREF —16—16—16ms
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.4 V.
Test load (A) is used with CL = 30 pF in general except for the measurement of access time
(note2) and tHZ (note3).
2. Access time is measured at 1.4 V. Test load (B) is used with current source.
3. tHZ (max) defines the time at which the outputs achieves ± 200 mV. Test load (A) is used with CL
= 5 pF and with current source.
4. When Active Suspend Exit, Power Down Exit or Self Refresh Exit is executed.
CKE should be kept “H” more than 1 cycle from these Exit cycles.
HM5283206 Series
62
Test Conditions
• Input and output timing reference levels: 1.4 V
• Input waveform and output load: See following figures
t
T
2.8 V
VSS
input 80%
20%
tT
500 Ω
+1.4 V
DQ
CL
50 Ω
+1.4 V
30 pF
LVTTL interface
Test Load (A) Test Load (B)*
Output
DQ I
IOL (max) = 20mA
IOH (min) = –20mA
*
HM5283206 Series
63
Relationship Between Frequency and Minimum Latency
HM5283206
Parameter -8 -10 -12
CL 321321321
t
CK (ns) Symbol 8 12 24 10 15 30 12 18 36 Notes
Last data in to active command
(Auto precharge, same bank) lAPW 532532532
Block write to active command
(Auto precharge, same bank) lAPBW 642642642
Precharge command to high
impedance lHZP 321321321
Last data out to active command
(Auto precharge, same bank) lAPR 111111111
Last data out to precharge lEP –2 –1 0 –2 –1 0 –2 –1 0
Column command to column
command lCCD 111111111
Write command to data in latency lWCD 000000000
DQM to data in lDID 000000000
DQM to data out lDOD 222222222
CKE to CLK disable lCLE 111111111
Burst stop to output valid data
hold lBSR 210210210
Burst stop to output high
impedance lBSH 321321321
Burst stop to write data ignore lBSW 000000000
MRS to data in latency lMSD 000000000
SMRS to data in latency lSSD 000000000
Register set to register set lRR 221221221
HM5283206 Series
64
Timing Waveforms
Read Cycle
Bank 0
Active Bank 0
Read Bank 0
Precharge
t
RAS
t
RCD
t
CMH
t
CMS
t
CMH
t
CMS
t
CH
t
t
CK
t
AC
t
AC
CL
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A0 to A7
DQM
DQ(input)
DQ(output)
t
CAC
t
AC
t
OH
t
OH
t
HZ
t
OH
t
RP
t
RC
Burst length = 4
Bank0 Access
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
AH
t
AS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AC
t
LZ
V
IH
HM5283206 Series
65
Write Cycle
CLK
CKE
CS
t
RAS
t
RCD
RAS
CAS
WE
A9
A8
DQM
DQ(input)
DQ(output)
t
CMH
t
CMS
t
CH
t
t
CK
t
DH
t
DH
CL
t
DH
t
DH
t
DS
t
DS
t
DS
t
DS
t
RP
t
RC
Burst length = 4
Bank 0 Access
t
WR
Bank 0
Write
t
CMH
t
CMS
Bank 0
Active Bank 0
Precharge
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
CMH
t
CMS
t
AH
t
AS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
CMH
t
CMS
t
AH
t
AS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
AH
t
AS
t
AH
t
AS
V
IH
A0 to A7
HM5283206 Series
66
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
CS
RAS
CAS
WE
A9(BS)
A0 to A7
DQM
DQ(input)
DQ(output)
High-Z
bb+3 b’ b’+1 b’+2 b’+3
t
valid C: b’
RSC
code
tRCD
tRP
Precharge
If needed Mode register
Set Bank 1
Active Bank 1
Read
R: b C: b
Output mask
V
IH
t
RCD
= 3
CAS latency = 3
Burst length = 4
Read Cycle/Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
R:a C:a R:b C:b C:b' C:b"
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
CLK
A9(BS)
R:a C:a R:b C:b C:b' C:b"
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1b"+2 b"+3
Bank 0
Active Bank 0
Read Bank 1
Active Bank 1
Read Bank 1
Read Bank 1
Read
Bank 0
Precharge Bank 1
Precharge
Bank 0
Active Bank 0
Write Bank 1
Active Bank 1
Write Bank 1
Write Bank 1
Write
Bank 0
Precharge Bank 1
Precharge
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
A9(BS)
High-Z
High-Z
V
IH
V
IH
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
HM5283206 Series
67
Read/Single Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
R:a C:a R:b C:a'
R:a C:a C:a
a
a
a
a
Bank 0
Active Bank 0
Read Bank 1
Active Bank 0
Write Bank 0
Precharge Bank 1
Precharge
Bank 0
Active Bank 0
Read Bank 0
Write Bank 0
Precharge
R:b
Bank 1
Active
C:a
Bank 0
Read
a a+1 a+2 a+3
Bank 0
Write Bank 0
Write
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
CLK
A9(BS)
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
A9(BS)
C:b
bc
a+1 a+3
a+1 a+2 a+3
C:c
VIH
VIH
Read/Single write
RAS-CAS delay = 3
CAS Latency = 3
Burst length = 4
HM5283206 Series
68
Read/Burst Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
R:a C:a R:b C:a'
R:a C:a C:a
a a+1 a+2 a+3
a+1
a a+1 a+2 a+3
Bank 0
Active Bank 0
Read Bank 0
Write Bank 0
Precharge
R:b
Bank 1
Active
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
CLK
A9(BS)
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
A9(BS)
a+1 a+2 a+3
a a+3
a
Bank 0
Active Bank 0
Read Bank 1
Active Clock
suspend Bank 0
Write Bank 0
Precharge Bank 1
Precharge
VIH
Read/Single write
RAS-CAS delay = 3
CAS Latency = 3
Burst length = 4
HM5283206 Series
69
Full Page Read/Write Cycle
High-Z
R:a C:a R:b
R:a C:a R:b
High-Z
Bank 0
Active Bank 0
Read Bank 1
Active Burst stop Bank 1
Precharge
Bank 0
Active Bank 0
Write Bank 1
Active Burst stop Bank 1
Precharge
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
CLK
A9(BS)
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
A9(BS)
V
IH
V
IH
a-2a a+1 a+2 a+3 a a+1 a+2 a+3 a+4a-1 a+5
Read cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = full page
Write cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = full page
a a+1 a+2 a+3 a+1 a+2 a+3 a+4 a+5
a+6
a+5a+4
01234567 8 9 260 261 262 263 264 265 266 267 268 269
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
CS
CAS
WE
A9(BS)
A0 to A7
DQM
DQ(input)
DQ(output)
High-Z
RP Refresh cycle and
Read cycle
RAS-CAS delay=2
CAS latency=2
Burst length=4
Precharge
If needed Auto Refresh Active
Bank 0
tRC
tRC
t
Auto Refresh Read
Bank 0
R:a C:a
A8=1
RAS
aa+1
VIH
HM5283206 Series
70
Self Refresh Cycle
CLK
CKE
CS
RAS
CAS
WE
A9(BS)
A0 to A7
DQM
DQ(input)
DQ(output)
Self refresh cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
Precharge command
If needed Self refresh entry
command Auto refresh
Self refresh exit
ignore command
or No operation
CKE Low
A8=1
RC
t
RP
t
High-Z
Clock Suspend Mode
012345 6 7 8 9 1011121314151617181920
R:a C:a R:b
a a+1 a+2 a+3 b b+1 b+2
R:a C:a R:b C:b
a a+1 a+2 b b+1 b+2 b+3
C:b
Bank0
Active Active clock
suspend start Active clock
supend end
Bank0
Read
Bank1
Active
Read suspend
start Read suspend
end Bank0
Precharge
Bank1
Read Earliest Bank1
Precharge
Bank0
Write
Bank0
Active Active clock
suspend start Active clock
suspend end Bank1
Active
Write suspend
start Write suspend
end Bank1
Write Bank0
Precharge Earliest Bank1
Precharge
b+3
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
CLK
A9(BS)
CKE
RAS
CS
CAS
WE
A0 to A7
DQM
DQ
(input)
DQ
(output)
A9(BS)
a+3
High-Z
High-Z
tCKS tCKH tCKS
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
Write cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
Power Down Mode
HM5283206 Series
71
CLK
CKE
CS
RAS
CAS
WE
A9(BS)
A0 to A7
DQM
DQ(input)
DQ(output)
Precharge command
If needed Power down entry
Active Bank 0
Power down
mode exit
CKE Low
R: a
A8=1
RP
t
High-Z
Power down cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
tCKS
HM5283206 Series
72
Mask Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK
CKE
CS
RAS
CAS
WE
DSF
A0 to A7
DQM
DQ in
aa+3 b
a+2
t
Cb
RSC
A5 = 1
tRP
Precharge
If needed Mask register
Set Bank 0
ACTVM Bank 1
ACTV
Ra Ca
VIH
A8
A9
Mask
Data
Ra
Mask
Rb
Rb
Bank 0
Write per bit
No Mask
b+1
Bank 1
Write
HM5283206 Series
73
Color Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK
CKE
CS
RAS
CAS
WE
DSF
A0 to A7
DQM
DQ in
Column
MASK
t
Cc
RSC
A6 = 1
tRP
Precharge
If needed Color register
Set Bank 0
ACTVM Bank 1
ACTV
Ra Ca
VIH
A8
A9
Color
Data
Ra
Mask
Rb
Rb
Bank 0
Mask Block Write
Bank 1
Block Write
No
Mask
Cb
Column
MASK Column
MASK
HM5283206 Series
74
Write Cycle (with I/O Mask)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK
CKE
CS
RAS
CAS
WE
DSF
A0 to A7
DQM
DQ in
Ra
Bank 0
ACTVM Bank 1
ACTV Bank 0
Write per bit Bank 1
Write
Rb Cb
VIH
A8
A9
a
Ra
Rb
Bank 0
Precharge
Ca
a + 2 a + 3 bb + 1 b + 3
HM5283206 Series
75
Block Write Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK
CKE
CS
RAS
CAS
WE
DSF
A0 to A7
DQM
DQ in
Ra
Bank 0
ACTVM Bank 0
Mask Block
Write
Bank 1
ACTV Bank 1
Block Write
Rb Cb
VIH
A8
A9
Column
MASK
Ra
Rb
Bank 0
Precharge
Ca
Cc
Cd
Column
MASK Column
MASK Column
MASK
Bank 0
Mask Block
Write
Bank 1
Block Write
BWC
t
HM5283206 Series
76
Package Dimensions
HM5283206FP Series (FP-100J)
0.13 M
0.32 ± 0.08
23.20 ± 0.20
20.00
80 51
50
31
30
1
100
81
17.20 ± 0.20
14.00
1.60
0.80 ± 0.20
3.00 Max
0.15 ± 0.15
0.17 ± 0.05
0.65
0.10
0.825
0.575
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-100J
—
Conforms
1.64 g
2.70
0° – 10°
0.30 ± 0.06
0.15 ± 0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HM5283206 Series
77
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
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7/F., North Tower, World Finance Centre,
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Tel: <852> (2) 735 9218
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Telex: 40815 HITEC HX
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Maidenhead
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Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
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Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA 94005-1897
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
For further information write to:
HM5283206 Series
78
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Oct. 20, 1994 Initial issue Y. Saiki T. Kizaki
0.1 Nov. 11, 1994 Commands Operation
Change of column block and DQ input at the block write
cycle and column mask location
Operation of HM5283206 Series
Change of column block and the order of burst operation
Addition of description for read command to write or
block write command interval (3)
Change of figure for bank active command interval
AC Characteristics
tOH min: 2/2/2 ns to 3/3/3 ns
tHZ (CL = 1) max: 10/12/14 ns to 13/15/17 ns
tCKS min: 3/2/2 ns to 3/3/3 ns
tCKH min: 1/2/2 ns to 1/1/1 ns
tRC min: 90/100/125 ns to 90/108/135 ns
tRAS min: 60/70/80 ns to 60/72/90 ns
Change of Timing Waveforms: Read Cycle/Write Cycle,
Color Register Set Cycle and Block Write Cycle
Y. Saiki T. Kizaki
0.2 Nov. 20, 1995 Deletion of HM5283206TT Series
Change of Simplified State Diagram
Commands Operation
Change of description for Commands Operation
Change of figure for Column address and write command
BL = 2
Change of description for Graphic Commands
Change of Command Truth Table and CKE Truth Table
Change of Function Truth Table:
Change of notes 5
Addition of notes 6
Operation of HM5283206 Series
Addition of note for read with auto precharge, write with
auto precharge and power down mode
Change of figure for write per bit, block write,
read command to read command interval,
write command to write command interval
and write command to precharge command
AC Characteristics
Change of figure for Test load (B)
DC Characteristics
ICC1 max: TBD to 180/150/120 mA
ICC2 max: TBD to 5/5/5 mA
ICC2 max: TBD to 3/3/3 mA
ICC2 max: TBD to 75/60/50 mA
ICC3 max: TBD to 10/10/10 mA
ICC3 max: TBD to 80/65/55 mA
ICC4 (CL = 1) max: TBD to 170/140/110 mA
ICC4 (CL = 2) max: TBD to 240/200/160 mA
ICC4 (CL = 3) max: TBD to 280/240/190 mA
ICC5 max: TBD to 150/120/100 mA
Y. Saiki T. Kizaki
HM5283206 Series
79
Rev. Date Contents of Modification Drawn by Approved by
0.2 Nov. 20, 1995 DC Characteristics
ICC6 max: 2/2/2 mA to 4/4/4 mA
Addition of ICC7 max: 160/130/110 mA
Y. Saiki T. Kizaki
0.2 Nov. 20, 1995 AC Characteristics
tHZ min: 2/2/2 ns to —/—/— ns
tDS, tAS, tCKS, tCMS min: 3/3/3 ns to 3/3.5/4 ns
tDH, tAH, tCKH, tCMH min: 1/1/1 ns to 1/1.5/2 ns
Addition of tRASC max: 80000/80000/80000 ns
Change of notes 4
Change of Timing Waveforms
Read cycle, auto refresh cycle, self refresh cycle,
clock suspend mode and power down mode
Y. Saiki T. Kizaki
0.3 Feb. 15, 1996 AC Characteristics
t
R AS ma x : 10000/ 10000/ 10000 ns 120000/ 120000/ 120000
ns
t
R ASC
ma x : 80000/ 80000/ 80000 ns
120000/ 120000/ 120000 ns
Change of notes 4
Y. Saiki T. Kizaki
1.0 May. 30, 1996 Commands Operation
Change of CKE Truth Table Y. Saiki T. Kizaki
2.0 Jul. 30, 1997 Addition of HM5283206-8 Series
Deletion of HM5283206-15 Series
Change of CKE Truth Table
AC Characteristics
tAC (CL = 1) max: 22 ns to 23 ns
Change of package informations: Height (max) 3.10 to 3.00
M. Suzuki T. Kizaki
3.0 Nov. 20, 1997 DC Characteristics
ICC1 max: TBD/180/150 mA to 210/180/150 mA
ICC2 max: TBD/5/5 mA to 5/5/5 mA
ICC2 max: TBD/3/3 mA to 3/3/3 mA
ICC2 max: TBD/75/60 mA to 95/75/60 mA
ICC3 max: TBD/10/10 mA to 15/10/10 mA
ICC3 max: TBD/80/65 mA to 100/80/65 mA
ICC4 (CL = 1) max: TBD/170/140 mA to 220/170/140 mA
ICC4 (CL = 2) max: TBD/240/200 mA to 280/240/200 mA
ICC4 (CL = 3) max: TBD/280/240 mA to 330/280/240 mA
ICC5 max: TBD/150/120 mA to 190/150/120 mA
ICC6 max: TBD/4/4 mA to 4/4/4 mA
ICC7 max: TBD/160/130 mA to 200/160/130 mA
H. Suzuki K. Hayakawa
4.0 Jan. 20, 1998 Correct error H. Suzuki K. Hayakawa
HM5283206 Series
80
Rev. Date Contents of Modification Drawn by Approved by
5.0 May. 19, 1998 Correct errors
Change of figures for
Column address and write command (BL = 2),
READ to PRECHARGE command interval:
Output all data (CL = 2),
Special mode register set (load mask) in idle state and
block write
Change of description for Precharge command and
Graphic commands note
Change of simplified State Diagram
AC Characteristics
tBWR (CL = 1), (CL = 2) min: 24/30/36 ns to 24/3034 ns
H. Suzuki K. Hayakawa
6.0 Oct. 2, 1998 Correct errors
Column address and block write command:
A0 to A1 HIGH or LOW to A0 to A2 HIGH or LOW
CKE Truth Table
Change of DSF (self refresh): L to ×
