HM5283206 Series 8M LVTTL interface SGRAM 125 MHz/100 MHz/83 MHz 128-kword x 32-bit x 2-bank ADE-203-223F (Z) Rev. 6.0 Oct. 2, 1998 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for graphic applications. Features * * * * * * * * * * * * * 3.3V Power supply Clock frequency: 125 MHz/100 MHz/83 MHz (max) LVTTL interface 2 Banks can operates simultaneously and independently Burst read/write operation and burst read/ single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Programmable CAS latency: 1/2/3 Byte control by DQM 8 column block write function with column address mask Write per bit function (old mask) Refresh cycles: 1024 refresh cycle/16 ms 2 variations of refresh Auto refresh Self refresh HM5283206 Series Ordering Information Type No. Frequency 1 HM5283206FP-8* HM5283206FP-10 HM5283206FP-12 Note: 125 MHz* 100 MHz 83 MHz Package 1 100-pin plastic QFP (FP-100J) 1. Under development Pin Arrangement 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC(Vref) DQM3 DQM1 CLK CKE DSF NC A8 HM5283206FP Series 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS A9 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ0 DQ1 VSSQ DQ2 (Top view) 2 A7 A6 A5 A4 VSS NC NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0 HM5283206 Series Pin Description Pin name Function A0 to A9 Address input Row address A0 to A8 Column address A0 to A7 Bank select address (BS) A9 DQ0 to DQ31 Data-input/output CS Chip select RAS Row address asserted bank enable CAS Column address asserted WE Write enable DQM0 to DQM3 Byte input/output mask CLK Clock input CKE Clock enable VDD Power for internal circuit VSS Ground for internal circuit VDDQ Power for DQ internal circuit VSS Q Ground for DQ internal circuit DSF Special function input flag NC No connection 3 HM5283206 Series Block Diagram A0 to A9 A0 to A7 Column address counter A0 to A9 Column address buffer Column decoder Memory array Bank 0 Output buffer Memory array Bank 1 512 row X 256 column X 32 bit Control logic & timing generator Mask register 512 row X 256 column X 32 bit Sense amplifier & I/O bus Row decoder Color register Sense amplifier & I/O bus Column decoder Row decoder Input buffer Refresh counter Row address buffer 4 DSF DQM0 DQM1 DQM2 DQM3 WE CAS RAS CS CKE CLK DQ0 to DQ31 HM5283206 Series Pin Functions CLK (input pin): CLK is the master clock input pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. DSF (input pin): DSF is a part of inputs of graphic commands of the HM5283206. If DSF is LOW, the HM5283206 operates as standard synchronous DRAM. A0 to A8 (input pins): Row address (AX0 to AX8) is determined by A0 to A8 pins at the CLK rising edge when a bank active command is input. Column address (AY0 to AY7) is determined by levels on A0 to A7 pins at the CLK rising edge when a read or write command is input. A8 determines precharge mode. When A8 is low, only the bank selected by A9 (BS) is precharged by a precharge command. When A8 is high, both banks are precharged by a precharge command. A9 (input pin): A9 is the bank select signal (BS). The memory array of the HM5283206 is divided into the bank 0 and the bank 1, both contain 512 row x 256 column x 32 bits. If A9 is Low, the bank 0 is selected, and if A9 is High, the bank 1 is selected. CKE (input pin): By referring low level on CKE pin, HM5283206 determines to go into clock suspend modes or power down modes. In self refresh mode, low level on this pin is also referred to turn on refresh process. DQM0, DQM1, DQM2 and DQM3 (input pins): DQM0 applies to DQ0 to DQ7. DQM1 applies to DQ8 to DQ15. DQM2 applies to DQ16 to DQ23. DQM3 applies to DQ24 to DQ31. In read mode, referring high level on DQM pins, HM5283206 floats related DQ pins. In write mode, referring high level on DQM pins, HM5283206 ignores input data through related DQ pins. DQ0 to DQ31 (input/output): These are the data line for the HM5283206. VDD and VDDQ (power supply pins): 3.3 V is applied. (VDD is for the internal circuit and VDDQ is power supply pin for DQ output buffer.) VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSS Q is for DQ output buffer.) 5 HM5283206 Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET *1 AUTO REFRESH REFRESH IDLE CKE SMRS CKE_ ACTIVM IDLE POWER DOWN ACTIV SPECIAL MODE REGISTER SET SMRS CKE ROW ACTIVE BST WRITE Write WRITE/ BWRITE SUSPEND CKE_ WRITE/ BWRITE WRITE/ BWRITEA SUSPEND READ WITH AP WRITE/ BWRITE WRITE/ BWRITE WITH AP WRITE/ BWRITEA Read CKE_ READ CKE POWER ON READ SUSPEND READ WITH AP CKE_ READA CKE PRECHARGE POWER APPLIED READ WITH AP PRECHARGE CKE_ CKE BST READ WRITE/ BWRITE WITH AP READ CKE WRITE WITH AP Active Suspend CKE_ READA SUSPEND PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 6 HM5283206 Series Commands Operation Commands Explanation Every operations of HM5283206 are executed by input commands. A command is input, at the rising edge of CLK, by setting the levels on CS, RAS, CAS, WE, A8 (auto precharge) and DSF pins, HIGH (VIH) or LOW (VIL ). Note: The setup and hold condition should be obeyed when command, address or data is input. Setup and Hold Condition of Command, Address and Data Input CLK Command tCMS t CMH Address t AS t AH Data t DS t DH 7 HM5283206 Series Precharge command [PRE, PALL]: At the CLK rising edge, by setting CS, RAS, WE, DSF are LOW, CAS is HIGH bank can be precharged to idle state. A8 = LOW: the bank selected by A9 is precharged. A8 = HIGH: both banks are precharged. [State transition] power on -- (precharge) -> Idle Row active -- (precharge) -> Idle Precharge Command CLK CKE VIH CS RAS CAS WE DSF A8 A9 A0 to A7 DQ 8 High-Z HM5283206 Series Mode register set command [MRS]: If both banks have been precharged or are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, WE, DSF; LOW an internal register (the mode register; MRS) are set. The data through address pins, at the cycle when this command is input, are stored in the mode register. A8, A9 bits determine burst write or single write. A6 to A4 bits determine CAS latency. A3 bit determines burst type, sequential or interleave. A2 to A0 bits determine burst length. A7 bit should be set to low. See table below for details. [State transition] Idle -- (Mode resister set) ->Idle Mode Register Set Command CLK CKE VIH CS RAS CAS WE DSF A8, A9 A6 to A4 A3 A2 to A0 OP CODE CAS Latency Burst type Burst length A7 DQ High-Z 9 HM5283206 Series Mode Register Configuration A9 A8 Operation CODE 0 0 Burst read and burst write 0 1 R 1 0 Burst read and single write 1 1 R A6 A5 A4 CAS latency 0 0 0 R 0 0 1 1 0 1 0 2 0 1 1 3 1 x x R A3 Burst type 0 Sequential 1 Interleave Burst length A2 A1 A0 BT = 0 BT = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 R R 1 0 1 R R 1 1 0 R R 1 1 1 Full page R Note: R: Reserved 10 HM5283206 Series Bank and row active command [ACTV, ACTVM]: If a bank has been precharged or is in idle state. At the CLK rising edge, by setting CS, RAS; LOW, CAS, WE: HIGH a row of the bank is activated. The bank is selected by setting the level on A9 pin HIGH (bank 1) or LOW (bank 0) at this timing. A0 to A8 determine the row address. [Option] DSF = LOW; write per bit function disable (ACTV) DSF = HIGH; write per bit function enable (ACTVM) [State transition] Idle -- (row active) ->Row active Bank and Row Active Command CLK CKE VIH CS RAS CAS WE DSF A9 A0 to A8 DQ High-Z 11 HM5283206 Series Column address and read command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF; LOW, RAS, WE; HIGH, data is output through DQ pins. A9 determines the bank address. A0 to A7 determine the column address. CAS latency stored in MRS determines the timing when data are driven. In case, CL (CAS latency) = 1, 1 clock cycle after the command input, data start to be output. In case CL = 2, 2 clock cycle after the command input, data start to be output. In case CL = 3, 3 clock cycle after the command input, data start to be output. Burst Length (BL) stored in MRS determines data length of output . [Option] A8 = HIGH; auto precharge mode or execute precharge automatically after finishing data output. A8 = LOW; Read mode without auto precharge. [State transition] Row active -- (Column address and read command) ->Row active Row active -- (Column address and read command) ->Idle (auto precharge) Column Address and Read Command CL = 1, BL = 1. CLK CKE VIH CS RAS CAS WE DSF A8 A9 A0 to A7 DQ (out) 12 High-Z HM5283206 Series Column address and write command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF, WE; LOW, RAS; HIGH, the data on DQ pins are input. A9 determines the bank address. A0 to A7 determine the column address. For write, data should start to be input at the same cycle of the command input. Burst length stored in MRS determines the expected data length to be input. If the bank, for which command is input, is activated by ACTVM, then I/O bit mask function or write per bit is available. [Option] A8 = HIGH; auto precharge mode or execute precharge automatically after finishing data input. A8 = LOW; write mode without auto precharge. [State transition] Row active -- (Column address and write command) ->Row active Row active -- (Column address and write command) ->Idle (auto precharge case) Column Address and Write Command (BL = 2) CLK CKE VIH CS RAS CAS WE DSF A8 A9 A0 to A7 DQ (in) High-Z 13 HM5283206 Series Burst stop command (BST): At the CLK rising edge, by setting CS, WE, DSF: LOW, RAS, CAS; HIGH, full page burst (BL = 256) read/write is interrupted. If BL is set to 1, 2, 4, 8, to try to execute this command is illegal. [State transition] Row active -- (Burst stop command) -> Row active Burst Stop Command CLK CKE VIH CS RAS CAS WE DSF A0 to A9 14 HM5283206 Series Auto refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, DSF; LOW, WE; HIGH, the HM5283206 starts auto-refresh (CBR type) operation. Refresh address is internally generated. No precharge commands are required after autorefresh, since precharge is automatically performed for both banks. [State transition] Idle -- (Auto refresh command) -> Idle Auto Refresh Command CLK CKE VIH CS RAS CAS WE DSF A0 to A9 DQ High-Z 15 HM5283206 Series Self refresh command (REF): If both banks are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, DSF; LOW, WE; HIGH, and if CKE's falling edge is detected, the HM5283206 starts self-refresh operation. Self-refresh operation is kept while CKE is LOW. [State transition] Idle -- (Self refresh command) -> Self refresh mode Self Refresh Command CLK CKE CS RAS CAS WE DSF A0 to A9 DQ 16 High-Z HM5283206 Series No operation command (NOP): At the CLK rising edge, by setting CS; LOW, WE, RAS, CAS; HIGH, [State transition] No transition No Operation Command CLK CKE VIH CS RAS CAS WE DSF A0 to A9 DQ High-Z Ignore command (DESL): At the CLK rising edge, by setting CS; HIGH, any input is ignored. 17 HM5283206 Series Graphic Commands Special mode register set command (SMRS): If each banks is in idle state or activated, at the CLK rising edge, by setting CS, RAS, CAS, WE; LOW, DSF; HIGH, an internal register (the special mode register; SMRS) are set. The data through address pins, at the cycle when this command is input, are stored in the special mode register. A0 to A4: reserved. should be LOW when SMRS is issued. A5: determines whether loading mask data or not when SMRS is issued. A6: determines whether loading color data or not when SMRS is issued. A7 to A9: reserved. should be set LOW when SMRS is issued. In case A5 bit of the mode register = HIGH, the data through DQ pins, at the cycle this command is issued, are stored in the MASK register (32 bits). If write per bit function is available*, and DQi (i = 0,..,31) bit of the MASK register = LOW, DQi data path to memory array is masked. In case A6 bit of the mode register HIGH, the data through DQ pins, at the cycle when this command is issued, are stored in the COLOR register (32 bits). This specific data is written to 8 columns in one clock cycle by block write command. Note: When bank active command is issued and DSF set to HIGH, write per bit function is enabled. Special Mode Register Set Command CLK CKE VIH CS RAS CAS WE DSF A0 to A4 A5 Load mask A6 Load color A7 to A9 DQ 18 High-Z HM5283206 Series Special Mode Register Configuration A5 A6 Function 0 x Disable 1 0 Enable x 0 Disable 0 1 Enable 1 1 ILLEGAL Load Mask Load Color Note: x: VIH or VIL Reserved Bits A0 A1 A2 A3 A4 A7 A8 A9 0 0 0 0 0 0 0 0 19 HM5283206 Series Graphic Function Block Diagram MASK register DQ 0 0 DQ 1 1 DQ 30 30 DQ 31 31 COLOR register 0 1 30 31 Memory Array I1 I2 When block write command is issued, data I1 stored in the COLOR register is loaded O into column block (8 columns) of memory array. For burst and single write, the data I2 from DQ pins are loaded into a single column. I1 I2 20 O When write per bit function is available, if mask data I1 stored in the MASK register is LOW then the data path from I2 to O is cut. HM5283206 Series Column address and block write command: For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, WE; LOW, RAS, DSF; HIGH, a block write *2 is executed. A9 determines the bank address. A0 to A2 HIGH or LOW (ignored). A3 to A7 determine the column block address. The data through DQ pins, at the cycle when the block write command input, are referred to stop the color data to be written onto the specific column. (Column mask) [Option] A8 = HIGH; Auto precharge mode or execute precharge automatically after finishing a block write execution. A8 = LOW; Write mode without auto precharge. [State transition] Row active -- (Block write command) ->Row active Row active -- (Block write command) ->Idle(auto precharge case) Column Address and Block Write Command CLK CKE VIH CS RAS CAS WE DSF A8 A9 A0 to A7 DQ High-Z 21 HM5283206 Series Column Block Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 0 0 a3 a4 a5 a6 a7 1 0 0 a3 a4 a5 a6 a7 0 1 0 a3 a4 a5 a6 a7 1 1 0 a3 a4 a5 a6 a7 0 0 1 a3 a4 a5 a6 a7 1 0 1 a3 a4 a5 a6 a7 0 1 1 a3 a4 a5 a6 a7 1 1 a3 a4 a5 a6 a7 1 Note: 22 1. a3, a4, a5, a6, a7; VIH or VIL. HM5283206 Series DQ Input at the Block Write Cycle and Column Mask Location Column location 1 Column mask DQ pin NO. DQ group* A0 A1 A2 No mask Mask DQ0 00 0 0 0 High Low DQ1 00 1 0 0 High Low DQ2 00 0 1 0 High Low DQ3 00 1 1 0 High Low DQ4 00 0 0 1 High Low DQ5 00 1 0 1 High Low DQ6 00 0 1 1 High Low DQ7 00 1 1 1 High Low DQ8 01 0 0 0 High Low DQ9 01 1 0 0 High Low DQ10 01 0 1 0 High Low DQ11 01 1 1 0 High Low DQ12 01 0 0 1 High Low DQ13 01 1 0 1 High Low DQ14 01 0 1 1 High Low DQ15 01 1 1 1 High Low DQ16 10 0 0 0 High Low DQ17 10 1 0 0 High Low DQ18 10 0 1 0 High Low DQ19 10 1 1 0 High Low DQ20 10 0 0 1 High Low DQ21 10 1 0 1 High Low DQ22 10 0 1 1 High Low DQ23 10 1 1 1 High Low DQ24 11 0 0 0 High Low DQ25 11 1 0 0 High Low DQ26 11 0 1 0 High Low DQ27 11 1 1 0 High Low DQ28 11 0 0 1 High Low DQ29 11 1 0 1 High Low DQ30 11 0 1 1 High Low DQ31 11 1 1 1 High Low Note: DQ group: 00; DQ0 to DQ7, 01; DQ8 to DQ15, 10; DQ16 to DQ23, 11; DQ24 to DQ31 23 HM5283206 Series Command Truth Table The HM5283206 recognizes the following commands specified by the CS, RAS, CAS, WE, DSF and address pins. All other combinations than those in the table bellow are illegal. CKE Function Symbol n-1 n CS RAS CAS WE DSF A9 A8 A0 to A7 Ignore command DESL* H x H x x x x x x x No operation NOP 2 H x L H H H x x x x Burst stop in full page 3 BST* H x L H H L L x x x Column address and read command READ H x L H L H L V L V Read with auto precharge READ A H x L H L H L V H V Column address and write command WRIT H x L H L L L V L V Write with auto precharge WRIT A H x L H L L L V H V Row address strobe and bank active ACTV H x L L H H L V V V Precharge select bank PRE H x L L H L L V L x Precharge all bank PALL H x L L H L L x H x Refresh (auto, self) REF, SELF H x L L L H L x x x Mode register set MRS H x L L L L L V V V Row address strobe and bank active and Masked write enable ACTVM H x L L H H H V V V Column address and block write command BWRIT H x L H L L H V L V Block write with auto precharge BWRITA H x L H L L H V H V Special mode register set SMRS H x L L L L H L L V Notes: 1. H: VIH. L: V IL. x: VIH or VIL. V: Valid address input. 2. When CS is high, the HM5283206 ignores command input. Internal operation is held. 3. Illegal if the burst length is 1, 2, 4 or 8. 24 HM5283206 Series DQM Truth Table CKE Function Symbol n-1 n DQM i Ith byte write enable/output enable ENB i H x L Ith byte write input/output disable MASK i H x H Note: H: VIH. L: V IL. x: VIH or VIL. i = 0, 1, 2, 3. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31 CKE Truth Table CKE Current state Function n-1 n CS RAS CAS WE DSF Address Active Clock suspend mode entry H L x x x x x x Any Clock suspend L L x x x x x x Clock suspend Clock suspend mode exit L H x x x x x x Idle Auto refresh command REF H H L L L H L x Idle Self refresh entry SELF H L L L L H L x Idle Power down entry H L x x x x x x Self refresh Self refresh exit L H L H H H x x L H H x x x x x L H L H H H x x L H H x x x x x Power down Power down exit Note: H: VIH. L: V IL. x: VIH or VIL. 25 HM5283206 Series Function Truth Table The following tables show how each command works and what command can be executed in the state given. Current state CS RAS CAS WE DSF Address Command Operation Precharge H x x x x x DESL NOP -> Idle after tRP L H H H x x NOP NOP -> Idle after tRP L H H L L x BST ILLEGAL*2, * 6 L H L H L BA, CA, A8 READ/READ A ILLEGAL*2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2 L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL NOP*3 L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 H x x x x x DESL NOP L H H H x x NOP NOP L H H L L x BST NOP*6 L H L H L BA, CA, A8 READ/READ A ILLEGAL*2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2 L L H H L BA, RA ACTV Bank and row active L L H L L BA, A8 PRE, PALL NOP*3 L L L H L x REF, SELF Auto self refresh*4 L L L L L MODE MRS Mode register set*4 L L H H H BA, RA ACTVM Bank and row active and write per bit enable L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 L L L L H Special MODE SMRS Idle 26 ILLEGAL ACTVM ILLEGAL*2 Special mode register set*5 HM5283206 Series Current state CS RAS CAS WE DSF Address Command Operation Row active H x x x x x DESL NOP L H H H x x NOP NOP L H H L L x BST NOP*6 L H L H L BA, CA, A8 READ/READ A Start read L H L L L BA, CA, A8 WRIT/WRIT A Start write L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL Precharge L L L x L L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A Start block write L L L L H Special MODE SMRS Special mode register set*5 H x x x x x DESL NOP -> Burst end -> Row active L H H H x x NOP NOP -> Burst end -> Row active L H H L L x BST Burst stop -> Row active*6 L H L H L BA, CA, A8 READ/READ A Term burst -> Start new read L H L L L BA, CA, A8 WRIT/WRIT A Term burst -> Start write L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL Term burst -> Precharge L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A Term burst -> Start block write Read with auto H precharge x x x x x DESL NOP -> Burst end -> Precharge L H H H x x NOP NOP -> Burst end -> Precharge L H H L L x BST ILLEGAL L H L H L BA, CA, A8 READ/READ A ILLEGAL*2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2 L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL ILLEGAL*2 L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 Read ILLEGAL ACTVM ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2 27 HM5283206 Series Current state CS RAS CAS WE DSF Address Command Operation Write/BWrite H x x x x x DESL NOP -> Burst end -> Write recovering L H H H x x NOP NOP -> Burst end -> Write recovering L H H L L x BST Burst stop -> Row active*6 L H L H L BA, CA, A8 READ/READ A Term burst -> Start read L H L L L BA, CA, A8 WRIT/WRIT A Term burst -> Start new write L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL Term burst -> Precharge L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A Term burst -> Start block write H x x x x x DESL NOP -> Burst end -> Write recovering with precharge L H H H x x NOP NOP -> Burst end -> Write recovering with precharge L H H L L x BST ILLEGAL L H L H L BA, CA, A8 READ/READ A ILLEGAL*2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2 L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL ILLEGAL*2 L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 H x x x x x DESL NOP -> Row active after t WR/tBWR L H H H x x NOP NOP -> Row active after t WR/tBWR L H H L L x BST NOP -> Row active after t WR/tBWR* 6 L H L H L BA, CA, A8 READ/READ A Start read*2 L H L L L BA, CA, A8 WRIT/WRIT A Start new write*2 L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL ILLEGAL*2 L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 Write/Bwrite with auto precharge Write/Bwrite recovering 28 ILLEGAL ACTVM ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2 HM5283206 Series Current state CS RAS CAS WE DSF Address Command Operation Write/Bwrite H recovering with precharge x x x x x DESL NOP -> Precharge after t WR/tBWR L H H H x x NOP NOP -> Precharge after t WR/tBWR L H H L L x BST ILLEGAL L H L H L BA, CA, A8 READ/READ A ILLEGAL*2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2 L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL ILLEGAL*2 L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 Row activating H x x x x x DESL NOP -> Row active after tRCD L H H H x x NOP NOP -> Row active after tRCD L H H L L x BST NOP -> Row active after t RCD* 6 L H L H L BA, CA, A8 READ/READ A ILLEGAL*2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL*2 L L H H L BA, RA ACTV ILLEGAL*2 L L H L L BA, A8 PRE, PALL ILLEGAL*2 L L L x x x L L H H H BA, RA L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL*2 H x x x x x DESL NOP -> Idle after tRC L H H H x x NOP NOP -> Idle after tRC L H H L L x BST NOP -> Idle after tRC* 6 L H L x x BA, CA, A8 ILLEGAL L L x x x x ILLEGAL H x x x x x DESL NOP -> Idle after tRSC L H H H x x NOP NOP -> Idle after tRSC L H H L L x BST ILLEGAL L H L x x BA, CA, A8 ILLEGAL L L x x x x ILLEGAL Refresh (auto precharge) Mode register set ILLEGAL ACTVM ILLEGAL*2 ILLEGAL ACTVM ILLEGAL*2 29 HM5283206 Series Current state CS RAS CAS WE DSF Address Command Operation Special Mode register set H x x x x x DESL NOP -> Idle after tRSC or row active after tSBW L H H H x x NOP NOP -> Idle after tRSC or row active after tSBW L H H L L x BST ILLEGAL L H L x x BA, CA, A8 ILLEGAL L L x x x x ILLEGAL Notes: 1. H: VIH. L: V IL. x: VIH or VIL. 2. To execute this command for the current bank is illegal. However this command can be executed for another bank depends on the state of another bank. 3. NOP for the current bank or the bank in idle state. Precharge for the bank in other state. 4. Illegal, if both banks are not in idle state. 5. Illegal, if another bank is not in active or idle state. 6. In burst read/write, if BL is set to 1, 2, 4, 8, to try to execute BST command is illegal. 30 HM5283206 Series Operations of HM5283206 Series Power on sequence: In order to get rid of data contention of I/O bus when power on, the following power on sequence recommended to be performed before any operation. 1. 2. 3. 4. Apply power and start clock. Keep a NOP condition. Maintain stable power, stable clock, and NOP condition for 200 s. Execute precharge command (PALL: A8 = HIGH). Execute 8 or more auto refresh commands (REF) tRP after the precharge command as dummy. An interval tRC is necessary between two consecutive auto refresh commands. 5. Execute a mode register set command (MRS) tRC after the last auto refresh command input. Power on Sequence CLK tRP Command Address NOP PALL REF REF MRS ACTV OP CODE A8='H' t RC t RC t RSA Repeat this auto-refresh cycle 8 times or more Read/Write Operations Bank active: A read/write operation begins with a bank active command (ACTV or ACTVM). The bank active command determines a bank (A9) and a row address (AX0 to AX8). For the bank and the row, a read/write command can be applied. An interval not less than tRCD, after an ACTV/ ACTVM command to a read/write command, is required. Read operation: Burst length (BL), CAS latency (CL) and burst type (BT) of the mode register are referred when read command is executed. Burst length (BL) determines the length of a sequential data by a single read command, which can be set to 1, 2, 4, 8 or 256 (full-page). Starting address of a burst data is defined by column address (AY0 to AY7) and bank select address (A9) loaded through A0 to A9 in the cycle when the read command is issued. CAS latency (CL) determines the delay of data output after read command input. When burst length is 1, 2, 4 or 8, DQ buffers automatically become High-Z at the next cycle after completion of burst read. When burst length is full-page (256), data are repeatedly output until a burst stop command, a read/write command or a precharge command is input. 31 HM5283206 Series Burst Length CLK t RCD Command ACT read Address row column 0 BL=1 BL=2 DQout BL=4 BL=8 BL=Full page 0 1 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 256 0 1 BL: Burst Length CAS Latency = 2 BT: sequential CAS Latency CLK t RCD Command ACT read Address row column DQ out CL= 1 CL= 2 CL= 3 0 1 2 3 0 1 2 3 0 1 2 3 Burst Length = 4 CL = CAS Latency BT: sequential Burst operation (on read or write): One burst data output/input by one read/write command are included in a column block determined by A1 to A7 in case BL (Burst Length) = 2, by A2 to A7 in case BL = 4 and by A3 to A7 in case BL = 8. Burst type (BT) determines the order how data of the column block are output/input. There are two burst types, sequential (wrap around) or interleave. The order of the burst data depends also on the start column location of the burst data. See tables below for details. 32 HM5283206 Series Column Block BL = 2 Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 a1 a2 a3 a4 a5 a6 a7 1 a1 a2 a3 a4 a5 a6 a7 Note: a1, a2, a3, a4, a5, a6, a7; VIH or VIL. BL = 4 Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 0 a2 a3 a4 a5 a6 a7 1 0 a2 a3 a4 a5 a6 a7 0 1 a2 a3 a4 a5 a6 a7 1 1 a2 a3 a4 a5 a6 a7 Note: a2, a3, a4, a5, a6, a7; VIH or VIL. BL = 8 Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 0 0 a3 a4 a5 a6 a7 1 0 0 a3 a4 a5 a6 a7 0 1 0 a3 a4 a5 a6 a7 1 1 0 a3 a4 a5 a6 a7 0 0 1 a3 a4 a5 a6 a7 1 0 1 a3 a4 a5 a6 a7 0 1 1 a3 a4 a5 a6 a7 1 1 1 a3 a4 a5 a6 a7 Note: a3, a4, a5, a6, a7; VIH or VIL. 33 HM5283206 Series The Order of Burst Operation BL = 2 Start column location Order in decimal BL = 2 A0 Sequential 0 0 1 0 1 1 1 0 1 0 Interleave BL = 4 Start column location Order in decimal BL = 4 A0 A1 Sequential 0 0 0 1 2 3 0 1 2 3 1 0 1 2 3 0 1 0 3 2 0 1 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 Interleave BL = 8 Start column location Order in decimal BL = 8 A0 A1 A2 Sequential 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 0 0 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 1 1 0 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 0 0 1 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 0 1 1 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 34 Interleave HM5283206 Series Write operation: OPCODE (A9, A8) of the mode register is referred when a write command is executed as well as BL (Burst Length) and BT (Burst Type). CL (CAS Latency) is ignored and CL is fixed to 0 for write operation, that is, write data input starts on the same cycle when the write command is issued. Burst write: Before executing a burst write operation, OPCODE (A9, A8) should be set to (0, 0). Burst length (BL) determines the length of a sequential data by the burst write command, which can be set to 1, 2, 4, 8 or 256 (full-page). Starting address of a burst data is defined by column address (AY0 to AY7) and bank select address (A9) loaded through A0 to A9 in the cycle when the burst write command is issued. CLK t RCD Command ACT write Address row column 0 BL=1 BL=2 DQ in BL=4 BL=8 BL=Full page 0 1 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 256 0 1 BL:Burst Length CAS Latency = 1, 2, 3 Single write: Before executing a single write operation, OPCODE (A9, A8) should be set to (1, 0). In the single write operation, data are only written to the single column defined by the column address and the bank select address loaded at the write command set cycle regardless of the defined burst length. (The latency of data input is 0). CLK t RCD Command ACT write Address row column DQ in 0 BL: Burst Length = 1, 2, 4, 8, full page 35 HM5283206 Series Write per bit: To use write per bit function, 1. Set mask data in advance, which define DQ paths to be masked, to the MASK register by SMRS command. An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. 2. Use ACTVM command to activate the bank for which write per bit operation is performed. An interval not less than tRCD, after an ACTVM command to a write or a block write command, is necessary. 3. Execute a write or a block write command. In this write operation, DQ paths defined by mask register are masked to preserve the previous data. (See the example below) Special Mode Register Set (Load Mask) in Idle State and Write Per Bit CLK t RCD SMRS ACTM write Address A5=1 A6=0 row column DQ in mask data Command 0 1 BL: Burst Length = 2 tRSC Special Mode Register Set (Load Mask) in Active State and Write Per Bit CLK Command SMRS write Address A5=1 A6=0 col DQ in mask data 0 tSBW 36 1 BL: Burst Length = 2 HM5283206 Series Write Per Bit Example MASK data stored in the MASK register DQ input data Data to be written DQ 0 A 0 DQ 1 B 1 B DQ 2 C 1 C DQ 3 D 0 DQ 28 E 1 DQ 29 DQ 30 DQ 31 F G H 0 1 0 E data through this bit will not be written. G Block write: Before executing a block write command, a color data (32 bit) should be set in advance, which is allowed to be written in 8 columns at one write cycle, to the color register by SMRS command. An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. If a SMRS command is executed in active state to set the color register, an interval not less than tSBW is required before executing a block write command after the SMRS command. If a block write command is applied to the bank which is activated by ACTVM command, write per bit function is also available. DQ inputs at the cycle, when a block write command is executed, are referred to mask the specific columns. See the example below. Special Mode Register Set (Load Mask) in Idle State and Block Write CLK t RCD Command SMRS ACTM Bwrite Address A5=0 A6=1 row column DQ in Color data Column MASK t RSC BL: Burst Length = 2 37 HM5283206 Series Block Write Example with Write Per Bit MASK data 0 1 A B 0 1 A B A B A B 7 D 0 D D D 24 E 1 E E E 30 G 1 G G G 31 H 0 H H H 0 1 7 k n DQ input 38 Data to be written (Column block) Color data DQ 0 1 DQ 1 0 DQ 7 1 DQ 24 1 DQ 25 1 DQ 31 0 lum s ma Co Column location data through this bit will not be written. k as Co lu m mn HM5283206 Series Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, so no precharge commands are necessary after each read operation. The command next to this command must be a bank active (ACTV, ACTVM) command. In addition, an interval defined by l APR is required prior to the next command. Note: In executing read with auto precharge command, every command to another bank is ignored until internal precharge completed. CAS latency Precharge start cycle 3 2 cycle before the last data out 2 1 cycle before the last data out 1 0 cycle before the last data out CLK t RCD Command CL=1 ACT read DQ out Command CL=2 0 ACT DQ out 1 3 ACT IAPR 0 ACT 2 read DQ out Command CL=3 ACT IAPR 1 2 3 read ACT IAPR 0 1 2 3 Internal precharge starts here 39 HM5283206 Series Write with auto precharge: In this operation, since precharge is automatically performed after completion of a burst write or a single write operation, so no precharge commands are necessary after the write operation. The command next to this command must be a bank active command (ACTV, ACTVM). In addition, an interval of lAPW is required between the last valid data and the following command. Note: In executing write with auto precharge command, every command to another bank is ignored until internal precharge completed. Burst Write (Burst Length = 4) CLK Command ACT write ACT Address row column row DQ in 0 1 2 3 IAPW Single Write CLK Command ACT write ACT Address row column row DQ in 0 I APW 40 HM5283206 Series Block write with auto-precharge: In this operation, since precharge is automatically performed after completion of a block write operation, so no need to execute precharge command. The following command must be a bank active command (ACTV, ACTVM). In addition, an interval of lAPBW is required between the last valid data input and the following command. Block Write with Auto Precharge CLK Command ACT Bwrite ACT Address row column row IAPBW Full Page Burst Stop Burst stop command during burst read: Burst stop command is used to stop data output during a fullpage burst read. This command sets the output buffer to High-Z and stops the full-page burst read. The timing, from command input to the last data, depends on CAS latency. BST command is legitimate only in case full page burst mode, and is illegal in case burst length 1, 2, 4 or 8. CAS latency BST to valid data BST to high impedance 1 0 1 2 1 2 3 2 3 41 HM5283206 Series CAS Latency = 1, Burst Length = Full Page CLK Command BST DQ out IBSH = 1 IBSR = 0 CAS Latency = 2, Burst Length = Full Page CLK Command BST DQ out IBSH = 2 IBSR = 1 CAS Latency = 3, Burst Length = Full Page CLK Command BST DQ out IBSH = 3 IBSR = 2 42 HM5283206 Series Burst stop command at burst write: For full page burst write cycle, when a burst stop command is issued, the write data at that cycle and the following write data input are ignored. The BST command is legitimate only in case full page burst mode, and is illegal for burst length 1, 2, 4 or 8. Burst Length = Full Page CLK Command DQ input Burst stop Precharge in in t WR 43 HM5283206 Series DQM Control The DQM i (i=0, 1, 2, 3) controls the ith byte of DQ data. DQM control operation for read and for write are different in terms of latency. Reading: When data are read, output buffer can be controlled by DQMi. By setting DQMi to LOW, the corresponding DQ output buffers become active. By setting DQMi to HIGH, the corresponding DQ output buffers are made floated so that the ith byte of data are not driven out. The latency of DQM operation for read operation is 2. CLK DQM DQout 0 1 3 IDOD= 2 Latency Writing: Input data can be controlled by DQMi. While DQMi is LOW, data is driven into the HM5283206. By setting DQMi to HIGH, corresponding ith byte of DQ input data are kept from being written to the HM5283206 and the previous data are protected. The latency of DQM control operation is 0. CLK DQM DQin 0 1 3 I DID = 0 Latency 44 HM5283206 Series Refresh Auto Refresh: All the banks must be precharged before executing an auto-refresh command. Auto refresh command increments the internal counter every time when it is executed. This command also determines the row to be refreshed. Therefore external address specification is not necessary. Refresh cycle is 1024 cycles/16 ms. (1024 cycles are required to refresh all the row addresses.) All output buffers become HighZ after auto-refresh start. No precharge commands are necessary after this operation. Self Refresh: When issuing a self refresh command, by changing the level on CKE pin from HIGH to LOW simultaneously, a self refresh operation starts and is kept while CKE is LOW. During the selfrefresh operation, all data schedule to be refreshed internally. This operation managed by an internal refresh timer. After exiting from the self refresh, since the last row refreshed cannot be determined, autorefresh commands should immediately be performed for all addresses. Change the level on the CKE pin from LOW to HIGH to exit from Self refresh mode. Others Power Down Mode: Power down mode is a state in which all input buffers except the CKE input buffer are made inactive and clock signal is masked to cut power dissipation. To enter into power down mode, CKE should be set to low. Power down mode is kept as long as CKE is low. Change the level on the CKE pin from LOW to HIGH to exit from Power down mode. In this mode, internal refresh is not performed. Clock Suspend: The HM5283206 enters into clock suspend mode from active mode by setting CKE to low. There are several types of clock suspend mode depends on the state when CKE level is changed from HIGH to LOW. ACTIVE clock suspend: If CKE-transition (1 to 0) happens during a bank active state, the bank active status is kept. Any input signals are ignored during this mode. READ and READ A suspend: If CKE transition (1 to 0) happens during a read operation, the read operation is kept or DQ output data is driven out until completion. Any input signals are ignored during this mode. WRITE (BLOCK WRITE) and WRITE A (BLOCK WRITE A) suspend: If CKE-transition (1 to 0) happens during a write operation, though any input signals include DQ input data ignored, the write operation is kept until completion. Any input signals are ignored during this mode. Change the level on the CKE pin from LOW to HIGH to exit from Clock suspend mode. 45 HM5283206 Series Command Intervals Read Command to Read Command Interval: 1. Operation for a column in the same row: Read command can be issued every cycle. Note that the latest read command has the priority to the preceding read command, that is, any read command can interrupt the preceding burst read operation to get valid data aimed by this interruption. CLK tRCD Command ACT Address row read read A B A9(BS) A0 DQ out Bank 0 Active B0 B1 Column A Column B Column A Column B read read Dout B2 B3 CAS Latency = 3 Burst Length = 4 Bank 0 Dout 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank-active command before executing the new read command. 3. Operation for another bank: For another bank in active state, the new read command can be executed in the next cycle after the preceding read command is issued. If another bank is in idle state, a bank active command should be executed before executing the new read command. CLK tRRD Command Address ACT ACT 0 1 read read A B A9(BS) DQ out A0 B0 B1 B2 B3 CAS Latency = 3 Burst Length = 4 Bank 0 Bank1 Column A Column B Bank0 Bank1 Active Active read read Dout Dout 46 HM5283206 Series Write Command to Write Command Interval: 1. Operation for a column in the same row : Write command can be issued every cycle. Note that the latest write command has the priority to the preceding write command, that is, any write command can interrupt the preceding burst write operation to get valid data CLK tRCD Command ACT Address row write write A B A0 B0 A9(BS) DQ in Bank 0 Active B1 B2 B3 Burst Write Mode CAS Latency = 3 Burst Length = 4 Column A Column B write write 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before executing the following write command. 3. Operation for another bank: For another bank in active state, the following burst write command can be executed in the next cycle after the preceding write command is issued. If another bank is in the idle state, bank active command should be executed. CLK tRRD Command Address ACT ACT 0 1 write write A B B0 B1 A9(BS) DQ in A0 Bank 0 Bank1 Bank0 Bank 1 Active Active write write B2 B3 Burst Write Mode CAS Latency = 3 Burst Length = 4 47 HM5283206 Series Block Write Command to Write or Block Write Command Interval: 1. Operation for a column in the same row: It is necessary to take no less than tBWC internal between a block write and another block write or the following write. If tCK is less than tBWC , NOP command should be issued for the cycle between a block write command and the following write or another block write command. CLK t BWC t RCD Command ACT Bwrite Address row A Bank 0 Active Bwrite /Write B Column A Column B Block write Block write /Write 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before the following write or another block write operation. 3. Operation for another bank: To execute the following write command or another block write command for another bank in active state, tBWC interval to the next command is necessary. If another bank is in the idle state, bank active command should be executed. If t CK is less than tBWC , NOP command should be issued for the cycle between block write command and the following write or another block write command. CLK t RRD Command Address t BWC ACT ACT Bwrite 0 1 A Bwrite /Write B A9(BS) Bank 0 Active 48 Bank1 Column A Column B Active Block write Block write /Write HM5283206 Series Read Command to Write or Block Write Command Interval: 1. Operation for a column in the same row: The write or the block write command following the preceding read command can be performed after an interval of no less than 1 cycle. To set DQ output High-Z when data are driven in, DQM must be used depending on CAS latency as the timing shown below. Note that the latest write or block write command has the priority to the preceding read command, that is, any write or block write command can interrupt the preceding burst read operation to get valid data. CLK Command read write CL= 1 DQM CL= 2 CL= 3 DQ in DQ out 0 1 2 3 High-Z 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before executing the next write or another block write command. 3. Operation for another bank: For another bank in active state, the following write or block write command can be executed from the next cycle after the preceding write command is issued. If another bank is in idle state, bank active command should be executed, prior to execute the following write or block write command. 49 HM5283206 Series Write Command to Read Command Interval: 1. Operation for a column in the same row: The read command following the preceding write command can be performed after an interval of no less than 1 cycle. Note that the latest read command has the priority to the preceding writing command, that is, any read command can interrupt the preceding write operation to get valid data. WRITE to READ Command Interval (1) CLK Command write read DQM DQ in A0 DQ out B0 Column A B1 B2 B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank 0 CAS Latency write Column B Column B read Dout WRITE to READ Command Interval (2) CLK Command write read DQM DQ in A0 A0 DQ out B0 Column A write B1 CAS Latency Column B Column B read B2 Dout B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank 0 2. Operation for a column in other row of the same bank: To execute the following read command, it is necessary to execute a precharge command and a bank active command. 3. Operation for another bank: For another bank in active state, the following read command can be executed from the next cycle after the preceding write command is issued. If another bank is in idle state, a bank active command should be executed prior to execute the following read command. 50 HM5283206 Series Block Write Command to Read Command Interval: 1. Operation for a column in the same row : Within the same row, it is necessary to take no less than t BWC between a block write and the following read command. If tCK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following read command. Block Write Command to Read Command Interval CLK Command DQM read Bwrite t BWC DQ out B0 Column A Block write B1 B2 CAS Latency B3 CAS Latency = 1 Burst Length = 4 Column B Column B read Dout 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before the following write or another block write operation. 3. Operation for another bank: To execute a read command for another bank in active state, tBWC interval to the next command is necessary. If another bank is in idle state, bank active command should be executed. If t CK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following read command. 51 HM5283206 Series Read Command to Precharge Command: The minimum interval between read command and precharge command is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by l EP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (Same Bank): Output All Data. CAS Latency = 1, Burst Length = 4 CLK Command Pre. read DQout 0 1 2 CL = 1 3 I EP = 0 cycle CAS Latency = 2, Burst Length = 4 CLK Command read Pre. 0 DQout 1 CL = 2 2 3 I EP = -1cycle CAS Latency = 3, Burst Length = 4 CLK Command read Pre. DQout 0 CL = 3 52 1 2 3 I EP = -2cycle HM5283206 Series READ to PRECHARGE Command Interval (Same Bank): Stop Output Data. CAS Latency = 1, Burst Length = 4 CLK Command read Pre. High-Z DQout 0 I HZP = 1 CAS Latency = 2, Burst Length = 4 CLK Command read Pre. High-Z DQout 0 I HZP = 2 CAS Latency = 3, Burst Length = 4 CLK Command read Pre. High-Z DQout 0 IHZP = 3 53 HM5283206 Series Write Command to Precharge Command: The minimum interval between a write command and the following precharge command is 1 cycle. However, if the burst write operation is not finished, input must be masked by means of DQM for the cycle defined by tWR, for assurance. WRITE to Precharge Command Interval (Same Bank) Burst Length = 4 (To Stop Write Operation) CLK Command write Pre. DQM DQin A0 A1 t WR Burst Length = 4 (To Write All Data) CLK Command write Pre. DQM DQin A0 A1 A2 A3 tWR 54 HM5283206 Series Block Write Command to Precharge Command Interval: The minimum interval between block write command and the following precharge command is tBWR . Block Write to Precharge Command Interval (Same Bank) CLK Command Pre. Bwrite t BWR Register set to register set interval: The minimum interval between two successive register set commands (mode/special mode) is lRR. Mode register set to special mode register interval CLK Command MRS SMRS Address A0-A9 A5,A6 color /mask DQ in IRR Special Mode Register Set to Block Write/Write Interval: The minimum interval between a special mode register set and a block write/write is tSBW. Special Mode Register Set to Burst Write Interval CLK Command SMRS write Address A5,A6 column DQ in color /mask 0 tSBW 1 Burst length = 2 55 HM5283206 Series Bank Active Command Interval: 1. Operation for the same bank: The interval between two bank-active commands must be no less than tRC. 2. Operation for another bank: The interval between two bank-active commands must be no less than tRRD. Bank Active to Bank Active for the Same Bank CLK Command ACT Address row ACT Pre row A9(BS) t RP t RAS t RC Bank Active to Bank Active for Another Bank CLK Command ACT ACT Address row row A9(BS) t RRD 56 HM5283206 Series Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to V SS VT -1.0 to +4.6 V 1 Supply voltage relative to VSS VDD -1.0 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Note: 1. VIH (max) = 5.75 V for pulse width 5 ns Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Max Unit Notes Supply voltage VDD, VDDQ 3.0 3.6 V 1 VSS , VSS Q 0 0 V Input high voltage VIH 2.0 4.6 V 1, 2 Input low voltage VIL -0.3 0.8 V 1, 3 Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns 57 HM5283206 Series DC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5283206 -8 -10 -12 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Note Operating current I CC1 -- 210 -- 180 -- 150 mA Burst length = 1 t RC = min, CL = 3 t CK = min 1 Standby current (Bank Disable) I CC2 -- 5 -- 5 -- 5 mA CKE = VIL, t CK = min -- 3 -- 3 -- 3 mA CKE = VIL CLK = VIL or VIH Fix ed -- 95 -- 75 -- 60 mA CKE = VIH, t CK = min NOP command -- 15 -- 10 -- 10 mA CKE = VIL, t CK = min, 1 DQ = High-Z -- 100 -- 80 -- 65 mA CKE = VIH, t CK = min, NOP command DQ = High-Z Active standby current (Bank active) I CC3 Burst operating current t CK = min, BL = 4, 2 bank operation (CL = 1) I CC4 -- 220 -- 170 -- 140 mA (CL = 2) I CC4 -- 280 -- 240 -- 200 mA (CL = 3) I CC4 -- 330 -- 280 -- 240 mA Refresh current I CC5 -- 190 -- 150 -- 120 mA t RC = min, CL = 3 t CK = min Self refresh current I CC6 -- 4 -- 4 -- 4 mA VIH V DD - 0.2 VIL 0.2 V Block write operating current I CC7 -- 200 -- 160 -- 130 mA t CK = min, CL = 3 1 bank operation, t RC = 150 ns Input leakage current I LI -10 10 -10 10 -10 10 A 0 Vin V DD Output leakage current I LO -10 10 -10 10 -10 10 A 0 Vout V DD DQ = disable Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- V I OH = -2 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 V I OL = 2 mA Note: 58 1. I CC depends on output load condition when the device is selected. ICC (max) is specified on condition that all output pins are floated. 1 HM5283206 Series Capacitance (Ta = 25C, VDD, VDDQ = 3.3 V 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 -- 5 pF 1 Input capacitance (Signals) CI2 -- 5 pF 1 Output capacitance (DQ) CO -- 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM = VIH to disable Dout. 59 HM5283206 Series AC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5283206 -8 -10 -12 Parameter Symbol Min Max Min Max Min Max Unit Notes System clock cycle time (CL = 1) t CK 24 -- 30 -- 36 -- ns 1 (CL = 2) t CK 12 -- 15 -- 18 -- ns (CL = 3) t CK 8 -- 10 -- 12 -- ns CLK high pulse width t CH 3 -- 3 -- 4 -- ns 1 CLK low pulse width t CL 3 -- 3 -- 4 -- ns 1 Access time from CLK (CL = 1) t AC -- 23 -- 28 -- 32 ns 1, 2 (CL = 2) t AC -- 11 -- 13 -- 15 ns (CL = 3) t AC -- 7 -- 8 -- 10 ns Access time from CAS t CAC -- 23 -- 28 -- 32 ns 1, 2 Data-out hold time t OH 3 -- 3 -- 3 -- ns 1 CLK to data-out low impedance t LZ 0 -- 0 -- 0 -- ns 1 CLK to data-out high impedance (CL = 1) t HZ -- 11 -- 13 -- 15 ns 1, 3 t HZ -- 6 -- 7 -- 9 ns Data-in setup time t DS 2.5 -- 3 -- 3.5 -- ns 1 Data-in hold time t DH 1 -- 1 -- 1.5 -- ns 1 Address setup time t AS 2.5 -- 3 -- 3.5 -- ns 1 Address hold time t AH 1 -- 1 -- 1.5 -- ns 1 CKE setup time t CKS 2.5 -- 3 -- 3.5 -- ns 1, 4 CKE hold time t CKH 1 -- 1 -- 1.5 -- ns 1, 4 Command (CS, RAS, CAS, WE, DQM, DSF) setup time t CMS 2.5 -- 3 -- 3.5 -- ns 1 Command (CS, RAS, CAS, WE, DQM, DSF) hold time t CMH 1 -- 1 -- 1.5 -- ns 1 Refresh/active to refresh/active command period t RC 72 -- 90 -- 108 -- ns 1 Active to precharge on full page mode t RASC -- 120000 -- 120000 -- 120000 ns 1 Active to precharge command period t RAS 48 120000 60 120000 72 120000 ns 1 Active command to column command t RCD 24 -- -- -- 1 (CL = 2,3) 60 30 36 ns HM5283206 Series AC Characteristics (Ta = 0 to 70C, VDD, V DD Q = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (cont) HM5283206 -8 -10 -12 Parameter Symbol Min Max Min Max Min Max Unit Notes Precharge to active command period t RP 24 -- 30 -- 36 -- ns 1 The last data-in to precharge lead time (CL = 1) t WR 12 -- 15 -- 18 -- ns 1 (CL = 2) t WR 12 -- 15 -- 18 -- ns (CL = 3) t WR 16 -- 20 -- 24 -- ns t BWR 24 -- 30 -- 34 -- ns (CL = 2) t BWR 24 -- 30 -- 34 -- ns (CL = 3) t BWR 24 -- 30 -- 36 -- ns Active (a) to active (b) command period t RRD 16 -- 20 -- 24 -- ns 1 Register set to active command t RSC 16 -- 20 -- 24 -- ns 1 Block write cycle time t BWC 16 -- 20 -- 24 -- ns 1 Special mode register set to column command t SBW 16 -- 20 -- 24 -- ns 1 Transition time (rise to fall) tT 1 5 1 5 1 5 ns Refresh period t REF -- 16 -- 16 -- 16 ms Block write to precharge lead time (CL = 1) 1 Notes: 1. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.4 V. Test load (A) is used with CL = 30 pF in general except for the measurement of access time (note2) and tHZ (note3). 2. Access time is measured at 1.4 V. Test load (B) is used with current source. 3. t HZ (max) defines the time at which the outputs achieves 200 mV. Test load (A) is used with CL = 5 pF and with current source. 4. When Active Suspend Exit, Power Down Exit or Self Refresh Exit is executed. CKE should be kept "H" more than 1 cycle from these Exit cycles. 61 HM5283206 Series Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures 2.8 V 80% input 20% V SS t T tT LVTTL interface Output +1.4 V 500 DQ CL DQ I +1.4 V 50 30 pF * IOL (max) = 20mA IOH (min) = -20mA Test Load (A) 62 Test Load (B)* HM5283206 Series Relationship Between Frequency and Minimum Latency HM5283206 Parameter -8 CL 3 -10 -12 2 1 3 2 1 3 2 1 tCK (ns) Symbol 8 12 24 10 15 30 12 18 36 Last data in to active command (Auto precharge, same bank) lAPW 5 3 2 5 3 2 5 3 2 Block write to active command (Auto precharge, same bank) lAPBW 6 4 2 6 4 2 6 4 2 Precharge command to high impedance lHZP 3 2 1 3 2 1 3 2 1 Last data out to active command (Auto precharge, same bank) lAPR 1 1 1 1 1 1 1 1 1 Last data out to precharge lEP -2 -1 0 -2 -1 0 -2 -1 0 Column command to column command lCCD 1 1 1 1 1 1 1 1 1 Write command to data in latency lWCD 0 0 0 0 0 0 0 0 0 DQM to data in lDID 0 0 0 0 0 0 0 0 0 DQM to data out lDOD 2 2 2 2 2 2 2 2 2 CKE to CLK disable lCLE 1 1 1 1 1 1 1 1 1 Burst stop to output valid data hold lBSR 2 1 0 2 1 0 2 1 0 Burst stop to output high impedance lBSH 3 2 1 3 2 1 3 2 1 Burst stop to write data ignore lBSW 0 0 0 0 0 0 0 0 0 MRS to data in latency lMSD 0 0 0 0 0 0 0 0 0 SMRS to data in latency lSSD 0 0 0 0 0 0 0 0 0 Register set to register set lRR 2 2 1 2 2 1 2 2 1 Notes 63 HM5283206 Series Timing Waveforms Read Cycle t CK t CH t CL CLK t RC VIH CKE t t RAS RP t RCD t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH CS t CMS t CMH t CMS t CMH RAS t CMS t CMH t CMS t CMH CAS t CMS t CMH t CMS t CMH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t CMS t CMH t CMS t CMH WE t AS t AH A9 t AS t AH t AS t AH A8 t AS t AH t AS t AH t AS t AH A0 to A7 t CMS t CMH DQM DQ(input) tCAC DQ(output) t AC t AC t AC Bank 0 Active 64 t AC Bank 0 Read t LZ t OH t OH Bank 0 Precharge t OH t HZ Burst length = 4 Bank0 Access HM5283206 Series Write Cycle t CK t CH t CL CLK t RC VIH CKE t RAS t RCD t CMS t CMH t RP t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH CS t CMS t CMH t CMS t CMH RAS t CMS t CMH t CMS t CMH CAS t CMS t CMH t CMS t CMH t CMS t CMH t AS t AH t AS t AH t AS t AH t AS t AH t CMS t CMH WE t AS t AH t AS t AH A9 t AS t AH t AS t AH A8 t AS t AH t AS t AH t AS t AH A0 to A7 t CMS t CMH DQM t DS t DH tDS t DH t DS t DH t DS t DH DQ(input) t WR DQ(output) Bank 0 Active Bank 0 Write Bank 0 Precharge Burst length = 4 Bank 0 Access 65 HM5283206 Series Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 b+3 b' b'+1 b'+2 b'+3 20 CLK VIH CKE CS RAS CAS WE A9(BS) A0 to A7 code valid C: b' C: b R: b DQM DQ(output) b High-Z DQ(input) t RSC t RP Precharge If needed Mode register Set t RCD Output mask Bank 1 Active Bank 1 Read tRCD = 3 CAS latency = 3 Burst length = 4 Read Cycle/Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 CS RAS CAS WE A9(BS) A0 to A7 DQM DQ (output) DQ (input) CKE R:a C:a R:b C:b a C:b' a+1 a+2 a+3 b C:b" b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Bank 1 Bank 0 Read Precharge Bank 1 Read Bank 1 Read Bank 1 Precharge Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 VIH CS RAS CAS WE A9(BS) A0 to A7 DQM R:a R:b C:b C:b' C:b" High-Z DQ (output) DQ (input) a Bank 0 Active 66 C:a Bank 0 Write a+1 a+2 a+3 Bank 1 Active b Bank 1 Write b+1 b+2 b+3 b' Bank 0 Precharge Bank 1 Write b'+1 b" Bank 1 Write b"+1 b"+2 b"+3 Bank 1 Precharge HM5283206 Series Read/Single Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH CS RAS CAS WE A9(BS) R:a A0 to A7 C:a R:b DQM DQ (input) DQ (output) a a Bank 0 Active CKE C:a' C:a Bank 0 Read Bank 1 Active C:a R:b a+1 a+2 a+3 a Bank 0 Bank 0 Write Read a+1 a+2 a+3 Bank 0 Precharge Bank 1 Precharge VIH CS RAS CAS WE A9(BS) A0 to A7 DQM DQ (input) DQ (output) R:a a Bank 0 Active Bank 0 Read Bank 1 Active a+1 C:a C:b C:c a b c a+3 Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst length = 4 67 HM5283206 Series Read/Burst Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE A9(BS) R:a A0 to A7 DQM DQ (input) DQ (output) CKE C:a R:b C:a' a a Bank 0 Active Bank 0 Read Bank 1 Active C:a R:b a+1 a+2 a+3 a+1 a+2 a+3 Clock suspend Bank 0 Write Bank 0 Precharge Bank 1 Precharge VIH CS RAS CAS WE A9(BS) A0 to A7 DQM R:a DQ (input) DQ (output) C:a a a Bank 0 Active Bank 0 Read Bank 1 Active a+1 a+1 a+2 a+3 a+3 Bank 0 Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst length = 4 68 HM5283206 Series Full Page Read/Write Cycle 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CLK CKE VIH Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page CS RAS CAS WE A9(BS) A0 to A7 DQM DQ (output) DQ (input) CKE R:a C:a R:b a a+1 a+2 a+3 a-2 a-1 a a+1 a+2 a+3 a+4 a+5 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Burst stop Bank 1 Precharge VIH Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page CS RAS CAS WE A9(BS) A0 to A7 R:a C:a DQM DQ (output) DQ (input) R:b High-Z a Bank 0 Active a+1 Bank 0 Write a+2 a+3 a+4 a+5 a+1 a+6 a+2 a+3 a+4 a+5 Bank 1 Active Burst stop Bank 1 Precharge Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 CLK CKE VIH CS RAS CAS WE A9(BS) A0 to A7 R:a A8=1 C:a DQM DQ(input) High-Z DQ(output) t RC t RP Precharge If needed Auto Refresh tRC Auto Refresh Active Bank 0 Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 69 HM5283206 Series Self Refresh Cycle CLK CKE Low CKE CS RAS CAS WE A9(BS) A0 to A7 A8=1 DQM DQ(input) High-Z DQ(output) tRP Precharge command If needed Self refresh entry command Clock Suspend Mode t CKS 0 1 2 CLK CKE CS RAS CAS WE A9(BS) A0 to A7 R:a 3 4 5 tRC Auto refresh Self refresh exit ignore command or No operation t CKS t CKH 6 7 C:a 8 9 10 11 12 13 R:b DQM DQ (output) DQ (input) a 14 15 16 17 18 19 C:b a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start Read suspend end Bank1 Read Bank0 Precharge Earliest Bank1 Precharge CS RAS CAS WE A9(BS) C:a R:b R:a C:b High-Z DQ (output) DQ (input) a Bank0 Active Active clock suspend start Power Down Mode 70 20 Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 CKE A0 to A7 DQM Self refresh cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 a+1 a+2 Active clock Bank0 Bank1 supend end Write Active Write suspend start a+3 b Write suspend end b+1 b+2 b+3 Bank1 Bank0 Write Precharge Earliest Bank1 Precharge Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 HM5283206 Series t CKS CLK CKE CS RAS CAS WE A9(BS) A0 to A7 DQM DQ(input) DQ(output) CKE Low R: a A8=1 High-Z tRP Precharge command If needed Power down entry Power down mode exit Active Bank 0 Power down cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 71 HM5283206 Series Mask Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK 14 CKE VIH CS RAS CAS WE DSF Mask No Mask A9 A8 A0 to A7 A5 = 1 Ra Rb Ra Rb Cb Ca DQM Mask Data DQ in t RP Precharge If needed 72 a a+2 a+3 b t RSC Mask register Set Bank 0 ACTVM Bank 1 Bank 0 ACTV Write per bit Bank 1 Write b+1 HM5283206 Series Color Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE VIH CS RAS CAS WE DSF Mask No Mask A9 A8 A0 to A7 A6 = 1 Ra Rb Ra Rb Ca Cb Cc Column MASK Column MASK Column MASK DQM Color Data DQ in t RP Precharge If needed t RSC Color register Set Bank 0 ACTVM Bank 1 ACTV Bank 0 Mask Block Write Bank 1 Block Write 73 HM5283206 Series Write Cycle (with I/O Mask) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE VIH CS RAS CAS WE DSF A9 A8 Ra Rb A0 to A7 Ra Rb Cb Ca DQM a DQ in Bank 0 ACTVM 74 Bank 1 ACTV Bank 0 Write per bit a+2 a+3 b Bank 1 Write b+1 b+3 Bank 0 Precharge HM5283206 Series Block Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE VIH CS RAS CAS WE DSF A9 A8 Ra Rb A0 to A7 Ra Rb Cc Cd Ca Cb Column MASK Column MASK Column MASK Column MASK Bank 0 Mask Block Write Bank 1 Block Write Bank 1 Block Write DQM DQ in tBWC Bank 0 ACTVM Bank 1 Bank 0 ACTV Mask Block Write Bank 0 Precharge 75 HM5283206 Series Package Dimensions HM5283206FP Series (FP-100J) Unit: mm 23.20 0.20 20.00 80 51 50 100 31 0.575 0.10 Dimension including the plating thickness Base material dimension 76 0.17 0.05 0.15 0.04 0.13 M 2.70 30 0.15 0.15 1 0.32 0.08 0.30 0.06 3.00 Max 0.65 17.20 0.20 14.00 81 0.825 1.60 0 - 10 0.80 0.20 Hitachi Code JEDEC EIAJ Weight (reference value) FP-100J -- Conforms 1.64 g HM5283206 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: <1> (800) 285-1601 Fax: <1> (303) 297-0447 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 77 HM5283206 Series Revision Record Rev. Date Drawn by Approved by Oct. 20, 1994 Initial issue Y. Saiki T. Kizaki 0.1 Nov. 11, 1994 Commands Operation Change of column block and DQ input at the block write cycle and column mask location Operation of HM5283206 Series Change of column block and the order of burst operation Addition of description for read command to write or block write command interval (3) Change of figure for bank active command interval AC Characteristics tOH min: 2/2/2 ns to 3/3/3 ns tHZ (CL = 1) max: 10/12/14 ns to 13/15/17 ns tCKS min: 3/2/2 ns to 3/3/3 ns tCKH min: 1/2/2 ns to 1/1/1 ns tRC min: 90/100/125 ns to 90/108/135 ns tRAS min: 60/70/80 ns to 60/72/90 ns Change of Timing Waveforms: Read Cycle/Write Cycle, Color Register Set Cycle and Block Write Cycle Y. Saiki T. Kizaki 0.2 Y. Saiki Nov. 20, 1995 Deletion of HM5283206TT Series Change of Simplified State Diagram Commands Operation Change of description for Commands Operation Change of figure for Column address and write command BL = 2 Change of description for Graphic Commands Change of Command Truth Table and CKE Truth Table Change of Function Truth Table: Change of notes 5 Addition of notes 6 Operation of HM5283206 Series Addition of note for read with auto precharge, write with auto precharge and power down mode Change of figure for write per bit, block write, read command to read command interval, write command to write command interval and write command to precharge command AC Characteristics Change of figure for Test load (B) DC Characteristics ICC1 max: TBD to 180/150/120 mA ICC2 max: TBD to 5/5/5 mA ICC2 max: TBD to 3/3/3 mA ICC2 max: TBD to 75/60/50 mA ICC3 max: TBD to 10/10/10 mA ICC3 max: TBD to 80/65/55 mA ICC4 (CL = 1) max: TBD to 170/140/110 mA ICC4 (CL = 2) max: TBD to 240/200/160 mA ICC4 (CL = 3) max: TBD to 280/240/190 mA ICC5 max: TBD to 150/120/100 mA T. Kizaki 0.0 78 Contents of Modification HM5283206 Series Rev. Date Contents of Modification Drawn by Approved by 0.2 Nov. 20, 1995 DC Characteristics ICC6 max: 2/2/2 mA to 4/4/4 mA Addition of ICC7 max: 160/130/110 mA Y. Saiki T. Kizaki 0.2 Nov. 20, 1995 AC Characteristics tHZ min: 2/2/2 ns to --/--/-- ns tDS, t AS , t CKS, tCMS min: 3/3/3 ns to 3/3.5/4 ns tDH, tAH, t CKH , t CMH min: 1/1/1 ns to 1/1.5/2 ns Addition of tRASC max: 80000/80000/80000 ns Change of notes 4 Change of Timing Waveforms Read cycle, auto refresh cycle, self refresh cycle, clock suspend mode and power down mode Y. Saiki T. Kizaki 0.3 Y. Saiki Feb. 15, 1996 AC Characteristics t R AS max : 10000/ 10000/ 10000 ns 120000/ 120000/ 120000 ns t R ASC max : 80000/ 80000/ 80000 ns 120000/ 120000/ 120000 ns Change of notes 4 T. Kizaki 1.0 May. 30, 1996 Commands Operation Change of CKE Truth Table T. Kizaki 2.0 Jul. 30, 1997 3.0 Nov. 20, 1997 DC Characteristics ICC1 max: TBD/180/150 mA to 210/180/150 mA ICC2 max: TBD/5/5 mA to 5/5/5 mA ICC2 max: TBD/3/3 mA to 3/3/3 mA ICC2 max: TBD/75/60 mA to 95/75/60 mA ICC3 max: TBD/10/10 mA to 15/10/10 mA ICC3 max: TBD/80/65 mA to 100/80/65 mA ICC4 (CL = 1) max: TBD/170/140 mA to 220/170/140 mA ICC4 (CL = 2) max: TBD/240/200 mA to 280/240/200 mA ICC4 (CL = 3) max: TBD/280/240 mA to 330/280/240 mA ICC5 max: TBD/150/120 mA to 190/150/120 mA ICC6 max: TBD/4/4 mA to 4/4/4 mA ICC7 max: TBD/160/130 mA to 200/160/130 mA H. Suzuki K. Hayakawa 4.0 Jan. 20, 1998 Correct error H. Suzuki K. Hayakawa Y. Saiki M. Suzuki Addition of HM5283206-8 Series Deletion of HM5283206-15 Series Change of CKE Truth Table AC Characteristics tAC (CL = 1) max: 22 ns to 23 ns Change of package informations: Height (max) 3.10 to 3.00 T. Kizaki 79 HM5283206 Series Rev. Date Drawn by Approved by 5.0 May. 19, 1998 Correct errors H. Suzuki Change of figures for Column address and write command (BL = 2), READ to PRECHARGE command interval: Output all data (CL = 2), Special mode register set (load mask) in idle state and block write Change of description for Precharge command and Graphic commands note Change of simplified State Diagram AC Characteristics tBWR (CL = 1), (CL = 2) min: 24/30/36 ns to 24/3034 ns K. Hayakawa 6.0 Oct. 2, 1998 80 Contents of Modification Correct errors Column address and block write command: A0 to A1 HIGH or LOW to A0 to A2 HIGH or LOW CKE Truth Table Change of DSF (self refresh): L to x