© 2004 Fairchild Semiconductor Corporation DS005950 www.fairchildsemi.com
October 1987
Revised January 2004
CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8
Decoded Outputs
CD4017BC CD4022BC
Decade Counter/Divider with 10 Decoded Outputs
Divide-by-8 Counter/Divider with 8 Decoded Outputs
General Description
The CD4 01 7B C is a 5 -sta ge divi d e- by-1 0 John son co unt er
with 10 decoded outputs and a carry out bit.
The CD4022BC is a 4-stage divide-by-8 Johnson counter
with 8 decoded outputs and a carry-out bit.
These c ounter s are clea red to t heir zero cou nt by a lo gical
“1” on their reset line. These counters are advanced on the
positive edge of the clock signal when the clock enable sig-
nal is in the logical “0” state.
The configuration of the CD4017BC and CD4022BC per-
mits medium speed operation and assures a hazard free
counting sequence. The 10/8 decoded outputs are nor-
mally in the lo gical “0” state and g o to the logical “1” state
only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry-out signal
completes a f ull cycle for ever y 10 /8 clo ck inp ut cy cles a nd
is used as a ripple carry signal to any succeeding stages.
Features
Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power Fan out of 2 driving 74L
TTL compatibility: or 1 driving 74LS
Medium speed operation: 5.0 MHz (typ.)
with 10V VDD
Low power: 10 µW (typ.)
Fully static operation
Applications
Automotive
Instrumentation
Medical electronics
Alarm systems
Industrial electronics
Remote metering
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appe nding the s uffix let t er X to the ordering code.
Connection Diagrams
CD4017B
Top View
CD4022B
Top View
Order Num b er Packag e Num b er Packa ge Des cri pt io n
CD4017BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4017BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4022BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4022BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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CD4017BC CD4022BC
Logic Diagrams
CD4017B
Terminal No. 8 = GND
Terminal No. 16 = VDD
CD4022B
Terminal No. 16 = VDD
Terminal No. 8 = GND
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CD4017BC CD4022BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions (Note 2)
Note 1: Absolute Maximum Ratings are those va lues beyond which the
safety of th e device ca nnot be guaranteed, th ey are not meant to imply th at
the devices should be operated at these limits. The table of Recom-
mended Operating Conditions and Electrical Characteristics provides
conditions for actual device operation.
Note 2: VSS = 0V unles s ot herwise s pecified .
DC Electrical Characteristics (Note 2)
Note 3: IOL and IOH are tes t ed one ou tp ut at a ti m e.
DC Supply Voltage (VDD)0.5 VDC to +18 VDC
Input Voltage (VIN)0.5 VDC to VDD +0.5 VDC
Storage Temperature (TS)65°C to +150°C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260°C
DC Supply Voltage (VDD)+3 VDC to +15 VDC
Input Voltage (VIN) 0 to VDD VDC
Operating Temperature Range (TA)55°C to +125°C
Symbol Parameter Conditions 55°C+25°+125°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V 5 0.3 5 150 µACurrent VDD = 10V 10 0.5 10 300
VDD = 15V 20 1.0 20 600
VOL LOW Level |IO| < 1.0 µA
Output Voltage VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05
VDD = 15V 0.05 0 0.05 0.05
VOH HIGH Level |IO| < 1.0 µA
Output Voltage VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95
VDD = 15V 14.95 14.95 15 14.95
VIL LOW Level |IO| < 1.0 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 VVDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0
VIH HIGH Level |IO| < 1.0 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VVDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0
VDD = 15V, VO = 1.5V or 13. 5V 11.0 11.0 11.0
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 3) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9
VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4
IOH HIGH Level Output VDD = 5V, VO = 4.6V 0.25 0.2 0.36 0.14 mACur rent (Note 3) VDD = 10V, VO = 9.5V 0.62 0.5 0.9 0.35
VDD = 15V, VO = 13.5V 1.8 1.5 3.5 1.1
IIN Input Current VDD = 15V, VIN = 0V 0.1 1050.1 1.0 µA
VDD = 15V, VIN = 15V 0.1 1050.1 1.0
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CD4017BC CD4022BC
AC Electrical Characteristics (Note 4)
TA= 25°C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Note 4: AC Parameters are guara nt eed by DC c orrelat ed testing.
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200 k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time Carry Out Line VDD = 5V 415 800 nsVDD = 10V 160 320
VDD = 15V 130 250
Carry Out Line VDD = 5V CL = 15 pF 240 480 nsVDD = 10V 85 170
VDD = 15V 70 140
Decode Out Lines VDD = 5V 500 1000 nsVDD = 10V 200 400
VDD = 15V 160 320
tTLH, tTHL Transition Time Carry Out and Decode Out Lines
tTLH VDD = 5V 200 360 nsVDD = 10V 100 180
VDD = 15V 80 130
tTHL VDD = 5V 100 200 nsVDD = 10V 50 100
VDD = 15V 40 80
fCL Maximum Clock Frequency VDD = 5V Measured with 1.0 2 MHzVDD = 10V Respect to Carry 2.5 5
VDD = 15V Output Line 3.0 6
tWL, tWH Minimum Clock Pulse Width VDD = 5V 125 250 nsVDD = 10V 45 90
VDD = 15V 35 70
trCL, tfCL Clock Rise and Fall Time VDD = 5V 20 µsVDD = 10V 15
VDD = 15V 5
tSU Minimum Clock Inhibit Data Setup Time VDD = 5V 120 240 nsVDD = 10V 40 80
VDD = 15V 32 65
CIN Average Input Capacitance 57.5pF
Symbol Parameter Conditions Min Typ Max Units
RESET OPERATION
tPHL, tPLH Propagation Delay Time
Carry Out Line VDD = 5V 415 800 nsVDD = 10V 160 320
VDD = 15V 130 250
Carry Out Line VDD = 5V 240 480 nsVDD = 10V CL = 15 pF 85 170
VDD = 15V 70 140
Decode Out Lines VDD = 5V 500 1000 nsVDD = 10V 200 400
VDD = 15V 160 320
tWMinimum Reset VDD = 5V 200 400 nsPulse Width VDD = 10V 70 140
VDD = 15V 55 110
tREM Minimum Reset VDD = 5V 75 150 nsRemoval Time VDD = 10V 30 60
VDD = 15V 25 50
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CD4017BC CD4022BC
Timing Diagrams
CD4017B
CD4022B
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CD4017BC CD4022BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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CD4017BC CD4022BC Decade Counter/Divi der with 10 Decoded Outputs Divide-by-8 Counter/Divider with 8
Decoded Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume an y responsibility fo r use of any circu itry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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