Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2679/7
5.03 1
IDT7200L
IDT7201LA
IDT7202LA
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9, 1K x 9
W
WRITE
CONTROL
READ
CONTROL
R
FLAG
LOGIC
EXPANSION
LOGIC
XI
WRITE
POINTER RAM
ARRAY
256 x 9
512 x 9
1024 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA OUTPUTS
EF
FF
XO
/
HF
RS
FL
/
RT
0(D –D8)
0(Q –Q8)
2679 drw 01
The IDT logo is a trademark of Integrated Device Technology, Inc.
FEATURES:
• First-In/First-Out dual-port memory
• 256 x 9 organization (IDT7200)
• 512 x 9 organization (IDT7201)
• 1K x 9 organization (IDT7202)
• Low power consumption
— Active: 770mW (max.)
—Power-down: 2.75mW (max.)
• Ultra high speed—12ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Pin and functionally compatible with 720X family
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• High-performance CEMOS technology
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function
• Industrial temperature range (-40oC to +85oC) is
available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load
and empty data on a first-in/first-out basis. The devices use
Full and Empty flags to prevent data overflow and underflow
and expansion logic to allow for unlimited expansion capability
in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (
W
) and Read (
R
) pins.
The devices utilizes a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (
RT
) capability
that allows for reset of the read pointer to its initial position
when
RT
is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT7200/7201/7202 are fabricated using IDT’s high-
speed CMOS technology. They are designed for those
applications requiring asynchronous and simultaneous read/
writes in multiprocessing and rate buffer applications. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.03 2
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
RECOMMENDED DC OPERATING
CONDITIONS
NOTE: 2679 tbl 03
1. VIH = 2.6V for
XI
input (commercial).
VIH = 2.8V for
XI
input (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CCM
Military Supply
Voltage 4.5 5.0 5.5 V
V
CCC
Commercial Supply
Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
V
IH(1)
Input High Voltage
Commercial 2.0 — — V
V
IH(1)
Input High Voltage
Mlitary 2.2 — — V
V
IL(2)
Input Low Voltage
Commercial and
Military
— — 0.8 V
W
D8
VCC
P28-1,
P28-2,
D28-1,
D28-3,
E28-2,
SO28-3
D4
1
228
27
D3D5326
D2D6425
D1D7524
D0
FL
/
RT
623
XI RS
722
FF EF
821
Q0
XO
/
HF
920
Q1Q710 19
Q2Q611 18
Q3Q512 17
Q8Q413 16
GND
R
14 15
2679 drw 02a
D
2
5
D
1
6
D
0
7
XI
8
FF
9
Q
0
10
Q
1
11
NC 12
Q
2
13
D
6
D
7
NC
FL
/
RT
RS
EF
XO
/
HF
Q
7
Q
6
29
28
27
26
25
24
23
22
21
43 2 132 31 30
14 15 16 17 18 19 20
Q3
Q8
GND
NC
R
Q4
Q5
D3
D8
W
NC
VCC
D4
D5
INDEX
J32-1
&
L32-1
2679 drw 02b
DIP/SOIC/CERPACK
TOP VIEW LCC/PLCC
TOP VIEW
NOTE:
1. CERPACK (E28-2) and 600-mil-wide DIP (P28-1 and D28-1) not available
for 7200.
NOTE:
1. LCC (L32-1) not available for 7200.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Com’l. Mil. Unit
VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
TAOperating 0 to +70 –55 to +125 °C
Temperature
TBIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
TSTG Storage –55 to +125 –65 to +155 °C
Temperature
IOUT DC Output 50 50 mA
Current
NOTE: 2679 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol Parameter(1) Condition Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 8 pF
NOTE: 2679 tbl 02
1. This parameter is sampled and not 100% tested.
5.03 3
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, T A = –55 °C to +125°C)
IDT7200L IDT7200L IDT7200L
IDT7201LA IDT7201LA IDT7201LA
IDT7202LA IDT7202LA IDT7202LA
Commercial Military Commercial
tA = 12, 15, 20 ns tA = 20 ns tA = 25, 35 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
ILI(1) Input Leakage Current (Any Input) –1 — 1 –10 — 10 –1 — 1 µA
ILO(2) Output Leakage Current –10 — 10 –10 — 10 –10 — 10 µA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — 2.4 — — V
VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 — — 0.4 V
ICC1(3) Active Power Supply Current — — 125(4) — — 140(4) — — 125(4) mA
ICC2(3) Standby Current (
R
=
W
=
RS
=
FL
/
RT
=VIH)——15——20——15mA
I
CC3(L)(3) Power Down Current (All Input = VCC - 0.2V) — — 0.5 — — 0.9 — — 0.5 mA
DC ELECTRICAL CHARACTERISTICS (Continued)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, T A = –55 °C to +125°C)
IDT7200L IDT7200L IDT7200L
IDT7201LA IDT7201LA IDT7201LA
IDT7202LA IDT7202LA IDT7202LA
Military Commercial Military
tA = 30, 40 ns tA = 50 ns tA = 50, 65, 80, 120 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
ILI(1) Input Leakage Current (Any Input) –10 — 10 –1 — 1 –10 — 10 µA
ILO(2) Output Leakage Current –10 — 10 –10 — 10 –10 — 10 µA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — 2.4 — — V
VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 — — 0.4 V
ICC1(3) Active Power Supply Current — — 140(4) — 50 80 — 70 100 mA
ICC2(3) Standby Current (
R
=
W
=
RS
=
FL
/
RT
=VIH)——20—58—815mA
I
CC3(L)(3) Power Down Current (All Input = VCC - 0.2V) — — 0.9 — — 0.5 — — 0.9 mA
2679 tbl 04
NOTES: 2679 tbl 05
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2.
R
≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
NOTES: 2679 tbl 05
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2.
R
≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
5.03 4
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
Commercial Com'l & Mil. Com'l Military Com'l
7200L12 7200L15 7200L20 7200L25 7200L30 7200L35
7201LA12 7201LA15 7201LA20 7201LA25 7201LA30 7201LA35
7202LA12 7202LA15 7202LA20 7202LA25 7202LA30 7202LA35
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tSShift Frequency — 50 — 40 — 33.3 — 28.5 — 25 — 22.2 MHz
tRC Read Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tAAccess Time — 12 — 15 — 20 — 25 — 30 — 35 ns
tRR Read Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tRPW Read Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRLZ Read Pulse Low to Data Bus at Low Z(3) 3—5—5—5— 5 — 5 —ns
t
WLZ Write Pulse High to Data Bus at Low Z(3, 4) 3—5—5—5— 5 —10—ns
t
DV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — 5 — 5 — ns
tRHZ Read Pulse High to Data Bus at High Z(3) — 12 — 15 — 15 — 18 — 20 — 20 ns
tWC Write Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tWPW Write Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tWR Write Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tDS Data Set-up Time 9 — 11 — 12 — 15 — 18 — 18 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — 0 — ns
tRSC Reset Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tRS Reset Pulse Width (2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRSS Reset Set-up Time(3) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRSR Reset Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tRTC Retransmit Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tRT Retransmit Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRTS Retransmit Set-up Time(3) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRTR Retransmit Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tEFL Reset to Empty Flag Low — 12 — 25 — 30 — 35 — 40 — 45 ns
tHFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 — 30 — 35 — 40 — 45 ns
tRTF Retransmit Low to Flags Valid — 20 — 25 — 30 — 35 — 40 — 45 ns
tREF Read Low to Empty Flag Low — 12 — 15 — 20 — 25 — 30 — 30 ns
tRFF Read High to Full Flag High — 14 — 15 — 20 — 25 — 30 — 30 ns
tRPE Read Pulse Width after
EF
High 12 — 15 — 20 — 25 — 30 — 35 — ns
tWEF Write High to Empty Flag High — 12 — 15 — 20 — 25 — 30 — 30 ns
tWFF Write Low to Full Flag Low — 14 — 15 — 20 — 25 — 30 — 30 ns
tWHF Write Low to Half-Full Flag Low — 17 — 25 — 30 — 35 — 40 — 45 ns
tRHF Read High to Half-Full Flag High — 17 — 25 — 30 — 35 — 40 — 45 ns
tWPF Write Pulse Width after
FF
High 12 — 15 — 20 — 25 — 30 — 35 — ns
tXOL Read/Write to
XO
Low — 12 — 15 — 20 — 25 — 30 — 35 ns
tXOH Read/Write to
XO
High — 12 — 15 — 20 — 25 — 30 — 35 ns
tXI
XI
Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tXIR
XI
Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tXIS
XI
Set-up Time 8 — 10 — 10 — 10 — 10 — 10 — ns
NOTES: 2679 tbl 06
1. Timings referenced as in AC Test Conditions. 3. Values guaranteed by design, not currently tested.
2. Pulse widths less than minimum value are not allowed. 4. Only applies to read data flow-through mode.
5.03 5
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (1) (Continued)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
Military Com'l & Mil. Military(2)
7200 L40 7200L50 7200L65 7200L80 7200L120
7201LA40 7201LA50 7201LA65 7201LA80 7201LA120
7202LA40 7202LA50 7202LA65 7202LA80 7202LA120
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tSShift Frequency — 20 — 15 — 12.5 — 10 — 7 MHz
tRC Read Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tAAccess Time — 40 — 50 — 65 — 80 — 120 ns
tRR Read Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tRPW Read Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tRLZ Read Pulse Low to Data Bus at Low Z(4) 5 — 10 — 10 — 10 — 10 — ns
tWLZ Write Pulse High to Data Bus at Low Z(4, 5) 10 — 15 — 15 — 20 — 20 — ns
tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — 5 — ns
tRHZ Read Pulse High to Data Bus at High Z(4) — 25 — 30 — 30 — 30 — 35 ns
tWC Write Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tWPW Write Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tWR Write Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tDS Data Set-up Time 20 — 30 — 30 — 40 — 40 — ns
tDH Data Hold Time 0 — 5 — 10 — 10 — 10 — ns
tRSC Reset Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tRS Reset Pulse Width (3) 40 — 50 — 65 — 80 — 120 — ns
tRSS Reset Set-up Time(4) 40 — 50 — 65 — 80 — 120 — ns
tRSR Reset Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tRTC Retransmit Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tRT Retransmit Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tRTS Retransmit Set-up Time(4) 40 — 50 — 65 — 80 — 120 — ns
tRTR Retransmit Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tEFL Reset to Empty Flag Low — 50 — 65 — 80 — 100 — 140 ns
tHFH,FFH Reset to Half-Full and Full Flag High — 50 — 65 — 80 — 100 — 140 ns
tRTF Retransmit Low to Flags Valid — 50 — 65 — 80 — 100 — 140 ns
tREF Read Low to Empty Flag Low — 30 — 45 — 60 — 60 — 60 ns
tRFF Read High to Full Flag High — 35 — 45 — 60 — 60 — 60 ns
tRPE Read Pulse Width after
EF
High 40 — 50 — 65 — 80 — 120 — ns
tWEF Write High to Empty Flag High — 35 — 45 — 60 — 60 — 60 ns
tWFF Write Low to Full Flag Low — 35 — 45 — 60 — 60 — 60 ns
tWHF Write Low to Half-Full Flag Low — 50 — 65 — 80 — 100 — 140 ns
tRHF Read High to Half-Full Flag High — 50 — 65 — 80 — 100 — 140 ns
tWPF Write Pulse Width after
FF
High 40 — 50 — 65 — 80 — 120 — ns
tXOL Read/Write to
XO
Low — 40 — 50 — 65 — 80 — 120 ns
tXOH Read/Write to
XO
High — 40 — 50 — 65 — 80 — 120 ns
tXI
XI
Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tXIR
XI
Recovery Time 10 — 10 — 10 — 10 — 10 — ns
tXIS
XI
Set-up Time 10 — 15 — 15 — 15 — 15 — ns
NOTES: 2679 tbl 07
1. Timings referenced as in AC Test Conditions 4. Values guaranteed by design, not currently tested.
2. Speed grades 65, 80 and 120 not available in the CERPACK 5. Only applies to read data flow-through mode.
3. Pulse widths less than minimum value are not allowed.
5.03 6
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
2679 tbl 08
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS
RS
)
Reset is accomplished whenever the Reset (
RS
) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
Read Enable (
R
R
) and Write Enable (
W
W
) inputs must be in
the high state during the window shown in Figure 2, (i.e.,
tRSS before the rising edge of
RS
RS
) and should not change
until tRSR after the rising edge of
RS
RS
. Half-Full Flag (
HF
HF
)
will be reset to high after Reset (
RS
RS
).
WRITE ENABLE (
W
W
)
A write cycle is initiated on the falling edge of this input if the
Full Flag (
FF
) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(
W
). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (
HF
) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (
HF
) is then
reset by the rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF
) will go low,
inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (
FF
) will go high after tRFF,
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from
W
, so external changes
in
W
will not affect the FIFO when it is full.
READ ENABLE (
R
R
)
A read cycle is initiated on the falling edge of the Read
Enable (
R
) provided the Empty Flag (
EF
) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (
R
) goes high,
2679 drw 03
30pF*
1.1K
5V
TO
OUTPUT
PIN
680Ω
the Data Outputs (Q0 – Q8) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (
EF
) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high imped-
ance state. Once a valid write operation has been accom-
plished, the Empty Flag (
EF
) will go high after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
R
so external changes in
R
will not
affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FL
FL
/
RT
RT
)
This is a dual-purpose input. In the Depth Expansion Mode,
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (
XI
).
The IDT7200/7201A/7202A can be made to retransmit
data when the Retransmit Enable control (
RT
) input is pulsed
low. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. Read
Enable (
R
) and Write Enable (
W
) must be in the high state
during retransmit. This feature is useful when less than 256/
512/1024 writes are performed between resets. The retrans-
mit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (
HF
), depending on the
relative locations of the read and write pointers.
EXPANSION IN (
XI
XI
)
This input is a dual-purpose pin. Expansion In (
XI
) is
grounded to indicate an operation in the single device mode.
Expansion In (
XI
) is connected to Expansion Out (
XO
) of the
previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (
FF
FF
)
The Full Flag (
FF
) will go low, inhibiting further write
operation, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (
RS
), the Full-Flag (
FF
) will go
low after 256 writes for IDT7200, 512 writes for the IDT7201A
and 1024 writes for the IDT7202A.
Figure 1. Output Load
* Includes scope and jig capacitances.
or equivalent circuit
5.03 7
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
EMPTY FLAG (
EF
EF
)
The Empty Flag (
EF
) will go low, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (
XO
XO
/
HF
HF
)
This is a dual-purpose output. In the single device mode,
when Expansion In (
XI
) is grounded, this output acts as an
indication of a half-full memory.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (
HF
) will be set low
and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (
HF
) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (
XI
) is con-
nected to Expansion Out (
XO
) of the previous device. This
output acts as a signal to the next device in the Daisy Chain
by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high
impedance condition whenever Read (
R
) is in a high state.
Figure 2. Reset
NOTES:
1.
EF
,
FF
,
HF
may change status during Reset, but flags will be valid at tRSC.
2.
W
and
R
= VIH around the rising edge of
RS
.
Figure 3. Asynchronous Write and Read Operation
HFH
tRSC
tRS
tRSS
tRSS
tEFL
, tFFHt
RS
W
R
EF
HF, FF
tRSR
2679 drw 04
t
A
R
t
RC
DATA OUT VALID DATA OUT VALID
t
RPW
t
RLZ
t
DV
t
A
t
RHZ
t
RR
t
WC
t
WR
t
WPW
DATA IN VALID DATA IN VALID
t
DS
t
DH
Q
0
– Q
8
2679 drw 05
W
D
0
– D
8
5.03 8
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE
R
IGNORED
WRITE FIRST READ ADDITIONAL
READS FIRST
WRITE
W
FF
tWFF tRFF
2679 drw 06
Figure 4. Full Flag From Last Write to First Read
Figure 6. Retransmit
t
RTC
t
RT
t
RTS
RT
W,R
HF, EF, FF
t
RTR
FLAG VALID
2679 drw 08
RTF
LAST READ
R
IGNORED
READ FIRST WRITE ADDITIONAL
WRITES FIRST
READ
W
EF
tREF tWEF
2679 drw 07
VALID VALID
tA
DATA OUT
Figure 5. Empty Flag From Last Read to First Write
5.03 9
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
EF
W
R
tWEF
tRPE
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
FF
R
W
tRFF
tWPF
2679 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
R
W
HF
t
RHF
2678 drw 11
HALF-FULL OR LESS
MORE THAN HALF-FULL
HALF-FULL OR LESS
t
WHF
Figure 9. Half-Full Flag Timing
R
W
XO
2679 drw 12
WRITE TO
LAST PHYSICAL
LOCATION
t
XOL
t
XOH
READ FROM
LAST PHYSICAL
LOCATION
t
XOL
t
XOH
Figure 10. Expansion Out
5.03 10
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
XI
R
2679 drw 13
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
tXIS
tXIRtXI
tXIS
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e.
FF
is monitored on the device
where
W
is used;
EF
is monitored on the device where
R
is
used). For additional information, refer to Tech Note 8:
Oper-
ating FIFOs on Full and Empty Boundary Conditions
and
Tech Note 6:
Designing with FIFOs.
Single Device Mode
A single IDT7200/7201A/7202A may be used when the
application requirements are for 256/512/1024 words or less.
The IDT7200/7201A/7202A is in a Single Device Configura-
tion when the Expansion In (
XI
) control input is grounded (see
Figure 12).
Depth Expansion
The IDT7200/7201A/7202A can easily be adapted to appli-
cations when the requirements are for greater than 256/512/
1024 words. Figure 14 demonstrates Depth Expansion using
three IDT7200/7201A/7202As. Any depth can be attained by
adding additional IDT7200/7201A/7202As. The IDT7200/
7201A/7202A operates in the Depth Expansion mode when
the following conditions are met:
1. The first device must be designated by grounding the First
Load (
FL
) control input.
2. All other devices must have
FL
in the high state.
3. The Expansion Out (
XO
) pin of each device must be tied to
the Expansion In (
XI
) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(
FF
) and Empty Flag (
EF
). This requires the ORing of all
EF
s and ORing of all
FF
s (i.e. all must be set to generate the
correct composite
FF
or
EF
). See Figure 14.
5. The Retransmit (
RT
) function and Half-Full Flag (
HF
) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9:
Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta-
tus flags (
EF
,
FF
and
HF
) can be detected from any one device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7200/7201A/7202As as shown
in Figure 16. Both Depth Expansion and Width Expansion
may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flow-
through mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of
W
, called the first write edge, and it remains on the
bus until the
R
line is raised from low-to-high, after which the
bus would go into a three-state mode after tRHZ ns. The
EF
line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The
R
line causes
the
FF
to be deasserted but the
W
line being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of
W
, the new word is loaded in the FIFO. The
W
line must be toggled when
FF
is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.03 11
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT
7200/
7201A/
7202A
XI XI
9918
9
18
HF
HF
9
DATA
WRITE (
W
)
FULL FLAG (
FF
)
RESET (
RS
)
(D)
IN
READ (
R
)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
DATA (Q)
OUT
IDT
7200/
7201A/
7202A
Figure 12. Block Diagram of Single 256/512/1024 x 9 FIFO
2679 drw 15
Figure 13. Block Diagram of 256/512/1024 x 18 FIFO Memory Used in Width Expansion Mode
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs Internal Status Outputs
Mode
RS
RS FL
FL XI
XI
Read Pointer Write Pointer
EF
EF FF
FF
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset All Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
NOTE: 2679 tbl 10
1.
XI
is connected to
XO
of previous device. See Figure 14.
RS
= Reset Input,
FL
/
RT
= First Load/Retransmit,
EF
= Empty Flag Output,
FF
= Flag Full Output,
XI
= Expansion Input,
HF
= Half-Full Flag Output
TABLE I—RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs Internal Status Outputs
Mode
RS
RS RT
RT XI
XI
Read Pointer Write Pointer
EF
EF FF
FF HF
HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment(1) Increment(1) XXX
NOTE: 2679 tbl 09
1. Pointer will increment if flag is High.
WRITE (
W
)
DATA IN (D)
FULL FLAG (
FF
)
RESET (
RS
)
9READ (
R
)
9DATA OUT (Q)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
EXPANSION IN (
XI
)
(
HF
)
IDT
7200/
7201A/
7202A
(HALF–FULL FLAG)
2679 drw 14
5.03 12
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion)
2679 drw 16
D
W
IDT
7200/
7201A/
7202A
FF EF
FL
XO
RS
FULL EMPTY
V
CC
R
9
9
99
XI
9Q
IDT
7200/
7201A/
7202A
IDT
7200/
7201A/
7202A
FF EF
FL
XO
XI
FF EF
FL
XO
XI
Figure 15. Compound FIFO Expansion
NOTES:
1. For depth expsansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
R
,
W
,
RS
•••
•••
•••
D0–DN
Q0–Q8Q9–Q17
Q9–Q17Q0–Q8
D0-D8
D9-DN
D9-D17
D18 -DN
D(N-8)-DN
D(N-8)-DN
Q(N-8) -QN
Q(N-8) -QN
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
2679 drw 17
5.03 13
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 16. Bidirectional FIFO Mode
2679 drw 19
DATAOUTVALID
tRPE
tREF
tWEF
tWLZ tA
DATAOUT
EF
R
W
DATAIN
Figure 17. Read Data Flow-Through Mode
Figure 18. Write Data Flow-Through Mode
2679 drw 20
tWPF
DATAOUT VALID
DATAIN
VALID
FF
W
R
DATAOUT
DATAIN
tWFF tDH
tDS
tRFF
tA
IDT
7201A
R
B
EF
B
HF
B
W
A
FF
A
W
B
FF
B
SYSTEM A SYSTEM B
Q
B 0-8
D
B 0-8
Q
A 0-8
R
A
HF
A
EF
A
IDT
7200/
7201A/
7202A
D
A 0-8
IDT
7200/
7201A/
7202A
2679 drw 18
5.03 14
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
2679 drw 21
* "A" to be included for 7201 and 7202 ordering part number.
IDT XXXX
Device Type
XXX
Speed
X
Power
X
Package
X
Process/
Temperature
Range
Blank
B
7200
7201
7202
12
15
20
25
30
35
40
50
65
80
120
Commercial (0°C to + 70°C)
Military (–55°C to + 125°C)
Compliant to MIL-STD-883, Class B
256 x 9-Bit FIFO
512 x 9-Bit FIFO
1024 x 9-Bit FIFO
Commerical Only
Commercial Only
Commercial Only
Military Only
Commercial Only
Military Only
Military only--
except XE
package
LA Low Power*
P
TP
D
TD
J
SO
L
XE
Plastic DIP (7201 & 7202 Only)
Plastic THINDIP
CERDIP (7201 & 7202 Only)
Ceramic THINDIP
Plastic Leaded Chip Carrier
SOIC
Leadless Chip Carrier (7201 & 7202 Only)
CERPACK (7201 & 7202 Only)
Access Time (tA)
Speed in Nanoseconds
