National Semiconductor MM5309, MM5311, MM5312, General Description -) These digital clocks are monolithie MOS tegrated circuits utilizing P-channel onal MOS teased mode and ion implanted. deptetion mode devices. The devices provide al! the togic required to build several types of clocks. Two display modes (4 or 6-digits} facilitate end-product designs of varied sophistication. The circuits interface to LED and gas discharge displays with minimal additional components, and require only a single power supply. The timekeeping function operates from either a 50 or 60 Hz input, and the dis- play format may be either 12 hours (with leading-zero blanking) or 24 hours. Outputs consist of multiplexed display drives (BCD and 7-segment) and digit enables. The devices operate over a power supply range of 11V to 19V and do not require a regulated supply. These clocks are packaged in dual-in-line Packages. Features = 50 or 60 Hz operation = 12 or 24-hour display format Digital Clocks MMS5313, VMM5314, IMM5315 Digital Clocks a Leading-zero blanking (12-hour format) a 7-segment outputs @ Single power supply Fast and slow set controls B Internal multiplex oscillator = For features of individual clocks, see Table | Applications Desk clocks = Automobile clocks Industrial clocks =@ Interval Timers TABLE! FEATURES MM5309 MM5311 MM5312 MM5313 MM5314 MM6315 BCD Outputs x x x x x 4/6-Digit Display Mode x x x x x Hold Count Control x x x x 1 Hz Output : x x Output Enable Control x x x Reset x x Connection Diagrams (Dual-In-Line Packages) Yoo OUTPUT EMABLE Yoo L ourrur enasve Beat 4/6 DIGIT SELECT OE 12 on overt sevect rep ourpurs | FEO tur TING sco ourpurs J FES Pe wx Tong wea |e a a Ea at mio Ri Mi8 ' 41 | oir od oeiT , woof uate, 2 af EMAL, $1 ee st MULTIPLEXED MULTIPLEXEG 7SEGMENT si T SEGMENT 2 S10 ourpurs | sovea vs neut ourvurs | LS sage in inPUT f FAST SET f LU rast SET SLOW SET +? sow ser 12/24 HOUR SELECT RESET 12/24 HOUR SELECT HS vou styeo Hz sevect 1 Vs 50/60 Hz SELECT LS veg TOP VIEW Order Number MM5300N_{/ See Package 23 TOP VIEW Order Number MM5311N See Package 23 5-13 z : z = 8 = = 3 ; 3 = = & > = = 3MM5309, MM5311, MM5312, MM5313, MM5314, MIM5315 Absolute Maximum Ratings Voltage at Any Pin Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) Vsg + 0.3 to Vgs ,20V -25C to +70C 65C to +150C 300 c 4 Electrical Characteristics TA within operating range, Vgg = 11V to 19V, Vpp = OV, unless otherwise specified. Order Number MM5314N See Package 22 /S See Package 23 1s P= Vso { Order Number MM5315N PARAMETER CONDITIONS MIN TYP. |) MAX - _ UNITS Power Supply Voltage Vss (Vpp = OV) / We 19 Vv Power Suppty Current Vss = 14V, (No Output Loads) 10 mA 50/60 Hz Input Frequency dc . 50.or 60. 60k Hz 50/60 Hz Input Voltage , Logical High Level Vss1 Vss Vss Vv Logical Low Level VoD Vop Vss-10 Vv Multiplex Frequency Determined by External R & C , 0.100 1.0 60. kHz All Logic Inputs Driven by External Timebase de 60 kHz ~ Logical High Level Internal Depletion Device to Vsg Vss-1 Vss. Vss Vv Logical Low Level . Vpp VpbbD Vsgs10 Vv BCD and 7-Segment Outputs : Logical High Level Loaded 2 k2. to Vpp 2.0 20 MA source Logical Low Level 0.01 mA source Digital Enable Outputs Logical High Level 0.3 mA source Logical Low Level Loaded 100 2 to Vsg 5.0 25 mA sink Connection Diagrams (Cont 8 Dual-In-Line Packages (Top Views) wuctiexes { #04 4 M icoe Yoo L28 aye picit seLect BCD OUTPUTS reas J p22 MUX TIMING wwecarive J 802 = Yoo wuiTiPuexen | 3 2B TRUE) bco 4 M1 aor 22 ux Timi sco OUTPUTS (NEGATIVE }aep> 4 emo -4j 127 aay True) | 5 * toi 24, ousit 1 = m0 ogi i 22 sof outputs oo! P21 { ourpurs ot aa5313 2 31 MULTIPLEXED ? wis312 a 8 24 TSEGMENT 4 P Ht0 o P $10 OUTPUTS MULTIPLEXED 9 2 e a) 17, 1 PPS OUTPUT TSEGMENT < d P= 1PPS OUTPUT OUTPUTS 10] 9 16 . LS sevso He INPUT = 0/60 He INPUT a tear 10; = HS rast ser 72 LY? stowser 12/20NR SELECT 4 stow ser 1224 up secect 4] PS How soso Hz sevect 124 BB vgs soso Hz sevect 144 LS sg Order Number MM5312N { Order Number MM5313N See Package 22 See Package 23 ouruT ENABLE 4 24 aye DiGiT SELECT Yoo 4 2 i DIGIT SELECT Vpo 4 122 saux Timur Core 7 aux TIMING i" Le seein |e re a bw mt |e Ee 5 Izo sn a Ce cm Ht 6 muctipLexeo | ; EWARLE . 7 F210 f outers 7SEGMENT d 4 19, H10f OUTPUTS b (5315, s1 OUTPUTS a Mista M8 gy pe [a : MULTIPLEXED 3] 20 8 TSEGMENT d P= 60/60 Hz INPUT = + sto OUTPUTS 19 9 16 e P FAST SET = = savea He INPUT ' He sow set 12/24 HR SELECT WJ 15 FAST SET 1 HOLD sora He sevect 4 LS suowser taza nn secect 43 HS eset Vs, wy 1 own sate Hz sevect 5-14eae Functional Description A block diagram of the MM5309 digital clock is shown in Figure 1. MM5311, MM5312, MM5313, MM5314 and MM5315 clocks are bending options of MM5309 clock. Table 1 shows the pin-outs for these clocks. 50 or 60 Hz Input: This input is applied to a Schmitt Trigger shaping circuit which provides _ approximately 5V of hysteresis and allows using a filtered sinewave input. A simple RC fitter such as shown in Figure 10 should be used to remove possible line voltage transients that could either cause the clock to gain time or damage the device. The shaper output drives a counter chain which performs the timekeeping function. 50 or 60 Hz Select Input: This input programs the Prescale counter to divide by either 50 or 60 to obtain a 1 Hz timebase. The counter is programmed for 60 Hz operation by connecting this input to Vpp. An internal depletion device is common to this pin; simply leaving this input unconnected programs the clock for 50 Hz operation. As shown in Figure 7, the prescale counter provides both 1.Hz and 10 Hz: signals, which can be ' brought out as bonding options. Time Setting Inputs: Both fast and slow setting inputs, as well as a hold input, are provided. tnternal depletion devics provide the normal timekeeping function. Switching any of these inputs (one at a time) to Vop results in the desired time setting function. The three gates in the counter chain (Figure 1) are used for setting time. During normal operation, gate A connects the shaper output to a prescale counter (+50 or +60); gates B and C cascade the remaining counters. Gate A is used to inhibit the input to the counters for the duration of slow, fast or hold time-setting input activity. Gate B is used to connect the shaper output directiy to a seconds counter (+60), the condition for slow advance. Likewise, gate C connects the shaper output directly to a minutes counter (+60) for fast advance. Fast set then, advances hours information at one hour per second and slow set advances minutes information at one minute per second. 12 or 24-Hour Select Input: This input is used to pro- gram the hours counter to divide by either 12 or 24, thereby. providing the desired display format. The 12-hour display format is selected by connecting this input to Vpp;: leaving the input unconnected (internal depletion device) selects the 24-hour format. Output Multiplexer Operation: The seconds, minutes, and hours counters continuously reflect the time of day. Outputs from each counter (indicative of both units and tens of seconds, minutes, and hours) are time- division multiplexed to provide digit-sequential access to the time data. Thus, instead of requiring 42 leads to interconnect a 6-digit clock and its display (7 segments per digit), only 13 output leads are required. The multi- plexer is addressed by a muitiplex divider decoder, which is driven by a multiplex oscillator. The oscillator and external timing components set the frequency of the multiplexing function and, as controlled by the 4 or 6-digit select input, the divider determines whether data will be output for 4 or 6 digits. A zero-blanking circuit suppresses the zero that would otherwise sometimes appear in the tens-of-hours display; blanking is effective only in the 12:hour format. The muttipiexer addresses also become the display digit-enable outputs. The multi- plexer outputs are applied to a decoder which is used to address a programmable (code converting) ROM. This ROM generates the final output codes, i.e., BCD and 7-segment. The sequential output- order. is from digit 6 (unit seconds) through digit 1 (tens of hours). Multiplex Timing Input: The multiplex oscillator is shown in Figure 2. Adding an external resistor and Capacitor to this circuit via the multiplex timing input (as shown in Figure 4a) produces a relaxation oscillator. The waveform at this input is a quasi-sawtooth that is squared by the shaping action of the Schmitt Trigger in Figure 2. Figure 3 provides guidelines for selecting the external components relative to desired multiplex frequency. Figure 4. also iliustrates two methods of synchronizing the multiplex oscillator to an external timebase. The external RC timing components may. be omitted: and this input may_be driven by an external timebase; the - required logic levels are the same as 60 or 60 Hz input. , Reset: Applying Vpp to this input resets the counters to 0:00:00.00 In 12-hour format and 00:00:00.00 in 24-hour formats leaving the input unconnected (internal depletion pull-up) selects normal operation. Proper reset will be ensured when Vpp to Vgs slew rate is no faster than one volt per microsecond. This can be accomplished with a capacitor from the reset input to Vsgs. 4 or 6-Digit Setect Input: Like the other control inputs, this input is provided with an internal depletion pull-up device. With no input connection the glock outputs data for a 4-digit display. Applying Vpp to this input.pro- vides a 6-digit display. Output Enable Input: With this pin unconnected the BCD and 7-segment outputs are enabled {via an internal depletion pull-up). Switching Vpp to'this input inhibits these outputs. (Not applicable to MM&312, MM5313, and MM5315 clocks.) Output Circuits: Figure Sa illustrates the circuit used for the BCD and 7- segment outputs. Figure 5b shows the digit enable output circuit. Figure 6 illustrates interfacing these outputs to standard and low power TTL. Figures 7 and 8 illustrate methods of interfacing these outputs to common anode and common cathode LED displays, respectively. A method of interfacing these clocks to gas discharge display tubes is shown in Figure 9. When driving gas discharge displays which enclose more than one digit in a common gas envelope, it is necessary to inhibit the segment drive voltage(s) during inter-digit transitions. Figure 9 also ilustrates a method of generating a voltage for application to the output enable input to accomplish the required inter- digit blanking, SLESININ' PLESIAIN SLESWIN ZLESININ LLEGININ GOESINIA 5-154, M 42, MM5312, MM5314, MMS315 Functional Description (cont'a) 50/60 He SELECT 50/60 Hz INPUT SLOW SET FAST SET RESET Vss Om YpO> 4/8 DIGIT SELECT MULTIPLEX TIMING oureuT Yoo 50/60 Hz INPUT OR MULTIPLEX. TIMING COMPONENTS SHAPING GATE CIRCUIT A SECONDS COUNTER (+60) AS REOD MULTIPLEX OFVIDER/ . DECODER MULTIPLEX OSCILLATOR FIGURE 1. MM5309 Digital HIGH Vay I: | Vss L 4 ' aA th#-o be a r 4 ! N I Dotted components added to shaping Msg circuit to form multiplex oscillator *Effectively FIGURE 2. 50/60 Hz Shaping Circuit/Multiplex Oscillator SECONDS, MINUTES, & nouns: MULTIPLEXER +50R-+6 Peete eo eon PRESCALE COUNTER MINUTES HOURS . COUNTER COUNTER 12/24 HOUR (+ 60) (1B. 0R 24) SELECT QUTPUT ENABLE MULTIPLEXED BCD ouTPuTS MULTIPLEXED 7-SEGMENT outeurs DECODER OIGIT ENABLE OUTPUTS Ctock Block Diagram 50/60 PPS OUTPUT OR MULTIPLEX OSCILLATOR OUTPUT 100k MULTIPLEX FREQUENCY (Hz) z =OV A= 100 0.0001. @.001 0.01 ot C CAPACITANCE (uF) WITH R = 220k FIGURE 3. Multiptex Timing Component Selection GuideFunctional Description (conta) Vgs o _i a MUX TIMING ams303 > > $8 Yoo FIGURE 4a. Relaxation Oscillator Vs 9 Vee ~~ e1 cz MULTIPLEX MULTIPLEX EXTEANAL EXTERNAL TIME o [4 TMING INPUT] sesso0 LJ CLOCK O-AAALMINGINEUT] tsz00 BASE t SIGNAL 10k (INPUT OR OUTPUT) - Sa > Yoo o Yoo FIGURE 4b. External Time Base FIGURE 4c. External Clock Note. Free running frequency should be set to run slightly fower than system frequency over temperature. External time base may be input or output. * R=100k,. . FIGURE 4. Synchronizing or Triggering Multiplex Oscillators Vss Vss a - Vss DIGIT ENABLE Vss ouTPuT a 100 Vop T-SEGMENT BCD OR tppg , ouTPUT >o| (OPEN DRAIN) f 600 Yoo Yoo FIGURE Sa FIGURE 5b FIGURE 5. Output Circuits 5-17MM5309, MM5311, MM5312, MM5313, MM5314, MM5315 Functional Description (conts) MOS to Low Power TTL Interface Vss AMY TTL GATE Veo *8 Lo Manns 308 , - > $F Yoo For Vss = 5, Vpo 2 12, R = 10k For Vgg = 10 to 17V, Vop * Gad, R = 3k Vss UVss TYPICAL Diet ENABLE ouTPUT 2630 OR EQUIV. (x7) 4 > S$ Stk Vss-Vop VF 0.6V Nig) Where R,_ as in kf And Ve = forward drop of LED 0.6V ~ voltage drop of transistors N = number of digits in display Ig = required average LED current RAL FIGURE 6. interfacing TTL MOS to TTL Interface Vg = SV ANY GATES Veg = 5V Voce=5 Vpp *-12 For Vgs = 5, Vpp 7 12, R = 7.5k Note.: Digit satect will drive TTL directly when 5, 12 supplies. are used. TYPICAL LED SEGMENTS {COMMON-CATHODE} SUCH AS HENTAR, Of Eautv. Vss Vppl/2 Ve 1.5V Nite) Where R__ is in kQ And Ve = forward drop of LED O.9V = voltage drop of transistors N = number of digits in display If = required average LED current Transistors may be replaced by DM75491, OM75492, DM8861, DM8863 or equivalent segment/digit drivers. FIGURE 7. interfacing Common Anode LED Displays FIGURE 8. Interfacing Common Cathode LED Displays 5-18(ov) | x * TYPICAL . 3 4 DIGIT ENABLE 2N5087 (X6) ouTeuT) ~ L (xe) oiGIT 270k COMMON-ANODE ANA TERMINAL . trea % SEGMENT M5309 SEGMENT CATHODE TERMINAL TYPICAL alien . yar SEGMENT 2N5087 (X7) OUTPUT i MULTIPLEX * 005 TIMING . ouTPuT ENABLE : 2 S20 oo < 2 > Ly 3 39k Yoo _ {-15V) . 7-7 MULTIPLEX TIMING AND INTER-DIGIT BLANKING 35 --<-- 125V ~--+ FIGURE 8S. interface Panaplex 11* Neon Display Tube *TM of Burroughs Corp. Nota 1 : ee i ar et 19 1% 27 DI 25 TYPICAL [ase vs te cmaoe _L 93 23 ; 265096 | eo Oss D4 22 03 stow | ony 1M =O OA M5303 | , 4 278k 1 Vop | S (xa) | 2NyONs 3 SEG + 14 abedetg 28 26 6 7 8 9 1011 12 ir K a: PM TYPICAL CATHODE raed 0.1 @200v DRIVER | og) 2 e | ] | Inst4 = Sak D 22% I r 5 5 -15V . | $ 220k 3 2% S$ 4% 1NS14 | INTER-DIGIT BLANKING CIRCUIT Son ; on Son = (07) -36V . = -105V _ FIGURE 10. MM5309 Driving Gas Discharge Display, Typical Applications 5-19 VLESINIA ELESININ ZLESININ LLESININ 6QGSINI SLESIAIA