TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 D D D Signal Processor (DSP) - TMS320C6414 - 2.5-, 2-, 1.67-ns Instruction Cycle Time - 400-, 500-, 600-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - Twenty-Eight Operations/Cycle - 3200, 4000, 4800 MIPS - Fully Software-Compatible With C62x - Pin-Compatible With C6415/16 Devices VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core - Eight Highly Independent Functional Units With VelociTI.2 Extensions: - Six ALUs (32-/40-Bit) Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Non-Aligned Load-Store Architecture With 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-, 16-, 32-, 64-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization - VelociTI.2 Increased Orthogonality L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) D D D D D D D D D D D D - 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Two External Memory Interfaces (EMIFs) - One 64-Bit (EMIFA) - One 16-Bit (EMIFB) - Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) - 1280M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Host-Port Interface (HPI) - User-Configurable Bus-Width (32-/16-bit) - Access to Entire Memory Map Three Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial Peripheral Interface (SPI) Compatible (Motorola) Three 32-Bit General-Purpose Timers General-Purpose I/O (GPIO) Pins - Thirteen Dedicated GPIO Pins - Total of Sixteen GPIO Pins - Programmable Interrupt/Event Generation Modes Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch 0.12-m/6-Level Metal Process - CMOS Technology 3.3-V I/Os, 1.2-V Internal (-400, -500 Speeds) 3.3-V I/Os, 1.4-V Internal (-600 Speed) PRODUCT PREVIEW D Highest-Performance Fixed-Point Digital Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2001, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Table of Contents PRODUCT PREVIEW GLZ BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block and CPU (DSP core) diagram . . . . . . . . . . . 6 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 recommended operating conditions . . . . . . . . . . . . . . . . 39 electrical characteristics over recommended ranges of supply voltage and operating case temperature . 39 parameter measurement information . . . . . . . . . . . . . . . input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . programmable synchronous interface timing . . . . . . . . synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port (McBSP) timing . . . . . timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing . . . . . JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GLZ BGA package (bottom view) GLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 2 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 40 42 46 49 53 62 63 64 66 67 72 83 84 85 86 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 description The TMS320C64x DSPs (including the TMS320C6414 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6414 (C6414) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelocTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x is a code-compatible member of the C6000 DSP platform. The C6414 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes three multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C6414 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. Other trademarks are the property of their respective owners. The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 PRODUCT PREVIEW With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6414 device offers cost-effective solutions to high-performance DSP programming challenges. The C6414 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-- with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C6414 can produce two 32-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6414 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 device characteristics Table 1 provides an overview of the C6414 DSP. The table shows significant features of the C6414 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6414 Processor HARDWARE FEATURES Peripherals Peri herals C6414 EMIFA (64-bit bus width) 1 EMIFB (16-bit bus width) 1 EDMA (64 independent channels) 1 HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32) McBSPs 3 32-Bit Timers 3 General-Purpose Input/Outputs (GPIOs) 16 Size (Bytes) PRODUCT PREVIEW On-Chip Memory 1056K 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 1024KB Unified Mapped RAM/Cache (L2) Organization CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) Frequency MHz Cycle Time Voltage 400, 500, 600 2.5 ns (C6414-400) 2 ns (C6414-500) 1.67 ns (C6414-600) ns 1.2 V (-400, -500) 1.4 V (-600) Core (V) I/O (V) 4 0x0C01 3.3 V PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12 BGA Package 23 x 23 mm 532-Pin BGA (GLZ) Process Technology m Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) Device Part Numbers (For more details on the C6000 DSP part numbering, see Figure 4) 0.12 m POST OFFICE BOX 1443 PP * HOUSTON, TEXAS 77251-1443 TMX320C6414GLZ TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 device compatibility The C64x family of devices has a diverse and powerful set of peripherals. The common peripheral set and pin-compatibility that the C6414, C6415, and C6416 devices offer lead to easier system designs and faster time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414, C6415, and C6416 devices. The C6414, C6415, and C6416 devices are pin-for-pin compatible, provided the following conditions are met: D All devices are using the same peripherals. The C6414 is pin-for-pin compatible with the C6415/C6416 when the PCI and UTOPIA peripherals on the C6415/C6416 are disabled. The C6415 is pin-for-pin compatible with the C6416 when they are in the same peripheral selection mode. [For more information on peripheral selection, see the Device Configurations section of the TMS320C6415 and TMS320C6416 device-specific data sheets (literature number SPRS146 and SPRS164, respectively).] D The BEA[9:7] pins are properly pulled up/down. PRODUCT PREVIEW [For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of the TMS320C6414, TMS320C6415, and TMS320C6416 device-specific data sheets (literature number SPRS134, SPRS146, and SPRS164, respectively).] Table 2. Peripherals and Coprocessors Available on the C6414, C6415, and C6416 Devices C6414 C6415 C6416 EMIFA (64-bit bus width) PERIPHERALS/COPROCESSORS EMIFB (16-bit bus width) EDMA (64 independent channels) HPI (32- or 16-bit user selectable) PCI (32-bit) -- McBSPs (McBSP0, McBSP1, McBSP2) UTOPIA (8-bit mode) -- Timers (32-bit) [TIMER0, TIMER1, TIMER2] GPIOs (GP[15:0]) -- -- VCP/TCP Coprocessors -- denotes peripheral/coprocessor is not available on this device. For more detailed information on the device compatibility and similarities/differences among the C6414, C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 functional block and CPU (DSP core) diagram SDRAM 64 SBSRAM 16 C6414 Digital Signal Processor EMIF A L1P Cache Direct Mapped 16K Bytes Total EMIF B SRAM ROM/FLASH Timer 2 ZBT SRAM C64x DSP Core Timer 1 FIFO Instruction Fetch I/O Devices Timer 0 Multichannel Buffered Serial Port 2 (McBSP2) PRODUCT PREVIEW Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Multichannel Buffered Serial Port 1 (McBSP1) Control Registers Instruction Dispatch Advanced Instruction Packet Control Logic Instruction Decode Data Path A Enhanced DMA Controller (64-channel) L2 Memory 1024K Bytes Total A Register File A31-A16 A15-A0 .L1 .S1 .M1 .D1 Data Path B Test B Register File B31-B16 B15-B0 .D2 .M2 .S2 Advanced In-Circuit Emulation .L2 Multichannel Buffered Serial Port 0 (McBSP0) 16 32 L1D Cache 2-Way Set Associative 16K Bytes Total GPIO Host Port Interface (HPI) PLL (x1, x6, x12) Power-Down Logic Boot Configuration Interrupt Selector 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 Interrupt Control TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include: Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data cross path"--a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically "true"). TMS320C62x is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 PRODUCT PREVIEW D D D D D D TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 CPU (DSP core) description (continued) The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 x 16-bit multiplies or four 8 x 8-bit multiplies per clock cycle. The .M unit can also perform 16 x 32-bit multiply operations, dual 16 x 16-bit multiplies with add/subtract operations, and quad 8 x 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. PRODUCT PREVIEW The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718) TMS320C67x is a trademark of Texas Instruments. 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 CPU (DSP core) description (continued) src1 .L1 src2 dst long dst long src ST1b (Store Data) ST1a (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A 8 8 Register File A (A0-A31) src2 See Note A See Note A long dst dst .M1 src1 src2 32 MSBs 32 LSBs DA1 (Address) .D1 PRODUCT PREVIEW LD1b (Load Data) LD1a (Load Data) dst src1 src2 2X 1X src2 .D2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) src1 dst 32 LSBs 32 MSBs src2 .M2 src1 dst See Note A See Note A long dst Register File B (B0- B31) src2 Data Path B .S2 src1 dst long dst long src ST2a (Store Data) ST2b (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst 8 8 .L2 src2 src1 Control Register File NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 1. TMS320C64x CPU (DSP Core) Data Paths POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 memory map summary Table 3 shows the memory map address ranges of the C6414 device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C6414 device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA. Table 3. TMS320C6414 Memory Map Summary MEMORY BLOCK DESCRIPTION PRODUCT PREVIEW Internal RAM (L2) 1M Reserved 23M External Memory Interface A (EMIFA) Registers 256K L2 Registers 256K HPI Registers 256K McBSP 0 Registers 256K McBSP 1 Registers 256K Timer 0 Registers 256K Timer 1 Registers 256K Interrupt Selector Registers 256K EDMA RAM and EDMA Registers 256K McBSP 2 Registers 256K EMIFB Registers 256K Timer 2 Registers 256K GPIO Registers 256K Reserved 5M - 256K QDMA Registers 52 Reserved 736M - 52 McBSP 0 Data 64M McBSP 1 Data 64M McBSP 2 Data 64M Reserved 576M EMIFB CE0 64M EMIFB CE1 64M EMIFB CE2 64M EMIFB CE3 64M Reserved 256M EMIFA CE0 256M EMIFA CE1 256M EMIFA CE2 256M EMIFA CE3 256M Reserved 10 BLOCK SIZE (BYTES) 1G POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 HEX ADDRESS RANGE 0000 0010 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01A8 01AC 01B0 01B4 0200 0200 3000 3400 3800 3C00 6000 6400 6800 6C00 7000 8000 9000 A000 B000 C000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0034 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 000F 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01A7 01AB 01AF 01B3 01FF 0200 2FFF 33FF 37FF 3BFF 5FFF 63FF 67FF 6BFF 6FFF 7FFF 8FFF 9FFF AFFF BFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0033 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 signal groups description TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMUCLK1 EMUCLK0 Reset and Interrupts Clock/PLL RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 RSV RSV RSV RSV RSV RSV Reserved IEEE Standard 1149.1 (JTAG) Emulation * * * PRODUCT PREVIEW CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE1 CLKMODE0 PLLV RSV RSV RSV Control/Status GP15 GP14 GP13 GP12 GP11 GP10 GP9 CLKS2/GP8 GPIO GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 GP3 CLKOUT6/GP2 CLKOUT4/GP1 GP0 General-Purpose Input/Output (GPIO) Port These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2 clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more detail, see the Device Configurations section of this data sheet. These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. Figure 2. CPU and Peripheral Signals POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 signal groups description (continued) 64 Data AED[63:0] AECLKIN ACE3 ACE2 Memory Map Space Select ACE1 ACE0 20 AEA[22:3] External Memory I/F Control Address ABE7 ABE6 ABE5 ABE4 Byte Enables ABE3 ABE2 PRODUCT PREVIEW ABE1 ABE0 Bus Arbitration AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT AHOLD AHOLDA ABUSREQ EMIFA (64-bit) 16 Data BED[15:0] BECLKIN BECLKOUT1 BECLKOUT2 BCE3 BCE2 BCE1 BCE0 Memory Map Space Select External Memory I/F Control 20 BEA[20:1] BBE1 BBE0 BARE/BSDCAS/BSADS/BSRE BAOE/BSDRAS/BSOE BAWE/BSDWE/BSWE BARDY BSOE3 BPDT Address Byte Enables Bus Arbitration BHOLD BHOLDA BBUSREQ EMIFB (16-bit) The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. Figure 3. Peripheral Signals 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 signal groups description (continued) HCNTL0 HCNTL1 HHWIL (HPI16 ONLY) Data HPI (Host-Port Interface) Control HAS HR/W HCS HDS1 HDS2 HRDY HINT Timer 0 TOUT0 TINP0 Register Select Half-Word Select TOUT1 TINP1 Timer 1 TOUT2 TINP2 2 Timer 1 Timers McBSP1 PRODUCT PREVIEW 32 HD[31:0] McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKR1 FSR1 DR1 Receive Receive CLKS1 Clock CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 Clock CLKS0 McBSP2 CLKX2 FSX2 DX2 Transmit CLKR2 FSR2 DR2 Receive CLKS2/GP8 Clock McBSPs (Multichannel Buffered Serial Ports) These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2 clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. See the Device Configurations section. Figure 3. Peripheral Signals (Continued) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 DEVICE CONFIGURATIONS multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. On the C6414 device, these multiplexed pins are configured by software and can be programmed to switch operating modes at anytime. Table 4 describes the multiplexed pins on the on the C6414 device. Table 4. C6414 Device Multiplexed Pins SIGNAL PRODUCT PREVIEW NAME NO. DEFAULT FUNCTION DEFAULT SETTING CLKOUT4/GP1 AE6 CLKOUT4 GP1EN = 0 CLKOUT6/GP2 AD6 CLKOUT6 GP2EN = 0 CLKS2/GP8 AE4 CLKS2 GP8EN = 0 DESCRIPTION These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly g y configured. g GP EN = 1: GPxEN 1 GPx GP pin i enabled bl d GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output debugging considerations It is recommended that external connections be provided to device configuration pins, including CLKMODE[1:0], BEA[20:14], and HD5. Although internal pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the BEA bus (BEA[13:1]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors for all device pins, see the terminal functions table. 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions SIGNAL NAME TYPE IPD/ IPU DESCRIPTION H4 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP1 AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKOUT6/GP2 AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKMODE1 G1 I IPD CLKMODE0 H2 I IPD PLLV J6 A TMS AB16 I IPU JTAG test-port mode select TDO AE19 O/Z IPU JTAG test-port data out TDI AF18 I IPU JTAG test-port data in TCK AF16 I IPU JTAG test-port clock TRST AB15 I IPD JTAG test-port reset EMU9 AE18 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected. EMU8 AC17 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected. EMU7 AF17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected. EMU6 AD17 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected. EMU5 AE17 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 AC16 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 AD16 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 AE16 I/O/Z IPU EMU1 AC15 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1# EMU0 AF15 I/O/Z IPU Emulation pin 0# EMUCLK1 AC18 I/O/Z IPU Emulation clock 1. Reserved for future use, leave unconnected. EMUCLK0 AD18 I/O/Z IPU Emulation clock 0. Reserved for future use, leave unconnected. NO. CLOCK/PLL CONFIGURATION CLKIN Clock mode select input (Bypass), * Selects whether the CPU clock frequency = in ut clock frequency x1 (By ass), x6, or x12. For more details on CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply PRODUCT PREVIEW JTAG EMULATION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET NMI GP7/EXT_INT7 AC7 I B4 I Device reset IPD Nonmaskable interrupt, edge-driven (rising edge) AF4 interrupts enGPIO (I/O/Z) or external interru ts (input only). The default after reset setting is GPIO en abled as input-only. GP6/EXT_INT6 AD5 * When these pins function as External Interrupts [by selecting the corresponding interrupt I/O/Z IPU GP5/EXT_INT5 AE5 enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently GP4/EXT_INT4 AF5 selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) PLLV is not part of external voltage supply. See CLOCK/PLL documentation for information on how to connect this pin. A = Analog signal (PLL Filter) # The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k resistor. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION PRODUCT PREVIEW RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED) GP15 G3 GP14 F2 GP13 G4 General-purpose input/output (GPIO) pins. By default, disabled. To enable these pins as GPIO pins, default these pins are disabled pins the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly ro erly configured. g GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: in is an out ut GPx pin output GP12 J3 GP11 F1 GP10 L2 GP9 M3 GP3 AC6 IPD General-purpose input/output (GPIO) pin. The default after reset setting is GPIO enabled as input-only. GP0 AF6 IPD General-purpose input/output (GPIO) pin.The default after reset setting is GPIO enabled as input-only. The GP0 pin (I/O/Z) can be configured as a general-purpose interrupt (GPINT) signal (output only). CLKS2/GP8 AE4 I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be programmed as a GPIO 8 pin (I/O/Z). CLKOUT6/GP2 AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKOUT4/GP1 AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). I/O/Z HOST-PORT INTERFACE (HPI) HINT R4 O Host interrupt (from DSP to host) HCNTL1 R1 I Host control - selects between control, address, or data registers HCNTL0 T4 I Host control - selects between control, address, or data registers HHWIL R3 I Host half-word select - first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] HR/W P1 I Host read or write select HAS T3 I Host address strobe HCS R2 I Host chip select HDS1 T1 I Host data strobe 1 HDS2 T2 I Host data strobe 2 HRDY P4 O Host ready (from DSP to host) HD31 J2 HD30 K3 HD29 J1 HD28 K4 HD27 K2 HD26 L3 HD25 K1 HD24 L4 HD23 L1 Host-port Hostort data * Used for transfer of data,, address,, and control * H Host-Port P b bus width id h iis user-configurable fi bl at d device i reset via i pullup/pulldown ll / lld resistor i on the HD5 pin: I/O/Z . HD5 pin = 0: HPI operates as an HPI16 (HPI b bus iis 16 bit bits wide. id HD[15 HD[15:0] 0] pins i are used d and d th the remaining i i HD[31 HD[31:16] 16] pins i are state ) reserved pins in the high-impedance state.) HD5 pin in = 1: HPI o operates erates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) HD22 M4 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) M2 HD20 N4 HD19 M1 HD18 N5 HD17 N1 HD16 P5 HD15 U4 HD14 U1 HD13 U3 HD12 U2 HD11 V4 HD10 V1 HD9 Host-port Hostort data * Used for transfer of data,, address,, and control * H Host-Port P b bus width id h iis user-configurable fi bl at d device i reset via i pullup/pulldown ll / lld resistor i on the HD5 pin: I/O/Z . V3 HD8 V2 HD7 W2 HD6 W4 HD5 Y1 HD4 Y3 HD3 Y2 HD2 Y4 HD1 AA1 HD0 AA3 HD5 pin = 0: HPI operates as an HPI16 (HPI b bus iis 16 bit bits wide. id HD[15 HD[15:0] 0] pins i are used d and d th the remaining i i HD[31 HD[31:16] 16] pins i are state ) reserved pins in the high-impedance state.) HD5 pin in = 1: HPI o operates erates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) PRODUCT PREVIEW HD21 EMIFA (64-bit) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY|| ACE3 L26 O/Z IPU ACE2 K23 O/Z IPU ACE1 K24 O/Z IPU ACE0 K25 O/Z IPU ABE7 T23 O/Z IPU ABE6 T24 O/Z IPU ABE5 R25 O/Z IPU ABE4 R26 O/Z IPU ABE3 M25 O/Z IPU ABE2 M26 O/Z IPU ABE1 L23 O/Z IPU ABE0 L24 O/Z IPU EMIFA memory space enables * Enabled by bits 28 through 31 of the word address * Only one pin in is asserted during any external data access EMIFA byte byte-enable enable control * Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. memory * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU O IPU EMIFA hold-request-acknowledge to the host DESCRIPTION EMIFA (64-BIT) - BUS ARBITRATION|| AHOLDA N22 AHOLD V23 I IPU EMIFA hold request from the host ABUSREQ P22 O IPU EMIFA bus request output PRODUCT PREVIEW EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL|| AECLKIN H25 I IPD EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins. AECLKIN is the default for the EMIFA input clock. AECLKOUT2 J23 O/Z IPD EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. AECLKOUT1 J26 O/Z IPD EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. AARE/ ASDCAS/ ASADS/ASRE J25 O/Z IPU EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable * For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal. AAOE/ ASDRAS/ ASOE J24 O/Z IPU EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable AAWE/ ASDWE/ ASWE K26 O/Z IPU EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable ASDCKE L25 O/Z IPU EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.] * If SDRAM is not in system, ASDCKE can be used as a general-purpose output. ASOE3 R22 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface) AARDY L22 I IPU Asynchronous memory ready input AEA22 T22 AEA21 V24 AEA20 V25 AEA19 V26 AEA18 U23 AEA17 U24 AEA16 U25 AEA15 U26 AEA14 T25 EMIFA (64-BIT) - ADDRESS|| AEA13 T26 AEA12 R23 AEA11 R24 O/Z IPD EMIFA external address (doubleword address) AEA10 P23 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. 18 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION EMIFA (64-BIT) - ADDRESS (CONTINUED)|| AEA9 P24 AEA8 P26 AEA7 N23 AEA6 N24 AEA5 N26 AEA4 M23 AEA3 M24 O/Z IPD EMIFA external address (doubleword address) EMIFA (64-bit) - DATA|| AF24 AED62 AF23 AED61 AE23 AED60 AE22 AED59 AD22 AED58 AF22 AED57 AD21 AED56 AE21 AED55 AC21 AED54 AF21 AED53 AD20 AED52 AE20 AED51 AC20 AED50 AF20 AED49 AC19 AED48 AD19 AED47 W24 AED46 W23 AED45 Y26 AED44 Y23 AED43 Y25 AED42 Y24 AED41 AA26 AED40 AA23 AED39 AA25 AED38 AA24 AED37 AB26 I/O/Z IPU PRODUCT PREVIEW AED63 EMIFA external data AED36 AB24 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION PRODUCT PREVIEW EMIFA (64-bit) - DATA|| (CONTINUED) AED35 AB25 AED34 AC25 AED33 AC26 AED32 AD26 AED31 C26 AED30 D26 AED29 D25 AED28 E25 AED27 E24 AED26 E26 AED25 F24 AED24 F25 AED23 F23 AED22 F26 AED21 G24 AED20 G25 AED19 G23 AED18 G26 AED17 H23 AED16 H24 AED15 C19 AED14 D19 AED13 A20 AED12 D20 AED11 B20 AED10 C20 AED9 A21 AED8 D21 AED7 B21 AED6 C21 AED5 A22 AED4 C22 AED3 B22 AED2 B23 AED1 A23 I/O/Z IPU EMIFA external data AED0 A24 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION EMIFB (16-bit) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY|| BCE3 A13 O/Z IPU BCE2 C12 O/Z IPU BCE1 B12 O/Z IPU BCE0 A12 O/Z IPU BBE1 D13 O/Z IPU BBE0 C13 O/Z IPU BPDT E12 O/Z IPU EMIFB peripheral data transfer, allows direct transfer between external peripherals EMIFB (16-BIT) - BUS ARBITRATION|| BHOLDA E13 O IPU EMIFB hold-request-acknowledge to the host BHOLD B19 I IPU EMIFB hold request from the host BBUSREQ E14 O IPU EMIFB bus request output EMIFB memory space enables * Enabled by bits 26 through 31 of the word address * Only one pin in is asserted during any external data access EMIFB (16-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL|| BECLKIN A11 I IPD EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins. BECLKIN is the default for the EMIFB input clock. BECLKOUT2 D11 O/Z IPD EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided by 1, 2, or 4. BECLKOUT1 D12 O/Z IPD EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. BARE/ BSDCAS/ BSADS/BSRE A10 O/Z IPU EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable * For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between BSADS and BSRE: If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal. If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal. BAOE/ BSDRAS/ BSOE B11 O/Z IPU EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable BAWE/BSDWE/ BSWE C11 O/Z IPU EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable BSOE3 E15 O/Z IPU EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface) BARDY E11 I IPU EMIFB asynchronous memory ready input I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 PRODUCT PREVIEW EMIFB byte-enable control * Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. memory * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION PRODUCT PREVIEW EMIFB (16-BIT) - ADDRESS|| BEA20 E16 IPU BEA19 D18 IPU BEA18 C18 BEA17 B18 BEA16 A18 BEA15 D17 BEA14 C17 BEA13 B17 BEA12 A17 BEA11 D16 BEA10 C16 BEA9 B16 BEA8 A16 BEA7 D15 BEA6 C15 BEA5 B15 BEA4 A15 BEA3 D14 BEA2 C14 BEA1 A14 I/O/Z IPD EMIFB external address (half-word address) * Also controls initialization of DSP modes at reset via pullup/pulldown ullu / ulldown resistors - Device Endian mode BEA20: BEA20 0 - Big Endian 1 - Little Endian - Boot mode BEA[19:18]: 00 - No boot 01 - HPI boot 10 - EMIFB 8-bit ROM boot with default timings (default mode) 11 - Reserved - EMIF clock select BEA[17:16]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) (AECLKIN SEL[1:0]) 00 - AECLKIN ((default mode)) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved BEA[15:14]: C Clock mode select ffor EMIFB ((BECLKIN_SEL[1:0]) C S ) 00 - BECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate R d 11 - Reserved EMIFB (16-bit) - DATA|| BED15 D7 BED14 B6 BED13 C7 BED12 A6 BED11 D8 BED10 B7 BED9 C8 BED8 A7 BED7 C9 BED6 B8 BED5 D9 BED4 B9 BED3 C10 BED2 A9 BED1 D10 I/O/Z IPU EMIFB external data BED0 B10 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) || The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. 22 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION TIMER 2 TOUT2 A4 O/Z IPD Timer 2 or general-purpose output TINP2 C5 I IPD Timer 2 or general-purpose input TIMER 1 TOUT1 B5 O/Z IPD Timer 1 or general-purpose output TINP1 A5 I IPD Timer 1 or general-purpose input TIMER 0 TOUT0 D6 O/Z IPD Timer 0 or general-purpose output TINP0 C6 I IPD Timer 0 or general-purpose input MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be programmed as a GPIO 8 pin (I/O/Z). CLKR2 AB1 I/O/Z IPD McBSP2 receive clock CLKX2 AC2 I/O/Z IPD McBSP2 transmit clock DR2 AB3 I IPU McBSP2 receive data. Connected to output data pin of other DX2 AA2 O/Z IPU McBSP2 transmit data FSR2 AC1 I/O/Z IPD McBSP2 receive frame sync FSX2 AB2 I/O/Z IPD McBSP2 transmit frame sync PRODUCT PREVIEW AE4 CLKS2/GP8 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 AC8 I CLKR1 AC10 I/O/Z McBSP1 external clock source (as opposed to internal) McBSP1 receive clock CLKX1 AB12 I/O/Z McBSP1 transmit clock DR1 AF11 I McBSP1 receive data DX1 AB11 O/Z McBSP1 transmit data FSR1 AC9 I/O/Z McBSP1 receive frame sync FSX1 AB13 I/O/Z McBSP1 transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 F4 I IPD McBSP0 external clock source (as opposed to internal) CLKR0 D1 I/O/Z IPD McBSP0 receive clock CLKX0 E1 I/O/Z IPD McBSP0 transmit clock DR0 D2 I IPU McBSP0 receive data DX0 E2 O/Z IPU McBSP0 transmit data FSR0 C1 I/O/Z IPD McBSP0 receive frame sync FSX0 E3 I/O/Z IPD McBSP0 transmit frame sync I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 23 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION RESERVED FOR TEST F3 RSV R5 Reserved. This pin in must be externally pulled ulled up u via a 10-k 10 k resistor for proper ro er device operation. G14 H7 RSV N20 Reserved. These pins ins must be connected directly to CVDD for proper ro er device operation. o eration. P7 Y13 RSV R6 Reserved. This pin must be connected directly to DVDD for proper device operation. A3 G2 H3 J4 PRODUCT PREVIEW K6 N3 P3 W3 W25 AA4 AB14 AC11 AC12 AC13 RSV AC14 Reserved (leave unconnected, unconnected do not connect to power or ground) AD1 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AE7 AE8 AE9 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) 24 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION RESERVED FOR TEST AE10 AE11 AE12 AE15 AF3 RSV AF7 Reserved (leave unconnected, do not connect to power ower or ground) AF9 AF10 AF12 AF14 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 25 PRODUCT PREVIEW AF13 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS A2 A25 B1 B14 B26 E7 E8 E10 E17 E19 E20 F9 PRODUCT PREVIEW F12 F15 F18 G5 G22 H5 H22 DVDD J21 S 3 3 V supply voltage 3.3-V K5 K22 L5 M5 M6 M21 N2 P25 R21 T5 U5 U22 V6 V21 W5 W22 Y5 Y22 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) AA9 AA12 AA15 AA18 AB7 AB8 AB10 DVDD AB17 S 3.3-V 3.3 V supply su ly voltage S 1.2-V supply 1.2 V su ly voltage ((-400, 400, -500 500 device sspeeds) eeds) 1.4-V supply voltage (-600 device speed) AB19 AB20 AE1 AE13 PRODUCT PREVIEW AE26 AF2 AF25 A1 A26 B2 B25 C3 C24 D4 D23 E5 E22 F6 F7 CVDD F20 F21 G6 G7 G8 G10 G11 G13 G16 G17 G19 G20 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) G21 H20 K7 K20 L7 L20 N7 P20 T7 T20 U7 U20 PRODUCT PREVIEW W7 W20 Y6 Y7 Y8 Y10 Y11 CVDD Y14 S 1.2-V 1 2 V supply l voltage lt ((-400, 400 -500 500 d device i speeds) d ) 1.4-V 1 4-V supply voltage (-600 device speed) Y16 Y17 Y19 Y20 Y21 AA6 AA7 AA20 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 28 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION GROUND PINS A8 A19 B3 B13 B24 C2 C4 C23 C25 D3 D5 D22 PRODUCT PREVIEW D24 E4 E6 E9 E18 E21 E23 VSS F5 GND Ground pins ins F8 F10 F11 F13 F14 F16 F17 F19 F22 G9 G12 G15 G18 H1 H6 H21 H26 J5 J7 I = Input, O = Output, Z = High iR7mpedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION GROUND PINS (CONTINUED) J20 J22 K21 L6 L21 M7 M20 N6 N21 N25 P2 P6 PRODUCT PREVIEW P21 R7 R20 T6 T21 U6 U21 VSS V5 GND Ground pins ins V7 V20 V22 W1 W6 W21 W26 Y9 Y12 Y15 Y18 AA5 AA8 AA10 AA11 AA13 AA14 AA16 AA17 I = Input, O = Output, Z = High iR7mpedance, S = Supply voltage, GND = Ground 30 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 Terminal Functions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION GROUND PINS (CONTINUED) AA19 AA22 AB4 AB6 AB9 AB18 AB21 AB23 AC3 AC5 VSS AC22 GND Ground pins ins AC24 PRODUCT PREVIEW AD2 AD4 AD23 AD25 AE3 AE14 AE24 AF8 AF19 I = Input, O = Output, Z = High iR7mpedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) PRODUCT PREVIEW The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 DSP family member devices, including documentation. See this document for further information on TMS320 DSP documentation or any TMS320 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies in the industry. To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For device-specific tools, select "Digital Signal Processors", choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLZ), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -600 is 600 MHz). Figure 4 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 PRODUCT PREVIEW Support tool development evolutionary flow: TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 device and development-support tool nomenclature (continued) TMS 320 C 6414 GLZ ( ) 600 PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMX= Experimental device, MIL SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535) DEVICE FAMILY 320 = TMS320t DSP family 100 MHz 120 MHz 150 MHz 167 MHz 400 MHz 500 MHz 600 MHz TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature DEVICE C6000 DSP: 6201 6202 6202B 6203 BGA = 200 MHz 233 MHz 250 MHz 300 MHz PACKAGE TYPE GFN = 256-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt GLZ = 532-pin plastic BGA TECHNOLOGY C = CMOS PRODUCT PREVIEW DEVICE SPEED RANGE 6204 6205 6211 6211B 6701 6711 6711B 6712 6414 6415 6416 Ball Grid Array Figure 4. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6414 Device) MicroStar BGA is a trademark of Texas Instruments. 34 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C6415 Fixed-Point Digital Signal Processor data sheet (literature number SPRS146) describes the features of the TMS320C6415 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device. The TMS320C6416 Fixed-Point Digital Signal Processor data sheet (literature number SPRS164) describes the features of the TMS320C6416 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the How To Begin Development Today with the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718), which describes in more detail the compatibility and similarities/differences among the C6414, C6415, C6416, and C6211 devices. C67x is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 PRODUCT PREVIEW The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, multichannel buffered serial ports (McBSPs), 32-/16-bit host-port interfaces (HPIs), expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); general-purpose timers, general-purpose input/output (GPIO) port, and power-down modes. This guide also includes information on internal data and program memories. TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 clock PLL Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended ranges of suppy voltage and operating case temperature table and the input and output clocks electricals section). Table 5 lists some examples of compatible CLKIN external clock sources: Table 5. Compatible CLKIN External Clock Sources PRODUCT PREVIEW COMPATIBLE PARTS FOR EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER MANUFACTURER JITO-2 Fox Electronix STA series, ST4100 series SaRonix Corporation Oscillators PLL SG-636 Epson America 342 Corning Frequency Control MK1711-S, ICS525-02 Integrated Circuit Systems 3.3V EMI Filter PLLV CLKMODE0 CLKMODE1 C3 10 mF Internal to C6414 PLL PLLMULT C4 0.1 mF PLLCLK CLKIN CLKIN 1 0 CPU CLOCK (For the PLL Options, CLKMODE Pins Setup, and PLL Clock Frequency Ranges see Table 6.) NOTES: A. Place all PLL external components (C3, C4, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 clock PLL (continued) Table 6. TMS320C6414 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time GLZ PACKAGE - 23 x 23 mm BGA CLKMODE1 CLKMODE0 CLKMODE (PLL MULTIPLY FACTORS) CLKIN RANGE (MHz) CPU CLOCK FREQUENCY RANGE (MHz) CLKOUT4 RANGE (MHz) CLKOUT6 RANGE (MHz) TYPICAL LOCK TIME (s) N/A 0 0 Bypass (x1) 30-75 30-75 7.5-18.8 5-12.5 0 1 x6 30-75 180-450 45-112.5 30-75 1 0 x12 30-50 360-600 90-150 60-100 75 PRODUCT PREVIEW 1 1 Reserved - - - - - These clock frequency range values are applicable to a C6414-600 speed device. For -400 and -500 device speed values, see the CLKIN timing requirements table for the specific device speed. Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C6414 device to one of the valid PLL multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail. PRODUCT PREVIEW Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. 38 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 absolute maximum ratings over operating case temperature range (unless otherwise noted) Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 1.16 1.2 1.24 CVDD Supply voltage, Core (-400, -500 device speeds) Supply voltage, Core (-600 device speed) 1.36 1.4 1.44 DVDD Supply voltage, I/O 3.14 3.3 3.46 V VSS VIH Supply ground 0 0 0 V High-level input voltage 2 VIL Low-level input voltage IOL Low level output current Low-level CLKOUT4 and CLKOUT6 except CLKOUT4 and CLKOUT6 CLKOUT4 and CLKOUT6 0.8 V -8 mA -16 mA 8 mA 16 mA TC Operating case temperature 0 90 _C Future variants of the C641x DSPs may operate at voltages ranging from 1.2 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of C641x devices. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) TEST CONDITIONS PARAMETER TYP MAX DVDD = MIN, Low-level output voltage DVDD = MIN, II IOZ Input current VI = VSS to DVDD VO = DVDD or 0 V IDD2V IDD2V Supply current, CPU + CPU memory access Supply current, peripherals CVDD = NOM, CPU clock = 400 MHz TBD mA CVDD = NOM, CPU clock = 400 MHz TBD mA IDD3V Ci Supply current, I/O pins DVDD = NOM, CPU clock = 400 MHz TBD Input capacitance 2.4 UNIT High-level output voltage Off-state output current IOH = MAX IOL = MAX MIN VOH VOL V 0.4 V 150 uA 10 uA mA 10 pF Co Output capacitance 10 pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, refer to the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 39 PRODUCT PREVIEW High level output current High-level V V except CLKOUT4 and CLKOUT6 IOH UNIT TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Vcomm Output Under Test CT IOH Where: IOL IOH Vcomm CT = = = = 2 mA 2 mA 0.8 V 10-15-pF typical load-circuit capacitance PRODUCT PREVIEW Figure 6. Test Load Circuit for AC Timing Measurements signal transition levels All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels. Vref = 1.5 V Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 8. Rise and Fall Transition Time Voltage Reference Levels 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 7 and Figure 9). Figure 9 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 7. IBIS Timing Parameters Example (see Figure 9) DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP setup time requirement 11 Data route delay PRODUCT PREVIEW NO. ECLKOUTx (Output from DSP) 1 ECLKOUTx (Input to External Device) Control Signals (Output from DSP) 2 3 4 5 Control Signals (Input to External Device) 6 7 Data Signals (Output from External Device) 8 10 9 11 Data Signals (Input to DSP) Control signals include data for Writes. Data signals are generated during Reads from an external device. Figure 9. IBIS Input/Output Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN for -400 speed devices (see Figure 10) -400 PLL MODE x12 NO. 1 2 3 PLL MODE x6 x1 (BYPASS) UNIT MIN MAX MIN MAX MIN MAX 30 33.3 15 33.3 13.3 33.3 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C 0.4C 0.45C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.45C ns 4 Transition time, CLKIN 5 The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 5 1 ns ns timing requirements for CLKIN for -500 speed devices (see Figure 10) -500 PLL MODE x12 PRODUCT PREVIEW NO. 1 2 3 4 PLL MODE x6 x1 (BYPASS) UNIT MIN MAX MIN MAX MIN MAX 24 33.3 13.3 33.3 13.3 33.3 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C 0.4C 0.45C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.45C Transition time, CLKIN 5 ns ns ns 5 1 ns The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. timing requirements for CLKIN for -600 speed devices (see Figure 10) -600 PLL MODE x12 NO. 1 2 3 4 PLL MODE x6 x1 (BYPASS) MAX MIN MAX MIN MAX 20 33.3 13.3 33.3 13.3 33.3 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C 0.4C 0.45C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.45C Transition time, CLKIN 5 5 The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 1 4 2 CLKIN 3 4 Figure 10. CLKIN Timing 42 POST OFFICE BOX 1443 UNIT MIN * HOUSTON, TEXAS 77251-1443 ns ns ns 1 ns TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT4 (see Figure 11) NO. -400 -500 -600 PARAMETER UNIT CLKMODE = x1, x6, x12 MIN 1 2 3 4 MAX tc(CKO4) tw(CKO4H) Cycle time, CLKOUT4 4P - 0.7 4P + 0.7 ns Pulse duration, CLKOUT4 high 2P - 0.7 2P + 0.7 ns tw(CKO4L) tt(CKO4) Pulse duration, CLKOUT4 low 2P - 0.7 2P + 0.7 ns 1 ns Transition time, CLKOUT4 1 PRODUCT PREVIEW The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns) 4 2 CLKOUT4 3 4 Figure 11. CLKOUT4 Timing switching characteristics over recommended operating conditions for CLKOUT6 (see Figure 12) NO. -400 -500 -600 PARAMETER UNIT CLKMODE = x1, x6, x12 MIN 1 2 3 4 MAX tc(CKO6) tw(CKO6H) Cycle time, CLKOUT6 6P - 0.7 6P + 0.7 ns Pulse duration, CLKOUT6 high 3P - 0.7 3P + 0.7 ns tw(CKO6L) tt(CKO6) Pulse duration, CLKOUT6 low 3P - 0.7 3P + 0.7 ns 1 ns Transition time, CLKOUT6 The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns) 1 4 2 CLKOUT6 3 4 Figure 12. CLKOUT6 Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN for EMIFA and EMIFB (see Figure 13) -400 -500 -600 NO. 1 2 3 4 UNIT MIN MAX 7.5 16P tc(EKI) tw(EKIH) Cycle time, ECLKIN Pulse duration, ECLKIN high 3.38 tw(EKIL) tt(EKI) Pulse duration, ECLKIN low 3.38 Transition time, ECLKIN ns ns ns 2 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted. 1 4 PRODUCT PREVIEW 2 ECLKIN 3 4 Figure 13. ECLKIN Timing for EMIFA and EMIFB switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and EMIFB modules#|| (see Figure 14) NO. 1 2 3 4 5 6 -400 -500 -600 PARAMETER UNIT MIN MAX E - 0.7 E + 0.7 ns Pulse duration, ECLKOUT1 high EH - 0.7 EH + 0.7 ns Pulse duration, ECLKOUT1 low EL - 0.7 EL + 0.7 ns 1 ns 8 ns tc(EKO1) tw(EKO1H) Cycle time, ECLKOUT1 tw(EKO1L) tt(EKO1) td(EKIH-EKO1H) td(EKIL-EKO1L) Delay time, ECLKIN high to ECLKOUT1 high 3 Delay time, ECLKIN low to ECLKOUT1 low 3 8 Transition time, ECLKOUT1 ns The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. || EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB. 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 INPUT AND OUTPUT CLOCKS (CONTINUED) ECLKIN 6 1 2 5 4 3 4 ECLKOUT1 Figure 14. ECLKOUT1 Timing for EMIFA and EMIFB Modules switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA and EMIFB modules (see Figure 15) PARAMETER MIN 1 2 3 4 5 UNIT MAX tc(EKO2) tw(EKO2H) Cycle time, ECLKOUT2 NE - 0.7 NE + 0.7 ns Pulse duration, ECLKOUT2 high 0.5NE - 0.7 0.5NE + 0.7 ns tw(EKO2L) tt(EKO2) Pulse duration, ECLKOUT2 low 0.5NE - 0.7 0.5NE + 0.7 ns td(EKIH-EKO2H) td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 high Transition time, ECLKOUT2 3 1 ns 8 ns 6 Delay time, ECLKIN high to ECLKOUT2 low 3 8 ns The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. The C64x has two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. N = the EMIF input clock divider; N = 1, 2, or 4. 5 6 ECLKIN 1 2 3 4 4 ECLKOUT2 Figure 15. ECLKOUT2 Timing for the EMIFA and EMIFB Modules POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 PRODUCT PREVIEW NO. -400 -500 -600 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles for EMIFA and EMIFB modules (see Figure 16 and Figure 17) -400 -500 -600 NO. MIN 3 4 6 PRODUCT PREVIEW 7 UNIT MAX tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high 6 ns Hold time, EDx valid after ARE high 1 ns tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, ARDY valid before ECLKOUT1 high 3 ns Hold time, ARDY valid after ECLKOUT1 high 1 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFA and EMIFB modules# (see Figure 16 and Figure 17) NO. -400 -500 -600 PARAMETER MIN 1 UNIT MAX tosu(SELV-AREL) toh(AREH-SELIV) Output setup time, select signals valid to ARE low RS * E - 1.5 Output hold time, ARE high to select signals invalid RH * E - 1.5 td(EKO1H-AREV) tosu(SELV-AWEL) Delay time, ECLKOUT1 high to ARE vaild Output setup time, select signals valid to AWE low WS * E - 1.5 ns Output hold time, AWE high to select signals invalid WH * E - 1.5 ns 10 toh(AWEH-SELIV) td(EKO1H-AWEV) 11 tosu(PDTV-AREL) Output setup time, PDT valid to ARE low RS * E - 1.5 ns 12 toh(AREH-PDTIV) Output hold time, ARE high to PDT invalid RH * E - 1.5 ns 13 tosu(PDTV-AWEV) toh(AWEH-PDTIV) Output setup time, PDT valid to AWE valid WS * E - 1.5 ns Output hold time, AWE high to PDT invalid WS * E - 1.5 2 5 8 9 14 Delay time, ECLKOUT1 high to AWE vaild 1.5 1.5 ns ns 5 5 ns ns ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0]. 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 ECLKOUT1 1 2 CEx 1 2 ABE[7:0] or BBE[1:0] BE 1 2 AEA[22:3] or BEA[20:1] Address 3 4 AED[63:0] or BED[15:0] 1 2 Read Data 5 5 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 7 6 7 6 ARDY 11 12 PDT The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. Figure 16. Asynchronous Memory Read Timing for EMIFA and EMIFB POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 PRODUCT PREVIEW AOE/SDRAS/SOE TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 Not Ready ECLKOUT1 8 9 CEx 8 9 ABE[7:0] or BBE[1:0] BE 8 9 AEA[22:3] or BEA[20:1] Address 8 9 AED[63:0] or BED[15:0] Write Data AOE/SDRAS/SOE PRODUCT PREVIEW ARE/SDCAS/SADS/SRE 10 10 AWE/SDWE/SWE 7 6 7 6 ARDY 13 14 PDT The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). Figure 17. Asynchronous Memory Write Timing for EMIFA and EMIFB 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING timing requirements for programmable synchronous interface cycles for EMIFA and EMIFB modules (see Figure 18) -400 -500 -600 NO. MIN 6 7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high UNIT MAX 2 ns 1.5 ns The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. NO. 1 2 3 4 5 8 9 10 11 12 PARAMETER -400 -500 -600 UNIT MIN MAX 1 5 ns 5 ns td(EKOxH-CEV) td(EKOxH-BEV) Delay time, ECLKOUTx high to CEx valid td(EKOxH-BEIV) td(EKOxH-EAV) Delay time, ECLKOUTx high to BEx invalid td(EKOxH-EAIV) td(EKOxH-ADSV) Delay time, ECLKOUTx high to EAx invalid 1 Delay time, ECLKOUTx high to SADS/SRE valid 1 5 ns td(EKOxH-OEV) td(EKOxH-EDV) Delay time, ECLKOUTx high to, SOE valid 1 5 ns 5 ns td(EKOxH-EDIV) td(EKOxH-WEV) Delay time, ECLKOUTx high to EDx invalid 1 Delay time, ECLKOUTx high to SWE valid 1 Delay time, ECLKOUTx high to BEx valid 1 Delay time, ECLKOUTx high to EAx valid ns 5 Delay time, ECLKOUTx high to EDx valid PRODUCT PREVIEW switching characteristics over recommended operating conditions for programmable synchronous interface cycles for EMIFA and EMIFB modules (see Figure 18-Figure 20) ns ns ns 5 ns 13 td(EKOxH-PDTV) Delay time, ECLKOUTx high to PDT valid 1 5 ns The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) READ latency = 2 ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 2 BE1 3 BE2 BE3 BE4 4 AEA[22:3] or BEA[20:1] EA1 5 EA3 EA2 6 EA4 EA3 7 AED[63:0] or BED[15:0] Q1 Q2 Q3 Q4 8 8 ARE/SDCAS/SADS/SRE PRODUCT PREVIEW 9 9 AOE/SDRAS/SOE AWE/SDWE/SWE 13 13 PDT# The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. # PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. Figure 18. Programmable Synchronous Interface Read Timing for EMIFA and EMIFB (With Read Latency = 2) 50 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 2 BE1 AEA[22:3] or BEA[20:1] 4 EA1 EA2 EA3 EA4 10 Q1 Q2 Q3 Q4 10 AED[63:0] or BED[15:0] ARE/SDCAS/SADS/SRE 3 BE2 BE3 BE4 5 11 8 8 12 12 13 13 AWE/SDWE/SWE PDT# The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. # PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). Figure 19. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write Latency = 0) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 PRODUCT PREVIEW AOE/SDRAS/SOE TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) Write Latency = 1 ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 2 BE1 3 BE2 BE3 BE4 5 4 AEA[22:3] or BEA[20:1] EA1 10 EA2 10 EA3 EA4 Q1 Q2 Q3 AED[63:0] or BED[15:0] 11 Q4 8 8 ARE/SDCAS/SADS/SRE PRODUCT PREVIEW AOE/SDRAS/SOE 12 12 AWE/SDWE/SWE 13 13 PDT# The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. # PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). Figure 20. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write Latency = 1) 52 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles for EMIFA and EMIFB modules (see Figure 21) -400 -500 -600 NO. MIN 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EDx valid before ECLKOUT1 high Hold time, read EDx valid after ECLKOUT1 high UNIT MAX 0.5 ns 2 ns The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. NO. 1 PARAMETER -400 -500 -600 UNIT MIN MAX 1 5 ns 5 ns td(EKO1H-CEV) td(EKO1H-BEV) Delay time, ECLKOUT1 high to CEx valid td(EKO1H-BEIV) td(EKO1H-EAV) Delay time, ECLKOUT1 high to BEx invalid td(EKO1H-EAIV) td(EKO1H-CASV) Delay time, ECLKOUT1 high to EAx invalid 1 Delay time, ECLKOUT1 high to SDCAS valid 1 td(EKO1H-EDV) td(EKO1H-EDIV) Delay time, ECLKOUT1 high to EDx valid Delay time, ECLKOUT1 high to EDx invalid 1 Delay time, ECLKOUT1 high to SDWE valid 1 5 ns 12 td(EKO1H-WEV) td(EKO1H-RAS) Delay time, ECLKOUT1 high to SDRAS valid 1 5 ns 13 td(EKO1H-ACKEV) Delay time, ECLKOUT1 high to ASDCKE valid (EMIFA only) 1 5 ns 2 3 4 5 8 9 10 11 Delay time, ECLKOUT1 high to BEx valid 1 Delay time, ECLKOUT1 high to EAx valid PRODUCT PREVIEW switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFA and EMIFB modules (see Figure 21-Figure 28) ns 5 ns ns 5 ns 5 ns ns 14 td(EKO1H-PDTV) Delay time, ECLKOUT1 high to PDT valid 1 5 ns The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) READ ECLKOUT1 1 1 CEx 2 BE1 ABE[7:0] or BBE[1:0] AEA[22:14] or BEA[20:12] AEA[12:3] or BEA[10:1] 4 Bank 5 4 Column 5 4 3 BE2 BE3 BE4 5 AEA13 or BEA11 6 PRODUCT PREVIEW AED[63:0] or BED[15:0] D1 7 D2 D3 D4 AOE/SDRAS/SOE 8 8 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 14 14 PDT The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. Figure 21. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) WRITE ECLKOUT1 1 2 CEx 2 3 4 ABE[7:0] or BBE[1:0] BE1 4 BE2 BE3 BE4 D2 D3 D4 5 Bank AEA[22:14] or BEA[20:12] 5 4 Column AEA[12:3] or BEA[10:1] 4 5 AEA13 or BEA11 10 9 D1 AOE/SDRAS/SOE 8 8 11 11 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 14 14 PDT The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). Figure 22. SDRAM Write Command for EMIFA and EMIFB POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 55 PRODUCT PREVIEW 9 AED[63:0] or BED[15:0] TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV ECLKOUT1 1 1 CEx ABE[7:0] or BBE[1:0] 4 Bank Activate 5 AEA[22:14] or BEA[20:12] 4 Row Address 5 AEA[12:3] or BEA[10:1] 4 Row Address 5 AEA13 or BEA11 PRODUCT PREVIEW AED[63:0] or BED[15:0] 12 12 AOE/SDRAS/SOE ARE/SDCAS/SADS/SRE AWE/SDWE/SWE The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 23. SDRAM ACTV Command for EMIFA and EMFB 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) DCAB ECLKOUT1 1 1 4 5 12 12 11 11 CEx ABE[7:0] or BBE[1:0] AEA[22:14, 12:3] or BEA[20:12, 10:1] AEA13 or BEA11 AED[63:0] or BED[15:0] AOE/SDRAS/SOE AWE/SDWE/SWE The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 24. SDRAM DCAB Command for EMIFA and EMIFB POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 57 PRODUCT PREVIEW ARE/SDCAS/SADS/SRE TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) DEAC ECLKOUT1 1 1 CEx ABE[7:0] or BBE[1:0] 4 AEA[22:14] or BEA[20:12] 5 Bank AEA[12:3] or BEA[10:1] 4 5 12 12 11 11 AEA13 or BEA11 AED[63:0] or BED[15:0] PRODUCT PREVIEW AOE/SDRAS/SOE ARE/SDCAS/SADS/SRE AWE/SDWE/SWE The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 25. SDRAM DEAC Command for EMIFA and EMIFB 58 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR ECLKOUT1 1 1 12 12 8 8 CEx ABE[7:0] or BBE[1:0] AEA[22:14, 12:3] or BEA[20:12, 10:1] AEA13 or BEA11 AED[63:0] or BED[15:0] ARE/SDCAS/SADS/SRE AWE/SDWE/SWE The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 26. SDRAM REFR Command for EMIFA and EMIFB POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 59 PRODUCT PREVIEW AOE/SDRAS/SOE TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) MRS ECLKOUT1 1 1 4 MRS value 5 12 12 8 8 11 11 CEx ABE[7:0] or BBE[1:0] AEA[22:3] or BEA[20:1] AED[63:0] or BED[15:0] AOE/SDRAS/SOE PRODUCT PREVIEW ARE/SDCAS/SADS/SRE AWE/SDWE/SWE The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 27. SDRAM MRS Command for EMIFA and EMIFB 60 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) TRAS cycles End Self-Refresh Self Refresh AECLKOUT1 ACEx ABE[7:0] AEA[22:14, 12:3] AEA13 AED[63:0] AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE 13 13 ASDCKE The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 28. SDRAM Self-Refresh Timing for EMIFA Only POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 61 PRODUCT PREVIEW AARE/ASDCAS/ASADS/ ASRE TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules (see Figure 29) -400 -500 -600 NO. MIN 3 toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. UNIT MAX E ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles for EMIFA and EMIFB modules (see Figure 29) NO. -400 -500 -600 PARAMETER MIN PRODUCT PREVIEW 1 2 4 5 6 7 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) Delay time, HOLD low to EMIF Bus high impedance td(HOLDH-EMLZ) td(EMLZ-HOLDAH) Delay time, HOLD high to EMIF Bus low impedance td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) Delay time, EMIF Bus high impedance to HOLDA low UNIT 2E MAX ns 0 2E ns 2E 7E ns Delay time, EMIF Bus low impedance to HOLDA high 0 ns Delay time, HOLD low to ECLKOUTx high impedance 2E 2E Delay time, HOLD high to ECLKOUTx low impedance 2E 7E ns ns E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT. For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT. The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 29. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus 1 4 C6414 C6414 ECLKOUTx 6 7 ECLKOUTx For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT. For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT. Figure 29. HOLD/HOLDA Timing for EMIFA and EMIFB 62 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles for EMIFA and EMIFB modules (see Figure 30) NO. 2 PARAMETER td(AEKO1H-ABUSRV) td(BEKO1H-BBUSRV) UNIT MIN MAX Delay time, AECLKOUT1 high to ABUSREQ valid 1 5.5 ns Delay time, BECLKOUT1 high to BBUSREQ valid 1 5.5 ns ECLKOUT1 1 1 2 2 ABUSREQ PRODUCT PREVIEW 1 -400 -500 -600 BBUSREQ Figure 30. BUSREQ Timing for EMIFA and EMIFB POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 63 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 RESET TIMING timing requirements for reset (see Figure 31) -400 -500 -600 NO. MIN MAX Width of the RESET pulse (PLL stable) 10P ns 250 s 4P ns 1 tw(RST) Width of the RESET pulse (PLL needs to sync up) 14 tsu(boot) th(boot) Setup time, boot configuration bits valid before RESET high Hold time, boot configuration bits valid after RESET high ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable. This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. EMIFB address pins BEA[20:13] are the boot configuration pins during device reset. PRODUCT PREVIEW 15 UNIT 4P switching characteristics over recommended operating conditions during reset#|| (see Figure 31) NO. 2 3 4 5 6 7 8 9 10 11 12 13 -400 -500 -600 PARAMETER UNIT MIN MAX td(RSTL-ECKI) td(RSTH-ECKI) Delay time, RESET low to ECLKIN synchronized internally 2E 3P + 20E ns Delay time, RESET high to ECLKIN synchronized internally 2E 3P + 20E ns td(RSTL-ECKO1HZ) td(RSTH-ECKO1V) Delay time, RESET low to ECLKOUT1 high impedance 2E td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) Delay time, RESET low to EMIF Z high impedance td(RSTL-EMIFHIV) td(RSTH-EMIFHV) Delay time, RESET low to EMIF high group invalid td(RSTL-EMIFLIV) td(RSTH-EMIFLV) Delay time, RESET low to EMIF low group invalid td(RSTL-ZHZ) td(RSTH-ZV) Delay time, RESET low to Z group high impedance Delay time, RESET high to ECLKOUT1 valid Delay time, RESET high to EMIF Z valid 3P + 20E ns 2E 2P + 5E ns 16E 3P + 20E ns 2E Delay time, RESET high to EMIF high group valid ns 3P + 20E 2E Delay time, RESET high to EMIF low group valid Delay time, RESET high to Z group valid ns ns 3P + 20E 0 2P ns ns ns 6P ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. || EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Z group consists of: HD[31:0], CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, TOUT0, TOUT1, TOUT2, GP[15:0], HRDY, and HINT. 64 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 RESET TIMING (CONTINUED) CLKOUT4 CLKOUT6 1 RESET 2 3 4 5 6 7 8 9 10 11 ECLKIN ECLKOUT1 ECLKOUT2 EMIF High Group EMIF Low Group 12 13 Z Group 15 14 Boot and Device Configuration Inputs The C64x has two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an "A" and all EMIFB signals are prefixed by a "B". Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted [e.g., ECLKIN, ECLKOUT1, and ECLKOUT2]. EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Z group consists of: HD[31:0], CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, TOUT0, TOUT1, TOUT2, GP[15:0], HRDY, and HINT. If BEA[20:14] and HD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 12, 13, 14, and 15. Boot and Device Configuration Inputs (during reset) include: EMIFB address pins BEA[20:14] and HD5. Figure 31. Reset Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 65 PRODUCT PREVIEW EMIF Z Group TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 32) -400 -500 -600 NO. MIN 1 2 tw(ILOW) tw(IHIGH) MAX Width of the interrupt pulse low 4P ns Width of the interrupt pulse high 4P ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 1 2 EXT_INTx/GPx, NMI PRODUCT PREVIEW Figure 32. External/NMI Interrupt Timing 66 UNIT POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 HOST-PORT INTERFACE (HPI) TIMING timing requirements for host-port interface cycles (see Figure 33 through Figure 40) -400 -500 -600 MIN 1 tsu(SELV-HSTBL) th(HSTBL-SELV) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low tw(HSTBL) tw(HSTBH) UNIT MAX 5 ns 2 ns Pulse duration, HSTROBE low 4P ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low 4P ns 5 ns Hold time, select signals valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 5 ns Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns Setup time, HAS low before HSTROBE low 2 ns 19 Hold time, HAS low after HSTROBE low 2 HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. ns 2 3 4 10 11 12 tsu(SELV-HASL) th(HASL-SELV) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) switching characteristics over recommended operating conditions during host-port interface cycles (see Figure 33 through Figure 40) NO. PARAMETER -400 -500 -600 MIN UNIT MAX Delay time, HCS to HRDY 1 7 ns 6 td(HCS-HRDY) td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 12 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns 8 td(HDV-HRDYL) toh(HSTBH-HDV) Delay time, HD valid to HRDY low 2P - 6 ns 9 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 only) 12 ns 5 Output hold time, HD valid after HSTROBE high 3 ns Delay time, HSTROBE high to HRDY high|| 17 td(HSTBH-HRDYH) 3 12 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after a word (HPI32) or the second half-word (HPI16) of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 67 PRODUCT PREVIEW NO. TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st halfword PRODUCT PREVIEW 5 2nd halfword 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 33. HPI16 Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 6 8 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 34. HPI16 Read Timing (HAS Used) 68 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 14 HSTROBE HCS 12 12 13 13 HD[15:0] (input) 1st halfword 5 17 2nd halfword 5 PRODUCT PREVIEW HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 35. HPI16 Write Timing (HAS Not Used, Tied High) 19 HAS 19 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 5 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 36. HPI16 Write Timing (HAS Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 69 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 2 1 2 HCNTL[1:0] HR/W 3 HSTROBE HCS 7 9 15 HD[31:0] (output) 5 8 17 5 8 17 5 HRDY (case 1) 6 PRODUCT PREVIEW HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 37. HPI32 Read Timing (HAS Not Used, Tied High) 19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 18 3 HSTROBE HCS 7 9 15 HD[31:0] (output) 5 8 17 5 8 17 5 HRDY (case 1) 6 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 38. HPI32 Read Timing (HAS Used) 70 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 2 1 2 HCNTL[1:0] HR/W 3 14 HSTROBE HCS 12 13 HD[31:0] (input) 5 17 5 PRODUCT PREVIEW HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 39. HPI32 Write Timing (HAS Not Used, Tied High) 19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 3 18 14 HSTROBE HCS 12 13 HD[31:0] (input) 5 17 5 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 40. HPI32 Write Timing (HAS Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 71 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING timing requirements for McBSP (see Figure 41) -400 -500 -600 NO. 2 PRODUCT PREVIEW 3 tc(CKRX) tw(CKRX) Cycle time, CLKR/X CLKR/X ext Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 5 tsu(FRH-CKRL) Setup time, time external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, time external FSR high after CLKR low 7 tsu(DRV-CKRL) time DR valid before CLKR low Setup time, 8 th(CKRL-DRV) Hold time, time DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, time external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, time external FSX high after CLKX low MIN 4P CLKR int 0.5tc(CKRX) - 1 9 CLKR ext 1 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0 CLKR int 3 CLKR ext 3 CLKX int 9 CLKX ext 1 CLKX int 6 CLKX ext 3 UNIT MAX ns ns ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 200 MHz (P = 5 ns), use 4P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. 72 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 41) PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 4 10 4P C - 1# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X CLKR/X int 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -1 3 CLKX int -1 3 9 td(CKXH-FXV) Delay time, time CLKX high to internal FSX valid CLKX ext 3 9 -1 4 tdis(CKXH-DXHZ) Disable time, DX high im impedance edance following last data bit from CLKX high CLKX int 12 CLKX ext CLKX int 3 -1+ D1|| 9 4 + D2|| 13 td(CKXH-DXV) Delay time, time CLKX high to DX valid CLKX ext 3 + D1|| 9 + D2|| 14 td(FXH-DXV) ns ns Delay time, FSX high to DX valid FSX int -1 3 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 200 MHz (P = 5 ns), use 4P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. # C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 2P, D2 = 4P POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 73 PRODUCT PREVIEW NO. -400 -500 -600 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 PRODUCT PREVIEW FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) Figure 41. McBSP Timing 74 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 (n-3) TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 42) -400 -500 -600 NO. MIN 2 tsu(FRH-CKSH) th(CKSH-FRH) MAX Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) PRODUCT PREVIEW 1 UNIT Figure 42. FSR Timing When GSYNC = 1 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 75 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 43) -400 -500 -600 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 - 12P ns 5 + 24P ns PRODUCT PREVIEW switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 43) NO. -400 -500 -600 PARAMETER MASTER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T-2 T+3 ns L-2 L+3 ns -2 L-2 MIN 4 12P + 4 MAX 20P + 17 L+3 ns ns 4P + 3 12P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). 76 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 Bit 0 (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 PRODUCT PREVIEW DR (n-2) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 77 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 44) -400 -500 -600 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 - 12P ns 5 + 24P ns PRODUCT PREVIEW switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 44) NO. -400 -500 -600 PARAMETER MASTER MIN UNIT SLAVE MAX MIN MAX 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid -2 4 12P + 4 20P + 17 ns tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low -2 4 12P + 3 20P + 17 ns 1 6 L-2 L+3 ns T-2 T+3 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+4 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 78 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 45) -400 -500 -600 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT SLAVE MIN MAX 2 - 12P ns 5 + 24P ns NO. -400 -500 -600 PARAMETER MASTER MIN 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MAX MIN MAX T-2 T+3 ns H-2 H+3 ns -2 H-2 4 12P + 4 20P + 17 H+3 ns ns 4P + 3 12P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 79 PRODUCT PREVIEW switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 45) TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) PRODUCT PREVIEW Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 80 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 46) -400 -500 -600 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT SLAVE MIN MAX 2 - 12P ns 5 + 24P ns NO. -400 -500 -600 PARAMETER MASTER UNIT SLAVE MIN MAX MIN MAX H-2 H+3 ns T-2 T+1 ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid -2 4 12P + 4 20P + 17 ns tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high -2 4 12P + 3 20P + 17 ns 1 6 7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+4 8P + 2 16P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 81 PRODUCT PREVIEW switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 46) TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) PRODUCT PREVIEW Figure 46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 82 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 TIMER TIMING timing requirements for timer inputs (see Figure 47) -400 -500 -600 NO. MIN 1 2 tw(TINPH) tw(TINPL) UNIT MAX Pulse duration, TINP high 4P ns Pulse duration, TINP low 4P ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. switching characteristics over recommended operating conditions for timer outputs (see Figure 47) PARAMETER MIN 3 4 tw(TOUTH) tw(TOUTL) UNIT MAX Pulse duration, TOUT high 8P - 3 ns Pulse duration, TOUT low 8P - 3 ns PRODUCT PREVIEW NO. -400 -500 -600 P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 TINPx 4 3 TOUTx Figure 47. Timer Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 83 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs (see Figure 48) -400 -500 -600 NO. MIN 1 2 tw(GPIH) tw(GPIL) UNIT MAX Pulse duration, GPIx high 4P ns Pulse duration, GPIx low 4P ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. switching characteristics over recommended operating conditions for GPIO outputs (see Figure 48) NO. -400 -500 -600 PARAMETER PRODUCT PREVIEW MIN 3 4 tw(GPOH) tw(GPOL) MAX Pulse duration, GPOx high 8P - 3 ns Pulse duration, GPOx low 8P - 3 ns P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 GPIx 4 3 GPOx Figure 48. GPIO Port Timing 84 UNIT POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49) -400 -500 -600 NO. MIN 1 UNIT MAX Cycle time, TCK 35 ns 3 tc(TCK) tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 49) 2 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MIN MAX -3 18 PRODUCT PREVIEW NO. -400 -500 -600 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 49. JTAG Test-Port Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 85 TMS320C6414 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS134C - FEBRUARY 2001 - REVISED SEPTEMBER 2001 MECHANICAL DATA GLZ (S-PBGA-N532) PLASTIC BALL GRID ARRAY 23,10 22,90 SQ 20,00 TYP 0,80 0,40 AF AE AD AC AB AA Y 0,80 W V U T R P N M 0,40 L PRODUCT PREVIEW K J H G F E D C B A 1 3 2 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Heat Slug 3,30 MAX 1,00 NOM Seating Plane 0,55 0,45 0,10 M 0,45 0,35 0,12 4201884/B 05/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL) Flip chip application only thermal resistance characteristics (S-PBGA package) NO 1 C/W Air Flow (m/s) RJC RJA Junction-to-case 3.54 N/A Junction-to-free air 16.9 0.00 RJA RJA Junction-to-free air 15.3 0.50 Junction-to-free air 14.0 1.00 5 RJA Junction-to-free air m/s = meters per second 12.9 2.00 2 3 4 86 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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