=> a CY7C387A PRELIMINARY CY7C388A Very High Speed 8K (24K) Gate CMOS FPGA Features 16-bit counter operating at 100 132 (7C387A) to 172 (7C388A) bidi- Very high a MHz consumes 50 mA rectional input/output pins very ign spee . Minimum Ioz of 12 mA andIon of 6 dedicated input/high-drive pins Loadable counter frequencies 8mA : . greater than 100 MHz | . 2clock/dedicated input pins with fan- . . . . Flexible logic cell architecture out-independent, low-skew nets Chip-to-chip operating frequencies . : . up to 85 MHz Wide fan-in (up to 14 input gates) Clock skew <1 ns Input + logic cell + output delays Multiple outputs in each cell * Input hysteresis provides high noise under 7 ns Very low cell propagation delay immunity Unparalleled FPGA performance for (1.7 ns) Thorough testability counters, data path, state machines, Powerful design toolsWarp3 Built-in scan path permits 100 per- arithmetic, and random logic Designs entered in VHDL, cent factory testing of logic and 1/O High usable density schematics, or mixed cells 24 x 32 array of 768 logic cells pro- Fast, fully automatic place and Automatic Test Vector Generation vides 24,000 total available gates route (ATVG) software supports user 8,000 typically usable gate array Waveform simulation with back an- testing after p rogramnmnng ; gates in 145-pin and 245-pin notated net delays 0.65y. CMOS process with ViaLink CPGA, 144-pin TQFP, 208-pin PC and workstation platforms programming technology BOA bashanes CQFP, and 225-pin Robust routing resources High-speed metal-to-metal link PCI compliant /O pins Fully automatic place and route of Non-volatile antifuse technology designs using up to 100 percent of 144-pin TQFP, 145-pin CPGA, and Low power, high output drive logic resources 160-pin CQFP are pin compatible Standby current typically 2 mA No hand routing required with the CY7C386A Logic Block Diagram PeVerereereee eee r errr ere ere ee oe ee : (O[o[o]o[o/o/ofo[ofofojofolfofololololololofofofojojfojfojojojojojo) s : (Golo/o[o[ofejofofolofojojofolfofejofolo[o[ol[olofofololojofojola] s sj ,o}o/o}ofofolojojojofolololofofofofolofo[ofojajojololgjolololg] = = /O/HIGH-DRIVE INPUT/ + Qolojofolafojofolofojojojaljaja/ofofolalofofojajofofoyY ojofo[o]: CLOCK CELLS : jofojofojoljojolojojafolajololofofofofolololofolojojofzZ, Sololol: {ofofo[olofofolofofofofofojolojofo[ofo[olojo[ololojajoy lefafol: = (o[olofolo/o/o/ofofofolofojolfofojo[ofo[ololofolfolniofo! plotoiol: : (Q[o[o[olo[ofolo[ofofolofolol[o[ojo[ofojo[ofolfojo \ : (2[olo[o[olol[olololofo[ofofo[ofojfajolojololololo SER PES * (ofolo|c|olo[ololofofofojololo[ofofo[olofofo[ojo See Set oe 5 -{Oololofolojafolojofalo[alolajofofolololofolofo See > (Olojo[olofololofojololofojololololole[olofojofey grrr 2 (O(Olofololololofofolofojafojafofojofajolfalofojo 4 ra : Ofofofolololo[olofofofolfololo[ofolol[olofolofolo qt Le = {Ofofofololofoelofo[ofololal[ofojofolofojololofofo J +o/ojofofofo[o[olofofolofofalojololo[ol[o[o[ofofo 33 s (Ofofojofofol[ololojololofololojolal[o[ol[o[o[ofo[o oe J (ofolofololololofofofolofololalolofofofololololoyy se: + |O/ofofofololojofofofolofofofofofelo[ojolofofolfoly = : (Ofalofofajofojofofofajofajolejo[ololelolofojojo : (Ofo/o]o[o[olojofofofojolofolofofofofolfofofofojofo 2 (oofofololojojofalojololalololofal[o[ololofojofolofalalojolojolols 2(O/ofo/ofolojojolofojolofojolojojojo[ololololofololaja[ojofofojols : (O]olo[ofololofjojojojojol[ojojojofojajojojolofojoljojal[olol[olojofal: 7C387A-1 144 and 208 PINS, 172 I/O CELLS, 6 INPUT HIGH DRIVE CELLS, 2 INPUT/CLK (HIGH DRIVE) CELLS ViaLink and pASIC are trademarks of QuickLogic Corporation. Warp3 is a trademark of Cypress Semiconductor Corporation. MB 2589662 0013257 THSCY7C387A PRELIMINARY CY7C388A = CYPRESS Functional Description The CY7C387A and CY7C388A are very high speed, CMOS, user-programmable ASIC (pASIC ) devices. The 768 logic cell field-programmable gate array (FPGA) offers 8,000 typically us- able gate array gates. This is equivalent to 24,000 EPLD or LCA gates. The CY7C387A is available in a 145-pin CPGA, 160-pin COFP, and 144-pin TOFP. The CY7C388A is available in 208-pin POFP, 245-pin CPGA, and 225-pin BGA packages. Low-impedance, metal-to-metal ViaLink interconnect technology provides non-volatile custom logic capable of operating at speeds above 150 MHz with input and output delays under 3 ns. This per- mits high-density programmable devices to be used with todays fastest CISC and RISC microprocessors. Designs are entered into the CY7C387A and CY7C388A using Cypress Warp3 software or one of several third-party tools. Warp3 is a sophisticated CAE package that features schematic entry, wa- veform-based timing simulation, and VHDL design synthesis. The CY7C387A and CY7C388A feature ample on-chip routing chan- nels for fast, fully automatic place and route of high gate utilization designs. For detailed information about the pASIC380 architecture, see the pASIC380 Family datasheet. Pin Configurations 144-Pin Thin Quad Flat Pack (TQFP) Top View esgegoeseSoeoogse Seong Seg e8e2geee9 eg#eggegegs 144 143 142 141 140 139138137 136 135134 133 132131 130 129 128 127 126 125124 123122 121120 119 148117 116 415 114 113142 111 116 109 3 ON On oN = 7C387A SBREBRAESBBNRSREBSR 97 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52.53 54 56 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105. 104 103 402 401 SSSFESBSIS SSFS FF F538 UUUUULU UUW UU UYU UU AN AAAPASSR SLR RIBAS LSREKRIB BB SSSsssg 555 gggeeeg 3 ggeegeeeegeggece TCR87A-2 4-46 Me 2589bbe 0013258 34]=e PRELIMINARY CY7C387A CY7C388A SS? CYPRESS Pin Configurations (continued) 208-Pin Plastic Quad Flat Pack (PQFP) Top View Yss 40 vO yO YO Vss gee vo Yo RR yo 1 vo vo 2 4O vo 3 rs) vO 4 yO vo 5 3) vo 6 vo vO 7 vO vO 8 vo vo 9 vO Veo 10 Veg Vss Veo vo yo vo vo vo vo ie} vO vO yo vo yo vO vo vo vo vo vo vO vo vo vo Vg Voc vo ' I 1 VCLK Vee Veo VCLK \ I t vO Voc Vss vo vo vo vo vo vo vo vo vo VO vo is) vO yo vo yo yo vo vo yo yo vo Veo Vss Vgs Voc vO vO vo vo yo vo vo yo vo yo vo vo vo vo vo vo vo vo SOLLOLNSHLLISLeg ggg ogg gee gegeg gegesggggg seggysgesegegg > > > 7C387A-3 4-47 MB 2585662 0013259 416aes CY7C387A ==. PRELIMINARY CY7C388A & CYPRESS Pin Configurations (continued) 160-Pin CQFP Top View ese8ggaggagge98e8 gggegegeegeregegegegegegeesoeese g AMIOMAAONAANA ANIA AATINAOOMNNNAAANAAN 160 189 188 187 156 155164153152 151150 149 148147146 145 144 143 142 141 140 199138 137136 195 134133 132 191 190 129 128 127 126 125 124 123 122 121 wo CS 1 120 vo CJ 2 119 OC) 3 11a vo (7) 4 117 vO (T= 5 116 vO C>[] 6 115 vol 7 114 vec =] 8 113 vo[_] 9 412 vo CE=| 10 1 vo C1 1140 vo (TF 12 109 vo Tl] 13 108 vo] 14 107 vo (7 15 106 vo C7] 16 105 Vss Co] 17 104 vo 7] 18 103 1] 1 7CR87A 102 vcLK [a] 20 101 Veo Co at 100 C=] 2 99 (Coa 23 98 Voc Li 24 97 vo (J 25 96 vo (Co) 26 95 vo Lj 2 os vo Lo] 2s es WL] 29 2 wo Cl 20 31 voC at 20 wT 2 39 Vss To] 33 88 vo CI] a4 87 vo [=] 35 86 vo CT] 2s a5 vo] a7 a4 vo C] 2s 3 vO [=] 39 a2 vO T=] 40 ai 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 UUUUUUUUUUU UU UU UUU UU HTT Er ett ttt ttt MB 2589bbe 0013e60 S3T yo vo VCLK vo vo yo vis) vo vo vo Veo yO vo 4O vo yo vo yoCY7C387A Se CYPRESS PRELIMINARY CY7C388A Pin Configurations (continued) 145-Pin CPGA Bottom View vo yo vo vo vo vO vo ie) vo yo yo vo vO vo oO 1 vo vo vO vO vo vo vO ie) vo vO vo vO vo vo vO 2 vo VO | Vss | VO | Voc | VO } Vss | VO | Veo | VO Vss vO Vec vo vO 3 vo | vo | vo a vo | vo | Vo 4 vo | WO | Veco Vsg } v0 vo 5 vo | vo | vo vo vO vO 6 1 1 Vss Veo | VO vo 7 vo 1 | VCLK 70387A VCLK I vo 8 vo | vO | Voc Vss \ I 8 vo | vo | vo vo vo vo |} 10 vo [ VO | Vss Veco | vo | vo | 1 vo 7 vo } VO vo | Vo vo | 12 VO | VO | Veg | VO | Vgg | VO | Veg | VO P Vss | WO | Voc | VO | Vss vo vo | 13 vO Vo VO yo va vO VO vO [| VO Vo VO yo vo vo yo 14 ie) vo vO yo vO vo yo Yo vO vo vo yO vo VO vo 1s 7C387A-5 MB 2589662 0013261 476 =CY7C387A =a: PRELIMINARY CY7C388A ss CYPRESS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Latch-Up Current ............ 0.50. s seer sees +200 mA not tested.) Storage Temperature Operating Range Ceramic ..... eee eee eee eee -65C to +150C Ambient Plastic 00... 0... cece eee ners eee eee 40C to +125C ren Lead T 300C Range Temperature Vec ead Temperature .... eee eee eee reece eee Commercial 0C to +70C 5V 5% Supply Voltage ....... 0... cece eee eee 0.5V to +7.0V - Input Voltage 2220... ... cece eee eee 0.5V to Vcc +0.5V Industrial 40C to +85C SV = 10% ESD Pad Protection ..... 6... cece eee e ee eee eee nen +2000 V Military 55C to +125C 5V + 10% DC Input Voltage .. 0... ccc eee eee ee 0.5V to 7.0V Delay Factor (K) Speed Military Industrial Commercial Grade Min. Max. Min. Max. Min. Max. -0 0.39 1.82 0.4 1.67 0.46 1.55 -1 0.39 1.56 0.4 1.43 0.46 133 -2 0.4 1.35 0.46 1.25 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Vou Output HIGH Voltage Toy = 4.0mA 3.7 Vv Ion = 8.0mA 2.4 Vv Toy = ~ 10.0 vA Vee 0.1 Vv VoL Output LOW Voltage Jo_ = 8.0 mA Military/Industrial 0.4 Vv Io_ = 12 mA Commercial Io = 10.0 pA 0.1 Vv Vin Input HIGH Voltage 2.0 Vv Vit Input LOW Voltage 0.8 Vv I Input Leakage Current Vin = Vec or Vss -10 +10 pA loz Three-State Output Leakage Current | Vin = Vcc or Vss ~10 +10 pA Tos Output Short Circuit Current Vout = Vss -10 -80 mA Vout =Vcc 30 140 mA Icc Standby Supply Current Vin; Vyo = Voc or Vss 10 mA Capacitance Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF Vec = 5.0V Cout Output Capacitance cc 10 pF 4-50 M8 2589bbe 00L32be 30c= CY7C387A + R Y A. SBD 7 Cypress PRELIMINARY CY7C388 Switching Characteristics Over the Operating Range Propagation Delays!!] with Fanout of Parameter Description 1 2 3 4 8 Unit LOGIC CELLS tpp Combinatorial Delayl4] 1.7 2.2 2.6 3.2 53 ns tsu Set-Up Timel?} 21 21 21 21 2.1 ns ty Hold Time 0.0 0.0 0.0 0.0 0.0 ns tcLK Clock to Q Delay 1.0 15 1.9 2.6 47 ns tcwHI Clock HIGH Time 2.0 2.0 2.0 2.0 2.0 ns tcWLo Clock LOW Time 2.0 2.0 2.0 2.0 2.0 ns tsET Set Delay 17 2.2 2.6 3.2 5.3 ns tRESET Reset Delay 15 19 2.2 2.7 44 ns tsw Set Width 19 19 1.9 1.9 19 ns trw Reset Width 18 18 18 18 18 ns Propagation Delays!!! with Fanout of Parameter Description 1 2 3 4 8 12 Unit INPUT CELLS tin Input Delay (HIGH Drive) 2.8 29 3.0 3.1 4.0 5.3 ns tin Input, Inverting Delay (HIGH Drive) 3.0 3.1 3.2 3.3 41 5.7 ns tio Input Delay (Bidirectional Pad) 14 19 2.2 2.2 4.7 6.5 ns tock Clock Buffer Delayl3] 2.7 28 2.9 3.0 3.1 33 ns tGCKHI Clock Buffer Min. HIGHU] 2.0 2.0 2.0 2.0 2.0 2.0 ns tGCKLO Clock Buffer Min. LOWL] 2.0 2.0 2.0 2.0 2.0 2.0 ns Propagation Delays!!) with Output Load Capacitance (pF) of Parameter Description 30 50 75 100 150 Unit OUTPUT CELLS touTLH Output Delay LOW to HIGH 2.7 3.4 42 5.0 6.7 ns touTHL Output Delay HIGH to LOW 28 3.7 47 5.6 7.6 ns tpzH Output Delay Three-State to HIGH 4.0 4.9 6.1 73 9.7 ns tezL Output Delay Three-State to LOW 3.6 4.2 5.0 5.8 73 ns teraz. Output Delay HIGH to Three-Statel4] 2.9 ns tpLz Output Delay LOW to Three-Statel4l 3.3 nis Notes: 1. Worst-case propagation delay times over process variation at Vcc = 3. Clock buffer fanout refers to the maximum number of flip-flops per 5.0V and Ta = 25C. Multiply by the appropriate delay factor, K, for haif column. The number of half columns used does not affect clock speed grade to get worst-case parameters over full Vcc and tempera- buffer delay. ture range as specified in the operating range. Allinputsare TTLwith 4. The following loads are used for tpxz: 3-ns linear transition time between 0 and 3 volts. 2. These limits are derived from worst-case values for a representative selection of the slowest paths through the pASIC logic cell including +ka 5 oF tke net delays. Guaranteed delay values for specific paths should be deter- p mined from simulation results. I tpHz SPF== tpiz 4-51 MB 2549bb2 0013263 245= CY7C387A == CYPRESS PRELIMINARY CY7C388A High Drive Buffer # High Drives Propagation Delays!) with Fanout of ire Parameter Description Together 12 24 48 72 96 Unit tIN High Drive Input Delay 1 5.3 6.7 ns 2 45 6.6 ns 3 53 6.2 7.2 ns 4 5.4 6.2 ns tint High Drive Input, Inverting Delay 1 5.7 7.2 ns 2 4.6 6.8 ns 3 5.5 6.4 7A ns 4 5.6 6.4 ns Switching Waveforms Combinatorial Delay INPUT I tep | OUTPUT K 7C387A-6 Set-Up and Hold Times D tsu >*_ ty town + tcwLo | CLOCK YY * tek Q 70987A-7 Set and Reset Delays SET + _______Y tsw | tser Qa x RESET rh tw ST 1 tReseT Q TC387A-8 Output Delay tourLy touTHL OUTPUT f NI 7C3B7A-9 ME 2586%bbe 0013264 165= CY7C387A Se 2 CYPRESS PRELIMINARY CY7C388A S> Switching Waveforms (continued) OUTPUT BUFFER ENABLE OUTPUT Ky Ky Three-State Delay THREE-STATE THREE-STATE THREE-STATE 7CO387A-10 Typical AC Characteristics Propagation delays depend on routing, fanout, load capacitance, Factor table. The effects of voltage and temperature variation are supply voltage, junction temperature, and process variation. The __ illustrated in the graphs below. Warp3 incorporates datasheet AC AC Characteristics are a design guide to provide initial timing esti- Characteristics into the design database for preplace-and-route mates at nominal conditions. Worst-case estimates are obtained _ simulations. The Warp3 Delay Modeler extracts specific timing pa- when nominal propagation delays are multiplied by the appropri- rameters for precise simulation results following place and route, ate Delay Factor, K, as specified by the speed grade in the Delay VOLTAGE FACTOR (Ky) VERSUS SUPPLY VOLTAGE (Vcc) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 4.50 4.76 5.00 5.25 5.50 7C387A-11 SUPPLY VOLTAGE, Voc (Volts) | TEMPERATURE FACTOR (Ky) VERSUS TEMPERATURE 1.30 1.25 1.20 1.15 1.05 1.00 0.95 0.90 0.85 0.80 -60 40 20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (C) 7CasTh.12 *THETA JA = 45 C/WATT FOR PLCC MB 2S4%bbe 00343265 O11nn = CY7C387A =, CYPRESS PRELIMINARY CY7C388A Combinatorial Delay Example (Load = 30 pF) tio tep tour 1.4ns } 1.7 ns >t 2.8 ns +| IN > ; > OUT IN2 > 7C387A-13 INPUT DELAY + COMBINATORIAL DELAY + OUTPUT DELAY = 5.9 ns Sequential Delay Example (Load = 30 pF) tio tsu tek tout |~<_- 1.4ns f 2.1ns | 1.0ns |__ 2.8 ns >| IN1 Ee PS OUT > le CLK > 7OS87A-14 INPUT DELAY + REG SET-UP + CLOCK TO OUTPUT + OUTPUT DELAY = 7.3 ns MB 254%bbe O013cbb T5h=>. CY7C387A =7 CYPRESS PRELIMINARY CY7C388A Ordering Information Speed Package Operating Grade Ordering Code Name Package Type Range 2 CY7C387A-2AC Al44 144-Pin Thin Quad Flat Pack Commercial CY7C387A-2GC G145 145-Pin Grid Array (Cavity Up) CY7C387A2Al A144 144-Pin Thin Quad Flat Pack Industrial CY7C387A-2GI1 G145 145-Pin Grid Array (Cavity Up) 1 CY7C387A-1AC Ald4 144-Pin Thin Quad Flat Pack Commercial CY7C387A-1GC G145 145-Pin Grid Array (Cavity Up) CY7C387A-1AI Al44 144-Pin Thin Quad Flat Pack Industrial CY7C387A1GI G145 145-Pin Grid Array (Cavity Up) CY7C387A-1GMB G145 145-Pin Grid Array (Cavity Up) Military CY7C387A1UMB U162 160-Lead Ceramic Quad Flatpack (Cavity Up) 0. CY7C387A0AC Al44 144-Pin Thin Quad Flat Pack Commercial CY7C387A-0GC G145 145-Pin Grid Array (Cavity Up) CY7C387AOAI Al44 144-Pin Thin Quad Flat Pack Industrial CY7C387A0GI G145 145-Pin Grid Array (Cavity Up) CY7C387A-0GMB G145 145-Pin Grid Array (Cavity Up) Military CY7C387A0UMB U162 160-Lead Ceramic Quad Flatpack (Cavity Up) Speed Package Operating Grade Ordering Code Name Package Type Range 2 CY7C388A2AC A208 208-Pin Thin Quad Flat Pack Commercial CY7C388A~2BGC B225 225-Pin Ball Grid Array CY7C388A2GC G245 245-Pin Grid Array (Cavity Up) CY7C388A 2AI A208 208-Pin Thin Quad Flat Pack Industrial CY7C388A2GI G245 245-Pin Grid Array (Cavity Up) 1 CY7C388A-1AC A208 208-Pin Thin Quad Flat Pack Commercial CY7C388A1BGC B225 225-Pin Ball Grid Array CY7C388A -1GC G245 245-Pin Grid Array (Cavity Up) CY7C388A-1AI A208 208-Pin Thin Quad Flat Pack Industrial CY7C388A-1GI G245 245-Pin Grid Array (Cavity Up) CY7C388A1GMB G245 245-Pin Grid Array (Cavity Up) Military 0 CY7C388A-0AC A208 208-Pin Thin Quad Flat Pack Commercial CY7C388A0BGC B225 225-Pin Ball Grid Array CY7C388A-0GC G245 245-Pin Grid Array (Cavity Up) CY7C388A0AI A208 208-Pin Thin Quad Flat Pack Industrial CY7C388A0GI G245 245-Pin Grid Array (Cavity Up) CY7C388A -0OGMB G245 245-Pin Grid Array (Cavity Up) Military Shaded area contains advanced information. Military Specifications Group A Subgroup Testing DC Characteristics Parameters Subgroups Vou 1,2,3 VoL 1, 2,3 Ioz 1, 2,3 Icci 1, 2,3 Document #: 3800373 M 258%bb2 0013267 994 omFeatures @ Very high speed Loadable counter frequencies greater than 100 MHz Chip-to-chip operating frequencies up to 85 MHz Input + logic cell + output delays under 7 ns Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic High usable density 32 x 36 array of 1152 logic cells provides 36,000 total available gates 12,000 typically usable gate array gates in 208-pin PQFR, 313-pin BGA, and 245-pin CQFP ADVANCED INFORMATION CY7C389A Very High Speed 12K (36K) Gate CMOS FPGA Low power, high output drive Standby current typically 2 mA 16-bit counter operating at 100 MHz consumes 50 Minimum Io, and Ioq of 8 mA Flexible logic cell architecture Wide fan-in (up to 14 input gates) Multiple outputs in each cell Very low cell propagation delay (1.7 ns) PCI compliant I/O pins Powerful design toolsWarp3 Designs entered in VHDL, schematics, or both Fast, fully automatic place and route Waveform simulation with back PC and workstation platforms Robust routing resources Fully automatic place and route of desigus using up to 100 percent of logic resources No hand routing required Input hysteresis provides high noise immunity Thorough testability Built-in scan path permits 100 percent factory testing of logic and 1/0 cells Automatic Test Vector Generation (ATVG) software supports user testing after programming 0.65u CMOS process with ViaLink programming technology High-speed metal-to-metal link packages annotated net delays Non-volatile antifuse technology Logic Block Diagram cence ees pees ceeee sen Be eS SSPE SEES OS Soe es Eee oe Oe ES es EP esesEs a Blo}ojofolojajo]* ofo}ojofalojolo]* DjojofA~jalafa[o]* BlojoY \ojo[ofo}" olojd, -xYolola}* Dlojoy jojofofo}: ololo} ololoini= raga as ba OO/O/OOsajojojolo|ojojojojoyajojojojojojojojojo/ojajojojojo oO,OO/o/O/0jO/O;a/oOj;oO/ojo/osoOjoOlojolojo;ojojojajojoo/ojojojoja goo o/oO,0/oOjojo/oOjaoOjooOjojolajojojojajojojojojoyjojojojojojo O,OJO/O,OjojO/O/ajojajojoOlosojojojojojojoajajojojyojojoajoajojojoja OVOO/BID/DJOjOjOJO/O/OjO[Os/ajojojajojojojojojojojojojajojojaja goOo/O/ojojojojajojo/ojojolojojojajojojojojojojojolojojojojoja OOo o/o/OjO/oOjoO/oojoololajojojolajojojojojajojojojajojojoja OJOfA/G[D[DjoOjOjOjO|O/OjO/Osajojojojojosojojojojojojojayojojoja gjojo|o/o|oojofjojojojojololojojojojajojojojojojojojojajojojojo OOjO/o/oOOjojoOjoOjojoojololojojojojojojyajojojojojolojajojojoja O,OJO/Osoj/OsoOjOfojojasojOloOojojosojajojojojojojojojojojojojajo OVOO/O/O/OjOjOjOjoO|a/OjoOjOsoalojajojolajojo|ojojojojojajoja qj qjajojoloyojojojojojolojoyojosajojoyojojojojojojojojojojojoja OOO oO Ojo ;oO;OjoOasoyoloOajojasojojojojojojoyojojojajojojojo O|O/DO/O/O/O/O/O/O/OjOjO/Osojojojolojojajojojajojofojafojajojoa OOOO C/O O/O/oO/ojo/osoOloyojoyojojojoojojojajojojojajojojoja OOO OOO oOo OoO/oOjojofojojojofojojojojojojo|ojojojajojojoja gojo/o/oO/Ofojojo;ojajololojojojojojo[ojojojoljojojofosjajojojojo O,OJO/O/O/OjOjojoo;ojo;o|ojajojofojofojojojojojojolojafojojoja OJO/O/O/OfO/ajojajojajojojojojojojajojojojojojojojojojajojojoja g|ojo/O/o/oojo/o/ojo/ojolojojolajojojojojojojajojolojoajolojojo OO/O/O/o/O;O/O/O/O/o/O/oOlofoyojojolajojajojajoljojojojajojojojo OFOO/GlOjOsOjyOsAjOsajOyO/O/ojojojojojojojojojojyojojojojojojoja OOo O/O/0jojo;o/oO/o/oO/o[o/ojoyalojojojojojajolojojojojojojojo OOOO C/O/GjO/oO/OjOjOpo olayasjojojojojojojajajojojojajojajoja OOO O/o/oOfojo/o/o;ojojO[olojoyojolojo;ojojojojojoo/ajojojo\ja OOo oO /O/ofoO/o/oO/O/oO/ojojojojojojoljofso;o|ojo|ojojojo/ajojojoja OOO O/O/0f/OjO/oO/O;O/OsoOj oO oojajolojolojaojajajojolojajojojojoa a ojojojojofojola]" Qjojofojojojojoj* olofojojofojalo}* ofojofojolfojafo}* I0389A4 ojofolofojojofo}* ofofolofofojofa): ofofojalojoljojal: ojofojolojajojo}* Ofololofajaajo! ss /O/HIGH-DRIVE O/D/ojojofa[o[o|* INPUT/GLOCK CELLS a Bjo[ofofojo[ofo}* BEES BRE CERES SETTER RR RRA RSRRRERE ERE SHRED EET ES ESE GE SR ERS REE RHBAseeee 313 PINS, 242 I/O CELLS, 6 INPUT HIGH DRIVE CELLS, 2 INPUT/CLK (HIGH DRIVE) CELLS ViaLink is a trademark of QuickLogic Corporation. Warp3 is a trademark of Cypress Semiconductor Corporation. 4-56 MB 258%9bbe 0013264 620