Macronix Proprietary
MX25U25645G 54
MX25U25645G 54
1.8V, 256M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• 4-Byte Address Mode permanent
• Quad I/O mode is permanently enabled
• Default 10 Dummy Cycle
• Support DTR (Double Transfer Rate) Mode
• 8/16/32/64 byte Wrap-Around Read Mode
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Contents
1. FEATURES ..............................................................................................................................................................5
2. GENERAL DESCRIPTION ..................................................................................................................................... 6
Table 1. Read performance Comparison ....................................................................................................6
3. PIN CONFIGURATIONS ......................................................................................................................................... 7
Table 2. PIN DESCRIPTION .......................................................................................................................7
4. BLOCK DIAGRAM ................................................................................................................................................... 8
5. MEMORY ORGANIZATION ..................................................................................................................................... 9
6. DATA PROTECTION .............................................................................................................................................. 10
6-1. Block lock protection .................................................................................................................................11
Table 3. Protected Area Sizes ................................................................................................................... 11
6-2. Additional 8K-bit secured OTP ................................................................................................................ 12
Table 4. 8K-bit Secured OTP Denition ....................................................................................................12
7. DEVICE OPERATION ............................................................................................................................................ 13
7-1. 256Mb Address Protocol .......................................................................................................................... 16
7-2. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 16
8. COMMAND SET .................................................................................................................................................... 17
Table 5. Read/Write Array Commands ...................................................................................................... 17
Table 6. Register/Setting Commands ........................................................................................................18
Table 7. ID/Security Commands ................................................................................................................19
Table 8. Reset Commands ........................................................................................................................ 20
9. REGISTER DESCRIPTION .................................................................................................................................... 21
9-1. Status Register ........................................................................................................................................ 21
9-2. Conguration Register ............................................................................................................................. 22
9-3. Security Register ..................................................................................................................................... 24
Table 9. Security Register Denition .........................................................................................................24
10. COMMAND DESCRIPTION ................................................................................................................................. 25
10-1. Write Enable (WREN) .............................................................................................................................. 25
10-2. Write Disable (WRDI) ............................................................................................................................... 26
10-3. Read Identication (RDID) ....................................................................................................................... 27
10-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 28
10-5. Read Electronic Manufacturer ID & Device ID (REMS) ........................................................................... 30
10-6. QPI ID Read (QPIID) ............................................................................................................................... 31
Table 10. ID Denitions ............................................................................................................................31
10-7. Read Status Register (RDSR) ................................................................................................................. 32
10-8. Read Conguration Register (RDCR) ...................................................................................................... 33
10-9. Write Status Register (WRSR) ................................................................................................................. 36
Table 11. Protection Modes ....................................................................................................................... 37
10-10. Read Data Bytes (READ) ........................................................................................................................ 39
10-11. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 40
10-12. Dual Output Read Mode (DREAD) .......................................................................................................... 41
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MX25U25645G 54
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Macronix Proprietary
P/N: PM2619
10-13. 2 x I/O Read Mode (2READ) ................................................................................................................... 42
10-14. Quad Read Mode (QREAD) .................................................................................................................... 43
10-15. 4 x I/O Read Mode (4READ) ................................................................................................................... 44
10-16. 4 x I/O Double Transfer Rate Read Mode (4DTRD) ................................................................................ 46
10-17. Preamble Bit ........................................................................................................................................... 48
10-18. Performance Enhance Mode ................................................................................................................... 52
10-19. Burst Read ............................................................................................................................................... 57
10-20. Fast Boot ................................................................................................................................................. 58
10-21. Sector Erase (SE) .................................................................................................................................... 61
10-22. Block Erase (BE32K) ............................................................................................................................... 62
10-23. Block Erase (BE) ..................................................................................................................................... 63
10-24. Chip Erase (CE) ....................................................................................................................................... 64
10-25. Page Program (PP) ................................................................................................................................. 65
10-26. 4 x I/O Page Program (4PP) .................................................................................................................... 67
10-27. Deep Power-down (DP) ........................................................................................................................... 68
10-28. Enter Secured OTP (ENSO) .................................................................................................................... 69
10-29. Exit Secured OTP (EXSO) ....................................................................................................................... 69
10-30. Read Security Register (RDSCUR) ......................................................................................................... 69
10-31. Write Security Register (WRSCUR) ......................................................................................................... 69
10-32. Write Protection Selection (WPSEL) ........................................................................................................ 70
10-33. Advanced Sector Protection .................................................................................................................... 72
10-34. Program Suspend and Erase Suspend ................................................................................................... 80
Table 12. Acceptable Commands During Suspend .................................................................................. 81
10-35. Program Resume and Erase Resume ..................................................................................................... 82
10-36. No Operation (NOP) ................................................................................................................................ 83
10-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 83
11. Serial Flash Discoverable Parameter (SFDP)................................................................................................... 85
11-1. Read SFDP Mode (RDSFDP) .................................................................................................................. 85
12. RESET.................................................................................................................................................................. 86
Table 13. Reset Timing-(Power On) ..........................................................................................................86
Table 14. Reset Timing-(Other Operation) ................................................................................................86
13. POWER-ON STATE ............................................................................................................................................. 87
14. ELECTRICAL SPECIFICATIONS ........................................................................................................................ 88
Table 15. ABSOLUTE MAXIMUM RATINGS ............................................................................................88
Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz .................................................................................... 88
Table 17. DC CHARACTERISTICS ..........................................................................................................90
Table 18. AC CHARACTERISTICS ........................................................................................................... 91
15. OPERATING CONDITIONS ................................................................................................................................. 93
Table 19. Power-Up/Down Voltage and Timing ........................................................................................ 95
15-1. INITIAL DELIVERY STATE ...................................................................................................................... 95
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MX25U25645G 54
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Macronix Proprietary
P/N: PM2619
16. ERASE AND PROGRAMMING PERFORMANCE .............................................................................................. 96
17. DATA RETENTION .............................................................................................................................................. 96
18. LATCH-UP CHARACTERISTICS ........................................................................................................................ 96
19. ORDERING INFORMATION ................................................................................................................................ 97
20. PART NAME DESCRIPTION ............................................................................................................................... 98
21. PACKAGE INFORMATION .................................................................................................................................. 99
22. REVISION HISTORY ......................................................................................................................................... 100
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program
operations
• 256Mb: 268,435,456 x 1 bit structure or
134,217,728 x 2 bits (two I/O mode) structure or
67,108,864 x 4 bits (four I/O mode) structure
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Fast read for SPI mode
- Support fast clock frequency up to 166MHz
- Support Fast Read, 2READ, DREAD, 4READ,
QREAD instructions
- Support DTR (Double Transfer Rate) Mode
- Congurable dummy cycle number for fast read
operation
• Permanently xed QE bit (The Quad Enable bit);
QE=1 and 4 I/O mode is always enabled.
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks
with 32K byte each or Equal Blocks with 64K byte
each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
1.8V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)
FLASH MEMORY
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits dene the size of
the area to be protected against program and erase
instructions
- Advanced sector protection function
• Additional 8K bit security OTP
- Features unique identier
- Factory locked identiable, and customer lockable
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identication
- JEDEC 1-byte manufacturer ID and 2-byte device
ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and
1-byte device ID
• Support Serial Flash Discoverable Parameters
(SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2
x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for
2 x I/O read mode and 4 x I/O read mode
• SIO2
- Serial input & Output for 4 x I/O read mode
• SIO3
- Serial input & Output for 4 x I/O read mode
• RESET#
- Hardware Reset pin
• PACKAGE
- 24-Ball BGA (5x5 ball array)
- All devices are RoHS Compliant and Halogen-
free
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
2. GENERAL DESCRIPTION
MX25U25645G is 256Mb bits Serial NOR Flash memory, which is congured as 33,554,432 x 8 internally. When
it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. MX25U25645G
feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in
single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).
Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for
address/dummy bits input and data output.
The MX25U25645G
MXSMIO (Serial Multi I/O)
provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25U25645G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Read performance Comparison
Numbers of
Dummy Cycles
Fast Read
(MHz)
Dual Output
Fast Read
(MHz)
Quad Output
Fast Read
(MHz)
Dual IO
Fast Read
(MHz)
Quad IO
Fast Read
(MHz)
Quad I/O DT
Read
(MHz)
4 - - - 84 70 42
6 133 133 104 104 84 66
8 133 133 133 133 104 84
10 166 * 166 * 166 * 166 * 133 * 102 *
Note: * mean default status
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
3. PIN CONFIGURATIONS Table 2. PIN DESCRIPTION
Note:
1. The pin of RESET# will remain internal pull up
function while this pin is not physically connected in
system conguration.
However, the internal pull up function will be
disabled if the system has physical connection to
RESET# pin.
SYMBOL DESCRIPTION
CS# Chip Select
SCLK Clock Input
RESET# Hardware Reset Pin Active low
SI/SIO0
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SIO2 Serial Data Input & Output (for 4xI/O
read mode)
SIO3 Serial Data Input & Output (for 4xI/O
read mode)
VCC Power Supply
GND Ground
NC No Connection
DNU Do Not Use (It may connect to
internal signal inside)
24-Ball BGA (5x5 ball array)
RESET#
VCC
SIO2
SIO3
NC
NC
GND
SI/SIO0
NC
NC
SCLK
SO/SIO1
NC
DNU
NC
NC
NC
NC
NC
NC NC
NC
NC
CS#
A
B
C
D
E
1 2 3 4 5
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
4. BLOCK DIAGRAM
Address
Generator
Memory Array
Y-Decoder
X-Decoder
Data
Register
SRAM
Buffer
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
HOLD# *
RESET# *
CS#
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
* Depends on part number options.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
5. MEMORY ORGANIZATION
Block(32K-byte) Sector
8191 1FFF000h 1FFFFFFh
…
8184 1FF8000h 1FF8FFFh
8183 1FF7000h 1FF7FFFh
…
8176 1FF0000h 1FF0FFFh
8175 1FEF000h 1FEFFFFh
…
8168 1FE8000h 1FE8FFFh
8167 1FE7000h 1FE7FFFh
…
8160 1FE0000h 1FE0FFFh
8159 1FDF000h 1FDFFFFh
…
8152 1FD8000h 1FD8FFFh
8151 1FD7000h 1FD7FFFh
…
…
……………
…
……………
8144 1FD0000h 1FD0FFFh
47 002F000h 002FFFFh
…
40 0028000h 0028FFFh
39 027000h 0027FFFh
…
32 0020000h 0020FFFh
31 001F000h 001FFFFh
…
24 0018000h 0018FFFh
23 0017000h 0017FFFh
…
16 0010000h 0010FFFh
15 000F000h 000FFFFh
…
80008000h 0008FFFh
70007000h 0007FFFh
…
………………
………………
00000000h 0000FFFh
1020
1019
1018
Address Range
1023
1022
1021
individual block
lock/unlock unit:64K-byte
individual 16 sectors
lock/unlock unit:4K-byte
individual block
lock/unlock unit:64K-byte
individual block
lock/unlock unit:64K-byte
Block(64K-byte)
509
2
1
0
511
510
0
5
4
3
2
1
individual 16 sectors
lock/unlock unit:4K-byte
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specic command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the ash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic
Signature command (RES), Erase/Program suspend command, Erase/Program resume command and softreset
command.
• Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
6-1. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area denition is shown as "Table 3. Protected Area Sizes", the protected
areas are more exible which may protect various area by setting value of BP0-BP3 bits.
Table 3. Protected Area Sizes
Protected Area Sizes (T/B bit = 1)
Protected Area Sizes (T/B bit = 0)
Status bit Protect Level
BP3 BP2 BP1 BP0 256Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 511th)
0 0 1 0 2 (2 blocks, protected block 510th-511th)
0 0 1 1 3 (4 blocks, protected block 508th-511th)
0 1 0 0 4 (8 blocks, protected block 504th-511th)
0 1 0 1 5 (16 blocks, protected block 496th-511th)
0 1 1 0 6 (32 blocks, protected block 480th-511th)
0 1 1 1 7 (64 blocks, protected block 448th-511th)
1 0 0 0 8 (128 blocks, protected block 384th-511th)
1 0 0 1 9 (256 blocks, protected block 256th-511th)
1 0 1 0 10 (512 blocks, protected all)
1 0 1 1 11 (512 blocks, protected all)
1 1 0 0 12 (512 blocks, protected all)
1 1 0 1 13 (512 blocks, protected all)
1 1 1 0 14 (512 blocks, protected all)
1 1 1 1 15 (512 blocks, protected all)
Status bit Protect Level
BP3 BP2 BP1 BP0 256Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 0th)
0 0 1 0 2 (2 blocks, protected block 0th-1st)
0 0 1 1 3 (4 blocks, protected block 0th-3rd)
0 1 0 0 4 (8 blocks, protected block 0th-7th)
0 1 0 1 5 (16 blocks, protected block 0th-15th)
0 1 1 0 6 (32 blocks, protected block 0th-31st)
0 1 1 1 7 (64 blocks, protected block 0th-63rd)
1 0 0 0 8 (128 blocks, protected block 0th-127th)
1 0 0 1 9 (256 blocks, protected block 0th-255th)
1 0 1 0 10 (512 blocks, protected all)
1 0 1 1 11 (512 blocks, protected all)
1 1 0 0 12 (512 blocks, protected all)
1 1 0 1 13 (512 blocks, protected all)
1 1 1 0 14 (512 blocks, protected all)
1 1 1 1 15 (512 blocks, protected all)
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
6-2. Additional 8K-bit secured OTP
The secured OTP for unique identier: to provide 8K-bit one-time program area for setting device unique serial
number. Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 8K-bit secured OTP by entering secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting secured OTP mode by writing Exit Security OTP
command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Denition" for
security register bit denition and "Table 4. 8K-bit Secured OTP Denition" for address range denition.
- Note: Once lock-down by factory or customer, the corresponding range cannot be changed any more. While in
secured OTP mode, array access is not allowed.
Table 4. 8K-bit Secured OTP Denition
Address range Size Lock-down
xxx000~xxx1FF 4096-bit Determined by Customer
xxx200~xxx3FF 4096-bit Determined by Factory
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
7. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD,
RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDLR, RDFBR, RDCR, the shifted-in instruction sequence is
followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL,
GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the
byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
SCLK
MSB
CPHA shift in shift out
SI
0
1
CPOL
0(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
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MX25U25645G 54
Rev. 1.0, March 12, 2019
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P/N: PM2619
Figure 2. Serial Input Timing (STR mode)
Figure 3. Serial Input Timing (DTR mode)
SCLK
SI
CS#
MSB
SO
tDVCH
High-Z
LSB
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
SCLK
tDVCH
tSLCH
tCHCL
tSHCH
tCHSL
CS#
tSHSL
SIO[3:0] MSB LSB
tCHDX
tCLDX
tDVCL
tCLCH
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P/N: PM2619
Figure 4. Output Timing (STR mode)
LSB
ADDR.LSB IN
tSHQZ
tCH
tCL
tCLQX
tCLQV
tCLQX
tCLQV
SCLK
SO
CS#
SI
Figure 5. Output Timing (DTR mode)
ADDR.LSB IN
tSHQZ
tCH
tCL
tCLQX
tCLQV
LSB
tCLQX
tCLQV
SCLK
SO
CS#
SI
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
7-1. 256Mb Address Protocol
The original 24 bit address protocol of Serial NOR Flash can only access density size below 128Mb. For the
memory device of 256Mb and above, the 32bit address is requested for access higher memory size. MX25U25645G
device provide whole new 4-Byte address protocol, for backward compatible to the legacy commands. All the
command request for 4-Byte (32 bit) address cycle in this device.
7-2. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface
in command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing command EQIO(35h), the QPI mode is enabled. After QPI mode is enabled, the device enters quad
mode (4-4-4) without QE bit status changed.
Figure 6. Enable QPI Sequence
MODE 3
SCLK
SIO0
CS#
MODE 0
234567
35h
SIO[3:1]
0 1
Reset QPI (RSTQIO)
To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device
returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).
Note:
For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.
Figure 7. Reset QPI Mode
SCLK
SIO[3:0]
CS#
F5h
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P/N: PM2619
8. COMMAND SET
Table 5. Read/Write Array Commands
Command
(byte)
READ
(normal read)
FAST READ
(fast read data)
2READ
(2 x I/O read
command)
DREAD
(1I 2O read)
4READ
(4 I/O read)
QREAD
(1I 4O read)
4DTRD (Quad
I/O DT Read)
Mode SPI SPI SPI SPI SPI/QPI SPI SPI/QPI
Address Bytes 4 4 4 4 4 4 4
1st byte 03 (hex) 0B (hex) BB (hex) 3B (hex) EB (hex) 6B (hex) ED (hex)
2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 ADD3
5th byte ADD4 ADD4 ADD4 ADD4 ADD4 ADD4 ADD4
6th byte Dummy* Dummy* Dummy* Dummy* Dummy* Dummy*
Data Cycles
Action
n bytes read
out until CS#
goes high
n bytes read
out until CS#
goes high
n bytes read
out by 2 x I/O
until CS# goes
high
n bytes read
out by Dual
output until
CS# goes high
n bytes read
out by 4 x I/O
until CS# goes
high
n bytes read
out by Quad
output until
CS# goes high
n bytes read
out (Double
Transfer Rate)
by 4xI/O until
CS# goes high
Command
(byte)
PP
(page program)
4PP
(quad page
program)
SE
(sector erase)
BE 32K
(block erase
32KB)
BE
(block erase
64KB)
CE
(chip erase)
Mode SPI/QPI SPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI
Address Bytes 4 4 4 4 4 0
1st byte 02 (hex) 38 (hex) 20 (hex) 52 (hex) D8 (hex) 60 or C7 (hex)
2nd byte ADD1 ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3 ADD3
5th byte ADD4 ADD4 ADD4 ADD4 ADD4
Data Cycles 1-256 1-256
Action
to program the
selected page
quad input to
program the
selected page
to erase the
selected sector
to erase the
selected 32K
block
to erase the
selected block
to erase whole
chip
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in conguration register.
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Table 6. Register/Setting Commands
Command
(byte)
WREN
(write enable)
WRDI
(write disable)
RDSR
(read status
register)
RDCR
(read
conguration
register)
WRSR
(write status/
conguration
register)
WPSEL
(Write Protect
Selection)
EQIO
(Enable QPI)
Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI SPI
1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 68 (hex) 35 (hex)
2nd byte Values
3rd byte Values
4th byte
5th byte
Data Cycles 1-2
Action
sets the (WEL)
write enable
latch bit
resets the
(WEL) write
enable latch bit
to read out the
values of the
status register
to read out the
values of the
conguration
register
to write new
values of the
status/
conguration
register
to enter and
enable individal
block protect
mode
Entering the
QPI mode
Command
(byte)
RSTQIO
(Reset QPI)
PGM/ERS
Suspend
(Suspends
Program/
Erase)
PGM/ERS
Resume
(Resumes
Program/
Erase)
DP
(Deep power
down)
RDP (Release
from deep
power down)
SBL
(Set Burst
Length)
Mode QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI
1st byte F5 (hex) B0 (hex) 30 (hex) B9 (hex) AB (hex) C0 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
Exiting the QPI
mode
enters deep
power down
mode
release from
deep power
down mode
to set Burst
length
Command
(byte)
RDFBR
(read fast boot
register)
WRFBR
(write fast boot
register)
ESFBR
(erase fast
boot register)
Mode SPI SPI SPI
1st byte 16(hex) 17(hex) 18(hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles 1-4 4
Action
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Table 7. ID/Security Commands
Command
(byte)
RDID
(read identic-
ation)
RES
(read electronic
ID)
REMS
(read electronic
manufacturer &
device ID)
QPIID
(QPI ID Read) RDSFDP
ENSO
(enter secured
OTP)
EXSO
(exit secured
OTP)
Mode SPI SPI/QPI SPI QPI SPI/QPI SPI/QPI SPI/QPI
Address Bytes 0 0 0 0 3 0 0
1st byte 9F (hex) AB (hex) 90 (hex) AF (hex) 5A (hex) B1 (hex) C1 (hex)
2nd byte x x ADD1
3rd byte x x ADD2
4th byte ADD1 ADD3
5th byte Dummy(8)(Note 4)
Action
outputs JEDEC
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
to read out
1-byte Device
ID
output the
Manufacturer
ID & Device ID
ID in QPI
interface
Read SFDP
mode
to enter the
secured OTP
mode
to exit the
secured OTP
mode
Command
(byte)
RDSCUR
(read security
register)
WRSCUR
(write security
register)
GBLK
(gang block
lock)
GBULK
(gang block
unlock)
WRLR
(write Lock
register)
RDLR
(read Lock
register)
WRSPB
(SPB bit
program)
Mode SPI/QPI SPI/QPI SPI SPI SPI SPI SPI
Address Bytes 0 0 0 0 0 0 4
1st byte 2B (hex) 2F (hex) 7E (hex) 98 (hex) 2C (hex) 2D (hex) E3 (hex)
2nd byte ADD1
3rd byte ADD2
4th byte ADD3
5th byte ADD4
Data Cycles 2 2
Action
to read value
of security
register
to set the lock-
down bit as
"1" (once lock-
down, cannot
be updated)
whole chip
write protect
whole chip
unprotect
Command
(byte)
ESSPB
(all SPB bit
erase)
RDSPB
(read SPB
status)
WRDPB
(write DPB
register)
RDDPB
(read DPB
register)
RDPASS
(read password
register)
WRPASS
(write password
register)
PASSULK
(password
unlock)
Mode SPI SPI SPI SPI SPI SPI SPI
Address Bytes 0 4 4 4 4 4 4
1st byte E4 (hex) E2 (hex) E1 (hex) E0 (hex) 27 (hex) 28 (hex) 29 (hex)
2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1
3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2
4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3
5th byte ADD4 ADD4 ADD4 ADD4 ADD4 ADD4
6th byte Dummy(8)(Note 4)
Data Cycles 1 1 1 8 8 8
Action
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Note 1: ADD=00H will output the manufacturer ID rst and ADD=01H will output device ID rst.
Note 2: It is not recommended to adopt any other code not in the command denition table, which will potentially enter the hid-
den mode.
Note 3: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
Note 4: The number in parentheses after “ADD” or “Data” or “Dummy” stands for how many clock cycles it has. For example,
"Data(8)" represents there are 8 clock cycles for the data in.
Table 8. Reset Commands
Command
(byte)
NOP
(No Operation)
RSTEN
(Reset Enable)
RST
(Reset
Memory)
Mode SPI/QPI SPI/QPI SPI/QPI
1st byte 00 (hex) 66 (hex) 99 (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
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Status Register
Note 1: see the "Table 3. Protected Area Sizes".
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Reserved
QE
(Quad
Enable)
BP3
(level of
protected
block)
BP2
(level of
protected
block)
BP1
(level of
protected
block)
BP0
(level of
protected
block)
WEL
(write enable
latch)
WIP
(write in
progress bit)
Reserved 1=Quad
Enabled (note 1) (note 1) (note 1) (note 1)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
Reserved Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit volatile bit volatile bit
9. REGISTER DESCRIPTION
9-1. Status Register
The denition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
conrmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area
(as dened in Table 3) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits dene the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0)
set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, a non-volatile bit which is permanently set to "1". The ash always performs
Quad I/O mode.
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9-2. Conguration Register
The Conguration Register is able to change the default status of Flash memory. Flash memory will be congured
after the CR bit is set.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
dened in Output Driver Strength Table) of the device. To write the ODS bits requires the Write Status Register (WRSR)
instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to congure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as
“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.
PBE bit
The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern
output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”,
the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status
Register (WRSR) instruction to be executed.
Conguration Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DC1
(Dummy
cycle 1)
DC0
(Dummy
cycle 0)
Reserved
PBE
(Preamble bit
Enable)
TB
(top/bottom
selected)
ODS 2
(output driver
strength)
ODS 1
(output driver
strength)
ODS 0
(output driver
strength)
(note 2) (note 2) x
0=Disable
1=Enable
0=Top area
protect
1=Bottom
area protect
(Default=0)
(note 1) (note 1) (note 1)
volatile bit volatile bit x volatile bit OTP volatile bit volatile bit volatile bit
Note 1: see "Output Driver Strength Table"
Note 2: see "Dummy Cycle and Frequency Table (MHz)"
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Dummy Cycle and Frequency Table (MHz)
Output Driver Strength Table
DC[1:0]
Numbers of
Dummy clock
cycles
Fast Read Dual Output Fast
Read
Quad Output
Fast Read
11 8 133 133 133
10 6 133 133 104
01 8 133 133 133
00 (default) 10 166 166 166
DC[1:0]
Numbers of
Dummy clock
cycles
Dual IO Fast
Read
11 4 84
10 6 104
01 8 133
00 (default) 10 166
DC[1:0]
Numbers of
Dummy clock
cycles
Quad IO Fast
Read
Quad I/O DTR
Read
11 6 84 66
10 4 70 42
01 8 104 84
00 (default) 10 133 102
ODS2 ODS1 ODS0 Description Note
0 0 0 146 Ohms
Impedance at VCC/2
(Typical)
0 0 1 76 Ohms
0 1 0 52 Ohms
0 1 1 41 Ohms
1 0 0 34 Ohms
1 0 1 30 Ohms
1 1 0 26 Ohms
1 1 1 24 Ohms (Default)
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bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
WPSEL E_FAIL P_FAIL Reserved
ESB
(Erase
Suspend bit)
PSB
(Program
Suspend bit)
LDSO
(indicate if
lock-down)
Secured OTP
indicator bit
0=normal
WP mode
1=individual
mode
(default=0)
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
-
0=Erase
is not
suspended
1= Erase
suspended
(default=0)
0=Program
is not
suspended
1= Program
suspended
(default=0)
0 = not lock-
down
1 = lock-down
(cannot
program/
erase
OTP)
0 = non-
factory
lock
1 = factory
lock
Non-volatile
bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit
Non-volatile
bit
(OTP)
Non-volatile
bit (OTP)
Table 9. Security Register Denition
9-3. Security Register
The denition of the Security Register bits is as below:
Write Protection Selection bit. Please reference to "Write Protection Selection bit"
Erase Fail bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase
operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation
succeeds. Please note that it will not interrupt or stop any operation in the ash memory.
Program Fail bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1" if
the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next
program operation succeeds. Please note that it will not interrupt or stop any operation in the ash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of ash memory. After the ash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of ash memory. After the ash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the Secured OTP
area cannot be updated any more. While it is in secured OTP mode, main array access is not allowed.
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Figure 8. Write Enable (WREN) Sequence (SPI Mode)
21 34567
High-Z
0
06h
Command
SCLK
SI
CS#
SO
Mode 3
Mode 0
Figure 9. Write Enable (WREN) Sequence (QPI Mode)
SCLK
SIO[3:0]
CS#
06h
0 1
Command
Mode 3
Mode 0
10. COMMAND DESCRIPTION
10-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
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10-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WPSEL command completion
- GBLK command completion
- GBULK command completion
- WRLR command completion
- WRSPB command completion
- ESSPB command completion
- WRDPB command completion
- WRFBR command completion
- ESFBR command completion
Figure 10. Write Disable (WRDI) Sequence (SPI Mode)
21 34567
High-Z
0Mode 3
Mode 0
04h
Command
SCLK
SI
CS#
SO
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10-3. Read Identication (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as "Table 10. ID Denitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 12. Read Identication (RDID) Sequence (SPI mode only)
21 3456789
Command
0
Manufacturer Identification
High-Z
MSB
15 14 13 3210
Device Identification
MSB
7 6 5 2 1 0
16 17 18 28 29 30 31
SCLK
SI
CS#
SO
9Fh
Mode 3
Mode 0
14 15
10 13
Figure 11. Write Disable (WRDI) Sequence (QPI Mode)
SCLK
SIO[3:0]
CS#
04h
0 1
Command
Mode 3
Mode 0
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10-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip
Select (CS#) must remain High for at least tRES1(max), as specied in "Table 18. AC CHARACTERISTICS".
Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will
release the Flash from deep power down mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 10 ID
Denitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction.
Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in
progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly
if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in
Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep
Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
Figure 13. Read Electronic Signature (RES) Sequence (SPI Mode)
23
21 3456789 10 28 29 30 31 32 33 34 35
22 21 3210
36 37 38
765432 0
1
High-Z Electronic Signature Out
3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
SCLK
CS#
SI
SO
ABh
Command
Mode 3
Mode 0
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SCLK
SIO[3:0]
CS#
MODE 0
MODE 3
MSB LSB
Data Out
Data In
H0XXXXXX L0
Deep Power-down Mode
Stand-by Mode
0
ABh
1 2 3 4 6 75
3 Dummy Bytes
Command
Figure 14. Read Electronic Signature (RES) Sequence (QPI Mode)
Figure 15. Release from Deep Power-down (RDP) Sequence (SPI Mode)
21 345670tRES1
Stand-by Mode
Deep Power-down Mode
High-Z
SCLK
CS#
SI
SO
ABh
Command
Mode 3
Mode 0
Figure 16. Release from Deep Power-down (RDP) Sequence (QPI Mode)
SCLK
SIO[3:0]
CS#
ABh
0 1
tRES1
Deep Power-down Mode Stand-by Mode
Command
Mode 3
Mode 0
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10-5. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values
are listed in Table 10 of ID Denitions.
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two
dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device
ID are shifted out on the falling edge of SCLK with the most signicant bit (MSB) rst. If the address byte is 00h,
the manufacturer ID will be output rst, followed by the device ID. If the address byte is 01h, then the device ID will
be output rst, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Notes:
(1) ADD=00H will output the manufacturer's ID rst and ADD=01H will output device ID rst.
Figure 17. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)
15 14 13 3 2 1 0
21 3456789 10
2 Dummy Bytes
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
Manufacturer ID
ADD (1)
MSB
76543210
Device ID
MSB MSB
7
47
765432 0
1
3531302928
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
90h
High-Z
Command
Mode 3
Mode 0
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10-6. QPI ID Read (QPIID)
User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue
QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most signicant
bit (MSB) rst.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 10. ID Denitions
Command Type MX25U25645G
RDID 9Fh Manufacturer ID Memory type Memory density
C2 95 39
RES ABh Electronic ID
39
REMS 90h Manufacturer ID Device ID
C2 39
QPIID AFh Manufacturer ID Memory type Memory density
C2 95 39
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10-7. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 18. Read Status Register (RDSR) Sequence (SPI Mode)
21 3456789 10 11 12 13 14 15
command
0
76543210
Status Register Out
High-Z
MSB
76543210
Status Register Out
MSB
7
SCLK
SI
CS#
SO
05h
Mode 3
Mode 0
Figure 19. Read Status Register (RDSR) Sequence (QPI Mode)
0 1 3
SCLK
SIO[3:0]
CS#
05h
2
H0 L0
MSB LSB
4 5 7
H0 L0
6
H0 L0 H0 L0
Status ByteStatus ByteStatus ByteStatus Byte
Mode 3
Mode 0
N
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-8. Read Conguration Register (RDCR)
The RDCR instruction is for reading Conguration Register Bits. The Read Conguration Register can be read at
any time (even in program/erase/write conguration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write conguration register operation
is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Conguration
Register data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 20. Read Conguration Register (RDCR) Sequence (SPI Mode)
21 3456789 10 11 12 13 14 15
command
0
76543210
Configuration register Out
High-Z
MSB
76543210
Configuration register Out
MSB
7
SCLK
SI
CS#
SO
15h
Mode 3
Mode 0
Figure 21. Read Conguration Register (RDCR) Sequence (QPI Mode)
0 1 3
SCLK
SIO[3:0]
CS#
15h
2
H0 L0
MSB LSB
4 5 7
H0 L0
6
H0 L0 H0 L0
Mode 3
Mode 0
Config. ByteConfig. ByteConfig. ByteConfig. Byte
N
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
WREN command
Program/erase command
Write program data/address
(Write erase address)
RDSR command
Read array data
(same address of PGM/ERS)
Program/erase successfully
Yes
Yes
Program/erase fail
No
start
Verify OK?
WIP=0?
Program/erase
another block?
Program/erase completed
No
Yes
No
RDSR command*
Yes
WEL=1? No
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
RDSR command
Read WEL=0, BP[3:0],
and QE data
Figure 22. Program/Erase ow with read array data
For user to check if Program/Erase operation is nished or not, RDSR instruction ow are shown as follows:
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 23. Program/Erase ow without read array data (read P_FAIL/E_FAIL ag)
WREN command
Program/erase command
Write program data/address
(Write erase address)
RDSR command
RDSCUR command
Program/erase successfully
Yes
No
Program/erase fail
Yes
start
P_FAIL/E_FAIL =1 ?
WIP=0?
Program/erase
another block?
Program/erase completed
No
Yes
No
RDSR command*
Yes
WEL=1? No
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
RDSR command
Read WEL=0, BP[3:0],
and QE data
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
Figure 24. Write Status Register (WRSR) Sequence (SPI Mode)
21 3456789 10 11 12 13 14 15
Status
Register In
Configuration
Register In
0
MSB
SCLK
SI
CS#
SO
01h
High-Z
command
Mode 3
Mode 0
16 17 18 19 20 21 22 23
765 4321 0 15 14 13 12 11 10 9 8
Figure 25. Write Status Register (WRSR) Sequence (QPI Mode)
SCLK
SIO[3:0]
CS#
2 3 510 4
H0 L0 H1 L1
Command SR in CR in
Mode 3 Mode 3
Mode 0 Mode 0
01h
10-9. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Conguration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to dene the protected area of memory (as shown in Table 3). The WRSR instruction cannot be executed
once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write
Enable Latch (WEL) bit is reset.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Table 11. Protection Modes
Note:
1. As dened by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3.
Mode Status register condition Memory
Software protection
mode (SPM)
Status register can be written
in (WEL bit is set to "1") and
the BP0-BP3
bits can be changed
The protected area cannot
be programmed or erased.
Software Protected Mode (SPM):
- The WREN instruction may set the WEL bit and can change the values of BP3, BP2, BP1, BP0. The protected
area, which is dened by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM).
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 26. WRSR ow
WREN command
WRSR command
Write status register data
RDSR command
WRSR successfully
Yes
Yes
WRSR fail
No
start
Verify OK?
WIP=0? No
RDSR command
Yes
WEL=1? No
RDSR command
Read WEL=0, BP[3:0],
and QE data
39
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-10. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The rst address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 4-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)
SCLK
CS#
Data Out 1
MSB MSB
MSB Data Out 2
High-Z
Command
D7
A31 A30 A29 A3 A2 A1 A0
D7D6 D5 D4 D3 D2 D1 D0
32-Bit Address
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
SI
SO
03h
Mode 3
Mode 0
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-11. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The rst address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 4-byte address on SI→ 10 dummy cycles (default)→ data out on SO→ to end FAST_READ
operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-12. Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The rst address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD
instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→ 4-byte address on
SIO0→ 10 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 29. Dual Read Mode Sequence
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
938 39 40 49 50 51 53 54 5552
3Bh D4
D5
D2
D3
D7
D6 D6 D4
D0
D7 D5
D1
Command 32 ADD Cycle
A31 A30 A1 A0
… …
…
Data Out
1
Data Out
2
Configurable
Dummy Cycle
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-13. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The rst address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ
instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 4-byte address
interleave on SIO1 & SIO0→ 10 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to
end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
9 10 21 22 23 24
BBh
25 26 33 34 35 36 37 38 39 40
Command Configurable
Dummy Cycle
Mode 3
Mode 0
Mode 3
Mode 0
16 ADD Cycles
A31 A29 A27 A5 A3 A1
A4 A2 A0A30 A28 A26
D6 D4
D7 D5
Data
Out 1
Data
Out 2
D2 D0
D3 D1
D0
D1
D6 D4
D7 D5
D2
D3
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-14. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The rst address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD
instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 4-byte address on
SI → 10 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation
can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 31. Quad Read Mode Sequence
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
High Impedance
21 3456780
SCLK
SIO0
SIO1
CS#
37
938 39 40 41 48 49 50 51 52
6Bh
High Impedance
SIO2
High Impedance
SIO3
10 dummy cycles
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4
D5
D6
D7
A31 A30 A2 A1 A0
Command 32 ADD Cycles Data
Out 1
Data
Out 2
Data
Out 3
…
…
…
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-15. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The rst address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ
instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending
4READ instruction→ 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 10 dummy cycles (Default) →data
out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data
out.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence
of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 4-byte address interleave
on SIO3, SIO2, SIO1 & SIO0→ 10 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
Figure 33. 4 x I/O Read Mode Sequence (QPI Mode)
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
High Impedance
21 3456780
SCLK
SIO0
SIO1
CS#
9 1210 11 13 14
EBh P4 P0
P5 P1
P6 P2
P7 P3
15 16 17 18 19 25 26 27 2724
High Impedance
SIO2
High Impedance
SIO3
Performance
Enhance
Indicator
(Note1, 2)
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4
D5
D6
D7
A28
A29
A30
A31
A24
A25
A26
A27
A20
A21
A22
A23
A16
A17
A18
A19
A12
A13
A14
A15
A0
A1
A2
A3
A8
A9
A10
A11
A4
A5
A6
A7
Command 8 ADD Cycles
Data
Out 1
Data
Out 2
Data
Out 3
Configurable
Dummy Cycle
(Note 3)
3 EDOM
SCLK
SIO[3:0]
CS#
MODE 3
MODE 0MODE 0
MSB
Data Out
EBh
H0 L0 H1 L1 H2 L2
X X X X X
0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24
Data In Configurable
Dummy Cycle
A28-
A31 A24-
A27 A20-
A23 A16-
A19 A12-
A15 A8-
A11 A4-
A7 A0-
A3
32 ADD Cycles
46
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-16. 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial NOR Flash in read mode.
The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave
on 4 I/O pins) shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock,
and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at
falling edge of clock. The rst address byte can be at any location. The address is automatically increased to the
next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD
instruction, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 34. Fast Quad I/O DT Read (4DTRD) Sequence (SPI Mode)
EDh
SIO0
SIO1
CS#
SIO2
SIO3
SCLK
P4 P0
D7 D3
D6 D2
D5 D1
D4 D0
D7 D3
D6 D2
D5 D1
D4 D0
D7
D6
D5
D4
Performance
Enhance Indicator
0 7 8 11 12 21 22 23
A0
A28 A24
A25A29
A26A30
A27A31
A4
A1A5
A2A6
A3
A7
Command 4 ADD Cycles
P7
P6
P5 P1
P2
P3
… ……
…
…
…
…
Configurable
Dummy Cycle
Mode 3
Mode 0
Figure 35. Fast Quad I/O DT Read (4DTRD) Sequence (QPI Mode)
Configurable
Dummy Cycle
EDh
SIO[3:0]
CS#
SCLK
P1 P0 H0 L0 H1 L1 H2
Performance
Enhance Indicator
0
Mode 3
Mode 0
1 2 5 6 15 16 17
Command 4 ADD Cycles
……
……
A24
|
A31
A20
|
A23
A4
|
A7
A0
|
A3
Notes:
1. Hi-impedance is inhibited for this clock cycle.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
3. Conguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
conguration register.
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
conguration register.
48
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-17. Preamble Bit
Figure 36. SDR 1I/O (10DC)
CS#
CMD
SCLK
SI
SO
A0
D7 D6
Command
cycle Address cycle
Dummy cycle
Preamble bits
7 6 5 4 3 2 1 0
An
…
…
…
…
Figure 37. SDR 1I/O (8DC)
CS#
CMD
SCLK
An A0
2D4
… …
…
Command
cycle Address cycle
Dummy cycle
Preamble bits
7 6 5 4 3 D5D7 D6
…
SI
SO
The Preamble Bit data pattern supports system/memory controller to determine valid window of data output more
easily and improve data capture reliability while the ash memory is running in high frequency.
Preamble Bit data pattern can be enabled or disabled by setting the bit4 of Conguration register (Preamble bit
Enable bit). Once the CR<4> is set, the preamble bit is inputted into dummy cycles.
Enabling preamble bit will not affect the function of enhance mode bit. In Dummy cycles, performance enhance
mode bit still operates with the same function. Preamble bit will output after performance enhance mode bit.
The preamble bit is a xed 8-bit data pattern (00110100). While dummy cycle number reaches 10, the complete
8 bits will start to output right after the performance enhance mode bit. While dummy cycle is not sufcient of 10
cycles, the rest of the preamble bits will be cut. For example, 8 dummy cycles will cause 6 preamble bits to output,
and 6 dummy cycles will cause 4 preamble bits to output.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 38. SDR 2I/O (10DC)
Figure 39. SDR 2I/O (8DC)
CS#
CMD
SCLK
SIO0 A0
A(n-1) 7 6 5 4 3 2 1 0 D6 D4
Command
cycle
Address cycle
Dummy cycle
Toggle
bits
Preamble bits
SIO1 A1An 7 6 5 4 3 2 1 0 D7 D5
D2 D0
D3 D1
…
…
…
…
…
…
CS#
CMD
SCLK
SIO0 A0
A(n-1) 7 6 5 4 3 2 D6 D4
Command
cycle
Dummy cycle
Toggle
bits
SIO1 A1An 7 6 5 4 3 2 D7 D5
D2 D0
D3 D1
Address cycle Preamble bits
……
…
…
…
…
50
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 40. SDR 4I/O (10DC)
CS#
CMD
SCLK
SIO0 A0
A(n-3)
A(n-2)
A(n-1)
7 6 5 4 3 2 1 0 D4 D0
Command
cycle
Dummy cycle
Toggle
bits
SIO1 A1 7 6 5 4 3 2 1 0 D5 D1
SIO2 A2 7 6 5 4 3 2 1 0 D6 D2
SIO3 A3An 7 6 5 4 3 2 1 0 D7 D3
Address cycle Preamble bits
…
…
…
…
…
…
…
…
…
…
Figure 41. SDR 4I/O (8DC)
CS#
CMD
SCLK
SIO0 A0
A(n-3)
A(n-2)
A(n-1)
7 6 5 4 3 2 D4 D0
Command
cycle
Dummy cycle
Toggle
bits
SIO1 A1 7 6 5 4 3 2 D5 D1
SIO2 A2 7 6 5 4 3 2 D6 D2
SIO3 A3An 7 6 5 4 3 2 D7 D3
Address cycle Preamble bits
…
…
…
…
…
…
…
…
…
…
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 42. DTR4IO (6DC)
CS#
CMD
SCLK
SIO0
SIO1
Toggle
Bits
Command
cycle Address cycle
A(n-3)
A(n-2)
A0
7 6 5 4 3 2 1 0
D4 D0
A1
7 6 5 4 3 2 1 0
D5 D1
SIO2
A(n-1)
A2
7 6 5 4 3 2 1 0
D6 D2
SIO3
An
A3
7 6 5 4 3 2 1 0
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
Dummy cycle
Preamble bits
…
…
…
…
…
…
…
…
…
…
52
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-18. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EBh” "EDh" and SPI “EBh” "EDh" commands support enhance mode. The performance enhance
mode is not supported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.
Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and
return to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the rst clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→sending 4
READ instruction→4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 8 dummy cycles (Default) →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →
4-bytes random access address.
53
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 43. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode)
21 3456780
SCLK
SIO0
SIO1
CS#
9 1210 11 13 14
EBh
15 16
n+1 ........... ...... ........... ...........n+9 n+11 n+19
17 18 24 25 26 27 28 n
SIO2
SIO3
SIO0
SIO1
SIO2
SIO3
Performance
enhance
indicator (Note 1)
SCLK
CS#
Performance
enhance
indicator (Note 1)
Mode 3
Mode 0
A21 A17 A13 A9 A5 A1
A8 A4 A0A20 A16 A12
A23 A19 A15 A11 A7 A3
A10 A6 A2A22 A18 A14
P4 P0
P5 P1
P6 P2
P7 P3
A24
A25
A26
A27
A28
A29
A30
A31
A24
A25
A26
A27
A28
A29
A30
A31
A21 A17 A13 A9 A5 A1
A8 A4 A0A20 A16 A12
A23 A19 A15 A11 A7 A3
A10 A6 A2A22 A18 A14
P4 P0
P5 P1
P6 P2
P7 P3
Command
Configurable
Dummy Cycle
(Note 2)
Configurable
Dummy Cycle
(Note 2)
8 ADD Cycles
8 ADD Cycles
D4 D0
D5 D1
Data
Out 1
Data
Out 2
Data
Out n
D4 D0
D5 D1
D4 D0
D5 D1
D6 D2
D7 D3
D6 D2
D7 D3
D6 D2
D7 D3
D4 D0
D5 D1
Data
Out 1
Data
Out 2
Data
Out n
D4 D0
D5 D1
D4 D0
D5 D1
D6 D2
D7 D3
D6 D2
D7 D3
D6 D2
D7 D3
Mode 3
Mode 0
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Conguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
conguration register.
3. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
54
MX25U25645G 54
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P/N: PM2619
Figure 44. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
conguration register.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
SCLK
SIO[3:0]
CS#
Data Out
EBh X
P(7:4) P(3:0)
X X H0 L0 H1 L1
performance
enhance
indicator
SCLK
SIO[3:0]
CS#
Data Out
MSB LSB MSB LSB
MSB LSB MSB LSB
X
P(7:4) P(3:0)
X X H0 L0 H1 L1
Configurable
Dummy Cycles
(Note 1)
performance
enhance
indicator
n+1 .............
0 1 2 3 4 5 6 7 8 9 10 11 12 13 19 2220 2321
Mode 3
Mode 0
Mode 0
8 ADD Cycles
8 ADD Cycles
Command
Configurable
Dummy Cycles
(Note 1)
A28-
A31 A24-
A27 A20-
A23 A16-
A19 A12-
A15 A8-
A11 A4-
A7 A0-
A3
A28-
A31 A24-
A27 A20-
A23 A16-
A19 A12-
A15 A8-
A11 A4-
A7 A0-
A3
55
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 45. 4 x I/O DT Read Performance Enhance Mode Sequence (SPI Mode)
EDh
SIO0
SIO1
CS#
SIO2
SIO3
SCLK
P4 P0
D7 D3
D6 D2
D5 D1
D4 D0
D7 D3
D6 D2
D5 D1
D4 D0
D7 D3
D6 D2
D5 D1
D4 D0
Performance
Enhance Indicator
0 7 8 11 12 21 22 23 n
A0
A28 A24
A25A29
A26A30
A27A31
A28 A24
A25A29
A26A30
A27A31
A4
A1A5
A2A6
A3
A7
Command 4 ADD Cycles
P7
P6
P5 P1
P2
P3
……… …
…
…
…
…
…
…
…
…
Configurable
Dummy Cycle
Mode 3
Mode 0
SIO0
SIO1
CS#
SIO2
SIO3
SCLK
P4 P0
D7 D3
D6 D2
D5 D1
D4 D0
D7 D3
D6 D2
D5 D1
D4 D0
Performance
Enhance Indicator
A0A4
A1A5
A2A6
A3
A7
4 ADD Cycles
P7
P6
P5 P1
P2
P3
…
…
…
…
…
…
Configurable
Dummy Cycle
n+1 n+5
… …
Mode 3
Mode 0
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
56
MX25U25645G 54
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Macronix Proprietary
P/N: PM2619
Figure 46. 4 x I/O DT Read Performance Enhance Mode Sequence (QPI Mode)
Configurable
Dummy Cycle
EDh
SIO[3:0]
CS#
SCLK
P1 P0 H0 L0 H1 L1 Hn Ln
Performance
Enhance Indicator
0
Mode 3
Mode 0
1 2 5 6 15 16 17 n
Command 4 ADD Cycles
……
……
…
…
A28
|
A31
A24
|
A27
……
A28
|
A31
A24
|
A27
A4
|
A7
A0
|
A3
Configurable
Dummy Cycle
SIO[3:0]
CS#
SCLK
P1 P0 H0 L0 H1 L1
Performance
Enhance Indicator
n+1 n+5
4 ADD Cycles
……
……
A4
|
A7
A0
|
A3
Mode 3
Mode 0
Notes:
1. Conguration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in
conguration register.
2. Reset the performance enhance mode, if P1=P0, ex: AA, 00, FF.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
The wrap around unit is dened with the 8/16/32/64Byte, with random initial address. It is dened as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. Both QPI and SPI “EBh”
support wrap around feature after wrap around is enabled. Both SPI (8 clocks) and QPI (2 clocks) command cycle
can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.
Data Wrap Around Wrap Depth
00h Yes 8-byte
01h Yes 16-byte
02h Yes 32-byte
03h Yes 64-byte
1xh No X
0
CS#
SCLK
SI
C0h D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 6 7 8 9 10 1112 13 14 155
Mode 3
Mode 0
Figure 47. SPI Mode
Figure 48. QPI Mode
0
CS#
SCLK
SIO[3:0]
H0
MSB LSB
L0C0h
1 2 3
Mode 3
Mode 0
Note: MSB=Most Signicant Bit
LSB=Least Signicant Bit
10-19. Burst Read
To set the Burst length, following command operation is required to issue command: “C0h” in the rst Byte (8-clocks),
following 4 clocks dening wrap around enable with “0h” and disable with“1h”.
The next 4 clocks are to dene wrap around depth. Their denitions are as the following table:
58
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Fast Boot Register (FBR)
10-20. Fast Boot
The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset
without any read instruction.
A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also dene the number of
delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and
ESFBR (erase fast boot register) can be used for the status conguration or alternation of the Fast Boot Register
bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default
number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access.
When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles).
After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In
the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.
Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,
reset command, or hardware reset operation.
The fast Boot feature can support Quad I/O interface. The QE bit of Status Register is set to “1”, the data is output
by Quad I/O interface.
Bits Description Bit Status Default State Type
31 to 4 FBSA (FastBoot Start
Address)
16 bytes boundary address for the start of boot
code access. FFFFFFF Non-
Volatile
3 x 1 Non-
Volatile
2 to 1 FBSD (FastBoot Start
Delay Cycle)
00: 7 delay cycles
01: 9 delay cycles
10: 11 delay cycles
11: 13 delay cycles
11 Non-
Volatile
0 FBE (FastBoot Enable) 0=FastBoot is enabled.
1=FastBoot is not enabled. 1Non-
Volatile
Note: If FBSD = 11, the maximum clock frequency is 133 MHz
If FBSD = 10, the maximum clock frequency is 104 MHz
If FBSD = 01, the maximum clock frequency is 84 MHz
If FBSD = 00, the maximum clock frequency is 70 MHz
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 49. Fast Boot Sequence (QE=1)
40
5 1 5 1
4 4 4
000
5 1
-------n
High Impedance
0
6 2 6 2 6 2
7 3 7 3 7 3
6 2
7 3
SCLK
CS#
SIO0
SIO1
SIO3
SIO2
MSB
Delay Cycles
n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9
Mode 3
Mode 0
Data
Out 1
51
High Impedance
High Impedance
High Impedance
Data
Out 2
Data
Out 3
Data
Out 4
4
5
6
7
Note: If FBSD = 11, delay cycles is 13 and n is 12.
If FBSD = 10, delay cycles is 11 and n is 10.
If FBSD = 01, delay cycles is 9 and n is 8.
If FBSD = 00, delay cycles is 7 and n is 6.
60
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 50. Read Fast Boot Register (RDFBR) Sequence
21 34567890
SCLK
CS#
SI
SO
16h
Command
Mode 3 3710 38 39 40 41
Mode 0
MSB
7 6 7 65 25 2426
High-Z
MSB
Data Out 1 Data Out 2
Figure 51. Write Fast Boot Register (WRFBR) Sequence
21 34567890
MSB
SCLK
CS#
SI
17h
Command
Mode 3 37 38 39
Mode 0
Fast Boot Register
SO
High-Z
7 6 25 2426
10
5
Figure 52. Erase Fast Boot Register (ESFBR) Sequence
21 34567
High-Z
0
18h
Command
SCLK
SI
CS#
SO
Mode 3
Mode 0
61
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 53. Sector Erase (SE) Sequence (SPI Mode)
Figure 54. Sector Erase (SE) Sequence (QPI Mode)
10-21. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (Please refer to "5. MEMORY ORGANIZATION")
is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least
signicant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 4-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Sector Erase (SE) instruction will not be executed on the block.
MSB
SCLK
CS#
SI
20h
Command 32-Bit Address
A31 A30 A2 A1 A0
…
…
0 1 2 3 4 5 6 7 8 9 37 38 39
SCLK
SIO[3:0]
CS#
20h
2 3 5 710
MSB
4 6
Command
Mode 3
Mode 0
32-Bit Address
89
A28-
A31
A24-
A27
A20-
A23
A16-
A19
A12-
A15
A8-
A11
A4-
A7
A0-
A3
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Macronix Proprietary
P/N: PM2619
10-22. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "5. MEMORY
ORGANIZATION") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the least signicant bit of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A15] (Am is the most signicant address) select the 32KB block address.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 4-byte address
on SI→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector
Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block.
Figure 55. Block Erase 32KB (BE32K) Sequence (SPI Mode)
Figure 56. Block Erase 32KB (BE32K) Sequence (QPI Mode)
21 34567890
A31 A30 A2 A1 A0
MSB
SCLK
CS#
SI
52h
Command
Mode 3
Mode 0
32-Bit Address
393837
SCLK
SIO[3:0]
CS#
52h
2 3 5 710
MSB
4 6
Command
Mode 3
Mode 0
32-Bit Address
8 9
A28-
A31
A24-
A27
A20-
A23
A16-
A19
A12-
A15
A8-
A11
A4-
A7
A0-
A3
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MX25U25645G 54
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Macronix Proprietary
P/N: PM2619
10-23. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "5. MEMORY
ORGANIZATION") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte
boundary (the least signicant bit of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 4-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),
the Block Erase (BE) instruction will not be executed on the block.
Figure 57. Block Erase (BE) Sequence (SPI Mode)
Figure 58. Block Erase (BE) Sequence (QPI Mode)
21 34567890
A31 A31 A2 A1 A0
393837
MSB
SCLK
CS#
SI
D8h
Command
Mode 3
Mode 0
32-Bit Address
SCLK
SIO[3:0]
CS#
D8h
2 310
MSB
4 5 6 7
Command
Mode 3
Mode 0
32-Bit Address
8 9
A28-
A31
A24-
A27
A20-
A23
A16-
A19
A12-
A15
A8-
A11
A4-
A7
A0-
A3
64
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-24. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be
executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".
When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be
executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected
in top or bottom 64K byte block, the protected block will also skip the chip erase command.
Figure 59. Chip Erase (CE) Sequence (SPI Mode)
21 345670
60h or C7h
SCLK
SI
CS#
Command
Mode 3
Mode 0
Figure 60. Chip Erase (CE) Sequence (QPI Mode)
SCLK
SIO[3:0]
CS#
60h or C7h
0 1
Command
Mode 3
Mode 0
65
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-25. Page Program (PP)
The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the
device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256
data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires
that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] species the starting
address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected
page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be
programmed, A[7:0] should be set to 0.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 4-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
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MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
Figure 61. Page Program (PP) Sequence (SPI Mode)
Figure 62. Page Program (PP) Sequence (QPI Mode)
32 ADD Cycles Data Byte 1 Data Byte 256
2080
2081
2082
2083
2084
2085
2086
2087
MSB MSB
SCLK
CS#
SI
02h
Command
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
A31 A30 A29 A3 A2 A1 A0
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
210
SCLK
SIO[3:0]
CS#
02h H255 L255
Data Byte
1
H0 L0
Data Byte
2
H1 L1
Data Byte
3
H2 L2
Data Byte
256
.....
.....
.....
Command
Mode 3
Mode 0
32 ADD Cycles
A28-
A31 A24-
A27 A20-
A23 A16-
A19 A12-
A15 A8-
A11 A4-
A7 A0-
A3
67
MX25U25645G 54
Rev. 1.0, March 12, 2019
Macronix Proprietary
P/N: PM2619
10-26. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to
"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,
SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of
application. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 4-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector
Protect Mode), the Quad Page Program (4PP) instruction will not be executed.
Figure 63. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
A20 A16 A12 A8 A4 A0
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
21 3456789
8 ADD cycles Data
Byte 1
Data
Byte 2
Data
Byte 256
0
A29 A25
A30 A26
A31 A27
A28 A24
SCLK
CS#
SIO0
SIO1
SIO3
SIO2
38h
Command
10 11 12 13 14 15 16 17
…
…
…
…
…
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
18 19 526 527
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10-27. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby
current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
Figure 64. Deep Power-down (DP) Sequence (SPI Mode)
21 345670tDP
Deep Power-down Mode
Stand-by Mode
SCLK
CS#
SI
B9h
Command
Mode 3
Mode 0
Figure 65. Deep Power-down (DP) Sequence (QPI Mode)
SCLK
SIO[3:0]
CS#
B9h
0 1
tDP
Deep Power-down Mode
Stand-by Mode
Command
Mode 3
Mode 0
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10-28. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While device is in secured OTPmode,
main array access is not available. The additional 8K-bit secured OTP is independent from main array and may be
used to store unique serial number for system identier. After entering the Secured OTP mode, follow standard read
or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it
is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Please note that after issuing ENSO command user can only access secure OTP region with standard read or
program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.
10-29. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
10-30. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
10-31. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be
updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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10-32. Write Protection Selection (WPSEL)
There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced
Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection
mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is
disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL
command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the
WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be
programmed back to “0”.
When WPSEL = 0: Block Protection (BP) mode,
The memory array is write protected by the BP3~BP0 bits.
When WPSEL =1: Advanced Sector Protection mode,
Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the
Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS,
RDPASS, PASSULK, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits of
the Status Register are disabled and have no effect.
The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced
Sector Protect mode → CS# goes high.
Write Protection Selection
Start
(Default in BP Mode)
Set
WPSEL Bit
WPSEL=0WPSEL=1
Bit 2 =0
Bit 2 =1
Block Protection
(BP)
Advanced
Sector Protection
Set
Lock Register
Password
Protection
Solid
Protection
Dynamic
Protection
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Figure 66. WPSEL Flow
RDSCUR command
RDSR command
RDSCUR command
WPSEL set successfully
Yes
Yes
WPSEL set fail
No
start
WPSEL=1?
WIP=0? No
WPSEL disable,
block protected by BP[3:0]
Yes
No
WREN command
WPSEL=1?
WPSEL command
WPSEL enable.
Block protected by Advance Sector Protection
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10-33. Advanced Sector Protection
There are two ways to implement software Advanced Sector Protection on this device. Through these two protection
methods, user can disable or enable the programming or erasing op eration to any individual sector or all sectors.
There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main ash array. Each
of the sectors is protected from programming or erasing operation when the bit is set.
The gure below helps describing an overview of these methods. The device is default to the Solid mode when
shipped from factory. The detail algorithm of advanced sector protection is shown as follows:
Figure 67. Advanced Sector Protection Overview
Start
Bit 2=1 Bit 2=0
Password Protection Mode
Set
Lock Register ?
Set
SPB Lock Down Bit ?
(SPBLKDN)
Bit 6 = 0
Bit 6 = 1
SPB Unlocked
SPB is changeable
Solid Protection Bits
(SPB)
Dynamic Protect Bit Register
(DPB)
SPB=1 Write Protect
SPB=0 Write Unprotect
SPB 0
SPB 1
SPB 2
:
:
SPB N-1
SPB N
SA 0
SA 1
SA 2
:
:
SA N-1
SA N
DPB 0
DPB 1
DPB 2
:
:
DPB N-1
DPB N
SPB Locked
All SPB can not be changeable
Solid Protection Mode
Set 64 bit Password
Sector Array
DPB=1 sector protect
DPB=0 sector unprotect
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Figure 68. Read Lock Register (RDLR) Sequence
21 3456789 10 11 12 13 14 15
command
0
76543210
High-Z
MSB
15 14 13 12 11 10 9 8
Register OutRegister Out
MSB
7
SCLK
SI
CS#
SO
2Dh
Mode 3
Mode 0
10-33-1. Lock Register
The Lock Register is a 16-bit register. Lock Register Bit[6] is SPB Lock Down Bit (SPBLKDN) which is assigned to
control all SPB bit status. Lock Register Bit[2] is Password Protection Mode Lock Bit. Both bits are defaulted as 1
when shipping from factory.
When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed.
Users can choose their favorite sector protecting method via setting Lock Register Bit[2] using WRLR command.
The device default status was in Solid Protection Mode (Bit[2]=1), Once Bit[2] has been programmed (cleared to
"0"), the device will enable the Password Protection Mode and lock in that mode permanently.
In Solid Protection Mode (Bit[2]=1, factory default), the SPBLKDN can be programmed using the WRLR command
and permanently lock down the SPB bits. After programming SPBLKDN to 0, all SPB can not be changed anymore,
and neither Lock Register Bit[2] nor Bit[6] can be altered anymore.
In Password Protection Mode (Bit[2]=0), the SPBLKDN becomes a volatile bit with default 0 (SPB bit protected).
A correct password is required with PASSULK command to set SPBLKDN to 1. To clear SPBLKDN back to 0, a
Hardware/Software Reset or power-up cycle is required.
If user selects Password Protection mode, the password setting is required. User can set password by issuing
WRPASS command before Lock Register Bit[2] set to 0.
Lock Register
Bits Description Bit Status Default Type
15 to 7 Reserved Reserved Reserved
6SPB Lock Down bit
(SPBLKDN)
0: SPB bit Protected
1: SPB bit Unprotected
Solid Protection Mode: 1
Password Protection Mode: 0
Bit 2=1: OTP
Bit 2=0: Volatile
5 to 3 Reserved Reserved Reserved
2Password Protection
Mode Lock Bit
0=Password Protection Mode Enable
1= Solid Protection Mode 1 OTP
1 to 0 Reserved Reserved Reserved
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10-33-2. Solid Protection Bits
The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.
The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom
and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits
is “0”, which has the sector/block write-protection disabled.
When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the
sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs
cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must
be executed to set the WEL bit before sending the WRSPB or ESSPB command.
The SPBLKDN bit must be “1” before any SPB can be modied. In Solid Protection mode the SPBLKDN bit defaults to “1”
after power-on or reset. Under Password Protection mode, the SPBLKDN bit defaults to “0” after power-on or reset,
and a PASSULK command with a correct password is required to set the SPBLKDN bit to “1”.
The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the
SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating
write-protection is enabled.
Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.
SPB Register
Bit Description Bit Status Default Type
7 to 0 SPB (Solid protected Bit) 00h= SPB for the sector address unprotected
FFh= SPB for the sector address protected 00h Non-volatile
Figure 69. Write Lock Register (WRLR) Sequence (SPI Mode)
21 3456789 10 11 12 13 14 15
Lock Register In
0
MSB
SCLK
SI
CS#
SO
2Ch
High-Z
Command
Mode 3
Mode 0
16 17 18 19 20 21 22 23
765 4321 0 15 14 13 12 11 10 9 8
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Figure 70. Read SPB Status (RDSPB) Sequence
21 34567890
MSB
SCLK
CS#
SI
SO
E2h
Command
Mode 3 37 38 39 40 41 42
Mode 0
32-Bit Address
A31 A30 A2 A1 A0
76543210
High-Z
MSB
Data Out
43 44 45 46 47
Figure 71. SPB Erase (ESSPB) Sequence
21 34567
High-Z
0
E4h
Command
SCLK
SI
CS#
SO
Mode 3
Mode 0
Figure 72. SPB Program (WRSPB) Sequence
21 34567890
MSB
SCLK
CS#
SI
E3h
Command
Mode 3 37 38 39
Mode 0
32-Bit Address
A31 A30 A2 A1 A0
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10-33-3. Dynamic Write Protection Bits
The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from
unintentional change, and is easy to disable when there are necessary changes.
All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB)
by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector.
The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is
cleared to “0”, the sector can be modied if the SPB state is unprotected state.
DPB Register
Bit Description Bit Status Default Type
7 to 0 DPB (Dynamic protected Bit) 00h= DPB for the sector address unprotected
FFh= DPB for the sector address protected FFh Volatile
Figure 73. Read DPB Register (RDDPB) Sequence
21 34567890
MSB
SCLK
CS#
SI
SO
E0h
Command
Mode 3 37 38 39 40 41 42
Mode 0
32-Bit Address
A31 A30 A2 A1 A0
76543210
High-Z
MSB
Data Out
43 44 45 46 47
Figure 74. Write DPB Register (WRDPB) Sequence
21 34567890
MSB
SCLK
CS#
SI
E1h
Command
Mode 3 37 38 39 40 41 42
Mode 0
32-Bit Address
A31 A30 A2 A1 A0
76543210
MSB
Data Byte 1
43 44 45 46 47
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10-33-4. Password Protection Mode
Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password
Protection mode, the SPBLKDN bit defaults to “0” after a power-on cycle or reset. When SPBLKDN=0, the SPBs
are locked and cannot be modied. A 64-bit password must be provided to unlock the SPBs.
The PASSULK command with the correct password will set the SPBLKDN bit to “1” and unlock the SPB bits. After
the correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will
clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modied. A WREN
command must be executed to set the WEL bit before sending the PASSULK command.
Several steps are required to place the device in Password Protection mode. Prior to entering the Password
Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the
password and the RDPASS command reads back the password. Password verication is permitted until the
Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming
the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it
cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can
neither be retrieved nor reprogrammed.
The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”.
The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password
options. A WREN command must be executed to set the WEL bit before sending the WRPASS command.
● The unlock operation will fail if the password provided by the PASSULK command does not match the stored
password. This will set the P_FAIL bit to “1” and insert a delay before clearing the WIP bit to “0”. User has to
wait 150us before issuing another PASSULK command. This restriction makes it impractical to attempt all
combinations of a 64-bit password (such an effort would take millions of years). Monitor the WIP bit to determine
whether the device has completed the PASSULK command.
● When a valid password is provided, the PASSULK command does not insert the delay before returning the WIP
bit to zero. The SPBLKDN bit will set to “1” and the P_FAIL bit will be “0”.
● It is not possible to set the SPBLKDN bit to “1” if the password had not been set prior to the Password Protection
mode being selected.
Password Register (PASS)
Bits Field
Name Function Type Default State Description
63 to 0 PWD Hidden
Password OTP FFFFFFFFFFFFFFFFh
Non-volatile OTP storage of 64 bit password. The
password is no longer readable after the Password
Protection mode is selected by programming Lock
Register bit 2 to zero.
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Figure 75. Read Password Register (RDPASS) Sequence
Figure 76. Write Password Register (WRPASS) Sequence
Figure 77. Password Unlock (PASSULK) Sequence
2 3 4 5 6 7 8 39 40 47 48 109 110
0 0 0 0
0 1
SCLK
CS#
SI
SO
27h
Command 32-bit Address 8 Dummy
Mode 3
Mode 0
MSB
7 6 57 5658
High-Z High-Z
Data Out
MSB
SCLK
CS#
SI
28h
Command
Mode 3
Mode 0
Password
7 6 58 57 56
SO
High-Z
2 3 4 5 6 7 8 39 40 102 103
0 1
0 0 0 0
32-bit Address
MSB
SCLK
CS#
SI
29h
Command
Mode 3
Mode 0
Password
7 6 58 57 56
SO
High-Z
2 3 4 5 6 7 8 39 40 102 103
0 1
0 0 0 0
32-bit Address
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10-33-5. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based
protected or unprotected operation. It can enable or disable all DPB.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
10-33-6. Sector Protection States Summary Table
Protection Status Sector State
DPB bit SPB bit
0 0 Unprotect
0 1 Protect
1 0 Protect
1 1 Protect
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10-34. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Program or Erase operation to allow the device conduct other operations.
After the device has entered the suspended state, the memory array can be read except for the page being
programmed or the sector being erased.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
When the Serial NOR Flash receives the Suspend instruction, Program Suspend Latency(tPSL) or Erase Suspend
latency(tESL) is required to complete suspend operation. (Refer to "Table 18. AC CHARACTERISTICS") After the
device has entered the suspended state, the WEL bit is clears to “0” and the PSB or ESB in security register is set to “1”,
then the device is ready to acceptanother command.
However, some commands can be executed without tPSL or tESL latency during the program/erase suspend, and
can be issued at any time during the Suspend.
Please refer to "Table 12. Acceptable Commands During Suspend".
Figure 78. Suspend to Read Latency
CS#
tPSL / tESL
Suspend Command Read Command
10-34-1. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page
Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase
operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be
issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to
nish before the suspended erase can be resumed. The Status Register can be polled to determine the status of
the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program
operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 79. Suspend to Program Latency
CS#
tPSL / tESL
Suspend Command
Program Command
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Table 12. Acceptable Commands During Suspend
Command Name Command Code
Suspend Type
Program Suspend Erase Suspend
Commands which require tPSL/tESL delay
READ 03h • •
FAST READ 0Bh • •
2READ BBh • •
DREAD 3Bh • •
4READ EBh • •
QREAD 6Bh • •
4DTRD EDh • •
RDSFDP 5Ah • •
RDID 9Fh • •
QPIID AFh • •
SBL C0h • •
ENSO B1h • •
EXSO C1h • •
WREN 06h • •
RESUME 30h • •
RDLR 2Dh • •
RDSPB E2h • •
RDFBR 16h • •
RDDPB E0h • •
EQIO 35h • •
RSTQIO F5h • •
Commands not required tPSL/tESL delay
WRDI 04h • •
RDSR 05h • •
RDCR 15h • •
RDSCUR 2Bh • •
RES ABh • •
REMS 90h • •
RSTEN 66h • •
RST 99h • •
NOP 00h • •
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10-35. Program Resume and Erase Resume
The Resume instruction resumes a suspended Program or Erase operation. After the device receives the Resume
instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”.The program or erase
operation will continue until it is completed or until another Suspend instruction is received.
To issue another Suspend instruction, the minimum resume-to-suspend latency (tPRS or tERS) is required.
However, in order to nish the program or erase progress, a period equal to or longer than the typical timing is
required.
To issue other command except suspend instruction, a latency of the self-timed Page Program Cycle time (tPP) or
Sector Erase (tSE) is required. The WEL and WIP bits are cleared to “0” after the Program or Erase operation is
completed.
Note:
The Resume instruction will be ignored during Performance Enhance Mode. Make sure the Serial NOR Flash has
exited the Performance Enhance Mode before issuing the Resume instruction.
Figure 80. Resume to Read Latency
CS#
tSE / tBE / tPP
Resume Command Read Command
Figure 81. Resume to Suspend Latency
CS#
tPRS / tERS
Resume
Command
Suspend
Command
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10-36. No Operation (NOP)
The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
during SPI mode.
10-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes
the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed rst to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For details, please refer to "Table 14. Reset Timing-
(Other Operation)" for tREADY2.
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Figure 82. Software Reset Recovery
CS#
Mode
66 99
tREADY2
Stand-by Mode
Figure 83. Reset Sequence (SPI mode)
CS#
SCLK
SIO0 66h
Mode 3
Mode 0
Mode 3
Mode 0
99h
Command Command
tSHSL
Figure 84. Reset Sequence (QPI mode)
MODE 3
SCLK
SIO[3:0]
CS#
MODE 3
99h66h
MODE 0
MODE 3
MODE 0MODE 0
Command Command
tSHSL
Note: Refer to "Table 14. Reset Timing-(Other Operation)" for tREADY2.
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The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial ash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address
bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#
to high at any time during data out.
SFDP is a JEDEC standard, JESD216B.
For SFDP register values detail, please contact local Macronix sales channel for Application Note.
Figure 85. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
23
21 3456789 10 28 29 30 31
22 21 3210
High-Z
24 BIT ADDRESS
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Cycle
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
5Ah
Command
11. Serial Flash Discoverable Parameter (SFDP)
11-1. Read SFDP Mode (RDSFDP)
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12. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Symbol Parameter Min. Typ. Max. Unit
tRHSL Reset# high before CS# low 10 us
tRS Reset# setup time 15 ns
tRH Reset# hold time 15 ns
tRLRH Reset# low pulse width 10 us
tREADY1 Reset Recovery time 35 us
Figure 86. RESET Timing
tRHSL
tRS
tRH
tRLRH
tREADY1 / tREADY2
SCLK
RESET#
CS#
Table 13. Reset Timing-(Power On)
Symbol Parameter Min. Typ. Max. Unit
tRHSL Reset# high before CS# low 10 us
tRS Reset# setup time 15 ns
tRH Reset# hold time 15 ns
tRLRH Reset# low pulse width 10 us
tREADY2
Reset Recovery time (During instruction decoding) 40 us
Reset Recovery time (for read operation) 40 us
Reset Recovery time (for program operation) 310 us
Reset Recovery time(for SE4KB operation) 12 ms
Reset Recovery time (for BE64K/BE32KB operation) 25 ms
Reset Recovery time (for Chip Erase operation) 1000 ms
Reset Recovery time (for WRSR operation) 40 ms
Table 14. Reset Timing-(Other Operation)
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13. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the ash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
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14. ELECTRICAL SPECIFICATIONS
Figure 87. Maximum Negative Overshoot Waveform Figure 88. Maximum Positive Overshoot Waveform
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specication is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Table 15. ABSOLUTE MAXIMUM RATINGS
Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter Min. Typ. Max. Unit Conditions
CIN Input Capacitance 8 pF VIN = 0V
COUT Output Capacitance 8 pF VOUT = 0V
0V
-1.0V
20ns
VCC+1.0V
2.0V
20ns
Rating Value
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.5V to VCC+0.5V
Applied Output Voltage -0.5V to VCC+0.5V
VCC to Ground Potential -0.5V to 2.5V
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Figure 89. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Figure 90. OUTPUT LOADING
AC
Measurement
Level
Input timing reference level Output timing reference level
0.8VCC 0.7VCC
0.3VCC
0.5VCC
0.2VCC
Note: Input pulse rise and fall time are <1ns
DEVICE UNDER
TEST
CL 25K ohm
25K ohm
+1.8V
CL=30pF Including jig capacitance
Figure 91. SCLK TIMING DEFINITION
VIH (Min.)
0.5VCC
VIL (Max.)
tCHCL
tCH
1/fSCLK
tCL
tCLCH
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Table 17. DC CHARACTERISTICS
Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V
Notes :
1. Typical values at VCC = 1.8V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. Pattern = Blank
Symbol Parameter Notes Min. Typ. Max. Units Test Conditions
ILI Input Load Current 1 ±2 uA VCC = VCC Max,
VIN = VCC or GND
ILO Output Leakage Current 1 ±2 uA VCC = VCC Max,
VOUT = VCC or GND
ISB1 VCC Standby Current 1 20 180 uA VIN = VCC or GND,
CS# = VCC
ISB2 Deep Power-down
Current 3 50 uA VIN = VCC or GND,
CS# = VCC
ICC1 VCC Read
(Note 3) 1
25 35 mA
f=100MHz, (DTR 4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
22 30 mA
f=133MHz, (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
18 25 mA
f=104MHz, (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
13 16 mA
f=84MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
ICC2 VCC Program Current
(PP) 1 30 40 mA Program in Progress,
CS# = VCC
ICC3 VCC Write Status
Register (WRSR) Current 20 40 mA Program status register in
progress, CS#=VCC
ICC4
VCC Sector/Block (32K,
64K) Erase Current
(SE/BE/BE32K)
1 30 40 mA Erase in Progress, CS#=VCC
ICC5 VCC Chip Erase Current
(CE) 1 20 40 mA Erase in Progress, CS#=VCC
VIL Input Low Voltage -0.4 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.2 V IOL = 100uA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
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Table 18. AC CHARACTERISTICS
Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V
Symbol Alt. Parameter Min. Typ. Max. Unit
fSCLK fC Clock Frequency for all commands(except Read Operation) D.C. 166 MHz
fRSCLK fR Clock Frequency for READ instructions 66 MHz
fTSCLK Clock Frequency for FAST READ, DREAD, 2READ,
QREAD, 4READ, 4DTRD
see "Dummy Cycle and
Frequency Table (MHz)" MHz
tCH(1) tCLH Clock High Time Others (fSCLK) 45% x (1/
fSCLK) ns
Normal Read (fRSCLK) 7 ns
tCL(1) tCLL Clock Low Time Others (fSCLK) 45% x (1/
fSCLK) ns
Normal Read (fRSCLK) 7 ns
tCLCH Clock Rise Time (peak to peak) 0.1 V/ns
tCHCL Clock Fall Time (peak to peak) 0.1 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 3 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 4 ns
tDVCH /
tDVCL tDSU Data In Setup Time STR 2 ns
DTR 2 ns
tCHDX /
tCLDX tDH Data In Hold Time STR 2 ns
DTR 2 ns
tCHSH CS# Active Hold Time (relative to SCLK) 3 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 3 ns
tSHSL tCSH CS# Deselect Time
From Read to next Read 7 ns
From Write/Erase/Program
to Read Status Register 30 ns
tSHQZ tDIS Output Disable Time 8 ns
tCLQV tV Clock Low to Output Valid
Loading: 30pF 5 ns
Loading: 15pF 4.5 ns
Loading: 10pF 4 ns
tCLQX tHO Output Hold Time 1 ns
tDP CS# High to Deep Power-down Mode 10 us
tRES1 CS# High to Standby Mode without Electronic Signature
Read 30 us
tRES2 CS# High to Standby Mode with Electronic Signature Read 30 us
tW Write Status/Conguration Register Cycle Time 40 ms
tBP Byte-Program 25 60 us
tPP Page Program Cycle Time 0.15 0.75 ms
tPP(4) Page Program Cycle Time (n bytes) 0.016 + 0.009*
(n/16) (5) 0.75 ms
tSE Sector Erase Cycle Time 25 400 ms
tBE32 Block Erase (32KB) Cycle Time 150 1000 ms
tBE Block Erase (64KB) Cycle Time 220 1300 ms
tCE Chip Erase Cycle Time 75 150 s
tESL(7) Erase Suspend Latency 25 us
tPSL(7) Program Suspend Latency 25 us
tPRS(8) Latency between Program Resume and next Suspend 0.3 100 us
tERS(9) Latency between Erase Resume and next Suspend 0.3 400 us
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Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Test condition is shown as Figure 89 and Figure 90.
4. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to
program the whole 256 bytes or only a few bytes between 1~256 bytes.
5. “n”=how many bytes to program(n>2). The number of (n/16) will be round up to next integer.
6. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".
7. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
8. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a
period equal to or longer than the typical timing is required in order for the program operation to make progress.
9. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a
period equal to or longer than the typical timing is required in order for the erase operation to make progress.
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Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the gure, please refer to
Table 18. AC CHARACTERISTICS.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 500000 us/V
15. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 92 and Figure 93 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the gures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 92. AC Timing at Device Power-Up
SCLK
SI
CS#
VCC
MSB IN
SO
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
tVR
VCC(min)
GND
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Figure 93. Power-Down Sequence
CS#
SCLK
VCC
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
Figure 94. Power-up Timing
VCC
VCC(min)
Chip Selection is Not Allowed
tVSL
time
Device is fully accessible
VCC(max)
VWI
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15-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 40h (all Status Register bits are 0 except QE bit: QE=1).
Figure 95. Power Up/Down and Voltage Drop
VCC
Time
VCC (max.)
VCC (min.)
V
tPWD
tVSL
Chip Select is not allowed
Full Device
Access
Allowed
PWD
(max.)
VWI
V_keep
Table 19. Power-Up/Down Voltage and Timing
Symbol Parameter Min. Max. Unit
VPWD
VCC voltage needed to below VPWD for ensuring initialization
will occur 0.8 V
V_keep Voltage that a re-initialization is necessary if VDD drop
below to VKEEP 1.5 V
tPWD The minimum duration for ensuring initialization will occur 300 us
tVSL VCC(min.) to device operation 1500 us
VCC VCC Power Supply 1.65 2.0 V
VWI Write Inhibit Voltage 1.0 1.5 V
When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 95. Power Up/Down and Voltage Drop" and "Table 19. Power-Up/
Down Voltage and Timing" below for more details.
Note: These parameters are characterized only.
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16. ERASE AND PROGRAMMING PERFORMANCE
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 1.8V, and checkerboard pattern.
2. Under worst conditions of 85°C and minimum operation voltage.
3. System-level overhead is the time required to execute the rst-bus-cycle sequence for the programming
command.
Parameter Condition Min. Max. Unit
Data retention 55˚C 20 years
17. DATA RETENTION
18. LATCH-UP CHARACTERISTICS
Min. Max.
Input Voltage with respect to GND on all power pins 1.5 VCCmax
Input current with respect to GND on all non-power pins -100mA +100mA
Test conditions are compliant to JEDEC JDESD78 standard
Parameter Min. Typ. (1) Max. (2) Unit
Write Status Register Cycle Time 40 ms
Sector Erase Cycle Time (4KB) 25 400 ms
Block Erase Cycle Time (32KB) 150 1000 ms
Block Erase Cycle Time (64KB) 220 1300 ms
Chip Erase Cycle Time 75 150 s
Byte Program Time (via page program command) 25 60 us
Page Program Time 0.15 0.75 ms
Erase/Program Cycle 100,000 cycles
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19. ORDERING INFORMATION
Please contact Macronix regional sales for the latest product selection and available form factors.
PART NO. Package Temp.
I/O Conguration H/W
Conguration Remark
Default I/O Dummy
Cycle Addressing
MX25U25645GXDI54 24-Ball BGA
(5x5 ball array)
-40°C to
85°C
Permanent
4 I/O
10
(default)
Permanent
4 Byte
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20. PART NAME DESCRIPTION
MX 25 U IXD 4
Option Code 2:
Describes H/W Configuration
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
XD: 24-Ball BGA (5x5 ball array)
DENSITY & MODE:
25645G: 256Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial NOR Flash
25645G 5
Option Code 1:
Describes I/O Configuration
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21. PACKAGE INFORMATION
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22. REVISION HISTORY
Revision Descriptions Page
June 12, 2018
0.00 1. Initial Release. All
August 06, 2018
0.01 1. Modied Document title as MX25U25645G 54. All
March 12, 2019
1.0 1. Removed "Advanced Information" to align with the product status ALL
2. Modied Serial Input Timing (STR mode/DTR mode) P14
3. Added tDVCL and tCLDX values P91
MX25U25645G 54
101
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specications without notice.
Except for customized products which have been expressly identied in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualied for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/
or distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2018-2019. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit,
Macronix NBit, HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech,
MXSMIO, Macronix vEE, RichBook, Rich TV, OctaRAM, OctaBus, OctaFlash, FitCAM, ArmorFlash. The
names and brands of third party referred thereto (if any) are for identication purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com