NJU8725
-1-
Ver.2005-02-15
CLASS D AMPLIFIER FOR DIGITAL AUDIO
! GENERAL DESCRIPTION
The NJU8725 is an 800mW-output class D
Amplifier featuring 6th ∆Σ modulation. It includes
Digital Attenuator, Mute, and De-emphasis circuits. It
converts digital source input to PWM signal output
which is converted to analog signal with simple
external LC low-pass filter. The NJU8725 realizes
very high power-efficiency by class D operation.
Therefore, it is suitable for battery-powered
applications and others.
! FEATURES
# Stereo BTL Power Amplifier
# Sixth-order 32fS Over Sampling ∆Σ & PWM
# Internal 8fS Over Sampling Digital Filter
# Sampling Frequency : 96kHz (Max.)
# De-Emphasis : 32kHz, 44.1kHz, 48kHz
# System Clock : 256fS
# Digital Processing : Attenuator 107step, LOG Curve
: Mute
# Digital Audio Interface : 16bit, 18bit
: I2S, LSB Justified, MSB Justified
# Short Circuit Protection
# Operating Voltage : 2.4 to 3.6V
# Driving Voltage : VDD to 5.25V
# C-MOS Technology
# Package Outline : SSOP24 / QFN28
! PIN CONFIGURATION
! PACKAGE OUTLINE
NJU8725V
NJU8725KN1
MUTE
OUTLP
VDD
STBY
TEST
VDDL
VSSL
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
OUTLN
VDDL
MODE LRCK
VDDR
OUTRN
VSSR
OUTRP
VDDR
DIN
F2/SCK
F1/REQ
F0/DATA
11
12 13
14
RST
VSS
BCK
MCK
MUTE
VDDL
OUTLP
VSSL
VSSL
OUTLN
VDDL
MODE
RST
VSS
MC
K
BC
K
LRC
K
NC
TEST
STBY
VDD
F0/DAT
A
F1/REQ
F2/SCK
NC
DIN
VDDR
OUTRP
VSSR
VSSR
OUTRN
VDDR
28
1
QFN28 SSOP24
NJU8725
- 2 - Ver.2005-02-15
! BLOCK DIAGR AM
System
Control
MUTE
STB
Y
F0/DAT
A
F2/SC
K
F1/REQ
MODE
RST
32fS 6th ∆Σ
&
PWM
BC
K
LRC
K
DIN
Serial
Audio Data
Interface
8fS
Over Sampling
Digital Filter
MCK
Power On
Reset Circuit
Synchronization
Circuit
VDD
VSS
VDDL
VSSL
OUTLN
VDDR
VSSR
OUT
RP
VDDR
VSSR
OUTRN
VDDL
VSSL
OUT
LP
Short Circuit
Protection
NJU8725
-3-
Ver.2005-02-15
! TERMINAL DESCRIPTION
No.
SSOP24 QFN28 SYMBOL I/O FUNCTION
1 26 VDD − Logic Power Supply, VDD=3.3V
2 27 STBY I
Standby Control Terminal
Low : Standby ON High : Standby OFF
3 28 TEST I
Manufacturer Testing Terminal
Normally connect to GND.
4 1 MUTE I
Mute Control Terminal
Low : Mute ON High : Mute OFF
5 2 VDDL − Lch Power Supply, VDDL=VDD to 5.0V
6 3 OUTLP O Lch Positive Output Terminal
7 4,5 VSSL − Lch Power GND, VSSL=0V
8 6 OUTLN O Lch Negative Output Terminal
9 7 VDDL − Lch Power Supply, VDDL=VDD to 5.0V
10 8 MODE I
Control Mode selection Terminal
Low : Parallel Control Mode High : Serial Control Mode
11 9 RST I
Reset Terminal
Low : Reset ON High : Reset OFF
12 10 VSS − Logic Power GND, VSS=0V
13 11 MCK I
Master Clock Input Terminal
256fS clock inputs this terminal.
14 12 BCK I
Serial Audio Data Bit Clock Input Terminal
This clock must synchronize with MCK input signal.
15 13 LRCK I
L/R Channel Clock Input Terminal
This clock must synchronize with MCK input signal.
16 15 VDDR − Rch Power Supply, VDDR=VDD to 5.0V
17 16 OUTRN O Rch Negative Output Terminal
18 17,18 VSSR − Rch Power GND, VSSR=0V
19 19 OUTRP O Rch Positive Output Terminal
20 20 VDDR − Rch Power Supply, VDDR=VDD to 5.0V
21 21 DIN I Serial Audio Data Input Terminal
22 23 F2/SCK I
MODE=”Low” : Serial Audio Interface Format Selection Terminal 2
MODE=”High” : Control Register Data Shift Clock Input Terminal
The data is fetched into the control register by rise edge of SCK
signal.
23 24 F1/REQ I
MODE=”Low” : Serial Audio Interface Format Selection Terminal 1
MODE=”High” : Control Register Data Request Input Terminal
24 25 F0/DATA I
MODE=”Low” : Serial Audio Interface Format Selection Terminal 0
MODE=”High” : Control Register Data Input Terminal
− 14,22 NC − Non connection
! INPUT TERMIN AL STRUCTURE
V
DD
V
SS
Input Terminal Inside Circuit
NJU8725
- 4 - Ver.2005-02-15
! FUNCTIONAL DESCRIPTION
(1) Signal Output
PWM signals of L channel and R output from OUTLP/LN and OUTRP/RN terminals respectively. These signals
are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from
VDDL, VDDR, VSSL, and VSSR are required high response power supply against voltage fluctuation like as switching
regulator because Output THD is effected by power supply stability.
(2) Master Clock
Master Clock is 256fS clock into MCK terminal for the internal circuit operation clock.
(3) Reset
“L” level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This
initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset
signal. This Reset signal initializes the internal function setting registers also. During initialization, the output
terminals are high-impedance.
(4) 8fS Over Sampling Digital Filter
8fS Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise.
It realizes Attenuation and De-Emphasis function by serial function control.
(5) 32fS 6th ∆Σ & PWM
32fS 6th ∆Σ & PWM convert from Audio data of the 8fS Over Sampling Digital Filter to the 32fS one bit PWM
data.
(6) Short Circuit Protection
Short Circuit Protection protects IC with output terminal of high-impedance condition when output terminal is
shorted to GND or other output terminal.
The high-impedance condition is released automatically with master clock input, not released without master
clock input.
Audio
Hi-Z : high-impedance
Figure 1. Reset Timing
RST
Output
Status Hi-Z BPZ Unmute Audio
BPZ : Charge of bipolar zero
1024/fs
about 350ms
over than 3ms
NJU8725
-5-
Ver.2005-02-15
(7) System Control
(7-1) Standby
Standby functions by “L” level input to the STBY terminal. In busy of Standby, conditions of digital audio
format set, attenuation level, de-emphasis, and attenuator operation time are kept and output terminals are
high-impedance.
(7-2) Control Mode Set
A control mode as shown below is selected by the MODE terminal.
MODE Control Method Function Terminals
0 Parallel Digital Audio interface Format Set F0, F1, F2
1 Serial Control Register serial data input DATA, REQ, SCK
Parallel : Digital Audio Interface Format is set directly by using F0, F1, and F2 terminals.
Serial : NJU8725 is controlled serial input data by 3-wire serial interface using DATA, REQ, and
SCK terminals
By this setting, the function of F0/DATA, F1/REQ, and F2/SCK are changed.
Refer to (8-5)F0,F1,F2 about function of F0, F1, and F2 terminals.
Refer to (8)Control Register about function of DATA, REQ, and SCK terminals.
(7-3) Mute
Mute functions by “L” signal into the MUTE terminal. In busy of mute, a current attenuation value
becomes -∞ by internal digital attenuator. And MUTE is stopped by “H” signal into the MUTE terminal, the
attenuation value returns from -∞ to previous value.
MUTE Attenuation Level
0 -∞
1 Set Value
1024/fS 1024/fS
-∞-∞
Set Value
MUTE
MCK
Attenuation Value
Set Value
Figure 2. Mute Timing
NJU8725
- 6 - Ver.2005-02-15
(8) Serial Audio Data Interface
(8-1) Input Data Format Selection
The digital audio interface format is selected out of I2S, MSB Justified or LSB Justified, and 16 bits or 18
bits data length.
(8-2) Input Timing
Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising
edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as
shown below:
Data Format Rising Edge Falling Edge
I2S Lch Input Register Rch Input Register
MSB Justified Rch Input Register Lch Input Register
LSB Justified Rch Input Register Lch Input Register
BCK and LRCK must be synchronized with MCK.
Figure 3.1. 16 bits I
2
S Data Format
Left Channel
Right Channel
LRC
K
BC
K
DIN 14 0
1
15 13 14 0
1
15 13
Right Channel
Left Channel
Figure 3.2. 16 bits MSB Justified Data Format
LRC
K
BC
K
DIN 13 0
1
14 0
1
1415 1315 15
Figure 3.3. 16 bits LSB Justified Data Format
Left Channel
Right Channel
14 0
12
30 15 14 0
1 2
3
15
LRC
K
BC
K
DIN
NJU8725
-7-
Ver.2005-02-15
(8-3) Failure of Synchronization Operation
If the MCK clock fluctuates over than ±10 clocks against the LRCK and failure of synchronization is
detected the attenuation value is set to -∞. When the LRCK synchronizes with MCK again, the
attenuation value returns from -∞ to previous level.
Normal Operation Out of Sync. Normal Operation
Set Value
-∞
Set Value
1024/fS
Internal Condition
Attenuation Value
Figure 4. Out of Synchronization Operation
Figure 3.4. 18 bits I
2
S Data Format
Left Channel
Right Channel
LRC
K
BC
K
DIN 16 0
1
17 15 16 0
1
17 15
Right Channel
Left Channel
Figure 3.5. 18 bits MSB Justified Data Format
LRC
K
BC
K
DIN 15 0
1
16 0
1
1617 1517 17
Figure 3.6. 18 bits LSB Justified Data Format
Left Channel
Right Channel
16 01
2
3
0 17 16 0 1 2
3
17
LRC
K
BC
K
DIN
NJU8725
- 8 - Ver.2005-02-15
(9) Control Register
When Control Mode is set to Serial control by the Mode terminal, the control register sets various modes.
The Control Data is fetched by the rising edge of F2/SCK and is set into the control register by the rising edge of
F1/REQ. The latest 8 bits data are valid before the F1/REQ rising pulse.
(9-1) Serial Data Format
B7 B6 B5 B4 B3 B2 B1 B0
0 ATTN6 ATTN5 ATTN4 ATTN3 ATTN2 ATTN1 ATTN0
1 0 0 0 0 0 DEMP1 DEMP0
1 0 0 1 F2 F1 F0 MUTE
1 0 1 0 0 0 0 RST
1 1 0 0 0 0 0 TEST
1 1 0 1 0 0 0 0
1 1 1 0 0 MUTT2 MUTT1 MUTT0
1 1 1 1 0 0 0 TRST
Do not set other data excepting this table.
(9-2) ATTN6 to ATTN0
When B7 is “0”, B0 to B6 set the attenuation data. When attenuation data is set, the attenuation value
is changed to the target value in the period of transition time set by MUTT0 to MUTT2. The attenuation
value (ATT) is fixed by following formula.
When ATT is 14h or less, the attenuator is set -∞ at reset. (When Control Mode is Parallel Control, ATT is
fixed 0db.)
ATT=DATA -121[dB] DATA : attenuation point
7Fh=6 dB
7Eh=5dB
7Dh=4dB
:
79h=0dB
:
16h=-99dB
15h=-100dB
14h=-∞
13h=-∞
:
00h=-∞ (initial value)
F1/REQ
F2/SC
K
F0/DAT
A
B7 B6 B5 B4 B3 B2 B1 B0
Figure 5. Control Register Timing
NJU8725
-9-
Ver.2005-02-15
(9-3) DEMP0, DEMP1
DEMP0 and DEMP1 control De-Emphasis on/off and sampling frequency.
DEMP1 DEMP0 De-Emphasis Initial Value
0 0 OFF
!
0 1 32kHz
1 0 44.1kHz
1 1 48kHz
(9-4) MUTE
Mute operation is controlled by the “MUTE” as same as the MUTE terminal control.
MUTE Mute Operation Initial Value
0 OFF
!
1 ON
(9-5) F0, F1, F2
F0, F1, and F2 select Digital Audio Interface Format. As same as the F0/DATA, F1/REQ, and F2/SCK
terminal control.
F0 F1 F2 Interface Format Bit Length Initial Value
0 0 0 I2S 16
!
0 0 1 MSB Justified 16
0 1 0 LSB Justified 16
1 0 0 I2S 18
1 0 1 MSB Justified 18
1 1 0 LSB Justified 18
(9-6) RST
When the RST is “1”, the control register and inner data (Digital filter, PWM modulator) are initialized.
RST Reset Operation Initial Value
0 OFF
!
1 ON
(9-7) TRST
When the TRST is “1”, only inner data (Digital filter, PWM modulator) is initialized.
TRST Data Bus Initialize Initial Value
0 OFF
!
1 ON
(9-8) MUTT2 to MUTT0
MUTT2 to MUTT0 set the attenuator transition time. This transition time is one attenuation step change
time.
MUTT2 MUTT1 MUTT0 Operation Time Initial Value
0 0 0 1 / fS !
0 0 1 2 / fS
0 1 0 4 / fS
0 1 1 8 / fS
1 0 0 16 / fS
1 0 1 32 / fS
1 1 0 64 / fS
1 1 1 128 / fS
NJU8725
- 10 - Ver.2005-02-15
! ABSOLUTE MAXIMUM R ATINGS
(Ta=25°C)
PARAMETER SYMBOL RATING UNIT
Supply Voltage
VDD
VDDL
VDDR
-0.3 to +4.0
-0.5 to +5.5
-0.5 to +5.5
V
V
V
Input Voltage Vin -0.3 to VDD+0.3 V
Operating Temperature Topr -40 to +85 °C
Storage Temperature Tstg -40 to +125 °C
SSOP24 600
Power Dissipation QFN28 PD 640 * mW
* : Mounted on two-layer board of based on the JEDEC.
Note 1) All voltage values are specified as VSS= VSSR= VSSL=0V.
Note 2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using
LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the
electrical characteristics conditions will cause malfunction and poor reliability.
Note 3) Decoupling capacitors should be connected between VDD-VSS, VDDR-VSSR and VDDL-VSSL due to the
stabilized operation.
! ELECTRICAL C HARACTE RISTICS
(Ta=25°C, VDD=VDDL=VDDR=3.3V, fS=44.1kHz, Input Signal=1kHz,
Input Signal Level at Full Scale Output, MCK=256fS, Load Impedance=8Ω,
Measuring Band=20Hz to 20kHz, 2nd-order 34kHz LC Filter (Q=0.85),
unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Note
VDDL, VDDR Supply Voltage VDD - 5.25 V
VDD Supply Voltage 3.0 3.3 3.6 V
Output Power Efficiency Eeff Vo= 0dB 80 - - % 4
Output THD THD Vo=-6dB - - 0.1 %
Output Power Po Vo= 0dB - 800 - mW/ch
S/N SN A weight 85 90 - dB
Dynamic Range Drange A weight 85 90 - dB
Channel Separation Echn EIAJ(1kHz) 60 - - dB
Output Level Difference
Between Lch and Rch CHD - - 3 dB
Maximum Mute Attenuation MAT 90 - - dB
Passband Response PR 20Hz to 20kHz - - ±1 dB
Power Supply Current
At Standby IST Stopping MCK,
BCK, LRCK, DIN - - 10 µA
Power Supply Current
At Operating IDD No-load operating
No signal inputted - 13 20 mA
VIH 0.7VDD - VDD V
Input Voltage VIL 0 - 0.3VDD V
Input Leakage Current ILK - - ±1.0 µA
Note 4)
= × 100
Power Efficiency (%)
OUTL Output Power + OUTR Output Power (W)
VDDL Supply Power + VDDR Supply Power (W)
NJU8725
-11-
Ver.2005-02-15
Note 5) Analog AC Characteristics Test System
Analog AC characteristics test system is shown in Figure 6. The analog AC characteristics of NJU8725
is measured with 2nd-order LC LPF on the test board and Filters in the Audio Analyzer.
2nd-order LPF : fc=34kHz, refer to the LPF on Application Circuit.
Filters : 22Hz HPF + 20kHz 10th-order LPF
(with the A-Weighting Filter at measuring S/N and Dynamic-range)
Digital
Data
Digital Audio
Interface
Receiver Chip
THD
Measuring
Apparatus
Filters
2nd-order
LC LPF
NJU8725 Evaluation Board Audio Analyzer
Figure 6. Analog AC Characteristics Measurement System
NJU8725
NJU8725
- 12 - Ver.2005-02-15
! TIMING CHARACTERISTICS
• Master Clock Input
(Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
MCK Frequency fMCKI 256fS 7.28 - 27.648 MHz
MCK Pulse Width (H) tMCKH 12 - - ns
MCK Pulse Width (L) tMCKL 12 - - ns
Note 6) tMCKI shows the cycle of the MCK signal.
• Reset Input
(Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Reset Low Level Width tRST 3 - - ms
• Digital Audio Signal Interface
(Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Audio DAC Sampling Rate fS 28 - 100 KHz
DIN Setup Time tDS 20 - - ns
DIN Hold Time tDH 20 - - ns
BCK Period tBCLK 1/(128fS)- - ns
BCK Pulse Width (H) tBCKH 20 - - ns
BCK Pulse Width (L) tBCKL 20 - - ns
LRCK Hold Time tBLR 20 - - ns
LRCK Setup Time tLRB 20 - - ns
tMCKH tMCKL
MC
K
RST
tRST
BC
K
DIN
tBCLK
tDS tDH
LRC
K
tLRB t
BCKL t
BCKH tBLR
NJU8725
-13-
Ver.2005-02-15
• Control Register Interface
(Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
F2/SCK Period tSCK 2 - - µs
F2/SCK Pulse Width (H) tSCH 0.8 - - µs
F2/SCK Pulse Width (L) tSCL 0.8 - - µs
F0/DATA Setup Time tDAS 0.8 - - µs
F0/DATA Hold Time tDAH 0.8 - - µs
F1/REQ Pulse Width (H) tREH 1.6 - - µs
F2/SCK Setup Time tRQS 0.8 - - µs
F1/REQ Hold Time tRQH 0.8 - - µs
• Input Signal Rise and Fall Time
(Ta=25°C, VDD=VDDL=VDDR=3.3V, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Rise Time tUP - - 100 ns
Fall Time tDN - - 100 ns
Note 7) All timings are based on 30% and 70% voltage level of VDD.
tREH
tRQH
tDAS
tDAH
F1/REQ
tRQS
F2/SC
K
tSCH
tSCL
tSCK
B7 B6 B5 B4 B3 B2 B1 B0
tDN
tUP
NJU8725
- 14 - Ver.2005-02-15
! APPLICATIO N CIRCUIT
Note 8) De-coupling capacitors must be connected between each power supply pin and GND pin.
Note 9) The power supply for VDDL and VDDR require fast driving response performance such as a switching
regulator for THD.
Note 10) The above circuit shows only application example and does not guarantee the any electrical
characteristics. Therefore, please consider and check the circuit carefully to fit your application.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
NJU8725
VDD
VSS
3.3V 1.0µF
10µF
Digital
Audio
Data
MCK
BCK
LRCK
DIN
Switching
Regulator
100µF
2.2µF
OUTLP
OUTRP
Mode
Control
MODE
F0/DATA
F1/REQ
F2/SCK
RST
STBY
MUTE
TEST VDD
R
2.2µF
2.2µF
VDDL
OUTLN
OUTRN
1.0µF
1.0µF
22µH Speaker
8Ω
22µH Speaker
8Ω
VSSL
VDDL
VSSR
VDDR
2.2µF
2.2µF
A915BY-220M
A915BY-220M
A915BY-220M
22µH
22µH
1.0µF
1.0µF
1(26)
12(10)
13(11)
14(12)
15(13)
21(21)
10(8)
24(25)
23(24)
22(23)
11(9)
2(27)
4(1)
3(28)
6(3)
8(6)
19(19)
17(16)
5(2)
9(7)
7(4,5)
20(20)
16(15)
18(1
7,
18)
•A915BY-220M is manufactured by TOKO, INC.
For further information, please refer to its technical papers.
* () indicates pin number of QFN28.
