XR77103 Universal PMIC 3-Output Programmable Buck Regulator Description The XR77103 features three synchronous wide input range high efficiency buck converters. Each converter is digitally programmable requiring minimal external components thus providing the smallest size solution possible. The converters can operate in 5V, 9V, and 12V systems and have integrated power switches. The output voltage of each converter can be adjusted by programming the values in the VOUT setting registers through I2C interface. The adjustable range is 0.8 to 6V with 50mV resolution. The output voltage also can be set externally using an external resistor divider. Output sequence among the outputs, soft-start time and the peak inductor current limit are also set through I2C. The switching frequency of the converters can either be set with I2C or can be synchronized to an external clock connected to SYNC pin if needed. The switching regulators are designed to operate from 300kHz to 2.2MHz. Each converter operates in phase or out-of-phase according to the value in the phase setting register. This can minimize the input filter requirements. XR77103 features a supervisor circuit that monitors each converter output. PGOOD pin is asserted once sequencing is done, all outputs are reported in regulation, and the reset timer expires. The polarity of the signal is active high. XR77103 also features a light load pulse skipping mode (PSM). It is set through I2C. The PSM mode allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. REV1C FEATURES 4.5V to 14V wide input supply voltage range Built-In MOSFET and synchronous rectifier I2C programmable supplies Output voltage (0.8 to 6V) Power on sequence Soft-start timing Switching frequency (300kHz to 2.2MHz) Individual current limit Optional power saving mode at light loads Non volatile memory (NVM) with up to 10,000 times write operation 0.8V, high accuracy reference (1%) Current-mode control with simple compensation circuit External synchronization Power good Protection Thermal shutdown Overvoltage transient protection Overcurrent protection 32-pin 4mm x 4mm TQFN package APPLICATIONS FPGA and DSP supplies Video processor supplies Applications processor power 1/28 XR77103 Typical Application PGOOD 28 VIN 4 VIN 6 24 PGOOD VCC Internal Supply VIN = 5.5 to 14V PGOOD OSC BST1 XR77103 VIN1 10 VIN2 15 VIN3 31 SYNC LX1 BUCK1 LX1 VOUT1 32 VOUT3 = 0.8 to 6V 30 29 1 2 3 COMP1 BST3 25 9 12 11 VOUT1 = 0.8 to 6V 8 7 LX3 LX3 BST2 BUCK3 VOUT3 LX2 COMP3 LX2 BUCK2 VOUT2 A0 COMP2 NVM nWR VL 23 20 16 14 13 VOUT2 = 0.8 to 6V 17 18 I2C Interface SDA SCL 21 22 EN 26 AGND DGND GND 27 19 5 EP 3.3V Figure 1. Typical Application REV1C 2/28 XR77103 Absolute Maximum Ratings Operating Conditions These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. VIN......................................................................4.5V to 14V VIN1, VIN2, VIN3, LX1, LX2, LX3........................ -0.3V to 18V NOTE: 1. LX# pins' DC range is from -0.3V, transient -1V for less than 10ns. VCC....................................................................4.5V to 5.5V LX#.................................................................-0.3V to 14V(1) Junction temperature range (TJ).................. -40C to 125C XR77103 package power dissipation max at 25C...... 3.4W XR77103 thermal resistance JA.............................. 30C/W VL, EN, SCL, SDA, nWR, A0, VCC..................... -0.3V to 7V PGOOD, SYNC.................................................. -0.3V to 7V BST# to LX#....................................................... -0.3V to 7V AGND, DGND to GND..................................... -0.3V to 0.3V Storage temperature..................................... -65C to 150C Junction temperature.................................................. 150C Power dissipation...................................... Internally Limited Lead temperature (soldering, 10 seconds)................. 260C CDM............................................................................. 700V ESD rating (HBM - human body model)........................ 2kV Electrical Characteristics TA = 25C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a *. Symbol Parameter Conditions * Min * * Typ Max Units 5.5 14 V 4.5 5.5 V Power Supply Characteristics VIN Input voltage range VIN Input voltage range VUVLO UVLO threshold UVLODEGLITCH UVLO deglitch IVIN IVINQ VIN supply current IVINQ_LP VCC tied to VIN for VIN = 5V UV = 0, VIN rising/falling 4.22/4.1 UV = 1, VIN rising/falling 7/6.88 V Rising/falling 110 s EN = GND 250 A 36 mA 2.6 mA EN = high, no load, CCM EN = high, no load, PSM Internal Supply Voltage VCC Internal biasing supply ILOAD = 0mA * IVCC Internal biasing supply current VIN = 12V * VUVLO UVLO threshold for VCC UVLODEGLITCH UVLO deglitch for VCC 4.9 5 5.1 V 10 mA VCC rising 3.8 V VCC falling 3.6 V Falling edge 110 s REV1C 3/28 XR77103 Electrical Characteristics (Continued) TA = 25C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a *. Symbol Parameter Conditions * TSD Thermal shutdown temperature HYTSD Thermal shutdown hysteresis Temperature rising, Non-latch off. TSD release threshold, temperature = TSD-HYTSD TSD_DEGLITCH Thermal shutdown deglitch VOVBUCK Threshold voltage for buck overvoltage Min Typ Max Units Protections 160 C 20 C 110 s Output rising (HS FET will be forced off) 109 % Output falling (HS FET will be allowed to switch) 107 % Buck Converter fSW Switching frequency VOUTx Output voltage range Output voltage resolution I2C control * 0.3 2.2 MHz * 0.8 6 V 0.05 V Adjustable soft-start period range * 0.5 4 ms ILIMx Peak inductor current limit range * 1 4 A ILIMx Peak inductor current limit accuracy Peak inductor current limit set at 3A * 25 25 % RON_HSx HS switch on-resistance VIN = 12V 200 m RON_LS1 LS switch on-resistance of Buck1 VIN = 12V 60 m RON_LS2/3 LS switch on-resistance of Buck2/3 VIN = 12V 80 m IO Output current capability Continuous loading 2(1) A DMAX Maximum duty cycle 95 % tON MIN Minimum on time 120 ns Line regulation (VOX/VINX) VINX = 5.5 to 14V, IOX = 1A 0.5 %VO Load regulation (VOX/IOX) IO = 10 to 90%, IO = MAX 0.5 %VO/A Output voltage accuracy VIN = 12V * -1 Normal 1 5.5V VIN 14V * -2 Normal 2 SYNCRANGE Synchronization range * fSW + 5% SYNCD_MIN Synchronization signal minimum duty cycle * 40 SYNCD_MAX Synchronization signal maximum duty cycle * 2.31 % MHz % 60 % NOTE: 1. Subject to thermal derating. Design must not exceed the package thermal rating. REV1C 4/28 XR77103 Electrical Characteristics (Continued) TA = 25C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a *. Symbol Parameter Conditions * Min Typ Max Units Power Good Reset Generator VUVBUCK Threshold voltage for buck under voltage Output falling, (disabled after tON_HICCUP) 85 Output rising, (PG will be asserted) 90 % tPG_DEGLITCH Deglitch time Rising and falling 11 ms tON_HICCUP Hiccup mode on time VUVBUCKX asserted 12 ms tOFF_HICCUP Hiccup mode off time Once tOFF_HICCUP elapses, all converters will start up again 15 ms tRP Minimum reset period 1 s RPG Power good pull-down on resistance 14 50 Input Threshold (SDA, SCL, nWR, A0) VIH Input threshold high VINPUT rising, VL = 3.3V * 1.52 1.83 V VIL Input threshold low VINPUT falling, VL = 3.3V * 0.98 1.24 V A0, nWR pull up resistor 100 k Input Threshold (SYNC, EN) VIH Input threshold high VINPUT rising * 2.07 2.53 V VIL Input threshold low VINPUT falling * 1.36 1.67 V REV1C 5/28 XR77103 Electrical Characteristics (Continued) TA = 25C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature range are denoted by a *. Symbol Parameter Conditions * Min Typ Max Units I2C Interface VL Supply voltage 3.3 VOL_I2C SDA logic output low voltage fSCL At 3mA sink current V * 0.4 V SCL clock frequency * 400 kHz tHIGH SCL clock high period * 0.6 s tLOW SCL clock low period * 1.3 s tSP I2C spike rejection filter pulse width * 0 tSU;DAT I2C data setup time * 100 tHD;DAT I2C data hold time * 0 tR SDA, SCL rise time CB = total capacitance of bus line in pF * tF SDA, SCL fall time CB = total capacitance of bus line in pF * tBUF I2C bus free time between stop and start * 1.3 s tSU;STA I2C repeated start condition setup time * 0.6 s tHD;STA I2C repeated start condition hold time * 0.6 s tSU;STO I2C stop condition setup time * 0.6 s tVD;DAT I C data valid time * 0.9 s tVD;ACK I2C data valid acknowledge time * 0.9 s CB I C bus capacitive load * 400 pF CSDA SDA input capacitance * 10 pF CSCL SCL input capacitance * 10 pF 2 2 Protocol Bit 7 MSB (A7) START condition (S) tSU;STA tLOW Bit 0 LSB (R/W) Bit 6 (A6) tHIGH Acknowledge (A) 50 ns ns 900 ns 20 + 0.1 x CB 300 ns 20 + 0.1 x CB 300 ns STOP condition (P) 1/fSCL SCL tR tBUF tF tSP SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO Figure 2. I2C Bus Timing Diagram REV1C 6/28 XR77103 BST3 VIN3 LX3 LX3 VIN AGND EN SYNC Pin Configuration 32 31 30 29 28 27 26 25 VOUT3 1 24 PGOOD COMP3 2 23 VL A0 3 22 SCL VIN 4 21 SDA GND 5 20 nWR VCC 6 19 DGND COMP1 7 18 COMP2 VOUT1 8 10 11 12 13 14 15 16 BST1 VIN1 LX1 LX1 LX2 LX2 VIN2 BST2 17 VOUT2 9 Pin Functions Pin Number Pin Name Description 1 VOUT3 Buck 3 output sense pin. 2 COMP3 Compensation pin for Buck 3. Connect a series RC circuit to this pin for compensation. 3 A0 4 VIN(1) IC supply pin. Connect a capacitor as close as possible to this pin and AGND. 5 GND Ground. 6 VCC Internal supply. Connect a ceramic capacitor from this pin to AGND. VCC tied to VIN for VIN = 5V 7 COMP1 Compensation pin for Buck 1. Connect a series RC circuit to this pin for compensation. 8 VOUT1 Buck 1 output sense pin. 9 BST1 Bootstrap capacitor for Buck 1. Connect a bootstrap capacitor from this pin to LX1. 10 VIN1(1) Input supply for Buck 1. Connect a capacitor as close as possible to this pin and PGND. 11 LX1 Switching node for Buck 1. 12 LX1 Switching node for Buck 1. 13 LX2 Switching node for Buck 2. 14 LX2 Switching node for Buck 2. 15 VIN2(1) Input supply for Buck 2. Connect a capacitor as close as possible to this pin and PGND. 16 BST2 Bootstrap capacitor for Buck 2. Connect a bootstrap capacitor from this pin to LX2. 17 VOUT2 Buck 2 output sense pin. 18 COMP2 Compensation pin for Buck 2. Connect a series RC circuit to this pin for compensation. 19 DGND 20 nWR I2C address select pin. A0 is internally pulled HIGH through a 100k pull up resistor. Digital ground. Write protection input for NVM. The data can be written to NVM when this pin is low. This pin is internally pulled high through 100k pull up resistance. NOTE: 1. VIN, VIN1, VIN2, and VIN3 must be tied together. REV1C 7/28 XR77103 Pin Functions (Continued) Pin Number Pin Name Description 21 SDA Data I/O pin for I2C serial interface. 22 SCL Clock input pin for I2C serial interface. 23 VL 24 PGOOD 25 SYNC 26 EN 27 AGND Analog ground. 28 VIN(1) IC supply pin. Connect a capacitor as close as possible to this pin and AGND. 29 LX3 Switching node for Buck 3. 30 LX3 Switching node for Buck 3. 31 VIN3 Input supply for Buck 3. Connect a capacitor as close as possible to this pin and PGND. 32 BST3 Bootstrap capacitor for Buck 3. Connect a bootstrap capacitor from this pin to LX3. - e-PAD Power ground (PGND). Supply pin for I2C interface. Supply 3.3V typically for I2C communication. This pin can be left floating if the I2C interface is not used. Power good output. Open drain output asserted after all converters are sequenced and within regulation. External clock input pin. Connect to AGND when unused. Enable control input. Set EN high to enable converters. (1) NOTE: 1. VIN, VIN1, VIN2, and VIN3 must be tied together. REV1C 8/28 XR77103 Typical Performance Characteristics All data taken at TA = 25C unless otherwise specified. 2 1.5 VOUT/VOUT (%) 1 0.5 Enable 0 Channel 3 -0.5 -1 Channel 2 -1.5 -2 Channel 1 0 0.4 0.8 1.2 1.6 2 IOUT (A) Figure 3. Load Regulation 12VIN, 3.3VOUT, fSW = 1MHz VOUT AC 20MHz Figure 4. Power-up Sequence with Delay 148.0mV VOUT AC 20MHz -132.0mV -66.0mV IOUT IOUT Di/Dt 2.5A/s Di/Dt 2.5A/s Figure 5. 12VIN, 3.3VOUT, fSW = 500kHz Transient Response, 0.5A to 1.0A VOUT AC 20MHz 68.0mV Figure 6. 5VIN, 1.8VOUT, fSW = 500kHz Transient Response, 0.5A to 1.0A 176.0mV VOUT AC 20MHz 132.0mV -120.0mV -164.0mV IOUT IOUT Di/Dt 2.5A/s Di/Dt 2.5A/s Figure 7. 12VIN, 5.0VOUT, fSW = 1MHz Transient Response, 0.5A to 1.0A Figure 8. 5VIN, 3.3VOUT, fSW = 1MHz Transient Response, 0.5A to 1.0A REV1C 9/28 XR77103 Typical Performance Characteristics (Continued) 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Efficiency fSW = 500kHz, TA = 25C, no airflow, only individual channel operating, inductor losses are included. 60 50 40 60 50 40 30 30 20 20 10 10 0 0 0.4 0.8 1.2 IOUT (A) 1.6 0 2 0 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 100 60 50 40 40 30 20 10 10 1.2 IOUT (A) 1.6 0 2 0 100 100 90 90 80 80 70 70 60 50 40 20 10 10 IOUT (A) 1.2 1.6 1.6 2 40 20 0.8 1.2 IOUT (A) 50 30 0.4 0.8 60 30 0 0.4 Figure 12. Efficiency Channel 2, 5VIN 1.8VOUT Efficiency (%) Efficiency (%) Figure 11. Efficiency Channel 2, 12VIN 1.8VOUT 0 2 50 20 0.8 1.6 60 30 0.4 1.2 Figure 10. Efficiency Channel 1, 5VIN 3.3VOUT 100 0 0.8 IOUT (A) Figure 9. Efficiency Channel 1, 12VIN 3.3VOUT 0 0.4 0 2 Figure 13. Efficiency Channel 3, 12VIN 1.2VOUT 0 0.4 0.8 1.2 IOUT (A) 1.6 2 Figure 14. Efficiency Channel 3, 5VIN 1.2VOUT REV1C 10/28 XR77103 Typical Performance Characteristics (Continued) 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Efficiency fSW = 1MHz, TA = 25C, no airflow, only individual channel operating, inductor losses are included. 60 50 40 60 50 40 30 30 20 20 10 10 0 0 0 0.4 0.8 1.2 1.6 2 0 0.4 0.8 IOUT (A) 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 100 60 50 40 50 40 30 20 20 10 10 0 0 0.4 0.8 1.2 1.6 2 0.4 0.8 1.2 1.6 IOUT (A) Figure 17. Efficiency Channel 2, 12VIN 1.8VOUT Figure 18. Efficiency Channel 2, 5VIN 1.8VOUT 100 90 90 80 80 70 70 60 50 40 50 40 30 20 20 10 10 0.4 0.8 1.2 IOUT (A) 1.6 0 2 2 60 30 0 0 IOUT (A) 100 0 2 60 30 0 1.6 Figure 16. Efficiency Channel 1, 5VIN 3.3VOUT Efficiency (%) Efficiency (%) Figure 15. Efficiency Channel 1, 12VIN 3.3VOUT 1.2 IOUT (A) 0 0.4 0.8 1.2 1.6 2 IOUT (A) Figure 19. Efficiency Channel 3, 12VIN 2.5VOUT Figure 20. Efficiency Channel 3, 5VIN 1.2VOUT REV1C 11/28 XR77103 Typical Performance Characteristics (Continued) 4 0.8 3.5 0.7 3 0.6 Power Loss (W) Power Dissipation in Package (W) Thermal Characteristics 2.5 2 1.5 0.5 0.4 0.3 1 0.2 0.5 0.1 0 0 10 20 30 40 50 60 70 TAMBIENT (C) 80 90 0 100 110 120 1.2V 1.8V 3.3V 0 0.8 1.6 2 Figure 22. Channel 1 Power Loss at fSW = 500kHz, VIN = 12V, No Airflow 0.9 0.9 1.2V 1.8V 3.3V 0.8 0.7 1.2V 1.8V 3.3V 0.8 0.7 Power Loss (W) 0.6 0.5 0.4 0.3 0.6 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 0 0 0.4 0.8 1.2 1.6 0 2 0.4 0.8 IOUT (A) 1.2 1.6 2 IOUT (A) Figure 23. Channel 2 Power Loss at fSW = 500kHz, VIN = 12V, No Airflow Figure 24. Channel 3 Power Loss at fSW = 500kHz, VIN = 12V, No Airflow 1.4 1.4 1.2V 1.8V 3.3V 1.2 1.2V 1.8V 3.3V 1.2 1 Power Loss (W) 1 Power Loss (W) 1.2 IOUT (A) Figure 21. Package Thermal Derating Power Loss (W) 0.4 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0 0.4 0.8 1.2 1.6 2 0 IOUT (A) 0.4 0.8 1.2 1.6 2 IOUT (A) Figure 25. Channel 1 Power Loss at fSW = 500kHz, VIN = 5V, No Airflow Figure 26. Channel 2 Power Loss at fSW = 500kHz, VIN = 5V, No Airflow REV1C 12/28 XR77103 Typical Performance Characteristics (Continued) Thermal Characteristics 1.4 1.4 1.2V 1.8V 3.3V 1.2 1 1 Power Loss (W) Power Loss (W) 1.8V 2.5V 3.3V 1.2 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0 0.4 0.8 1.2 1.6 2 0 IOUT (A) 1.6 2 1.4 1.8V 2.5V 3.3V 1.8V 2.5V 3.3V 1.2 1 1 0.8 Power Loss (W) Power Loss (W) 1.2 Figure 28. Channel 1 Power Loss at fSW = 1MHz, VIN = 12V, No Airflow 1.4 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0.4 0.8 1.2 1.6 0 2 0 IOUT (A) 1.2 1.6 2 1.4 1.2V 1.8V 2.5V 3.3V 1 0.8 Figure 30. Channel 3 Power Loss at fSW = 1MHz, VIN = 12V, No Airflow 1.4 1.2 0.4 IOUT (A) Figure 29. Channel 2 Power Loss at fSW = 1MHz, VIN = 12V, No Airflow 1.2V 1.8V 2.5V 3.3V 1.2 1 0.8 Power Loss (W) Power Loss (W) 0.8 IOUT (A) Figure 27. Channel 3 Power Loss at fSW = 500kHz, VIN = 5V, No Airflow 1.2 0.4 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0 0.4 0.8 1.2 1.6 2 0 0.4 0.8 1.2 1.6 IOUT (A) IOUT (A) Figure 31. Channel 1 Power Loss at fSW = 1MHz, VIN = 5V, No Airflow Figure 32. Channel 2 Power Loss at fSW = 1MHz, VIN = 5V, No Airflow REV1C 2 13/28 XR77103 Typical Performance Characteristics (Continued) Thermal Characteristics 1.4 1.2V 1.8V 2.5V 3.3V 1.2 Power Loss (W) 1 0.8 0.6 0.4 0.2 0 0 0.4 0.8 1.2 1.6 2 IOUT (A) Figure 33. Channel 3 Power Loss at fSW = 1MHz, VIN = 5V, No Airflow Functional Block Diagram 28 VIN 4 VIN 6 24 PGOOD VCC Internal Supply PGOOD OSC BST1 XR77103 VIN1 10 VIN2 15 VIN3 31 SYNC LX1 BUCK1 LX1 VOUT1 32 30 29 1 2 3 COMP1 BST3 25 9 12 11 8 7 LX3 LX3 BST2 BUCK3 LX2 VOUT3 COMP3 BUCK2 LX2 VOUT2 A0 COMP2 NVM nWR VL 23 20 16 14 13 17 18 IC Interface 2 SDA SCL 21 22 EN 26 AGND DGND GND 27 19 5 EP Figure 34. Functional Block Diagram REV1C 14/28 XR77103 Applications Information Operation XR77103 is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. XR77103 can support 4.5V to 14V input supply, high load current, 300kHz to 2.2MHz clocking. The buck converters have an optional PSM mode which can improve power dissipation at light loads. Alternatively, the device implements a constant frequency mode. The wide switching frequency of 300kHz to 2.2MHz allows for efficiency and size optimization. The switching frequency is adjustable by writing data through I2C. The SYNC pin also provides means to synchronize the power converter to an external clock signal. Input ripple is reduced by 180 degree out-of-phase operation among converters. All three buck converters have peak current mode control which simplifies external frequency compensation. Each buck converter has an individual peak inductor current limit which is set through I2C. The adjustable current limit enables high efficiency design with smaller and less expensive inductors. The device has a power good comparator monitoring the output voltages. Each converter has its own soft-start independently controlled through I2C. Continuous Conduction Mode (CCM) This is a natural mode of a synchronous buck converter. Advantage of the CCM mode is that the switching frequency is always constant and allows for better EMI control in the system. The downside of CCM mode is that at light loads system efficiency will become lower. Pulse Skipping Mode (PSM) In order to improve efficiency at light load the device implements two functions. Both functions are enabled simultaneously. One function is a Zero Current Detect comparator (ZCD) which detects zero current in the inductor and turns off synchronous MOSFET, preventing negative inductor current. This ensures that the device enters DCM mode as the load decreases. In this mode the device still operates at a constant frequency. The second function is an internal skip comparator. This comparator detects low level of output current. If this low level is detected the device will start to skip pulses. This is done to improve light load efficiency by effectively reducing switching frequency. For details contact powertechsupport@exar.com. Output Voltage Setting Output voltage of each converter can be programmed by I2C interface. It can be set from 0.8V to 6V with 6-bit resolution. The registers 00h to 02h are allocated to setting each output of the converters. Alternatively, output voltages can be set externally using external resistor dividers. Setting EXTx (bit 7) of the registers 00h to 02h allows external resistor divider for feedback. Output voltage is determined by the following equation. VOX = 0.8V x 1 + R1 R2 VtOX RP = 1 x 106 fSW VOX R1 XR77103 XR77103 R2 Figure 35. Output Voltage Setting This feature can make the device applicable to AVS (automatic voltage scaling) system. Output voltage can be adjusted automatically by external DC voltage. Figure 36 shows application circuit of supply for AVS system. REV1C VOX XR77103 AVS SUPPLY SOC R1 RDAC VOUTX VDAC PVT MNT R2 Figure 36. AVS Control 15/28 XR77103 Applications Information (Continued) Frequency Compensation In order to properly frequency compensate the device, the following component selection is recommended. The table below is for 2A loads. VIN (V) VOUT (V) L (H) COUT (F) RCOMP (k) CCOMP (nF) The soft-start times are relative to switching frequency. They scale with switching frequency. 500kHz Switching Frequency 12/5.0 1.0 2.2 22 x 3 10 4.7 12/5.0 1.2 2.2 22 x 3 10 4.7 12/5.0 1.5 3.3 22 x 3 20 4.7 12/5.0 1.8 3.3 22 x 2 20 4.7 12/5.0 2.5 4.7 22 x 2 20 4.7 12/5.0 3.3 4.7 22 x 1 20 4.7 12 5.0 6.8 22 x 1 20 4.7 Soft-start Time Setting Soft-start time of each converter can be set individually (see Figure 36). Lower 3 bits of the registers 03h, 04h and 05h are allocated to setting the soft-start time of Buck 1, Buck 2 and Buck 3 respectively. At switching frequency set at 1MHz, the available soft-start range is from 0.5ms to 4ms with a 0.5ms step. At switching frequency set at 500kHz, the available soft-start range is from 1ms to 8ms with a 1ms step. EN 1MHz Switching Frequency VOUT1 5.0 1.0 1.5 22 x 3 10 4.7 5.0 1.2 1.5 22 x 3 10 4.7 5.0 1.5 1.5 22 x 2 20 4.7 12/5.0 1.8 1.5 22 x 2 20 4.7 12/5.0 2.5 3.3 22 x 1 20 4.7 12/5.0 3.3 3.3 22 x 1 20 4.7 12 5.0 3.3 22 x 1 20 4.7 For configurations not listed powertechsupport@exar.com. above tDLY1 tSS3 VOUT2 tDLY2 tSS2 VOUT3 tDLY3 contact Switching Frequency Setting Switching frequency can be set from 300kHz to 2.2MHz with a 100kHz step. Lower 5 bits of the register 09h are allocated to setting the switching frequency. Current Limit Setting Peak inductor current limit level of each converter can be set individually from 1A to 4A with a 0.5A step. Lower 3 bits of the registers 06h, 07h and 08h are allocated to setting the peak inductor current limit of Buck 1, Buck 2 and Buck 3 respectively. tSS3 Figure 37. Programmable Soft-start Time and Delay Time of each Converter Delayed Start-Up All outputs start up once EN pin is high and select bits of each converter are set. If a delayed start-up is required on any of the buck converters, set delay time of each converter. The bits [6:4] of the registers 03h, 04h and 05h are allocated to setting delay time of Buck 1, Buck 2 and Buck 3 respectively. The soft-start delay times are relative to switching frequency. They scale with switching frequency. At switching frequency set at 1MHz, the available soft-start delay time range is from 0ms to 35ms with a 5ms step. At switching frequency set at 500kHz, the available soft-start delay time range is from 0ms to 70ms with a 10ms step. REV1C 16/28 XR77103 Applications Information (Continued) Synchronization The status of the SYNC pin will be ignored during start-up and the XR77103's control will only synchronize to an external signal after the PGOOD signal is asserted. When synchronization is applied, the PWM oscillator frequency must be lower than the sync pulse frequency to allow the external signal trumping the oscillator pulse reliably. When synchronization is not applied, the SYNC pin should be connected to AGND. Two Buck Regulators in Parallel Operation (Current Sharing) The XR77103 can be used in parallel operation to increase output current capacity. Figure 39 shows one of possible configurations. To enable this a user needs: Hardware Configuration a) To connect both VOUTx together. b) To connect both COMPx together. Although the device can lock to external clock running up to 2.31MHz, doing this will alter the start-up times, start-up delays and PGOOD delays, and there will be higher losses than what is shown in Figures 22-33. For details contact powertechsupport@exar.com. Out-of-Phase Operation All converters operate in phase, or one converter operates 180 degrees out-of-phase with the other two converters (see Figure 38). The phase shift among the converter is programmable. The bits 6, 5 of the register 09h are allocated for this feature. This enables the system, having less input ripple, to lower component cost, save board space and reduce EMI. Software Configuration a) To set 180 out-of-phase operation between buck regulators (register 09h). b) Programming both VOUTx to the same output. Then, two out of three bucks will run in parallel and load current is shared in average. The ideal case is to use Buck 2 and Buck 3 in parallel operation since they are both identical in design. LX2 LX2 BUCK2 LX1 LX1 LX2 LX2 LX3 COMP3 Buck1 and Buck2/3 are 180 out-of-phase LX1 LX1 LX2 LX2 LX3 LX3 Buck3 and Buck1/2 are 180 out-of-phase VOUT2 COMP2 LX3 All converters in phase VOUT BUCK3 LX3 LX3 VOUT3 Buck2 and Buck1/3 are 180 out-of-phase Figure 39. Parallel Operation Figure 38. Out-of-Phase Operation REV1C 17/28 XR77103 Applications Information (Continued) Power Good The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when selected buck converters' outputs are more than 90% of their nominal output voltage and the PGOOD reset timer expires. The polarity of the PGOOD is active high. The PGOOD reset time is determined by following equation. Figure 40 shows the relationship between switching R1example, when frequency and the PGOOD VOX = reset 0.8V xtime. 1 +For R2 the switching frequency is 1MHz, the PGOOD reset time is 1s. In case VIN is below 8V, writing to NVM is not possible in which case the nWR pin must be pulled high or left floating to assure reliable writing to run time registers. tRP = 1 x 106 fSW 3.50 VL VIN EN nWR I2C Write Behavior 3.3V 8V LOW LOW Write to NVM, values loaded to run-time registers 3.3V 8V HIGH LOW Not supported 3.3V 8V X LOW Write has no effect 3.3V 4.5V to 14V LOW HIGH Write to run-time registers with offsets > 02h 3.3V 4.5V to 14V HIGH HIGH Not supported 3.3V 4.5V to 14V X HIGH Write to run-time registers with offsets 02h PGOOD Reset Time(s) 3.00 In addition, the nWR pin state determines where data gets read from in case a read I2C command is transmitted on the bus. When initiating read transaction while the nWR pin is pulled high or left floating, the data is read from the run time registers. Reading run time registers can be done at any time. 2.50 2.00 1.50 1.00 On the other hand if the nWR pin is pulled low at the time when a read transaction is sent, the data is read from NVM. It is recommended not to permanently pull the nWR pin low. In designs where the nWR pin is pulled low permanently, the host shall not initiate read transaction while channels are enabled. Failing to do so will cause regulation interruption. Reading in this scenario shall be done while EN is low and channels are shut down. 0.50 0.00 0.5 1.0 1.5 Switching Frequency (MHz) 2.0 Figure 40. PGOOD Reset Time vs. fSW Selectable UVLO Threshold The threshold for UVLO is selectable (7V/4.2V). When input voltage is higher, 9V and 12V for example, both settings can be used. However, when the input voltage is 5V, the UVLO setting must be 4.2V. Supply Voltage for Data Programming and Writing to NVM VL is the supply voltage for I2C interface and is required for all I2C transactions. The VL pin can be left floating if the I2C interface is not used. To write data to NVM, VIN must be 8V or higher. The state of the nWR pin determines where the data gets written to. If the nWR pin is pulled low to ground, the data is written to the NVM. The I2C write transaction can start immediately after the nWR pin has been pulled low. A 100ms delay shall be added in between consecutive I2C writes to the NVM. After each byte is written to NVM location, the data gets automatically transferred to the run time equivalent register. If the nWR pin is pulled high or left floating, the data gets written to run time registers. VL VIN EN nWR I2C Read Behavior 3.3V 4.5V to 14V LOW LOW Read from NVM (when all channels are disabled) 3.3V 4.5V to 14V HIGH LOW Not supported 3.3V 4.5V to 14V X HIGH Read from run-time registers At power-on, the run-time registers are loaded with their default values from the NVM. This process takes approximately 200s. No I2C operation should be performed during this time. REV1C 18/28 XR77103 Applications Information (Continued) Thermal Design Proper thermal design is critical in controlling device temperatures and in achieving robust designs. There are a number of factors that affect the thermal performance. One key factor is the temperature rise of the devices in the package, which is a function of the thermal resistances of the devices inside the package and the power being dissipated. I2C Bus Interface The XR77103 features an I2C compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the IC and the master device at clock rates up to 400kHz. The I2C interface follows all standard I2C protocols. Some information is provided below. For additional information, refer to the I2C-bus specifications. The thermal resistance of the XR77103 (30C/W) is specified in the Operating Conditions section of this datasheet. The JA thermal resistance specification is based on the XR77103 evaluation board operating without forced airflow. Since the actual board design in the final application will be different, the thermal resistances in the final design may be different from those specified. The package thermal derating and power loss curves are shown in Figures 21 through 33. These correspond to input voltages of 12V and 5V, and 500kHz and 1MHz switching frequencies. Layout Guidelines Proper PCB layout is crucial in order to obtain a good thermal and electrical performance. For thermal considerations it is essential to use a number of thermal vias to connect the central thermal pad to the ground layer(s). In order to achieve good electrical and noise performance following steps are recommended: Place the output inductor close to the LX pins and minimize the area of the connection. Doing this on the same layer is advisable. Central thermal pad, PGND, shall be connected as many layers as possible for good thermal performance. The input capacitors connected between VIN1, VIN2, VIN3 and PGND represent an AC current loop which should be minimized. PGND should connect to the system ground with vias placed at the output filtering capacitors. SDA SCL S P START Condition STOP Condition Figure 41. I2C Start and Stop Conditions Start Condition The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41. Slave Address Cycle After the start condition, the first byte sent by the master is the 7-bit address and the read/write direction bit R/W on the SDA line. If the address matches the XR77103's internal fixed I2C slave address, the XR77103 will respond with an acknowledge by pulling the SDA line low for one clock cycle while SCL is high. Data Cycle After the master detects this acknowledge, the next byte transmitted by the master is the sub-address. This 8-bit sub-address contains the address of the register to access. The XR77103 Register Map is on page 20. The AC current loop created by the output inductors, output filtering capacitors, and the regulator pins should also be minimized. However this loop is less critical than the input capacitors. GND, AGND, DGND can all be connected at the device and be connected to system ground at the output capacitor. Compensation networks shall be placed close to the pins and referenced to AGND. VCC bypass capacitor shall be placed close to the pin and connected to AGND. REV1C 19/28 XR77103 Applications Information (Continued) Stop Condition To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high, as shown in Figure 41. Figures 42 and 43 illustrate a write and a read cycle. For complete details, see the I2C-bus specifications. SLAVE ADDRESS S W A REGISTER ADDRESS A DATA A P NOTES: White Block = host to XR77103, Orange Block = XR77103 to host. Figure 42. Master Writes to Slave SLAVE ADDRESS S W A REGISTER ADDRESS A SLAVE ADDRESS S R A DATA NA P NOTES: White Block = host to XR77103, Orange Block = XR77103 to host. Figure 43. Master Reads from Slave Slave Address The slave address is one byte of data which is used as the unique identifier. The first 7 bits of the slave address are hardcoded and the least significant bit (LSB) of the slave address byte is the read/write (R/W) bit which is used to determine whether a command is a write command or a read command. The slave address is the first byte of information sent to the device after the START condition. Table below shows the possible slave addresses for the XR77103. Device Address (A0 = Low) Address (A0 = High) XR77103 0x74 0x75 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 0 1 0 A0 R/W Register Map Register Address Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Factory Default NVM Value Register Name Bit 7 00h VBUCK1 EXT1 01h VBUCK2 EXT2 02h VBUCK3 EXT3 03h Soft-start and Delay 1 - DLY1 [2:0] - SST1 [2:0] 04h Soft-start and Delay 2 - DLY2 [2:0] - SST2 [2:0] 05h Soft-start and Delay 3 - DLY3 [2:0] - SST3 [2:0] 06h Current Limit 1 - - - - - LIM1 [2:0] 07h Current Limit 2 - - - - - LIM2 [2:0] 08h Current Limit 3 - - - - - LIM3 [2:0] 09h Switching Frequency and Phase - PHS [1:0] - FRQ [4:0] - - - - 42h 0Ah PWR - UV - - PSM Buck3 Buck2 Buck1 7Fh VBUCK1 [6:0] VBUCK2 [6:0] VBUCK3 [6:0] REV1C 00h 15h 05h 20/28 XR77103 Applications Information (Continued) VBUCK1 Register (00h) The VBUCK1 register has 7 bits of data for setting output of Buck 1 and 1 bit of data for use of external feedback voltage through a resistor divider. The Buck 1 programmable voltage range is from 0.8V to 6V with 0.05V resolution. When EXT1 is set to 1, the output voltage is adjusted by the external resistor divider from the output to ground with the center tap connected to VOUT1 pin regardless of the value of the output voltage setting register. The factory default NVM value is 00h (0.8V). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT1 D6 D5 D4 D3 D2 D1 D0 Hex VOUT (V) Hex VOUT (V) Hex VOUT (V) Hex VOUT (V) 00 0.8 1A 2.1 35 3.45 50 4.8 01 0.85 1B 2.15 36 3.5 51 4.85 02 0.9 1C 2.2 37 3.55 52 4.9 03 0.95 1D 2.25 38 3.6 53 4.95 04 1 1E 2.3 39 3.65 54 5 05 1.05 20 2.4 3A 3.7 55 5.05 06 1.1 21 2.45 3B 3.75 56 5.1 07 1.15 22 2.5 3C 3.8 57 5.15 08 1.2 23 2.55 3D 3.85 58 5.2 09 1.25 24 2.6 3E 3.9 59 5.25 0A 1.3 25 2.65 40 4 5A 5.3 0B 1.35 26 2.7 41 4.05 5B 5.35 0C 1.4 27 2.75 42 4.1 5C 5.4 0D 1.45 28 2.8 43 4.15 5D 5.45 0E 1.5 29 2.85 44 4.2 5E 5.5 10 1.6 2A 2.9 45 4.25 60 5.6 11 1.65 2B 2.95 46 4.3 61 5.65 12 1.7 2C 3 47 4.35 62 5.7 13 1.75 2D 3.05 48 4.4 63 5.75 14 1.8 2E 3.1 49 4.45 64 5.8 15 1.85 30 3.2 4A 4.5 65 5.85 16 1.9 31 3.25 4B 4.55 66 5.9 17 1.95 32 3.3 4C 4.6 67 5.95 18 2 33 3.35 4D 4.65 68 6 19 2.05 34 3.4 4E 4.7 REV1C 21/28 XR77103 Applications Information (Continued) VBUCK2 Register (01h) The VBUCK2 register has 7 bits of data for setting output of Buck 2 and 1 bit of data for use of external feedback voltage through a resistor divider. The Buck 2 programmable voltage range is from 0.8V to 6V with 0.05V resolution. When EXT2 is set to 1, the output voltage is adjusted by the external resistor divider from the output to ground with the center tap connected to VOUT2 pin regardless of the value of the output voltage setting register. The factory default NVM value is 00h (0.8V). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT2 D6 D5 D4 D3 D2 D1 D0 SST1 and DLY1 Register (03h) Soft-start time 1 and delay time 1 register has 6 effective bits. Three bits are for setting soft-start time of Buck 1 and three bits are for setting delay time from EN to Buck 1 start-up. The factory default soft-start and delay times are 6ms and 10ms respectively at 500kHz switching frequency. Both soft-start and delay times are relative to the switching frequency. They will be two times smaller at 1MHz switching frequency. VBUCK3 Register (02h) The VBUCK3 register has 7 bits of data for setting output of Buck 3 and 1 bit of data for use of external feedback voltage through a resistor divider. The Buck 3 programmable voltage range is from 0.8V to 6V with 0.05V resolution. When EXT3 is set to 1, the output voltage is adjusted by the external resistor divider from the output to ground with the center tap connected to VOUT3 pin regardless of the value of the output voltage setting register. The factory default NVM value is 00h (0.8V). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT3 D6 D5 D4 D3 D2 D1 D0 REV1C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X D6 D5 D4 X D2 D1 D0 D2 D1 D0 tSS (ms) at fSW = 500kHz tSS (ms) at fSW = 1MHz 0 0 0 1 0.5 0 0 1 2 1 0 1 0 3 1.5 0 1 1 4 2 1 0 0 5 2.5 1 0 1 6 3 1 1 0 7 3.5 1 1 1 8 4 D6 D5 D4 tDLY (ms) at fSW = 500kHz tDLY (ms) at fSW = 1MHz 0 0 0 0 0 0 0 1 10 5 0 1 0 20 10 0 1 1 30 15 1 0 0 40 20 1 0 1 50 25 1 1 0 60 30 1 1 1 70 35 22/28 XR77103 Applications Information (Continued) SST2 and DLY2 Register (04h) Soft-start time 2 and delay time 2 register has 6 effective bits. Three bits are for setting soft-start time of Buck 2 and three bits are for setting delay time from EN to Buck 2 start-up. The factory default soft-start and delay times are 6ms and 10ms respectively at 500kHz switching frequency. Both soft-start and delay times are relative to the switching frequency. They will be two times smaller at 1MHz switching frequency. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X D6 D5 D4 X D2 D1 D0 Current Limit 2 Register (07h) Current limit 2 register has 3 effective bits. The factory default value is 3.5A (05h). Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X D6 D5 D4 X D2 D1 D0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X D2 D1 D0 Current Limit 3 Register (08h) Current limit 3 register has 3 effective bits. The factory default value is 3.5A (05h). SST3 and DLY3 Register (05h) Soft-start time 3 and delay time 3 register has 6 effective bits. Three bits are for setting soft-start time of Buck 3 and three bits are for setting delay time from EN to Buck 3 start-up. The factory default soft-start and delay times are 6ms and 10ms respectively at 500kHz switching frequency. Both soft-start and delay times are relative to the switching frequency. They will be two times smaller at 1MHz switching frequency. Bit 7 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X D2 D1 D0 Current Limit 1 Register (06h) Current limit 1 register has 3 effective bits. The factory default value is 3.5A (05h). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X D2 D1 D0 D2 D1 D0 ILIM1(A) 0 0 0 1 0 0 1 1.5 0 1 0 2 0 1 1 2.5 1 0 0 3 1 0 1 3.5 1 1 0 4 REV1C 23/28 XR77103 Applications Information (Continued) Switching Frequency and Phase Register (09h) Switching frequency and phase register has 7 effective bits. The 5 least significant bits are setting switching frequency. The factory default value is 500kHz (00010b). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X D6 D5 D4 D3 D2 D1 D0 D [4:0] Hex fSW [MHz] D [4:0] Hex fSW [MHz] 00 0.3 0A 1.3 01 0.4 0B 1.4 02 0.5 0C 1.5 03 0.6 0D 1.6 04 0.7 0E 1.7 05 0.8 0F 1.8 06 0.9 10 1.9 07 1 11 2 08 1.1 12 2.1 09 1.2 13 2.2 PWR Register (0Ah) PWR register has 5 effective bits. The bits 0-2 select which channels will be enabled at transition of ENABLE pin from low to high. The state of the bit 3 determines whether buck converters operate in Pulse Skipping Mode or not. Setting this bit to 1 allows Pulse Skipping Mode operation to minimize power losses at light load levels. The bit 6 determines threshold voltage for VIN UVLO. The factory default of this register is 7Fh. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X UV X X PSM BUCK 3 BUCK 2 BUCK 1 0 1 D0 BUCK 1 Not Used Select D1 BUCK 2 Not Used Select D2 BUCK 3 Not Used Select D3 PSM Disable Enable D6 UV 4.2V 7V The bits 5 and 6 are for setting phase shift among buck converters. The factory default value is channel 3 180 out-of-phase in respect to the channels 1 and 2 (10b). D6 D5 Phase Shift 0 0 All converters operate in phase 0 1 Buck1 and Buck2/3 operate 180 out-of-phase 1 0 Buck1/2 and Buck3 operate 180 out-of-phase 1 1 Buck1/3 and Buck2 operate 180 out-of-phase REV1C 24/28 XR77103 Applications Information (Continued) Typical Applications VOUT3 VIN LOUT_CH3 VIN VIN3 COUT_CH3 C2_IN CBST_CH3 47nF C1_IN EN SYNC CIN_CH3 RGND VIN3 A0 SCL 4 VIN SDA 5 GND 6 VCC 7 COMP1 DGND COMP2 VOUT1 VIN1 VL SCL 22 21 SDA 20 nWR 19 CP_CH2 18 17 CC_CH2 BST2 VIN2 PG 23 VIN2 CIN_CH1 VOUT1 RC_CH2 VOUT2 VIN2 VIN1 24 16 LX2 15 14 LX2 VOUT2 9 VOUT1 nWR XR77103 BST1 CC_CH1 SYNC 25 3 8 RC_CH1 AGND 27 EN 26 VL LX1 CP_CH1 COMP3 13 CVCC 2 LX1 VIN PGOOD 12 A0 VOUT3 VIN1 VCC RPG 1 11 CP_CH3 LX3 29 VIN 28 CC_CH3 10 RC_CH3 e-PAD 33 BST3 32 VOUT3 VIN3 31 LX3 30 VCC CIN_CH2 CBST_CH1 47nF CBST_CH2 47nF LOUT_CH2 LOUT_CH1 COUT_CH1 VOUT2 COUT_CH2 Figure 44. Typical Applications Schematic REV1C 25/28 XR77103 Mechanical Dimensions TOP VIEW BOTTOM VIEW SIDE VIEW TERMINAL DETAILS Drawing No.: POD-00000079 Revision: C REV1C 26/28 XR77103 Recommended Land Pattern and Stencil TYPICAL RECOMMENDED LAND PATTERN TYPICAL RECOMMENDED STENCIL Drawing No.: POD-00000079 Revision: C REV1C 27/28 XR77103 Order Information(1) Part Number Operating Temperature Range Lead-Free Package -40C TJ 125C Yes(2) 32-pin, 4mm x 4mm TQFN package XR77103ELB XR77103ELBTR XR77103EVB-DEMO-1 XR77103 evaluation board XR77103EVB-DEMO-1-KIT XR77103 evaluation board with interface board and software Packaging Method Bulk Tape and Reel NOTE: 1. Refer to www/exar.com/XR77103 for most up-to-date Ordering Information. 2. Visit www.exar.com for additional information on Environmental Rating. Revision History Revision Date 1A March 2016 1B May 2016 1C November 2017 Corporate Headquarters: 5966 La Place Court Suite 100 Carlsbad, CA 92008 Tel.:+1 (760) 692-0711 Fax: +1 (760) 444-8598 www.maxlinear.com Description Initial Release Clarified Pin Descriptions. Added description for Continuous Conduction Mode and Pulse Skipping Mode. Added I2C Bus Timing waveform and updated I2C symbols and functional description. Added details for NVM programming and behavior. Added factory default NVM value to Register Map table. Updated Application Circuit. Updated layout guidelines. Added MaxLinear logo. Updated format and ordering information format. Changed Packaging Description section name to Mechanical Dimensions and Recommended Land Pattern and Stencil. Corrected typo on Mechanical Dimensions, dimension A. High Performance Analog: 1060 Rincon Circle San Jose, CA 95131 Tel.: +1 (669) 265-6100 Fax: +1 (669) 265-6101 Email: powertechsupport@exar.com www.exar.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. 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Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated. (c) 2016 - 2017 MaxLinear, Inc. All rights reserved XR77103_DS_112117 REV1C 28/28