M48T212A-85MH6TR - STMicroelectronics

1/30May 2002

M48T212A

3.3V TIMEKEEPERSUPERVISOR

FEATURES SUMMARY

■INTEGRATED REAL TIME CLOCK, POWER-

FAIL CONTROL CIRCUIT

■CONVERTS LOW POWER SRAM INTO

NVRAMs

■YEAR 2000 COMPLIANT (4-Digit Year)

■BATTERY LOW FLAG

■MICROPROCESSOR POWER-ON RESET

■PROGRAMMABLE ALARM OUTPUT ACTIVE

IN THE BATTERY BACKED-UP MODE

■WATCHDOG TIMER

■AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■WRITE PROTECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T212A: VCC = 3.0 to 3.6V

2.7V ≤ VPFD ≤ 3.0V

■PACKAGING INCLUDES A 44-LEAD SOIC

■USES SUPER CAPACITOR OR LITHIUM

BATTERY (User Supplied)

Figure 1. 44-pin SOIC Package

SO44 (MH)

M48T212A

2/30

TABLE OF CONTENTS

DESCRIPTION . . ..................................................................4

Logic Diagram(Figure 2.) . ........................................................4

Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . .....................................4

SOIC Connections (Figure 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Hardware Hookup (Figure 4.) . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....6

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................7

Absolute Maximum Ratings(Table 2.) . .. ............................................7

DC AND AC PARAMETERS. . . . . . . . . . ................................................8

DC and AC Measurement Conditions (Table 3.). . . .....................................8

AC Testing Load Circuit(Figure 5.). . . . . . . . . .........................................8

Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DC Characteristics(Table 5.) . . . . . . ................................................9

Crystal Electrical Characteristics (Externally Supplied) (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . 9

OPERATION .....................................................................10

Address Decoding . . ............................................................10

Operating Modes(Table 7.). . . . . . . ................................................10

Truth Table for SRAM Bank Select (Table 8.). ........................................11

Chip Enable Control and Bank Select Timing (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable Control and Bank Select Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . ........11

READ Mode...................................................................12

READ Cycle Timing: RTC Control Signal Waveforms (Figure 7.). . . . . . . . . . . . . . . . . . . . . . . . . . 12

READ Mode AC Characteristics (Table 10.) . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . ........................................14

WRITE Cycle Timing: RTC Control Signal Waveforms(Figure 8.) . . . . . . . . . . . . . . . . . . . . . ....14

WRITE Mode AC Characteristics(Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Retention Mode. . . . . .......................................................16

Power Down/Up Mode AC Waveforms (Figure 9.) .....................................17

Power Down/Up Mode AC Characteristics (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3/30

M48T212A

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............18

TIMEKEEPERRegisters. . . .....................................................18

Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................18

Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................18

Stopping and Starting the Oscillator .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............18

TIMEKEEPERRegister Map (Table 13.) . . . ........................................19

Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Setting the Alarm Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........21

Alarm Interrupt Reset Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . ...............21

Alarm Repeat Modes (Table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Back-up Mode Alarm Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....22

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . ........................................22

CC Switch Output. . ............................................................23

Power-on Reset. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............23

(RSTIN1 & RSTIN2) Timing Waveforms (Figure 12.) . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ....23

Reset AC Characteristics (Table 15.) . . . . . . . .. . . . . . . . . ..............................23

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Initial Power-on Defaults . . . . . . . . . . ...............................................24

Default Values (Table 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 24

Crystal Accuracy Across Temperature (Figure 13.) ....................................25

Calibration Waveform (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 25

VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . ............................26

Supply Voltage Protection (Figure 15.) . . . . . . . .......................................26

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........27

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

REVISION HISTORY. ..............................................................29

M48T212A

4/30

DESCRIPTION

The M48T212A is a self-contained device that in-

cludes a real time clock (RTC), programmable

alarms, a watchdog timer, and two external chip

enable outputs which provide control of up to four

(two in parallel) external low-power static RAMs.

A built-in 32.768 kHz oscillator (external crystal

controlled) is used for the clock/calendar function.

Access to all TIMEKEEPERfunctions and the

external RAM is the same as conventional byte-

wide SRAM.The 16 TIMEKEEPER Registers offer

Century, Year, Month, Date, Day, Hour, Minute,

Second, Control, Alarm, Watchdog, and Flags.

Externally attached static RAMs are controlled by

the M48T212A via the E1CON and E2CON signals

(see Table 9, page 11).

Figure 2. Logic Diagram Table 1. Signal Names

AI03047

A0-A3

DQ0-DQ7

VCC

M48T212A

VSS

E2CON

E1CON

RSTIN2

RSTIN1

RST

IRQ/FT

VOUT

WDI

VCAP/

VBAT+

VCCSW

VBAT–

A0-A3 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

XO Oscillator Output

XI Oscillator Input

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

RST Reset Output (Open Drain)

WDI Watchdog Input

A Bank Select Input

E Chip Enable Input

EX External Chip Enable Input

G Output Enable Input

W WRITE Enable Input

E1CON RAM Chip Enable 1 Output

E2CON RAM Chip Enable 2 Output

IRQ/FT Int/Freq Test Output (Open Drain)

VCCSW VCC Switch Output

VOUT Supply Voltage Output

VCAP/VBAT+ Super Capacitor Input

VBAT– Battery Ground Pin (optional)

VCC Supply Voltage

VSS Ground

NC Not Connected internally

5/30

M48T212A

Figure 3. SOIC Connections

AI03048

VSS

E1CON

VOUT

VCC

M48T212A

XO EX

VCCSW

WDI

E2CON DQ7

DQ5DQ0

DQ1 DQ3

DQ4

DQ6

RSTIN2

RST

VCAP/VBAT+

VBAT–

RSTIN1

DQ2

IRQ/FT

M48T212A

6/30

Figure 4. Hardware Hookup

Note: 1. See description in Power Supply Decoupling and Undershoot Protection.

2. Traces connecting E1CON and E2CON to external SRAM should be as short as possible.

3. If the second chip enable pin (E2) is unused, it should be tied to VOUT.

AI03049

A0-A3

DQ0-DQ7

VCC

WDI

RSTIN1

RSTIN2

VCAP

E2(3)

VCC

A0-Axx

0.1µF

3.3V

E2CON

RST

IRQ/FT

M48T212A

CMOS

SRAM

VOUT

E1CON Note 2

MOTOROLA

MTD20P06HDL

VCCSW

1N5817(1)

A0-A18

VCC

CMOS

SRAM

VSS

SuperCap Supply

A0-Axx

kHz

Crystal

E2(3)

7/30

M48T212A

MAXIMUM RATING

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affectde-

vice reliability. Refer also to the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 2. Absolute Maximum Ratings

Note: 1. Reflow at peak temperature of 215°Cto225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120

seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG Storage Temperature –55 to 125 °C

TSLD(1) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltage –0.3 to 4.6 V

VCC Supply Voltage –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M48T212A

8/30

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operatingconditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. DC and AC Measurement Conditions

Note: Output High Z is defined as the point where data is no longer driven.

Figure 5. AC Testing Load Circuit

Notes:Excluding open-drain output pins.

1. DQ0-DQ7

2. E1CON and E2CON

Table 4. Capacitance

Note: 1. Effective capacitance measured with power supply at 3.3V; sampled only, not 100% tested.

2. At 25°C, f =1MHz.

3. Outputs deselected.

Parameter M48T212A

VCC Supply Voltage 3.0 to 3.6V

Ambient Operating Temperature Grade 1 0 to 70°C

Grade 6 –40 to 85°C

Load Capacitance (CL)50pF

Input Rise and Fall Times ≤5ns

Input Pulse Voltages 0to3V

Input and Output Timing Ref. Voltages 1.5V

AI05610

CL= 50pF or 5pF (1)

CL=30pF(2)

645Ω

DEVICE

UNDER

TEST

1.75V

CLincludes JIG capacitance

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

COUT(3) Input/Output Capacitance 10 pF

9/30

M48T212A

Table 5. DC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA= 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).

2. Outputs deselected.

3. RSTIN1 andRSTIN2 internally pulled-up to VCC through 100KΩresistor. WDI internally pulled-down to VSS through 100KΩresistor.

4. For IRQ/FT & RST pins (Open Drain).

5. Conditioned outputs (E1CON -E2

CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-

rents will reduce battery life.

6. External SRAM must match TIMEKEEPERSUPERVISOR chip VCC specification.

7. When fully charged.

Table 6. Crystal Electrical Characteristics (Externally Supplied)

Note: 1. Load capacitors are integrated within the M48T212A. Circuit board layout considerations for the 32kHz crystal of minimum trace

lengths and isolation from RF generating signals should be taken into account. ST recommends the KDS DT-38 Tuning Fork Type

quartz crystal for all temperature operations. KDS can be contacted at 913-491-6825 or at

http://www.kdsj.co.jp

for forther informa-

tion on this crystal type.

2. At 25°C.

Symbol Parameter Test Condition(1) Min Typ Max Unit

ILI(3) Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO(2) Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC Supply Current E=V

Outputs open 410mA

CC1 Supply Current (Standby) TTL E=V

IH 3mA

CC2 Supply Current (Standby) CMOS E = VCC –0.2 2 mA

IBAT Battery Current OSC ON 575 800 nA

Battery Current OSC OFF 100 nA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.0 VCC +0.3 V

OL Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Voltage (open drain)(4) IOL = 10mA 0.4 V

VOH Output High Voltage IOH = –1.0mA 2.4 V

VOHB(5) VOH Battery Back-up IOUT2 = –1.0µA2.0 3.6 V

IOUT1(6) VOUT Current (Active) VOUT1 >V

CC –0.3 70 mA

IOUT2 VOUT Current (Battery Back-up) VOUT2 >V

BAT –0.3 100 µA

VPFD Power-fail Deselect Voltage 2.7 2.9 3.0 V

VSO Battery Back-up Switchover Voltage VPFD –100mV V

VBAT Battery Voltage 3.0 V

VCAP Capacitor Voltage (7) VCC V

Symbol Description(1,2) Min Typ Max Unit

fOResonant Frequency 32,768 kHz

RSSeries Resistance 50 70 kΩ

CLLoad Capacitance 12.5 pF

M48T212A

10/30

OPERATION

Automatic backup and write protection for an ex-

ternal SRAM is provided through VOUT,E1

CON

and E2CON pins. (Users are urged to insure that

voltage specifications, for both the SUPERVISOR

chip and external SRAM chosen, are similar).

The lithium energy source (or super capacitor)

used to permanently power the real time clock is

also used to retain RAM data in the absence of

VCC power through the VOUT pin.

The chip enable outputs to RAM (E1CON and

E2CON) are controlled during power transients to

prevent data corruption. The date is automatically

adjusted for months with less than 31 days and

corrects for leap years (valid until 2100). The inter-

nal watchdog timer provides programmable alarm

windows.

The nine clock bytes (Fh-9h and 1h, see Table 13,

page 19) are not the actual clock counters, they

are memory locations consisting of BiPORTTM

READ/WRITE memory cells within the static RAM

array. Clock circuitry updates the clock bytes with

current information once per second.The informa-

tion can be accessedby the userin the same man-

ner as any other location in the static memory

array.

Byte 8his the clock control register. This byte con-

trols user access to the clock information and also

stores the clock calibration setting. Byte 7h con-

tains the watchdog timer setting. The watchdog

timer can generate either a reset or an interrupt,

depending on the state of the Watchdog Steering

Bit (WDS). Bytes 6h-2h include bits that, when

programmed, provide forclockalarm functionality.

Alarms are activated when the register content

matches the month, date, hours, minutes, and

seconds of the clock registers. Byte 1h contains

century information. Byte 0h contains additional

flag information pertaining to the watchdog timer,

alarm and battery status.

The M48T212A also has its own Power-Fail De-

tect circuit. This control circuitry constantly moni-

tors the supply voltage for an out of tolerance

condition. When VCC isout of tolerance, the circuit

write protects the TIMEKEEPERRegister data

and external SRAM, providing data security in the

midst of unpredictable system operation. As VCC

falls, the control circuitry automatically switches to

the battery, maintaining data and clock operation

until valid power is restored.

Address Decoding

The M48T212A accommodates 4 address lines

(A3-A0) which allow access to the sixteen bytes of

the TIMEKEEPER clock registers. All TIMEKEEP-

ER registers reside in the SUPERVISOR chip it-

self. All TIMEKEEPER registers are accessed by

enabling E (Chip Enable).

Table 7. Operating Modes

Note: X = VIH or VIL;V

SO = Battery Back-up Switchover Voltage

1. See Table 5, page 9 for details.

Mode VCC E G W DQ7-DQ0 Power

Deselect

3.0V to 3.6V

VIH X X High-Z Standby

WRITE VIL XVIL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High-Z Active

Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby

Deselect ≤VSO(1) X X X High-Z Battery Back-Up

11/30

M48T212A

Table 8. Truth Table for SRAM Bank Select

Note: X = VIH or VIL;V

SO = Battery Back-up Switchover Voltage

1. See Table 5, page 9 for details.

Figure 6. Chip Enable Control and Bank Select Timing

Table 9. Chip Enable Control and Bank Select Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA= 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).

Mode VCC EX A E1CON E2CON Power

Select 3.0V to 3.6V

Low Low Low High Active

Low High High Low Active

Deselect High X High High Standby

Deselect VSO to VPFD (min)(1) X X High High CMOS Standby

Deselect ≤VSO(1) X X High High Battery Back-Up

Symbol Parameter(1) M48T212A Unit

Min Max

tEXPD EX to E1CON or E2CON (Low or High) 15 ns

tAPD AtoE1

CON or E2CON (Low or High) 15 ns

AI02639

tEXPD tAPD

tEXPD

E1CON

E2CON

M48T212A

12/30

READ Mode

The M48T212A executes a READ cycle whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The unique address specified by the address

inputs (A3-A0) defines which one of the on-chip

TIMEKEEPERregisters is to be accessed. When

the address presented to the M48T212A is in the

range of 0h-Fh, one of the on-board TIMEKEEP-

ER registers is accessed and valid data will be

available to the eight data output drivers within

tAVQV after the address input signal is stable, pro-

viding that the E and G access times are also sat-

isfied. If they are not, then data access must be

measured from the latter occurring signal (E or G)

and the limiting parameter is either tELQV for E or

tGLQV for G rather than the address access time.

When EX input is low, an external SRAM location

will be selected.

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

Figure 7. READ Cycle Timing: RTC Control Signal Waveforms

Note: EX is assumed High.

AI02640

DQ7-DQ0

DATA OUT

VALID

ADDRESS

tAVAV

tELQV

tAVAV tAVAV

READ READ WRITE

DATA IN

VALID

DATA OUT

VALID

tAVQV tWHAXtAVWL

tELQX

tGLQV

tGHQZ

tWLWH

tAXQXtGLQX

13/30

M48T212A

Table 10. READ Mode AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA= 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).

2. CL= 5pF.

Symbol Parameter(1) M48T212A Unit

Min Max

tAVAV READ Cycle Time 85 ns

tAVQV Address Valid to Output Valid 85 ns

tELQV Chip Enable Low to Output Valid 85 ns

tGLQV Output Enable Low to Output Valid 35 ns

tELQX(2) Chip Enable Low to Output Transition 5 ns

tGLQX(2) Output Enable Low to Output Transition 0 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 25 ns

tGHQZ(2) Output Enable High to Output Hi-Z 25 ns

tAXQX Address Transition to Output Transition 5 ns

M48T212A

14/30

WRITE Mode

The M48T212A is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are in a

low state after the address inputs are stable. The

start of a WRITE is referenced from the latter oc-

curring falling edge of W or E. A WRITE is termi-

nated by the earlier rising edge of W or E. The

addresses must be held valid throughout the cy-

cle. E or W must return high for a minimum of tE-

HAX from Chip Enable or tWHAX from WRITE

Enable prior to the initiation of another READ or

WRITE cycle. Data-in must be valid tDVWH prior to

the end of WRITE and remain valid for tWHDX af-

terward.

G should be kept high during WRITE cycles to

avoid bus contention; although, if the output bus

has been activated by a low on E and G a low on

W will disable the outputs tWLQZ after W falls.

When E is low during the WRITE, one of the on-

board TIMEKEEPERregisters will be selected

and data will be written into the device. When EX

is low(and E is high) an external SRAM location is

selected.

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

Figure 8. WRITE Cycle Timing: RTC Control Signal Waveforms

Note: EX is assumed High.

AI02641

DQ0-DQ7

DATA IN

VALID

ADDRESS

tAVAV

tAVEH

tAVAV tAVAV

WRITE WRITE READ

DATA OUT

VALID

DATA OUT

VALID

tAVWH

tAVQV

tWLWH

tWHDX

tWHAX

tWHQX tWLQZ

tDVWH

tGLQV

tEHQZ tDVEH

DATA IN

VALID

tELEH tEHAX

tAVEL

tEHDX

tAVWL

15/30

M48T212A

Table 11. WRITE Mode AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA= 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).

2. CL= 5pF

3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Symbol Parameter(1) M48T212A Unit

Min Max

tAVAV WRITE Cycle Time 85 ns

tAVWL Address Valid to WRITE Enable Low 0 ns

tAVEL Address Valid to Chip Enable Low 0 ns

tWLWH WRITE Enable Pulse Width 55 ns

tELEH Chip Enable Low to Chip Enable High 60 ns

tWHAX WRITE Enable High to Address Transition 0 ns

tEHAX Chip Enable High to Address Transition 0 ns

tDVWH Input Valid to WRITE Enable High 30 ns

tDVEH Input Valid to Chip Enable High 30 ns

tWHDX WRITE Enable High to Input Transition 0 ns

tEHDX Chip Enable High to Input Transition 0 ns

tWLQZ(2,3) WRITE Enable Low to Output High-Z 25 ns

tAVWH Address Valid to WRITE Enable High 65 ns

tAVEH Address Valid to Chip Enable High 65 ns

tWHQX(2,3) WRITE Enable High to Output Transition 5 ns

M48T212A

16/30

Data Retention Mode

With valid VCC applied, the M48T212A can be ac-

cessed as described above with READ or WRITE

cycles. Should the supply voltage decay, the

M48T212A will automatically deselect, write pro-

tecting itself (and any external SRAM) when VCC

falls between VPFD (max) and VPFD (min). This is

accomplished by internally inhibiting access to the

clock registers via the E signal. At this time, the

Reset pin (RST) is driven active and will remain

active until VCC returns to nominal levels.

External RAM access isinhibited ina similar man-

ner by forcing E1CON and E2CON to a high level.

This level is within 0.2V of the VBAT.E1

CON and

E2CON will remain at this level as long as VCC re-

mains at an out-of-tolerance condition.

When VCC falls below the level of the battery

(VBAT), power input is switched from the VCC pin

to the battery and the clock registers and external

SRAM are maintained from the attached battery

supply. All outputs become high impedance. The

VOUT pin is capable of supplying 100µA of current

to the attached memory with less than 0.3V drop

under this condition. On power up, when VCC re-

turns to a nominal value, write protection contin-

ues for 200ms (max) by inhibiting E1CON or

E2CON.

The RST signal also remains active during this

time (see Figure 9, page 17).

Note: Most low power SRAMs on the market to-

day can be used with the M48T212A TIMEKEEP-

ERSUPERVISOR. There are, however some

criteria which should be used in making the final

choice of an SRAM to use. The SRAM must be de-

signed in a way where the chip enable input dis-

ables all other inputs to the SRAM. This allows

inputs to the M48T212A and SRAMs to be “Don’t

care” once VCC falls below VPFD(min). The SRAM

should also guarantee data retention down to VCC

= 2.0V. The chip enable access time must be suf-

ficient to meet the system needs with the chip en-

able output propagation delays included.

If the SRAM includes a second chip enable pin

(E2), this pin should be tied to VOUT.

If data retention lifetime is a critical parameter for

the system, it isimportant to review the data reten-

tion current specifications for the particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0V.Manufacturers gen-

erally specify a typical condition for room temper-

ature along with a worst case condition (generally

at elevated temperatures). The system level re-

quirements will determine the choice ofwhich val-

ue to use.

The dataretention currentvalue of the SRAMscan

then be added to the IBAT value of the M48T212A

to determine the total current requirements for

data retention. The available battery capacity can

then be divided by this current to determine the

amount of data retention available.

For a furthermore detailed review oflifetime calcu-

lations, please see Application Note AN1012.

17/30

M48T212A

Figure 9. Power Down/Up Mode AC Waveforms

Table 12. Power Down/Up Mode AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA= 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).

Symbol Parameter(1) Min Max Unit

tFVPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB VPFD (min) to VSS VCC Fall Time 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tREC VPFD (max) to RST High 40 200 ms

tRB VSS toVPFD (min) VCC Rise Time 5µs

AI02638

VCC

INPUTS

RST

OUTPUTS

DON’T CARE

HIGH-Z

tFB

tRECtRB

VALID VALID

VPFD (max)

VPFD (min)

VSO

VALID VALID

VCCSW

M48T212A

18/30

CLOCK OPERATION

TIMEKEEPERRegisters

The M48T212A offers 16 internal registers which

contain TIMEKEEPER, Alarm, Watchdog, Flag,

and Control data. These registers are memory lo-

cations which contain external (user accessible)

and internal copies of the data (usually referred to

as BiPORTTIMEKEEPER cells).

The external copies are independent of internal

functions except that they are updated periodically

by the simultaneous transfer of the incremented

internal copy. TIMEKEEPER and Alarm Registers

store data in BCD. Control, Watchdog and Flags

Registers store data in Binary Format.

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. The BiPORT TIMEKEEPER

cells in the RAM array are only data registers and

not the actual clock counters, so updating the reg-

isters can be halted without disturbing the clock it-

self.

Updating is halted when a ’1’ is written to the

READ Bit, D6 in the ControlRegister (8h). As long

as a’1’remains in that position, updating is halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs 1 second after the

READ Bit is reset to a ’0.’

Setting the Clock

Bit D7 of the Control Register (8h) is the WRITE

Bit. Setting the WRITE Bit to a ’1,’ like the READ

Bit, halts updates to the TIMEKEEPER registers.

The user can then load them with the correct day,

date, and time data in 24 hour BCD format (see

Table 13).

Resetting the WRITE Bit to a ’0’then transfers the

values of alltime registers (Fh-9h, 1h) to theactual

TIMEKEEPER counters and allows normal opera-

tion to resume. After the WRITE Bit is reset, the

next clock update will occur one second later.

Note: Upon power-up following a power failure,

the READ Bitwill automaticallybe set to a’1.’ This

will prevent the clock from updating the TIME-

KEEPER registers, and will allow the user to read

the exact time of the power-down event.

Resetting the READ Bit to a ’0’will allow the clock

to update these registers with the current time.

The WRITE Bitwill be reset to a ’0’ upon power-up.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time onthe shelf, the oscillator canbe turned off to

minimize current drain on the battery. The STOP

Bit is located at Bit D7 within the Seconds Register

(9h). Settingit toa ’1’ stops the oscillator. When re-

set to a ’0,’ the M48T212A oscillator starts within

one second.

Note: It is not necessary to set the WRITE Bit

when setting or resetting the FREQUENCY TEST

Bit (FT) or the STOP Bit (ST).

19/30

M48T212A

Table 13. TIMEKEEPERRegister Map

Keys: S = Sign Bit

FT = Frequency Test Bit

R = READBit

W = WRITE Bit

ST = Stop Bit

0 = Must be set to ’0’

BL = Battery Low Flag (Read only)

BMB0-BMB4 = Watchdog Multiplier Bits

AFE = Alarm Flag Enable Flag

RB0-RB1 = Watchdog Resolution Bits

WDS = Watchdog Steering Bit

ABE = Alarm in Battery Back-Up Mode Enable Bit

RPT1-RPT5 = Alarm Repeat Mode Bits

WDF = Watchdog Flag (Read only)

AF = Alarm Flag (Read only)

Y = ’1’or ’0’ (Read only)

Address Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

Fh 10 Years Year Year 00-99

Eh 0 0 0 10M Month Month 01-12

Dh 0 0 10 Date Date: Day of Month Date 01-31

Ch 0 FT 0 0 0 Day of Week Day 01-7

Bh 0 0 10 Hours Hours (24 Hour Format) Hours 00-23

Ah 0 10 Minutes Minutes Min 00-59

9h ST 10 Seconds Seconds Sec 00-59

8h W R S Calibration Control

7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

5h RPT4 RPT5 AI 10 Date Alarm Date A Date 01-31

4h RPT3 0 AI 10 Hour Alarm Hour A Hour 00-23

3h RPT2 Alarm 10 Minutes Alarm Minutes A Min 00-59

2h RPT1 Alarm 10 Seconds Alarm Seconds A Sec 00-59

1h 1000 Year 100 Year Century 00-99

0h WDF AF Y BL Y Y Y Y Flag

M48T212A

20/30

Calibrating the Clock

The M48T212Aisdriven bya quartz-controlledos-

cillator witha nominal frequencyof 32,768Hz. The

devices are tested not to exceed ±35 PPM (parts

per million) oscillator frequency error at 25°C,

which equates to about ±1.53 minutes per month

(see Figure13, page 25). Whenthe Calibration cir-

cuit is properly employed, accuracy improves to

better than +1/–2 ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature. TheM48T212A designemploys periodic

counter correction. The calibration circuit adds or

subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 14,

page 25. The number of times pulses which are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five Calibration bits found in

the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in the Control Register 8h.These bits

can be set to represent any value between 0 and

31 in binary form. Bit D5 is a Sign Bit; ’1’ indicates

positive calibration, ‘0’ indicates negative calibra-

tion. Calibration occurs within a 64 minute cycle.

The first 62 minutes in the cycle may, once per

minute, have one second either shortened by 128

or lengthened by 256 oscillator cycles.

If a binary ’1’ is loaded into the register, only the

first 2 minutes in the 64 minute cycle will be modi-

fied; if a binary 6 is loaded, the first 12 will be af-

fected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 PPM of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillatoris running at exactly 32,768 Hz, each

of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month

which correspondsto a totalrange of+5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T212A may require.

The first involves setting the clock, letting itrun for

a monthand comparing it to a known accurate ref-

erence and recording deviation over a fixed period

of time.Calibrationvalues, including the numberof

seconds lost or gained in a given period, can be

found in Application Note AN934, “TIMEKEEP-

ERCalibration.”

This allows the designer to give the end user the

ability to calibrate theclock as the environment re-

quires, even if the final product is packaged in a

non-user serviceable enclosure. The designer

could provide a simple utility that accesses the

Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pin will toggle at 512Hz, when the

Stop Bit (ST, D7 of 9h) is ’0,’ the Frequency Test

Bit (FT, D6 of Ch)is ’1,’the Alarm Flag Enable Bit

(AFE, D7 of 6h) is ’0,’ and the Watchdog Steering

BIt (WDS, D7of 7h) is ’1’or the Watchdog Register

(7h=0) is reset.

Any deviation from 512 Hz indicates the degree

and directionof oscillator frequency shiftat thetest

temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscilla-

tor frequency error, requiring a –10 (WR001010)

to be loaded into the Calibration Byte for correc-

tion.

Note: Setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT pin is an open drain output which re-

quires a pull-up resistor to VCC for proper opera-

tion. A 500-10kΩresistor is recommended in order

to control the rise time. The FT Bit is cleared on

power-down.

21/30

M48T212A

Setting the Alarm Clock

Address locations 6h-2h contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M48T212A is in the

battery back-up to serveas a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeatmode

of operation. Table 14 shows the possible config-

urations. Codes not listed in thetable default to the

once per second mode to quickly alert the user of

an incorrect alarm setting.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT5-RPT1, the AF (Alarm Flag) is set.

If AFE (Alarm Flag Enable) is also set, the alarm

condition activates the IRQ/FT pin. To disable

alarm, write ’0’ to the Alarm Date registers and

RPT1-5. TheIRQ/FT outputis cleared by a READ

to the Flags Register as shown in Figure 10. A

subsequent READ of the Flags Register is neces-

sary to see that the value of the Alarm Flag has

been reset to ’0.’

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE Bits are resetduring power-up, therefore

an alarm generated during power-up will only set

AF. The user can read the Flag Register at system

boot-up to determine if an alarm was generated

while the M48T212A was in the deselect mode

during power-up. Figure 11, page 22 illustrates the

back-up mode alarm timing.

Figure 10. Alarm Interrupt Reset Waveforms

Table 14. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

1 1 1 1 1 Once per Second

1 1 1 1 0 Once per Minute

1 1 1 0 0 Once per Hour

1 1 0 0 0 Once per Day

1 0 0 0 0 Once per Month

0 0 0 0 0 Once per Year

AI03021

A0-A3

ACTIVE FLAG BIT

ADDRESS 0h

IRQ/FT

HIGH-Z

1h Fh

M48T212A

22/30

Figure 11. Back-up Mode Alarm Waveforms

Watchdog Timer

The watchdog timer can be used todetect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 7h.

Bits BMB4-BMB0 store a binary multiplier and the

two lower-order bits RB1-RB0 select the resolu-

tion, where 00=1/16 second, 01=1/4 second, 10=1

second, and 11=4 seconds. The amount of time-

out is then determined to be the multiplication of

the five-bitmultiplier value with the resolution. (For

example: writing 00001110 in the Watchdog Reg-

ister = 3*1 or 3 seconds).If the processor does not

reset the timer within the specified period, the

M48T212A sets the WDF (Watchdog Flag) and

generates a watchdog interrupt or a microproces-

sor reset. WDF is reset by reading the Flags Reg-

ister (Address 0h).

The most significant bit of the Watchdog Register

is the Watchdog Steering Bit (WDS). When set to

a ’0.’ the watchdog will activate the IRQ/FT pin

when timed-out. When WDS is set to a ’1,’ the

watchdog will output a negative pulse on the RST

pin for 40 to 200 ms. The Watchdog Register,

AFE, ABE, and the FT Bits will reset to a ’0’at the

end of a Watchdog time-out when the WDS Bit is

set to a ’1.’

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a WRITE of the

Watchdog Register.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin. In the order to perform a software reset

of the watchdog timer, the original time-out period

can be written into the Watchdog Register, effec-

tively restarting the count-down cycle.

Should the watchdog timer time-out, and the WDS

Bit is programmed tooutput an interrupt, a valueof

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT pin. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A READ of the Flags Register

will reset theWatchdog Flag (Bit D7; Register 0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog function is set to output to

the IRQ/FT pin and the Frequency Test function is

activated, the watchdog or alarm function prevails

and the Frequency Test function is denied.

AI03622

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE Bit/ABE Bit

AF Bit in Flags Register

HIGH-Z

tREC

23/30

M48T212A

VCC Switch Output

VCCSW output goes low when VOUT switches to

VCC turning on a customer supplied P-Channel

MOSFET (see Figure 4, page 6). The Motorola

MTD20P06HDL is recommended. This MOSFET

in turn connects VOUT to a separate supply when

the current requirement is greater than IOUT1 (see

Table 5, page 9). This output may also be used

simply to indicate the status of the internalbattery

switchover comparator, which controls the source

(VCC or battery) of the VOUT output.

Power-on Reset

The M48T212A continuously monitors VCC. When

VCC falls to thepower fail detecttrip point, the RST

pulls low (open drain) and remains low on power-

up for 40 to 200ms after VCC passes VPFD (max).

The RST pin isan open drain output andan appro-

priate pull-up resistor to VCC should be chosen to

control rise time.

Note: If the RST output is fed back into either of

the RSTIN inputs (for a microprocessor with a bi-

directional reset) then a 1kΩ(max) pull-up resistor

is recommended.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T212A provides two independent inputs

which can generate an output reset. The duration

and function of these resets is identical to a reset

generated by a power cycle. Table 15 and Figure

12 illustrate the AC reset characteristics of this

function. During the time RST is enabled (tR1HRH

R2HRH), the Reset Inputs are ignored.

Note: RSTIN1 and RSTIN2 are each internally

pulled up to VCC througha 100KΩresistor.

Figure 12. (RSTIN1 & RSTIN2) Timing Waveforms

Table 15. Reset AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA= 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).

2. Pulse width lessthan 50ns will result in no RESET (for noise immunity).

3. Pulse width lessthan 20ms will result in no RESET (for noise immunity).

4. CL= 5pF (see Figure 5, page 8).

Symbol Parameter(1) Min Max Unit

tR1(2) RSTIN1 Low to RSTIN1 High 200 ns

tR2(3) RSTIN2 Low to RSTIN2 High 100 ms

tR1HRH(4) RSTIN1 High to RST High 40 200 ms

tR2HRH(4) RSTIN2 High to RST High 40 200 ms

AI02642

RSTIN1

RST

RSTIN2

tR1

tR1HRH

tR2

tR2HRH

M48T212A

24/30

Battery Low Warning

The M48T212A automatically performs battery

voltage monitoring upon power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL Bitwill remain asserted until completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If abattery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent periods of battery back-up mode, the

battery should be replaced. The battery should be

replaced with VCC powering the device to avoid

data loss.

The M48T212A only monitors the battery when a

nominal Vccis applied to the device. Thus applica-

tions which require extensive durations in the bat-

tery back-up mode should be powered-up

periodically (at least once every few months) in or-

der for this technique to be beneficial.

Additionally, if a battery low is indicated, data in-

tegrity should be verified upon power-up via a

checksum or other technique.

Note: Battery Low warning is only valid when us-

ing a 3V button cell battery. Use a super capacitor

for back-up supply causes the BL Flag to be in-

valid.

Initial Power-on Defaults

Upon application of power to the device, the fol-

lowing register bits are set to a ‘0’ state: WDS,

BMB0-BMB4, RB0-RB1, AFE, ABE, W, and FT

(see Table 16).

Table 16. Default Values

Note: 1. WDS, BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. State of other control bits remains unchanged.

4. Assuming these bits set to ’1’ prior to power-down.

Condition W R FT AFE ABE WATCHDOG

Initial Power-up (Battery Attach)(2) 01000 0

RESET(3) 00000 0

Power-down(4) 01011 0

Subsequent Power-up 0 1 0 0 0 0

25/30

M48T212A

Figure 13. Crystal Accuracy Across Temperature

Figure 14. Calibration Waveform

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T0)2±10%

Fppm

T0=25°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T212A

26/30

VCC Noise And Negative Going Transients

ICC transients, including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spikes on the VCC bus. These transients

can be reduced if capacitors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor value of 0.1µF (as shown in Figure

15) is recommended in order to provide the need-

ed filtering.

In addition to transients that are caused by normal

SRAM operation, powercycling can generate neg-

ative voltage spikes on VCC that drive it to values

below VSS byas much asone volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, STMicroelectronics recom-

mends connecting a schottky diode from VCC to

VSS (cathode connected to VCC, anode to VSS).

Schottky diode 1N5817 is recommended for

through hole and MBRS120T3 is recommended

for surfacemount.

Figure 15. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

27/30

M48T212A

PART NUMBERING

Table 17. OrderingInformation Example

For a listof available options (e.g.,Speed, Package) or for further information on anyaspect of thisdevice,

please contact the ST Sales Office nearest to you.

Example: M48T 212A –85 MH 1 TR

Device Type

M48T

Supply and Write Protect Voltage

212A = VCC = 3.0 to 3.6V;= 2.7V≤VPFD ≤3.0V

Speed

–85 = 85ns

Package

MH = SO44

Temperature Range

1=0to70°C

6=–40to85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

M48T212A

28/30

PACKAGE MECHANICAL INFORMATION

Figure 16. SO44 – 44-lead Plastic Small Package Outline

Note: Drawing is not to scale.

Table 18. SO44 – 44-lead Plastic Small, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0°8°0°8°

N44 44

CP 0.10 0.004

SOH-C

LA1 α

29/30

M48T212A

REVISION HISTORY

Table 19. Document Revision History

Date Revision Details

October 1999 First Issue

03/01/00

SNAPHAT Battery & Crystal removed

Hardware Hookup scheme changed (Figure 4)

Back-Up Mode Alarm Waveforms changed (Figure 11)

Default Values Tableadded (Table 16)

SOH44 package silhouette, mechanical drawings and mechanical data changed (Figure 16)

05/30/01 Changed “Controller” references to “SUPERVISOR”

09/10/01 Reformatted; added temp/voltage info. to tables (Table4, 5, 10, 11, 12); improve text in “Setting the

Alarm Clock” section

05/13/02 Modify refow time and temperature footnote (Table 2)

M48T212A

30/30

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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