5V9910A-7SOGI8 - Integrated Device Technology

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

SEPTEMBER 2001

2001 Integrated Device Technology, Inc. DSC 5847/1c

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Eight zero delay outputs

• <250ps of output to output skew

• Selectable positive or negative edge synchronization

• Synchronous output enable

• Output frequency: 15MHz to 85MHz

• 3 skew grades:

IDT5V9910A-2: tSKEW0<250ps

IDT5V9910A-5: tSKEW0<500ps

IDT5V9910A-7: tSKEW0<750ps

• 3-level inputs for PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <200ps peak-to-peak

• Available in SOIC package

FUNCTIONAL BLOCK DIAGRAM

GND/sOE

REF

PLL

VCCQ/PE

IDT5V9910A

3.3V LOW SKEW

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

DESCRIPTION:

The IDT5V9910A is a high fanout phase locked-loop clock driver

intended for high performance computing and data-communications appli-

cations. It has eight zero delay LVTTL outputs.

When the GND/sOE pin is held low, all the outputs are synchronously

enabled. However, if GND/sOE is held high, all the outputs except Q2 and

Q3 are synchronously disabled.

Furthermore, when the VCCQ/PE is held high, all the outputs are

synchronized with the positive edge of the REF clock input. When VCCQ/

PE is held low, all the outputs are synchronized with the negative edge of

REF.

The FB signal is compared with the input REF signal at the phase detector

in order to drive the VCO. Phase differences cause the VCO of the PLL to

adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the phase

detector. The loop filter transfer function has been chosen to provide minimal

jitter (or frequency variation) while still providing accurate responses to input

frequency changes.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

PIN CONFIGURATION

NOTE:

1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Max Unit

Supply Voltage to Ground –0.5 to +7 V

VIDC Input Voltage –0.5 to VCC+0.5 V

REF Input Voltage –0.5 to +5.5 V

Maximum Power Dissipation (TA = 85°C) 530 mW

TSTG Storage Temperature –65 to +150 °C

NOTE:

1. Capacitance applies to all inputs except TEST and FS. It is characterized but not

production tested.

CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)

Parameter Description Typ. Max. Unit

CIN Input Capacitance 5 7 pF

PIN DESCRIPTION

Pin Name Type Description

REF IN Reference Clock Input

FB IN Feedback Input

TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.

GND/ sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the

feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.

VCCQ/PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the

reference clock.

FS(2) IN Frequency range select:

FS = GND: 15 to 35MHz

FS = MID (or open): 25 to 60MHz

FS = VCC: 40 to 85MHz

Q0 - Q7OUT Eight clock output

VCCN PWR Power supply for output buffers

VCCQ PWR Power supply for phase locked loop and other internal circuitry

GND PWR Ground

SOIC

TOP VIEW

NOTES:

1. When TEST = MID and GND/sOE = HIGH, PLL remains active.

2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional

lock time before all data sheet limits are achieved.

REF

VCCQ/PE

GND

TEST

GND/sOE

GND

VCCN

VCCQ

VCCN

SO24-2

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

RECOMMENDED OPERATING RANGE IDT5V9910A-5, -7 IDT5V9910A-2

(Industrial) (Commercial)

Symbol Description Min. Max. Min. Max. Unit

VCC Power Supply Voltage 3 3.6 3 3.6 V

TAAmbient Operating Temperature -40 +85 0 +70 °C

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Typ.(2) Max. Unit

ICCQ Quiescent Power Supply Current VCC = Max., TEST = MID, REF = LOW, 8 25 mA

GND/sOE = LOW, All outputs unloaded

∆ICC Power Supply Current per Input HIGH VCC = Max., VIN = 3V 1 30 µA

ICCD Dynamic Power Supply Current per Output VCC = Max., CL = 0pF 55 90 µA/MHz

ITOT Total Power Supply Current VCC = 3.3V, FREF = 25MHz, CL = 160pF(1) 34 —

VCC = 3.3V, FREF = 33MHz, CL = 160pF(1) 42 — mA

VCC = 3.3V, FREF = 66MHz, CL = 160pF(1) 76 —

NOTE:

1. For eight outputs, each loaded with 20pF.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Conditions Min. Max. Unit

VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 2 — V

VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) — 0.8 V

VIHH Input HIGH Voltage(1) 3-Level Inputs Only VCC−0.6 — V

VIMM Input MID Voltage(1) 3-Level Inputs Only VCC/2−0.3 VCC/2+0.3 V

VILL Input LOW Voltage(1) 3-Level Inputs Only — 0. 6 V

IIN Input Leakage Current VIN = VCC or GND — ± 5 µA

(REF, FB Inputs Only) VCC = Max.

VIN = VCC HIGH Level — ±200

I33-Level Input DC Current (TEST, FS) VIN = VCC/2 MID Level — ± 50 µA

VIN = GND LOW Level — ±200

IPU Input Pull-Up Current (VCCQ/PE) VCC = Max., VIN = GND — ±100 µA

IPD Input Pull-Down Current (GND/sOE)VCC = Max., VIN = VCC — ±100 µA

VOH Output HIGH Voltage VCC = Min., IOH = −12mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 12mA — 0.55 V

NOTE:

1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and

timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

INPUT TIMING REQUIREMENTS

Symbol Description (1) Min. Max. Unit

tR, tFMaximum input rise and fall times, 0.8V to 2V — 1 0 ns/V

tPWC Input clock pulse, HIGH or LOW 3 — ns

DHInput duty cycle 1 0 9 0 %

REF Reference clock input 15 85 MHz

NOTE:

1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

IDT5V9910A-2 IDT5V9910A-5 IDT5V9910A-7

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

FS = LOW 15 — 35 15 — 35 15 — 35

FREF REF Frequency Range FS = MED 25 — 6 0 25 — 6 0 25 — 60 MHz

FS = HIGH 40 — 85 40 — 85 40 — 85

tRPWH REF Pulse Width HIGH(8) 3—— 3——3——ns

tRPWL REF Pulse Width LOW(8) 3—— 3——3——ns

tSKEW0 Zero Output Skew (All Outputs)(1,3,4) — 0.1 0.25 — 0.25 0.5 — 0.3 0.75 ns

tDEV Device-to-Device Skew(1,2,5) — — 0.75 — — 1.25 — — 1.65 ns

tPD REF Input to FB Propagation Delay(1,7) −0.25 0 0.25 −0.5 0 0.5 −0.7 0 0.7 ns

tODCV Output Duty Cycle Variation from 50%(1) −1.2 0 1.2 −1.2 0 1.2 −1.2 0 1.2 ns

tORISE Output Rise Time(1) 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns

tOFALL Output Fall Time(1) 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns

tLOCK PLL Lock Time(1,6) — — 0.5 — — 0.5 — — 0.5 ms

tJR Cycle-to-Cycle Output Jitter(1) RMS — — 25 — — 25 — — 25 ps

Peak-to-Peak — — 200 — — 200 — — 200

NOTES:

1. All timing and jitter tolerances apply for FNOM > 25MHz.

2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.

3. tSKEW is the skew between all outlets. See AC TEST LOADS.

4. For IDT5V9910A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.

5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)

6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is

measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.

7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.

8. Refer to INPUT TIMING REQUIREMENTS for more detail.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

150Ω

VCC

Output

2.0V

tORISE tOFALL

0.8V

≤1ns ≤1ns

2.0V

0.8V

3.0V

Vth =1.5V

20pF

REF

OTHER Q

tREF

tPD

tSKEW

tJR

tODCV

tRPWH

tRPWL

tSKEW

tODCV

AC TEST LOADS AND WAVEFORMS

Test Load

LVTTL Input Test Waveform

LVTTL Output Waveform

AC TIMING DIAGRAM

NOTES:

Sk ew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω to VCC/2.

tSKEW: The skew between all outputs.

tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)

tODCV: The deviation of the output from a 50% duty cycle.

tORISE and tOFALL are measured between 0.8V and 2V.

tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459

www.idt.com

IDT XXXXX X

Package Process

De vice Type

Blank

5V9910A-2

5V9910A-5

5V9910A-7

3.3V Low Skew PLL Clock Driver TurboC lock Jr.

Sm all Outline IC (300-mil) (SO 24-2)

C o mme rc ia l (0° C to +7 0 °C)

Industrial (-40°C to +85°C )