Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager Check for Samples: bq30z554-R1 FEATURES DESCRIPTION * The bq30z554-R1 device is a fully integrated Impedance TrackTM gas gauge and analog monitoring single-package solution that provides protection and monitoring with authentication for 2-series, 3-series, and 4-series cell Li-Ion battery packs. The bq30z554R1 device incorporates sophisticated algorithms that offer cell balancing while charging or at rest. 1 2 * * * * * * * * * * * * * Fully Integrated 2-Series, 3-Series, and 4Series Li-Ion or Li-Polymer Cell Battery Pack Manager and Protection High Side N-CH Protection FET Drive Impedance TrackTM Gas Gauging Integrated Cell Balancing While Charging or At Rest PF Snapshot and Black Box Technology Analyze Returned Packs AC Peak Power Information Capability (TURBO Mode) SBS v1.1 Interface Low Power Modes - Low Power: < 180 A - Sleep < 76 A Complete Set of Advanced Protections: - Internal Cell Short - Cell Imbalance - Cell Voltage - Overcurrent - Temperature - FET Protection Sophisticated Charge Algorithms - JEITA - Enhanced Charging - Adaptive Charging - Cell Balancing While Charging or At Rest General Purpose Output for Power Interrupt Diagnostic Lifetime Data Monitor SHA-1 Authentication Small Package: TSSOP The device communicates via an SBS v1.1 interface, providing high accuracy cell parameter reporting and control of battery pack operation, and can be designed into systems that require AC peak power (TURBO mode), using a method to ensure that system performance is not disrupted. An optimum balance of quick response hardwarebased protection along with intelligent CPU control delivers an ideal pack solution. The device has flexible user-programmable settings of critical system parameters, such as voltage, current, temperature, and cell imbalance, among other conditions. The bq30z554-R1 device has advanced charge algorithms, including JEITA support, enhanced cell charging, and adaptive charging compensating charge losses, enabling faster charging. In addition, the bq30z554-R1 device can monitor critical parameters over the life of the battery pack, tracking usage conditions. A general purpose output is used for power interruption, employing an external push button switch. The advanced snapshot and black box functionality show critical information for analysis of returned battery packs. SHA-1 authentication with secure memory for authentication keys enables identification for genuine battery packs beyond doubt. APPLICATIONS * * * Notebook/Netbook PCs Medical and Test Equipment Portable Instrumentation 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Impedance Track is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2013, Texas Instruments Incorporated Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION ORDERING INFORMATION (1) TA PART NUMBER PACKAGE PACKAGE DESIGNATOR PACKAGE MARKING TUBE (2) TAPE AND REEL (3) -40C to 85C bq30z554-R1 TSSOP-30 DBT bq30z554-R1 bq30z554DBT-R1 bq30z554DBTR-R1 (1) (2) (3) For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI website at www.ti.com. A single tube quantity is 50 units. A single reel quantity is 2000 units. THERMAL INFORMATION bq30z554-R1 THERMAL METRIC (1) TSSOP UNITS 30 PINS JA, High K Junction-to-ambient thermal resistance (2) 73.1 (3) JC(top) Junction-to-case(top) thermal resistance JB Junction-to-board thermal resistance JT Junction-to-top characterization parameter JB Junction-to-board characterization parameter JC(bottom) (1) (2) (3) (4) (5) (6) (7) 2 17.5 (4) 34.5 (5) Junction-to-case(bottom) thermal resistance 0.3 (6) (7) C/W 30.3 n/a For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 TYPICAL IMPLEMENTATION 3M PACK + 5.1k VCC CHG 10k DSG 5.1k FUSE BAT 5.1k 3M PACK FUSE Control Cell Balancing High Side N-CH FET Drive 16-bit Voltage Sensing Voltage Protections Impedance Track Gauging SHA-1 Authentication 3.3V LDO 16-bit Current Sensing Current Protections Internal Cell Short Detection JEITA Charging Algorithm 2.5V LDO 16-bit Temperature Sensing Voltage Protections Lifetime Data Collection Black Box Recorder SMBus 1.1 VC1 CD VH 1k VM 1k VC2 OUT VC3 VDD VL 1k VC4 GND VB 1k REG33 REG25 SMBD SMBD SMBC 200 100 PRES 200 100 PTC SMBC SBD 1.1 0.1F 0.1F TS2 100 1k 10k 0.1F SRN 10k SRP 10k VSS TS1 10k PRES PACK- 5m Figure 1. bq30z554-R1 Implementation Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 3 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com TERMINAL FUNCTIONS 4 PIN NAME PIN NUMBER TYPE DESCRIPTION CHG 1 O Discharge N-FET gate drive BAT 2 P Alternate power source VC1 3 I Sense input for positive voltage of the top-most cell in the series, and cell balancing input for the top-most cell in the series VC2 4 I Sense input for positive voltage of the third lowest cell in the series, and cell balancing input for the third lowest cell in the series VC3 5 I Sense input for positive voltage of the second lowest cell in the series, and cell balancing input for the second lowest cell in the series VC4 6 I Sense input for positive voltage of the lowest cell in the series, and cell balancing input for the lowest cell in the series VSS 7 P Device ground TS1 8 AI Temperature sensor 1 thermistor input SRP 9 AI Differential coulomb counter input TS2 11 AI Temperature sensor 2 thermistor input Differential coulomb counter input SRN 10 AI PRES 12 I SMBD 13 I/OD Host system present input SBS 1.1 data line NC 14 -- SMBC 15 I/OD Not connected, connect to VSS SBS 1.1 clock line GPIO 16 I/OD General Purpose Input-Output NC 17,18,19,20 -- Not connected RBI 21 P RAM backup REG25 22 P 2.5-V regulator output VSS 23 P Device ground REG33 24 P 3.3-V regulator output PTC 25 -- Test pin connect to VSS FUSE 26 O Fuse drive VCC 27 P GPOD 28 I/OD Power supply voltage PACK 29 P Alternate power source DSG 30 O Charge N-FET gate drive High voltage general purpose I/O Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 PINOUT DIAGRAM CHG 1 30 DSG BAT 2 29 PACK VC1 3 28 GPOD VC2 4 27 VCC VC3 5 26 FUSE VC4 6 25 PTC VSS 7 24 REG33 TS1 8 23 VSS SRP 9 22 REG25 SRN 10 21 RBI TS2 11 20 NC PRES 12 19 NC SMBD 13 18 NC NC 14 17 NC SMBC 15 16 GPIO Figure 2. bq30z554-R1 Pinout Diagram PIN EQUIVALENT DIAGRAMS Power FET Drive GPOD BAT GPOD CHG Charge Pump VCC DSG Charge Pump PACK Figure 3. Pin Equivalent Diagram 1 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 5 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com Power Supply SMB SMBC BAT SBS Engine FUSE, PTC VCC SMBD CHG Charge Pump 1M 1M REG33 REG25 Regulator Regulator Thermistor input REG25 PTC PTC 18k 80 TSx ADC PACK FUSE PACK BAT DSG Chargepump FUSE Figure 4. Pin Equivalent Diagram 2 6 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 V1, V2, V3, V4 V1, V2, V3, V4 PRES ADC MUX REG25 880k PRES 180k Cell Balancing SRN, SRP V4 SRN SC, OL comparator V3 Coulomb Counter SRP V2 RBI REG25 RBI V1 VSS Figure 5. Pin Equivalent Diagram 3 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 7 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) DESCRIPTION Supply voltage range, VMAX Input voltage range, VIN PINS VALUE VCC, PTC, PACK w.r.t. Vss -0.3 V to 34 V VC1, BAT VVC2 - 0.3 V to VVC2 + 8.5 or 34 V, whichever is lower VC2 VVC3 - 0.3 V to VVC3 + 8.5 V VC3 VVC4 - 0.3 V to VVC4 + 8.5 V VC4 VSRP- 0.3 V to VSRP + 8.5 V SRP, SRN -0.3 V to 0.3 V SMBC, SMBD VSS - 0.3 V to 6.0 V TS1, TS2, PRES, GPIO -0.3 V to VREG25 + 0.3 V DSG -0.3 V to VPACK + 20 V or VSS + 34 V, whichever is lower CHG -0.3 V to VBAT + 20 V or VSS+ 34 V, whichever is lower GPOD, FUSE -0.3 V to 34 V RBI, REG25 -0.3 V to 2.75 V REG33 -0.3 V to 5.0 V Output voltage range, VO Maximum VSS current, ISS 50 mA Current for cell balancing, ICB 10 mA ESD Rating HBM, VCx Only 1 kV Functional Temperature, TFUNC -40 to 110 C Storage temperature range, TSTG -65 to 150 C Lead temperature (soldering, 10 s), TSOLDER 300 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) MIN Supply voltage VSTARTUP VIN Input voltage range VCC, PACK BAT Start up voltage at PACK 3.8 MAX UNIT 25 V VVC2 + 5.0 3.0 5.5 VC1, BAT VVC2 VVC2 + 5.0 VC2 VVC3 VVC3 + 5.0 VC3 VVC4 VVC4 + 5.0 VC4 VSRP VSRP + 5.0 0 5.0 VCn - VC(n+1), (n=1, 2, 3, 4) PACK PTC SRP to SRN CREG33 External 3.3-V REG capacitor 0 2 -0.2 0.2 -40 Submit Documentation Feedback V V V F 1 TOPR Operating temperature V 25 1 CREG25 External 2.5-V REG capacitor 8 TYP F 85 C Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 ELECTRICAL CHARACTERISTICS: Supply Current Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER ICC TEST CONDITIONS MIN TYP MAX UNIT Normal CHG on, DSG on, no Flash write 410 A Sleep CHG off, DSG on, no SBS Communication 129 A CHG off, DSG off, no SBS Communication 83 A Shutdown 1 A ELECTRICAL CHARACTERISTICS: Power On Reset (POR) Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) MIN TYP MAX UNIT VIT- Negative-going voltage input PARAMETER At REG25 TEST CONDITIONS 1.9 2.0 2.1 V VHYS POR Hysteresis At REG25 65 125 165 mV ELECTRICAL CHARACTERISTICS: WAKE FROM SLEEP Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VWAKE VWAKE Threshold MIN TYP MAX UNIT VWAKE = 1.2 mV TEST CONDITIONS 0.2 1.2 2.0 mV VWAKE = 2.4 mV 0.4 2.4 3.6 VWAKE = 5 mV 2.0 5.0 6.8 VWAKE = 10 mV 5.3 10 13 VWAKE_TCO Temperature drift of VWAKE accuracy 0.5 tWAKE Time from application of current and wake of bq30z554-R1 0.2 %/C 1 ms ELECTRICAL CHARACTERISTICS: RBI RAM Backup Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VRB > V(RB)MIN, VCC < VIT I(RBI) RBI data-retention input current V(RBI) RBI data-retention voltage TYP MAX UNIT 20 1100 nA VRB > V(RB)MIN, VCC < VIT, TA = 0 C to 70 C 500 1 V ELECTRICAL CHARACTERISTICS: 3.3-V Regulator Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VREG33 IREG33 Regulator output voltage TEST CONDITIONS MIN 3.8 V < VCC or BAT 5 V, ICC 4 mA 2.4 5 V < VCC or BAT 6.8 V, ICC 13 mA 3.1 6.8 V < VCC or BAT 20 V, ICC 30 mA 3.1 Regulator Output Current TYP MAX UNIT 3.5 V 3.3 3.5 V 3.3 3.5 V 2 mA Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 9 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS: 3.3-V Regulator (continued) Typical values stated where TA = 25 C and VCC = 14.4 V, Min/Max values stated where TA = -40 C to 85 C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(VDDTEMP) Regulator output change with temperature VCC or BAT = 14.4 V, IREG33 = 2 mA 0.2 V(VDDLINE) Line regulation VCC or BAT = 14.4 V, IREG33 = 2 mA 1 13 mV V(VDDLOAD) Load regulation VCC or BAT = 14.4 V, IREG33 = 2 mA 5 18 mV VCC or BAT = 14.4 V, REG33 = 3 V 70 mA VCC or BAT = 14.4 V, REG33 = 0 V 33 I(REG33MAX) Current limit % ELECTRICAL CHARACTERISTICS: 2.5-V Regulator Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.35 2.5 2.55 V VREG25 Regulator output voltage IREG25 Regulator Output Current V(VDDTEMP) Regulator output change with temperature VCC or BAT = 14.4 V, IREG25 = 2 mA 0.25 V(VDDLINE) Line regulation VCC or BAT = 14.4 V, IREG25 = 2 mA 1 4 mV VCC or BAT = 14.4 V, IREG25 = 2 mA 20 40 mV VCC or BAT = 14.4 V, REG25 = 2.3 V 65 mA VCC or BAT = 14.4 V, REG25 = 0 V 23 V(VDDLOAD) Load regulation I(REG33MAX) Current limit IREG25 = 10 mA 3 mA % ELECTRICAL CHARACTERISTICS: PRES, SMBD, SMBC, GPIO Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VIH VIL TEST CONDITIONS MIN High-level input PRES, SMBD, SMBC, GPIO 2.0 Low-level input PRES, SMBD, SMBC, GPIO IL = -0.5 mA VOL Low-level output voltage SMBD, SMBC, GPIO, IL = 7 mA Input capacitance PRES, SMBD, SMBC, GPIO ILKG Input leakage current PRES, SMBD, SMBC, GPIO IWPU Weak Pull Up Current PRES, GPIO, VOH = VREG25 - 0.5 V 60 RPD(SMBx) SMBC, SMBD Pull-Down TA = -40 C to 100 C 550 Submit Documentation Feedback MAX UNIT V 0.8 CIN 10 TYP 0.4 5 V pF 1 775 V A 120 A 1000 k Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 ELECTRICAL CHARACTERISTICS: CHG, DSG FET Drive Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER V(FETON) V(FETOFF) tr tf Output voltage, charge, and discharge FETs on Output voltage, charge and discharge FETs off Rise time Fall time TEST CONDITIONS MIN TYP MAX UNIT VO(FETONDSG) = V(DSG) - VPACK, VGS connect 10 M, VCC 3.8 V to 8.4 V 8.0 9.7 12 V VO(FETONDSG) = V(DSG) - VPACK, VGS connect 10 M, VCC > 8.4 V 9.0 11 12 V VO(FETONCHG) = V(CHG) - VBAT, VGS connect 10 M, VCC 3.8 V to 8.4 V 8.0 9.7 12 V VO(FETONCHG) = V(CHG) - VBAT, VGS connect 10 M, VCC > 8.4 V 9.0 11 12 V VO(FETOFFDSG) = V(DSG) - VPACK -0.4 0.4 V VO(FETOFFCHG) = V(CHG) - VBAT -0.4 0.4 V CL = 4700 pF RG= 5.1 k VCC <8.4 VDSG: VBAT to VBAT + 4 V, VCHG: VPACK to VPACK + 4 V 800 1400 s CL = 4700 pF RG= 5.1 k VCC >8.4 VDSG: VBAT to VBAT + 4 V, VCHG: VPACK to VPACK + 4 V 200 500 s CL = 4700 pF RG= 5.1 k VDSG: VBAT+ VO(FETONDSG) to VBAT + 1V VCHG: VPACK + VO(FETONCHG) to VPACK + 1 V 80 200 s ELECTRICAL CHARACTERISTICS: GPOD Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VPU_GPOD GPOD Pull Up Voltage VOL_GPOD GPOD Output Voltage Low TEST CONDITIONS IOL = 1 mA MIN TYP MAX UNIT VCC V 0.3 V ELECTRICAL CHARACTERISTICS: FUSE Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VOH(FUSE) High Level FUSE Output TEST CONDITIONS MIN VCC = 3.8 V to 9 V 2.4 VCC = 9 V to 25 V 7 TYP 8 MAX UNIT 8.5 V 9 V 2.8 VIH(FUSE) Weak Pull Up Current in off state Ensured by design. Not production tested. tR(FUSE) FUSE Output Rise Time CL = 1 nF, VCC = 9 V to 25V, VOH(FUSE) = 0 V to 5 V ZO(FUSE) FUSE Output Impedance V 100 nA 5 20 s 2 5 k Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 11 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS: PTC Thermistor Support Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER RPTC PTC IO(PTC) PTC tPTC PTC Blanking Delay TEST CONDITIONS MIN TYP MAX UNIT 1.3 2 2.7 M TA = -40 C to 110 C -450 -370 -230 nA TA = -40 C to 110 C 60 80 110 ms VPTC = 0 to 2 V, TA = -40 C to 110 C VPTC = 0 to 2 V ELECTRICAL CHARACTERISTICS: COULOMB COUNTER Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS Input voltage range SRP - SRN Conversion time Single conversion Resolution (no missing codes) VIN MIN TYP -0.20 MAX 0.25 250 Single conversion, signed Offset error Post Calibrated Full-scale error bits 15 bits 10 Offset error drift -0.8% V 0.3 0.5 0.2% 0.8% Full-scale error drift 150 Effective input resistance V ms 16 Effective resolution UNIT 2.5 V/C PPM/C M ELECTRICAL CHARACTERISTICS: VC1, VC2, VC3, VC4 Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VIN TEST CONDITIONS Input voltage range VC4 - VC3, VC3 - VC2, VC2 - VC1, VC1 - VSS Conversion time Single conversion Resolution (no missing codes) R(BAL) MIN TYP -0.20 MAX UNIT 8 V 32 ms 16 bits bits Effective resolution Single conversion, signed 15 RDS(ON) for internal FET at VDS > 2V VDS = VC4 - VC3, VC3 - VC2, VC2 - VC1, VC1 - VSS 200 310 430 RDS(ON) for internal FET at VDS > 4V VDS = VC4 - VC3, VC3 - VC2, VC2 - VC1, VC1 - VSS 60 125 230 ELECTRICAL CHARACTERISTICS: TS1, TS2 Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER R Internal Pull Up Resistor RDRIFT Internal Pull Up Resistor Drift from 25 C RPAD Internal Pin Pad resistance 12 TEST CONDITIONS MIN TYP MAX UNIT 16.5 17.5 19.0 K 200 PPM/C 84 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 ELECTRICAL CHARACTERISTICS: TS1, TS2 (continued) Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER Input voltage range TEST CONDITIONS TS1 - VSS, TS2 - VSS MIN TYP -0.20 MAX UNIT 0.8xVREG2 V 5 Conversion Time VIN 16 Resolution (no missing codes) 16 Effective resolution 11 ms Bits 12 Bits ELECTRICAL CHARACTERISTICS: Internal Temperature Sensor Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS Temperature sensor voltage V(TEMP) MIN TYP MAX UNIT -1.9 -2.0 -2.1 mV/C Conversion Time 16 Resolution (no missing codes) 16 Effective resolution 11 ms Bits 12 Bits ELECTRICAL CHARACTERISTICS: Internal Thermal Shutdown Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 125 MAX UNIT TMAX Maximum REG33 temperature TRECOVER Recovery hysteresis temperature 10 175 C tPROTECT Protection time 5 s ELECTRICAL CHARACTERISTICS: High Frequency Oscillator Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER f(OSC) f(EIO) t(SXO) (1) (2) (3) TEST CONDITIONS MIN Operating frequency of CPU Clock Frequency error (1) (2) Start-up time (3) TYP MAX 4.194 MHz TA = -20 C to 70 C -2% 0.25% 2% TA = -40 C to 85 C -3% 0.25% 3% 3 6 TA = -25 C to 85 C UNIT ms The frequency error is measured from 4.194 MHz. The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25C. The startup time is defined as the time it takes for the oscillator output frequency to be 3% when the device is already powered. ELECTRICAL CHARACTERISTICS: Low Frequency Oscillator Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER f(LOSC) f(LEIO) Frequency error (1) (2) t(LSXO) Start-up time (3) (1) (2) (3) TEST CONDITIONS MIN Operating frequency TYP MAX UNIT 32.768 kHz TA = -20 C to 70 C -1.5% 0.25% 1.5% TA = -40 C to 85 C -2.5% 0.25% 2.5% TA = -25 C to 85 C 100 s The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25 C. The frequency error is measured from 32.768 kHz. The startup time is defined as the time it takes for the oscillator output frequency to be 3 %. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 13 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS: Internal Voltage Reference Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VREF TEST CONDITIONS Internal Reference Voltage VREF_DRIFT Internal Reference Voltage Drift MIN TYP MAX UNIT 1.215 1.225 1.230 V TA = -25 C to 85 C 80 PPM/C TA = 0 C to 60 C 50 PPM/C ELECTRICAL CHARACTERISTICS: Flash Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER (1) TEST CONDITIONS Data retention Flash programming write-cycles MIN TYP MAX UNIT 10 Years Data Flash 20k Cycles Instruction Flash 1k Cycles ICC(PROG_DF) Data Flash-write supply current TA = -40C to 85C 3 4 mA ICC(ERASE_DF) Data Flash-erase supply current TA = -40C to 85C 3 18 mA (1) Assured by design. Not production tested. ELECTRICAL CHARACTERISTICS: OCD Current Protection Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER OCD detection threshold voltage range, typical V(OCD) TEST CONDITIONS MIN TYP MAX UNIT RSNS = 0 50 200 mV RSNS = 1 25 100 mV RSNS = 0 10 mV V(OCDT) OCD detection threshold voltage program step V(OFFSET) OCD offset -10 10 V(Scale_Err) OCD scale error -10 10 % t(OCDD) Overcurrent in Discharge Delay 1 31 ms t(OCDD_STEP) OCDD Step options RSNS = 1 5 mV 2 t(DETECT) Current fault detect time VSRP - SRN = VTHRESH + 12.5 mV tACC Overcurrent and Short Circuit delay time accuracy Accuracy of typical delay time -20 mV ms 160 s 20 % ELECTRICAL CHARACTERISTICS: SCD1 Current Protection Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT 450 mV 225 mV V(SDC1) V(SCD1T) SCD1 detection threshold voltage RSNS = 0 program step RSNS = 1 V(OFFSET) SCD1 offset -10 10 V(Scale_Err) SCD1 scale error -10 10 % AFE.STATE_CNTL[SCDDx2] = 0 0 915 s AFE.STATE_CNTL[SCDDx2] = 1 0 1830 s t(SCD1D) Short Circuit in Discharge Delay t(SCD1D_STEP) 14 SCD1D Step options 100 MAX SCD1 detection threshold voltage RSNS = 0 range, typical RSNS = 1 50 50 mV 25 mV mV AFE.STATE_CNTL[SCDDx2] = 0 61 s AFE.STATE_CNTL[SCDDx2] = 1 122 s Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 ELECTRICAL CHARACTERISTICS: SCD1 Current Protection (continued) Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS t(DETECT) Current fault detect time VSRP-SRN = VTHRESH + 12.5 mV tACC Overcurrent and Short Circuit delay time accuracy Accuracy of typical delay time MIN TYP -20 MAX UNIT 160 s 20 % ELECTRICAL CHARACTERISTICS: SCD2 Current Protection Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT 450 mV 225 mV V(SDC2) V(SCD2T) SCD2 detection threshold voltage RSNS = 0 program step RSNS = 1 V(OFFSET) SCD2 offset -10 10 V(Scale_Err) SCD2 scale error -10 10 % AFE.STATE_CNTL[SCDDx2] = 0 0 458 s AFE.STATE_CNTL[SCDDx2] = 1 0 915 s t(SCD1D) t(SCD2D_STEP) Short Circuit in Discharge Delay SCD2D Step options 100 MAX SCD2 detection threshold voltage RSNS = 0 range, typical RSNS = 1 50 50 mV 25 mV mV AFE.STATE_CNTL[SCDDx2] = 0 30.5 s AFE.STATE_CNTL[SCDDx2] = 1 61 s t(DETECT) Current fault detect time VSRP - SRN = VTHRESH + 12.5 mV tACC Overcurrent and Short Circuit delay time accuracy Accuracy of typical delay time -20 160 s 20 % ELECTRICAL CHARACTERISTICS: SCC Current Protection Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) MAX UNIT V(SCCT) SCC detection threshold voltage range, typical PARAMETER RSNS = 0 TEST CONDITIONS -100 MIN TYP -300 mV RSNS = 1 -50 -225 mV V(SCCDT) SCC detection threshold voltage program step RSNS = 0 -50 RSNS = 1 -25 V(OFFSET) SCC offset -10 10 mV V(Scale_Err) SCC scale error -10 10 % t(SCCD) Short Circuit in Charge Delay 915 ms t(SCCD_STEP) SCCD Step options 0 mV mV 61 t(DETECT) Current fault detect time VSRP - SRN = VTHRESH + 12.5 mV tACC Overcurrent and Short Circuit delay time accuracy Accuracy of typical delay time -20 ms 160 s 20 % ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS fSMB SMBus operating frequency SLAVE mode, SMBC 50% duty cycle fMAS SMBus master clock frequency MASTER mode, no clock low slave extend MIN TYP 10 MAX UNIT 100 kHz 51.2 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 kHz 15 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics (continued) Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tBUF Bus free time between start and stop 4.7 s tHD:STA Hold time after (repeated) start 4.0 s tSU:STA Repeated start setup time 4.7 s tSU:STO Stop setup time 4.0 s tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 250 tTIMEOUT Error signal/detect See (1) tLOW Clock low period tHIGH Clock high period See (2) tHIGH Clock high period See (2) tLOW:SEXT Cumulative clock low slave extend time See tLOW:MEXT Cumulative clock low master extend time tF tR (1) (2) (3) (4) (5) (6) ns 25 35 4.7 ms s Disabled 4.0 50 s (3) 25 ms See (4) 10 ms Clock/data fall time See (5) 300 ns Clock/data rise time See (6) 1000 ns The bq30z554-R1 times out when any clock low exceeds tTIMEOUT. tHIGH, Max, is the minimum bus idle time. SMBC = 1 for t > 50 s causes reset of any transaction involving bq30z554-R1 in progress. This specification is valid when the THIGH_VAL = 0. If THIGH_VAL = 1 then the value of THIGH is set by THIGH_1,2 and the timeout is not SMBus standard. tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. Rise time tR = VILMAX - 0.15) to (VIHMIN + 0.15) Fall time tF = 0.9 VDD to (VILMAX - 0.15) ELECTRICAL CHARACTERISTICS: SBS XL Timing Characteristics Typical values stated where TA = 25C and VCC = 14.4 V, Min/Max values stated where TA = -40C to 85C and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MAX UNIT 400 kHz SMBus XL operating frequency tBUF Bus free time between start and stop 4.7 s tHD:STA Hold time after (repeated) start 4.0 s tSU:STA Repeated start setup time 4.7 s tSU:STO Stop setup time 4.0 tTIMEOUT Error signal/detect tLOW Clock low period tHIGH Clock high period 16 See (1) See (2) 40 TYP fSMBXL (1) (2) SLAVE mode MIN 5 s 20 ms 20 s 20 s The bq30z554-R1 times out when any clock low exceeds tTIMEOUT. tHIGH, Max, is the minimum bus idle time. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 tR tSU(STOP) tF tF tDH(STA) T(BUF) tW(H) SMBC SMBC SMBD SMBD P tR S tW(L) tHD(DATA) tSU(DATA) tSU(STA) t(TIMEOUT) SMBC SMBC SMBD SMBD S Figure 6. SMBus Timing Diagram Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 17 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com FEATURE SET Protections Safety Features The bq30z554-R1 supports a wide range of battery and system protection features that can easily be configured. The Protections safety features include: * * * * * * * * * * * * * * * * * Cell Undervoltage Protection Cell Undervoltage I*R Compensated Protection Cell Overvoltage Protection Overcurrent in Charge Protection 1 and 2 Overcurrent in Discharge Protection 1 and 2 Overload in Discharge Protection Short Circuit in Charge Protection Short Circuit in Discharge Protection 1 and 2 Overtemperature in Charge Protection Overtemperature in Discharge Protection Overtemperature FET protection SBS Host Watchdog Protection Precharge Timeout Protection Fast Charge Timeout Protection Overcharge Protection Overcharging Current Protection Overcharging Voltage Protection Permanent Fail Safety Features The FUSE pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. Upon a Permanent Fail event trigger, critical system information is written to non-volatile memory to simplify failure analysis. In addition, the black box stores the sequence of safety events also into non-volatile memory to simplify failure analysis. The Permanent Fail safety features include: * Cell Undervoltage Protection * Cell Overvoltage Protection * Copper Deposition * Overtemperature Cell * Overtemperature FET * QMAX Imbalance * Cell Balancing * Capacity Degradation * Impedance * Voltage Imbalance at Rest * Voltage Imbalance Active * Charge FET and Discharge FET * Thermistor * Chemical FUSE * AFE Register * AFE Communication * 2nd-Level Protection * PTC * Instruction Flash * Open Cell Tab Connection * Data Flash 18 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 Charge Control Features The bq30z554-R1 Charge Control features include: * Supports JEITA temperature ranges T1, T2, T3, T4, T5, T6. Reports charging voltage and charging current, according to the active temperature range. * Handles more complex charging profiles. Allows for splitting the standard temperature range into two subranges, and allows for varying the charging current according to the cell voltage. * Reports the appropriate charging current needed for constant current charging and the appropriate charging voltage needed for constant voltage charging to a smart charger using SMBus broadcasts. * Determines the chemical state of charge of each battery cell using Impedance Track and can reduce the charge difference of the battery cells in a fully charged state of the battery pack, gradually using the cell balancing algorithm during rest and charging. This prevents fully charged cells from overcharging and causing excessive degradation, and also increases the usable pack energy by preventing premature charge termination. * Supports precharging/zero-volt charging * Supports charge inhibit and charge suspend if the battery pack temperature is out of temperature range. * Reports charging fault and also indicates charge status via charge and discharge alarms. Gas Gauging The bq30z554-R1 uses the Impedance Track technology to measure and calculate the available charge in battery cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge or discharge learning cycle required. See the Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application report (SLUA364B) for further details. Lifetime Data Logging Features The bq30z554-R1 offers extended lifetime data logging where important measurements are stored for warranty and analysis purposes. The data monitored includes lifetime: * Maximum cell voltage cell0, cell1, cell2, cell3 * Minimum cell voltage cell0, cell1, cell2, cell3 * Maximum cell voltage delta * Maximum charge and discharge current * Maximum average discharge current * Maximum average discharge power * Maximum cell temperature * Minimum cell temperature * Maximum cell temperature delta * Maximum device temperature * Minimum device temperature * Maximum FET temperature * Total accumulated safety events and last safety event in term of charging cycle * Total accumulated charging events and charging events * Total accumulated gauging events and gauging events * Total accumulated cell balancing time cell0, cell1, cell2, cell3 * Total device firmware runtime * Accumulated runtime in JEITA undertemperature range * Accumulated runtime in JEITA low temperature range * Accumulated runtime in JEITA standard temperature range * Accumulated runtime in JEITA recommended temperature range * Accumulated runtime in JEITA high temperature range * Accumulated runtime in JEITA overtemperature range Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 19 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com Authentication * * The bq30z554-R1 supports authentication by the host using SHA-1. SHA-1 authentication by the gas gauge is required for unsealing and full access. Power Modes The bq30z554-R1 supports five power modes to reduce power consumption: * In NORMAL mode, the bq30z554-R1 performs measurements, calculations, protection decisions, and data updates in 0.25-s intervals. Between these intervals, the bq30z554-R1 is in a reduced power stage. In addition, the device will provide information for peak TURBO mode power operation. * The bq30z554-R1 supports a TURBO mode operation by providing information to the host MCU about the battery pack's ability to deliver peak power. The method of operation is based on the host MCU reading register 0x59 (TURBO_POWER) to determine if the selected power level for TURBO mode operation of the MCU is below the max power reported by the gas gauge. Additionally, the device reports current information during the power pulse by reading register 0x5E (TURBO_CURRENT). The information reported by these two registers allows the MCU to determine if the selected TURBO mode operation is safe and will not cause any system reset due to transient power pulses. * In SLEEP mode, the bq30z554-R1 performs measurements, calculations, protection decisions, and data updates in adjustable time intervals. Between these intervals, the bq30z554-R1 is in a reduced power stage. The bq30z554-R1 has a wake function that enables exit from SLEEP mode when current flow or failure is detected. * In SHUTDOWN mode, the bq30z554-R1 is completely disabled. * In SHIP mode, the bq30z554-R1 enters a low-power mode with no voltage, current, and temperature measurements, the FETs are turned off, and the MCU is in a halt state. The device wakes up upon SMBus communication detection. NOTE For a detailed description of the SBS Commands and Data Flash (DF) Registers, refer to the bq30z554-R1 Technical Reference Manual (SLUUA79). Configuration System Present Operation The bq30z554-R1 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system, the bq30z554-R1 detects this as system present. Battery Power Interrupt Operation The bq30z554-R1 can interrupt the battery power by using an external push-button switch and detecting a lowlevel threshold signal on the GPIO terminal (pin should be configured with an internal pull-up). Once the push button is pressed, there is a delay of 1 s (default) for debounce to detect the low-level threshold. There is also a data flash command for the battery power interrupt timeout. The default value is 30 minutes. If the push-button switch is selected before this timeout, the battery power is restored based on this action. Timeout Configuration The timeout feature allows the battery power to be restored once the timer expires. Alternatively, if the value is set to 0, this feature is disabled. Class Subclass ID Subclass Offset Name Type Min Max Default Unit Power 248 Power Off 0 Timeout U2 0 65535 30 min 20 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 BATTERY PARAMETER MEASUREMENTS Charge and Discharge Counting The bq30z554-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage and temperature measurements. The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar signals from -0.25 V to 0.25 V. The bq30z554-R1 detects charge activity when VSR = V(SRP) - V(SRN) is positive, and discharge activity when VSR = V(SRP) - V(SRN) is negative. The bq30z554-R1 continuously integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.65 nVh. Voltage The bq30z554-R1 updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the bq30z554-R1 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the Impedance Track gas gauging. Current The bq30z554-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 5-m to 20-m typ. sense resistor. Auto Calibration The bq30z554-R1 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for maximum charge measurement accuracy. The bq30z554-R1 performs auto-calibration when the SMBus lines stay low continuously for a minimum of 5 s. Temperature The bq30z554-R1 has an internal temperature sensor and inputs for four external temperature sensors. All five temperature sensor options are enabled individually and configured for cell or FET temperature. Two configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET temperature, which may be of a higher temperature type. CELL BALANCING The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time. Higher cell balance current can be achieved by using an external cell balancing circuit. In EXTERNAL CELL BALANCING mode, only one cell at a time can be balanced. The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of all cells. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 21 Not Recommended for New Designs bq30z554-R1 SLUSBD4 - OCTOBER 2013 www.ti.com Internal Cell Balancing When internal cell balancing is configured, the cell balance current is defined by the external resistor RVC at the VCx input. RVC VC1 RVC VC2 RVC VC3 RVC VC4 VSS External Cell Balancing When internal cell balancing is configured, the cell balance current is defined by RB. Only one cell at a time can be balanced. RVC VC1 RVC VC2 RVC VC3 RVC VC4 RB RB RB RB VSS 22 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 Not Recommended for New Designs bq30z554-R1 www.ti.com SLUSBD4 - OCTOBER 2013 Push Button Switch bq30z554-R1 Application Schematic Figure 7. bq30z554-R1 Schematic Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links :bq30z554-R1 23 PACKAGE OPTION ADDENDUM www.ti.com 4-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) BQ30Z554DBT-R1 NRND TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ30Z554 BQ30Z554DBTR-R1 NRND TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ30Z554 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Sep-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ30Z554DBTR-R1 Package Package Pins Type Drawing TSSOP DBT 30 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ30Z554DBTR-R1 TSSOP DBT 30 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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