AN32183A
Page 1 of 56
Product Standards
FEATURES DESCRIPTION
9 x 9 Dots Matrix LED Driver LSI
AN32183A is a 81 Dots Matrix LED Driver.
It can drive up to 27 RGB LEDs.
9 9 LED Matrix Driver
(Total LED that can be driven = 81)
LED Selectable Maximum Current
LED Music Synchronizing Function
I2C interface (Standard Mode, Fast Mode and
Fast Mode Plus)
(4 Slave address selectable)
24 pin Shrink Small Outline Package (SSOP24 Type)
TYPICAL APPLICATION
APPLICATIONS
Note)
This application circuit is an example. The operation of the mass production set is not guaranteed. Customers shall perform
enough evaluation and verification on the design of mass production set. Customers shall be fully responsible for the incorporation
of the above application circuit and information in the design of the equipment.
VCC1
VCC2
Battery
AGND
PGND1
PGND2
SDA
NRST
39 k
SCL
SLAVSEL
IREF
CLKIO
LDO
1.0 F
CPU I/F
VDD
Z4
Z3
Z5
Z1
Z2
Z9
Z8
Z10
Z6
Z7
http://www.semicon.panasonic.co.jp/en/
Mobile Phone
Smart Phone
PCs
Game Consoles
Home Appliances etc.
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 2 of 56
Product Standards
CONTENTS
FEATURES ……………………………………………………………………… 1
DESCRIPTION ……………………………………………………………………… 1
APPLICATIONS ……………………………………………………………………… 1
TYPICAL APPLICATION ………………………………………………………………… 1
ABSOLUTE MAXIMUM RATINGS ……………………………………………………… 3
POWER DISSIPATION RATING ………………………………………………………… 3
RECOMMENDED OPERATING CONDITIONS ………………………………………… 4
ELECTRICAL CHARACTERISTICS .…………………………………………………… 5
PIN CONFIGURATION …………………………………………………………………… 11
PIN FUNCTIONS …………………………………………………………………………12
FUNCTIONAL BLOCK DIAGRAM ……………………………………………………… 13
OPERATION ……………………………………………………………………………… 15
PACKAGE INFORMATION ………………………………………………………………55
IMPORTANT NOTICE………………………………………………………………………56
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 3 of 56
Product Standards
ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION RATING
Note) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply
voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does
not exceed the allowable value.
*2C– 30 to + 85Topr
Operating ambience temperature
*2C– 30 to + 125Tj
Operating junction temperature
*2C–55to+125Tstg
Storage temperature
—V– 0.3 to 6.0
SLAVSEL, SCL, SDA,
CLKIO, NRST
Input Voltage Range
Output Voltage Range —V– 0.3 to 6.0
LDO, CLKIO,
Z1, Z2, Z3, Z4, Z5,
Z6, Z7, Z8, Z9, Z10
—kV2.0HBMESD
*1V6.0VDDMAX
NoteUnitRatingSymbolParameter
*1V6.0VCCMAX
Supply voltage
Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum
rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than
our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the
reliability of the product may be affected.
*1: VCCMAX = VCC, VDDMAX = VDD.
The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for
Ta = 25C.
0.296 W0.740 W135.1 C /W
24 pin Shrink Small Outline Package (SSOP24 Type)
PD(Ta=85 C)PD(Ta=25 C)JA
PACKAGE
CAUTION
Although this LSI has built-in ESD protection circuit, it may still sustain permanent damage if not handled
properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS
gates.
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 4 of 56
Product Standards
RECOMMENDED OPERATING CONDITIONS
*2VVDD + 0.3—–0.3
SLAVSEL, SCL, SDA,
CLKIO
Input Voltage Range
*2VVCC + 0.3—–0.3NRST
*2VVCC + 0.3—–0.3
LDO, CLKIO,
Z1, Z2, Z3, Z4, Z5,
Z6, Z7, Z8, Z9, Z10
Output Voltage Range
*1V
5.55.03.1VCC
5.0
Typ.
1.7
Min.
*1V
5.5VDD
Supply voltage range
NoteUnitMax.SymbolParameter
Note) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
Do not apply external currents and voltages to any pin not specifically mentioned.
Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, PGND1 and GND2.
VCC is voltage for VCC1 and VCC2. VDD is voltage for VDD.
*2 : (VCC + 0.3 ) V must not exceed 6 V. (VDD + 0.3) V must not exceed 6 V.
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 5 of 56
Product Standards
V2.952.852.75ILDO = – 10 mAVL1Output voltage (1)
Constant Voltage Source (LDO)
Internal Oscillator
—A500250—NRST = HighICC2
Circuit Current (2)
OFF Mode
SCAN Switch
—MHz2.882.401.92VCC = 3.6 VFDC1Oscillation Frequency
V2.952.852.75ILDO = –15mAVL2Output voltage (2)
—31.5—
VCC = 3.6 V
IZ1~Z9 = – 20 mA
RSCANSwitch On Resistance
—V
VDD
+ 0.3
—
0.7
VDD
High Level Acknowledged
Voltage (At External CLK
Input Mode)
VIH1High Level Input Voltage Range
CLKIO
—V
VDD
+ 0.3
—
0.8
VDD
ICLKIO = –1mA
(At Internal CLK Output
Mode)
VOH1High Level Output Voltage
—V
0.3
VDD
—–0.3
Low Level Acknowledged
Voltage (At External CLK
Input Mode)
VIL1Low Level Input Voltage Range
—V
0.2
VDD
—–0.3
ICLKIO = 1 mA
(At Internal CLK Output
Mode)
VOL1Low Level Output Voltage
—A10–1
VCC = 5.5 V
VCLKIO = 5.5 V
IIH1High Level input Current
—A10–1
VCC = 5.5 V
VCLKIO = 0 V
IIL1Low Level input Current
—A10—NRST = 0VICC1
Circuit Current (1)
OFF Mode
Circuit Current
Limits
Typ Unit
Max Note
Min
Condition SymbolParameter
ELECTRICAL CHARACTERISTICS
VCC = 3.6 V, VDD = 1.85 V
Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 6 of 56
Product Standards
—%5—–5
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
Difference of Z1 to 10 current from
the average current value
IMXCHChannel Difference
Voltage at which LED driver can keep constant current value
—V——0.4
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
Voltage at which LED Current
change within 5 % compared with
LED Current of pin voltage = 0.5 V.
VLD2LED Driver Voltage
—A1—–1
VCC = 5.5 V, VDD = 5.5 V
OFF Mode
VZ1~Z10 =0V
IMXOFF2OFF Mode Leak Current2
*1 mA212019
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
VZ1~Z10 =1 V
IMX1Output Current (1)
Constant Current Source (Matrix LED)
—A1—–1
VCC = 5.5 V, VDD = 5.5 V
OFF Mode
VZ1~Z10 =5.5V
IMXOFF1OFF Mode Leak Current1
—mA420
DAC Constant Current Mode
LED Current Setting = 20 mA
IMAX = [011], BRTXX = [1010]
VZ1~Z10 = 1V, IDAC1 = IZ1~Z10
LED Current Setting = 22 mA
IMAX = [011], BRTXX = [1011]
VZ1~Z10 = 1 V, IDAC2 = IZ1~Z10
DACSTEP = IDAC2 – IDAC1
DACSTEPDAC Current Step
Limits
Typ Unit
Max Note
Min
Condition SymbolParameter
Note) * 1: This is allowable value when recommended parts (ERJ2RHD393X) are used for the terminal IREF.
ELECTRICAL CHARACTERISTICS (continued)
VCC = 3.6 V, VDD = 1.85 V
Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 7 of 56
Product Standards
—V
0.2
VDD
—0
VDD < 2 V
ISDA = 3 mA
VOL2
Low-level output voltage 2
—V0.4—0
VDD > 2 V
ISDA = 3 mA
VOL1
Low-level output voltage 1
*2V
VDDmax
+ 0.5
—
0.7
VDD
Voltage which recognized that
SDA and SCL are High-level
VIH
High-level input voltage
*2V
0.3
VDD
—–0.5
Voltage which recognized that
SDA and SCL are Low-level
VIL
Low-level input voltage
—mA——20VSDA = 0.4 VIOL
Low-level output current
—A100–10
VCC = 5.5 V, VDD = 5.5 V
VSCL, VSDA = 0.1 VDDmax to 0.9
VDDmax
Ii
Input current each I/O pin
—A10–1
VCC = 5.5 V
VSLAVSEL = 0 V
IIL2Low Level Input Current
—A10–1
VCC = 5.5 V
VSLAVSEL = 3.6 V
IIH2High Level Input Current
—V
0.3
VDD
—–0.3Low Level Acknowledged VoltageVIL2
Low Level Input Voltage
Range
—V0.6—–0.3Low Level Acknowledged Voltage VIL3
Low Level Input Voltage
Range
—V
VCC
+ 0.3
—1.5High Level Acknowledged VoltageVIH3
High Level Input Voltage
Range
NRST
—A10–1
VCC = 5.5 V
VNRST = 0 V
IIL3Low Level Input Current
—A10–1
VCC = 5.5 V
VNRST = 3.6 V
IIH3High Level Input Current
I2C bus (Internal I/O stage characteristics)
—V
VDD
+ 0.3
—
0.7
VDD
High Level Acknowledged VoltageVIH2
High Level Input Voltage
Range
SLAVSEL
—kHz1 000—0—fSCL
SCL clock frequency
Limits
Typ Unit
Max Note
Min
Condition SymbolParameter
Note) VDDmax refers to the maximum operating supply voltage of VDD.
*2 : The input threshold voltage of I2C bus (Vth) is linked to VDD (I2C bus I/O stage supply voltage).
In case the pull-up voltage is not VDD, the threshold voltage (Vth) is fixed to ((VDD / 2) (Schmitt width) / 2 ) and
High-level, Low-level of input voltage are not specified. In this case, pay attention to Low-level (max.) value (VILMAX).
It is recommended that the pull-up voltage of I2C bus is set to the I2C bus I/O stage supply voltage (VDD).
ELECTRICAL CHARACTERISTICS (continued)
VCC = 3.6 V, VDD = 1.85 V
Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 8 of 56
Product Standards
MaxTyp NoteUnit
Limits
Condition SymbolParameter Min
—
0
—
0.1
VDD
0.05
VDD
—
—
—
—
—
—
—
*5
*6
ns50—tSP
Pulse width of spikes which must
be suppressed by the input filter
*5
*6
ns120
Bus capacitance :
10pF to 550pF
IP20 mA (VOLmax = 0.4 V)
IP: Max. sink current
tof
Output fall time from VIHmin to
VILmax
*5
*6
V—
VDD < 2 V,
Hysteresis of SDA, SCL
Vhys2
Hysteresis of Schmitt trigger
input 2
*5
*6
pF10—Ci
Capacitance for each I/O pin
*3
*4
C—150—
Temperature which Constant
current circuit, and Matrix SW
turn off.
TdetDetection temperature
Constant Voltage Source (LDO)
*4dB—–50
VCC = 3.6 V + 0.3 V[p-p]
f = 1 kHz
IP13 = –15 mA
PSL11 = 20log(acVP13 / 0.3)
PSL11Ripple rejection ratio (1)
*4dB—–40
VCC = 3.6 V + 0.3 V[p-p]
f = 10 kHz
IP13 = –15 mA
PSL12 = 20log(acVP13 / 0.3)
PSL12Ripple rejection ratio (2)
TSD (Thermal shutdown protection circuit)
I2C bus (Internal I/O stage characteristics) (Continued)
*4mA—40
VP13 = 0 V
IPT1 = IP13
IPT1Short-circuit protection current
*5
*6
V—
VDD > 2 V,
Hysteresis of SDA, SCL
Vhys1
Hysteresis of Schmitt trigger
input 1
Note) *3 : Constant current circuit, and Matrix SW turn off and LSI reset when TSD operates.
*4 : Typical Design Value
*5 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page.10. All values referred to VIHMIN and VILMAX level.
*6 : These are values checked by design but not production tested.
ELECTRICAL CHARACTERISTICS (continued)
VCC = 3.6 V, VDD = 1.85 V
Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 9 of 56
Product Standards
MaxTyp NoteUnit
Limits
Condition SymbolParameter Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
*5
*6
s0.26—tSU:STA
Set-up time for a repeat START
condition
*5
*6
s—0.26—tHIGH
High period of the SCL clock
*5
*6
s—0.5—tLOW
Low period of the SCL clock
*5
*6
ns120——tr
Rise time of both SDA and SCL
signals
*5
*6
ns—50—tSU:DAT
Data set-up time
*5
*6
s—0—tHD:DAT
Data hold time
*5
*6
s—0.5—tBUF
Bus free time between STOP
and START condition
*5
*6
s—0.26—tSU:STO
Set-up time of STOP condition
*5
*6
ns120——tf
Fall time of both SDA and SCL
signals
*5
*6
s0.45——tVD:ACK
Data valid acknowledge
*5
*6
s0.45——tVD:DAT
Data valid time
*5
*6
pF550—Cb
Capacitive load for each bus line
I2C bus (Bus line specifications) (Continue)
*5
*6
V—
0.1
VDD
—VnL
Noise margin at the Low-level
for each connected device
*5
*6
s—0.26
The first clock pulse is
generated after tHD:STA.
tHD:STA
Hold time
(repeated) START condition
*5
*6
V—
0.2
VDD
—VnH
Noise margin at the High-level
for each connected device
Note) *5 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page 10. All values referred to VIHMIN and VILMAX level.
*6 : These are values checked by design but not production tested.
ELECTRICAL CHARACTERISTICS (continued)
VCC = 3.6 V, VDD = 1.85 V
Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 10 of 56
Product Standards
ELECTRICAL CHARACTERISTICS (continued)
VCC = 3.6 V, VDD = 1.85 V
Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned
S : START condition
Sr : Repeat START condition
P : STOP condition
tftr
tf
70 %
30 %
SDA
SCL
tHD;STA
70 %
30 %
70 %
30 %
S1 / fSCL
1st clock cycle
tHD;DAT
tSU;DAT
70 %
30 %
70 %
30 %
tr
tLOW
70 %
30 %
tHIGH
tVD;DAT
●●●
cont.
9th clock
●●●
cont.
tHD;STA
Sr
tSP
70 %
30 %
tSU;STO
VILMAX = 0.3 VDD
VIHMIN = 0.7 VDD
tSU;STA
9th clock
tVD;ACK
tBUF
P S
SDA
SCL
●●●
●●●
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 11 of 56
Product Standards
PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
SCL
SDA
SLAVSEL
Z10
Z9
VCC2
Z8
PGND2
Z7
Z6
Z5
IREF
AGND
NRST
N.C.
CLKIO
Z1
Z2
VCC1
Z3
PGND1
Z4
LDO
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 12 of 56
Product Standards
PIN FUNCTIONS
(Required pin)Power supply for I2C interfacePower supplyVDD1
(Required pin)Clock input pin for I2C interfaceInputSCL 2
(Required pin)Data input / output pin for I2C interfaceInput/OutputSDA3
GND or VCC or
SCL or SDA
Slave address selection pin for I2C interfaceInputSLAVSEL4
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ105
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ96
Battery or External
power supply
Power supply for matrix driver, Internal reference circuitPower supplyVCC27
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ88
(Required pin)Power Ground pinGroundPGND29
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ710
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ611
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ512
(Required pin)LDO output pin OutputLDO13
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ414
(Required pin)Power Ground pinGroundPGND115
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ316
Battery or External
power supply
Power supply for matrix driver, Internal reference circuitPower supplyVCC117
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ218
Open
Constant current circuit, PWM control output pin,
Control switch pin for matrix driver
OutputZ119
OpenReference clock input output / Music Input pinInput/OutputCLKIO20
—N.C ——21
(Required pin)Reset input pinInputNRST22
(Required pin)Ground pinGroundAGND23
(Required pin)Resistor connection pin for constant current setupOutputIREF24
Pin processing
at unused
DescriptionTypePin namePin No.
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 13 of 56
Product Standards
FUNCTIONAL BLOCK DIAGRAM
(2)
(1)
(3)
SCL
SDA
VDD
(4)
SLAVSEL
I2C
serial
interface
Frame and brightness
controller
Moving pattern
generator
Logic
PWM Step control
(24) IREF
Reference
Generator (23) AGND
(22) NRST
Clock Output
Music
Synchronize
Function
CLKIO
(20)
No Connection
(21)
Periodical Scanning Selectors
&
LED drivers
(13) LDO
Voltage
regulators
Z10 (5)
Z9 (6)
Z8 (8)
Z7 (10)
Z6 (11)
Z5 (12)
Z1(19)
Z2(18)
Z3(16)
Z4(14)
VCC2 (7)
PGND2 (9)
VCC1(17)
PGND1
(15)
Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.
Doc No.
TA4-EA-06028
Revision.
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Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 14 of 56
Product Standards
Power ON
Power OFF
1. Power Supply Sequence
Serial Input is possible
NRST
>1 ms
VCC
VDD
>3 ms
Note) For the Startup Timing of VCC and VDD, it is possible to be changed.
NRST
Serial Input is
possible
VDD
VCC
1 ms or more
Note) For the Shut down Timing of VCC and VDD, it is possible to be changed.
OPERATION
Doc No.
TA4-EA-06028
Revision.
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Established
:
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Revised
:
2013-03-22
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Page 15 of 56
Product Standards
2. Register Map
MLDI9
--------------R/W00hMLDEN111Bh
GRP9_1GRP9_2GRP9_8GRP9_9
--------R/W00hMLDMODE12Ah
THOLD[7:0]
R/W00hTHOLD2Bh
MLDI1MLDI2MLDI3MLDI4MLDI5MLDI6MLDI7MLDI8
R/W00hMLDEN101Ah
MLDH2MLDH3MLDH4MLDH5MLDH6MLDH7MLDH8MLDH9
R/W00hMLDEN919h
MLDG3MLDG4MLDG5MLDG6MLDG7MLDG8MLDG9MLDH1
R/W00hMLDEN818h
MLDF4MLDF5MLDF6MLDF7MLDF8MLDF9MLDG1MLDG2
R/W00hMLDEN717h
MLDE5MLDE6MLDE7MLDE8MLDE9MLDF1MLDF2MLDF3
R/W00hMLDEN616h
MLDD6MLDD7MLDD8MLDD9MLDE1MLDE2MLDE3MLDE4
R/W00hMLDEN515h
MLDC7MLDC8MLDC9MLDD1MLDD2MLDD3MLDD4MLDD5
R/W00hMLDEN414h
MLDB8MLDB9MLDC1MLDC2MLDC3MLDC4MLDC5MLDC6
R/W00hMLDEN313h
MLDA9MLDB1MLDB2MLDB3MLDB4MLDB5MLDB6MLDB7
R/W00hMLDEN212h
MLDA1MLDA2MLDA3MLDA4MLDA5MLDA6MLDA7MLDA8
R/W00hMLDEN111h
PWMI9
--------------R/W00hPWMEN1110h
PWMI1PWMI2PWMI3PWMI4PWMI5PWMI6PWMI7PWMI8
R/W00hPWMEN100Fh
PWMH2PWMH3PWMH4PWMH5PWMH6PWMH7PWMH8PWMH9
R/W00hPWMEN90Eh
PWMG3PWMG4PWMG5PWMG6PWMG7PWMG8PWMG9PWMH1
R/W00hPWMEN80Dh
PWMF4PWMF5PWMF6PWMF7PWMF8PWMF9PWMG1PWMG2
R/W00hPWMEN70Ch
PWME5PWME6PWME7PWME8PWME9PWMF1PWMF2PWMF3
R/W00hPWMEN60Bh
PWMD6PWMD7PWMD8PWMD9PWME1PWME2PWME3PWME4
R/W00hPWMEN50Ah
PWMC7PWMC8PWMC9PWMD1PWMD2PWMD3PWMD4PWMD5
R/W00hPWMEN409h
PWMB8PWMB9PWMC1PWMC2PWMC3PWMC4PWMC5PWMC6
R/W00hPWMEN308h
PWMA9PWMB1PWMB2PWMB3PWMB4PWMB5PWMB6PWMB7
R/W00hPWMEN207h
PWMA1PWMA2PWMA3PWMA4PWMA5PWMA6PWMA7PWMA8
R/W00hPWMEN106h
MTXONIMAX[2:0]
IMAX
Reserved
------
R/W1EhMTXON05h
EXTCLKCLKOUTMLDACTZPDEN
--------R/W00hOPTION04h
--------------------reserved03h
OSCEN
------------R/W00hPOWERCNT02h
SRSTRAMRST
------------W00hRST01h
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
Note) "Reserved" registers and data bits indicated by "--" cannot be accessed. "Reserved" registers are not used.
For data bits indicated by "--" in other registers except from "reversed" registers, will return "zero" value if these bits are read.
Writing to these bits will be ignored. IMAX Reserved will give default value [1].
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 16 of 56
Product Standards
DTB9[7:0]R/W00hDTB951h
DTB8[7:0]R/W00hDTB850h
DTB7[7:0]R/W00hDTB74Fh
DTB6[7:0]R/W00hDTB64Eh
DTB5[7:0]R/W00hDTB54Dh
DTB4[7:0]R/W00hDTB44Ch
DTB3[7:0]R/W00hDTB34Bh
DTB2[7:0]R/W00hDTB24Ah
DTB1[7:0]R/W00hDTB149h
DTA9[7:0]R/W00hDTA948h
DTA8[7:0]R/W00hDTA847h
DTA7[7:0]R/W00hDTA746h
DTA6[7:0]R/W00hDTA645h
DTA5[7:0]R/W00hDTA544h
DTA4[7:0]R/W00hDTA443h
DTA3[7:0]R/W00hDTA342h
DTA2[7:0]R/W00hDTA241h
DTA1[7:0]R/W00hDTA140h
SCANSET[3:0]--------R/W08hSCANSET36h
----
----------------reserved
35h
--------------------reserved
34h
MLDCOM[2:0]----------R/W03hMLDCOM33h
SLOPEEXTH[1:0]SLOPEEXTL[1:0]FADTIM------R/W00hSLPTIME32h
Y7MSKY8MSKY9MSK----------R/W00hMASKY9_731h
Y1MSKY2MSKY3MSKY4MSKY5MSKY6MSK----R/W00hMASKY6_130h
Y7Y8Y9----------R/W00h
CONSTY9_7
2Fh
Y1Y2Y3Y4Y5Y6----R/W00h
CONSTY6_1
2Eh
X7X8X9X10--------R/W00h
CONSTX10_7
2Dh
X1X2X3X4X5X6----R/W00h
CONSTX6_1
2Ch
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
Note) "Reserved" registers and data bits indicated by "--" cannot be accessed. "Reserved" registers are not used.
For data bits indicated by "--" in other registers except from "reversed" registers, will return "zero" value if these bits are read.
Writing to these bits will be ignored.
2. Register Map (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 17 of 56
Product Standards
DTF2[7:0]R/W00hDTF26Eh
DTF1[7:0]R/W00hDTF16Dh
DTE9[7:0]R/W00hDTE96Ch
DTE8[7:0]R/W00hDTE86Bh
DTE7[7:0]R/W00hDTE76Ah
DTE6[7:0]R/W00hDTE669h
DTE5[7:0]R/W00hDTE568h
DTE4[7:0]R/W00hDTE467h
DTE3[7:0]R/W00hDTE366h
DTE2[7:0]R/W00hDTE265h
DTE1[7:0]R/W00hDTE164h
DTD9[7:0]R/W00hDTD963h
DTD8[7:0]R/W00hDTD862h
DTD7[7:0]R/W00hDTD761h
DTD6[7:0]R/W00hDTD660h
DTD5[7:0]R/W00hDTD55Fh
DTD4[7:0]R/W00hDTD45Eh
DTD3[7:0]R/W00hDTD35Dh
DTD2[7:0]R/W00hDTD25Ch
DTD1[7:0]R/W00hDTD15Bh
DTC9[7:0]
R/W00hDTC95Ah
DTC8[7:0]R/W00hDTC859h
DTC7[7:0]R/W00hDTC758h
DTC6[7:0]R/W00hDTC657h
DTC5[7:0]R/W00hDTC556h
DTC4[7:0]R/W00hDTC455h
DTC3[7:0]R/W00hDTC354h
DTC2[7:0]R/W00hDTC253h
DTC1[7:0]R/W00hDTC152h
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
2. Register Map (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 18 of 56
Product Standards
DTI4[7:0]R/W00hDTI48Bh
DTI3[7:0]R/W00hDTI38Ah
DTI2[7:0]R/W00hDTI289h
DTI1[7:0]R/W00hDTI188h
DTH9[7:0]R/W00hDTH987h
DTH8[7:0]R/W00hDTH886h
DTH7[7:0]R/W00hDTH785h
DTH6[7:0]R/W00hDTH684h
DTH5[7:0]R/W00hDTH583h
DTH4[7:0]R/W00hDTH482h
DTH3[7:0]R/W00hDTH381h
DTH2[7:0]R/W00hDTH280h
DTH1[7:0]R/W00hDTH17Fh
DTG9[7:0]R/W00hDTG97Eh
DTG8[7:0]R/W00hDTG87Dh
DTG7[7:0]R/W00hDTG77Ch
DTG6[7:0]R/W00hDTG67Bh
DTG5[7:0]R/W00hDTG57Ah
DTG4[7:0]R/W00hDTG479h
DTG3[7:0]R/W00hDTG378h
DTG2[7:0]
R/W00hDTG277h
DTG1[7:0]R/W00hDTG176h
DTF9[7:0]R/W00hDTF975h
DTF8[7:0]R/W00hDTF874h
DTF7[7:0]R/W00hDTF773h
DTF6[7:0]R/W00hDTF672h
DTF5[7:0]R/W00hDTF571h
DTF4[7:0]R/W00hDTF470h
DTF3[7:0]R/W00hDTF36Fh
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
2. Register Map (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
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:
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Revised
:
2013-03-22
AN32183A
Page 19 of 56
Product Standards
SDTC6[2:0]--BRTC6[3:0]R/W00hC6A8h
SDTC5[2:0]--BRTC5[3:0]R/W00hC5A7h
SDTC4[2:0]--BRTC4[3:0]R/W00hC4A6h
SDTC3[2:0]--BRTC3[3:0]R/W00hC3A5h
SDTC2[2:0]--BRTC2[3:0]R/W00hC2A4h
SDTC1[2:0]--BRTC1[3:0]R/W00hC1A3h
SDTB9[2:0]--BRTB9[3:0]R/W00hB9A2h
SDTB8[2:0]--BRTB8[3:0]R/W00hB8A1h
SDTB7[2:0]--BRTB7[3:0]R/W00hB7A0h
SDTB6[2:0]--BRTB6[3:0]R/W00hB69Fh
SDTB5[2:0]--BRTB5[3:0]R/W00hB59Eh
SDTB4[2:0]--BRTB4[3:0]R/W00hB49Dh
SDTB3[2:0]--BRTB3[3:0]R/W00hB39Ch
SDTB2[2:0]--BRTB2[3:0]R/W00hB29Bh
SDTB1[2:0]--BRTB1[3:0]
R/W00hB19Ah
SDTA9[2:0]--BRTA9[3:0]R/W00hA999h
SDTA8[2:0]--BRTA8[3:0]R/W00hA898h
SDTA7[2:0]--BRTA7[3:0]R/W00hA797h
SDTA6[2:0]--BRTA6[3:0]R/W00hA696h
SDTA5[2:0]--BRTA5[3:0]R/W00hA595h
SDTA4[2:0]--BRTA4[3:0]R/W00hA494h
SDTA3[2:0]--BRTA3[3:0]R/W00hA393h
SDTA2[2:0]--BRTA2[3:0]R/W00hA292h
SDTA1[2:0]--BRTA1[3:0]R/W00hA191h
DTI9[7:0]R/W00hDTI990h
DTI8[7:0]R/W00hDTI88Fh
DTI7[7:0]R/W00hDTI78Eh
DTI6[7:0]R/W00hDTI68Dh
DTI5[7:0]R/W00hDTI58Ch
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
Note) Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.
Writing to these bits will be ignored.
2. Register Map (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 20 of 56
Product Standards
SDTF8[2:0]--BRTF8[3:0]R/W00hF8C5h
SDTF7[2:0]--BRTF7[3:0]R/W00hF7C4h
SDTF6[2:0]--BRTF6[3:0]R/W00hF6C3h
SDTF5[2:0]--BRTF5[3:0]R/W00hF5C2h
SDTF4[2:0]--BRTF4[3:0]R/W00hF4C1h
SDTF3[2:0]--BRTF3[3:0]R/W00hF3C0h
SDTF2[2:0]--BRTF2[3:0]R/W00hF2BFh
SDTF1[2:0]--BRTF1[3:0]R/W00hF1BEh
SDTE9[2:0]--BRTE9[3:0]R/W00hE9BDh
SDTE8[2:0]--BRTE8[3:0]R/W00hE8BCh
SDTE7[2:0]--BRTE7[3:0]R/W00hE7BBh
SDTE6[2:0]--BRTE6[3:0]R/W00hE6BAh
SDTE5[2:0]--BRTE5[3:0]R/W00hE5B9h
SDTE4[2:0]--BRTE4[3:0]R/W00hE4B8h
SDTE3[2:0]--BRTE3[3:0]
R/W00hE3B7h
SDTE2[2:0]--BRTE2[3:0]R/W00hE2B6h
SDTE1[2:0]--BRTE1[3:0]R/W00hE1B5h
SDTD9[2:0]--BRTD9[3:0]R/W00hD9B4h
SDTD8[2:0]--BRTD8[3:0]R/W00hD8B3h
SDTD7[2:0]--BRTD7[3:0]R/W00hD7B2h
SDTD6[2:0]--BRTD6[3:0]R/W00hD6B1h
SDTD5[2:0]--BRTD5[3:0]R/W00hD5B0h
SDTD4[2:0]--BRTD4[3:0]R/W00hD4AFh
SDTD3[2:0]--BRTD3[3:0]R/W00hD3AEh
SDTD2[2:0]--BRTD2[3:0]R/W00hD2ADh
SDTD1[2:0]--BRTD1[3:0]R/W00hD1ACh
SDTC9[2:0]--BRTC9[3:0]R/W00hC9ABh
SDTC8[2:0]--BRTC8[3:0]R/W00hC8AAh
SDTC7[2:0]--BRTC7[3:0]R/W00hC7
A9h
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
2. Register Map (continued)
OPERATION ( continued )
Note) Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.
Writing to these bits will be ignored.
Doc No.
TA4-EA-06028
Revision.
3
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:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 21 of 56
Product Standards
SDTI9[2:0]--BRTI9[3:0]R/W00hI9E1h
SDTI8[2:0]--BRTI8[3:0]R/W00hI8E0h
SDTI7[2:0]--BRTI7[3:0]R/W00hI7DFh
SDTI6[2:0]--BRTI6[3:0]R/W00hI6DEh
SDTI5[2:0]--BRTI5[3:0]R/W00hI5DDh
SDTI4[2:0]--BRTI4[3:0]R/W00hI4DCh
SDTI3[2:0]--BRTI3[3:0]R/W00hI3DBh
SDTI2[2:0]--BRTI2[3:0]R/W00hI2DAh
SDTI1[2:0]--BRTI1[3:0]R/W00hI1D9h
SDTH9[2:0]--BRTH9[3:0]R/W00hH9D8h
SDTH8[2:0]--BRTH8[3:0]R/W00hH8D7h
SDTH7[2:0]--BRTH7[3:0]R/W00hH7D6h
SDTH6[2:0]--BRTH6[3:0]R/W00hH6D5h
SDTH5[2:0]--BRTH5[3:0]R/W00hH5D4h
SDTH4[2:0]--BRTH4[3:0]
R/W00hH4D3h
SDTH3[2:0]--BRTH3[3:0]R/W00hH3D2h
SDTH2[2:0]--BRTH2[3:0]R/W00hH2D1h
SDTH1[2:0]--BRTH1[3:0]R/W00hH1D0h
SDTG9[2:0]--BRTG9[3:0]R/W00hG9CFh
SDTG8[2:0]--BRTG8[3:0]R/W00hG8CEh
SDTG7[2:0]--BRTG7[3:0]R/W00hG7CDh
SDTG6[2:0]--BRTG6[3:0]R/W00hG6CCh
SDTG5[2:0]--BRTG5[3:0]R/W00hG5CBh
SDTG4[2:0]--BRTG4[3:0]R/W00hG4CAh
SDTG3[2:0]--BRTG3[3:0]R/W00hG3C9h
SDTG2[2:0]--BRTG2[3:0]R/W00hG2C8h
SDTG1[2:0]--BRTG1[3:0]R/W00hG1C7h
SDTF9[2:0]--BRTF9[3:0]R/W00hF9C6h
D0D1D2D3D4D5D6D7
DATA
R/WDefault
Register
Name
ADDR
2. Register Map (continued)
OPERATION ( continued )
Note) Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.
Writing to these bits will be ignored.
Doc No.
TA4-EA-06028
Revision.
3
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:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 22 of 56
Product Standards
Default
01h
Address
SRSTRAMRST------------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
RSTRegister Name
Default
02h
Address
OSCEN--------------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
POWERCNTRegister Name
D1 : RAMRST RAM reset
[0] : RAM can be overwrite (default)
[1] : Clear all PWM duty setting and intensity setting
D0 : SRST Soft reset control
[0] : Reset release state (default)
[1] : Reset reset
D0 : OSCEN Internal oscillator ON/OFF bit
[0] : Internal oscillator OFF (default)
[1] : Internal oscillator ON
This register will auto-return to zero when written with "High" logic value.
Oscillator will auto turn ON if any of the LED drivers are enabled (MTXON = 1) even if this bit is Low.
3. Register map Detailed Explanation
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
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Revised
:
2013-03-22
AN32183A
Page 23 of 56
Product Standards
--
Default
04h
Address
EXTCLKCLKOUTMLDACTZPDEN------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
OPTIONRegister Name
IMAX[2:0]
IMAX
Reserved
--
Default
05h
Address
MTXON----R/W
011110001Eh
D0D1D2D3D4D5D6D7R/W
MTXONRegister Name
D3 : ZPDEN Ghost Image Prevention Enable
[0] : Turn off ghost image prevention (default)
[1] : Turn on ghost image prevention
D2 : MLDACT External Melody Input Selection
[0] : Turn off melody mode (default)
[1] : Turn on melody mode
D1 : CLKOUT Internal clock output enable
[0] : Internal clock is not output from CLKOUT (default)
[1] : Internal clock is output from CLKOUT
D0 : EXTCLK Internal/external synchronous clock selection
[0] : Internal clock operation (default)
[1] : External clock operation
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Ghost Image Prevention may not remove the ghost image perfectly. It depends on the LED color combination
and LED connection method. Please refer to Page.46 for details.
Please refer to Page.47 for details especially when this LSI is used for RGB driver.
• For D2, D1 and D0 cannot be set to High at the same time. In such case, the priority of operation will be
EXTCLK then CLKOUT and then Melody Mode will have the least priority.
D3-1 : IMAX Maximum current setup selection
[000] : 7.5 mA [100] : 37.5 mA
[001] : 15 mA [101] : 45 mA
[010] : 22.5 mA [110] : 52.5 mA
[011] : 30 mA [111] : 60 mA (default)
D0 : MTXON LED Matrix Set up ON/OFF control
[0] : OFF (default)
[1] : ON
Doc No.
TA4-EA-06028
Revision.
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:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 24 of 56
Product Standards
Default
06h
Address
PWMA1PWMA2PWMA3PWMA4PWMA5PWMA6PWMA7PWMA8R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
PWMEN1Register Name
D7 : PWMA8 A8 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D6 : PWMA7 A7 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D5 : PWMA6 A6 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D4 : PWMA5 A5 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D3 : PWMA4 A4 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D2 : PWMA3 A3 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D1 : PWMA2 A2 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
D0 : PWMA1 A1 PWM mode enable
[0] : Not PWM mode (default)
[1] : PWM mode
The definition for register addresses #07h to #10h is the same as address #06h.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 25 of 56
Product Standards
Default
11h
Address
MLDA1MLDA2MLDA3MLDA4MLDA5MLDA6MLDA7MLDA8R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
MLDEN1Register Name
D7 : MLDA8 A8 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D6 : MLDA7 A7 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D5 : MLDA6 A6 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D4 : MLDA5 A5 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D3 : MLDA4 A4 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D2 : MLDA3 A3 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
D1 : MLDA2 A2 Melody mode enable
[0] : Not PWM mode (default)
[1] : Melody mode
D0 : MLDA1 A1 Melody mode enable
[0] : Not Melody mode (default)
[1] : Melody mode
The definition for register addresses #12h to #1Bh is the same as address #11h.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
Doc No.
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Revision.
3
Established
:
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Revised
:
2013-03-22
AN32183A
Page 26 of 56
Product Standards
D3 : GRP9_9 Column 9 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I9 H9 G9 F9 E9 D9 C9 B9 A9)
D2 : GRP9_8 Column 8 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I8 H8 G8 F8 E8 D8 C8 B8 A8)
D1 : GRP9_2 Column 2 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I2 H2 G2 F2 E2 D2 C2 B2 A2)
D0 : GRP9_1 Column 1 blink with external input as a group
[0] : Normal (default)
[1] : Melody mode (I1 H1 G1 F1 E1 D1 C1 B1 A1)
Default
2Ah
Address
GRP9_1GRP9_2GRP9_8GRP9_9--------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
MLDMODE1Register Name
Threshold 4
Threshold 5
Threshold 6
Threshold 7
Threshold 8
Threshold 8
GRP9_1
GRP9_2
GRP9_8
GRP9_9
Threshold 1
Threshold 2
Threshold 3
A
B
C
D
E
F
G
H
I
12 3 4 56 7 89
During Bar Meter Mode, auto threshold detection should be used. This LSI does not support Bar Meter
Mode with fixed threshold setting.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 27 of 56
Product Standards
Default
2Bh
Address
THOLD[7:0]R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
THOLDRegister Name
D7 : THOLD[7] Threshold 8 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 8 is used. (Threshold 8 is about 1.93 V)
D6 : THOLD[6] Threshold 7 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 7 is used. (Threshold 7 is about 1.80 V)
D5 : THOLD[5] Threshold 6 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 6 is used. (Threshold 6 is about 1.67 V)
D4 : THOLD[4] Threshold 5 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 5 is used. (Threshold 5 is about 1.55 V)
D3 : THOLD[3] Threshold 4 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 4 is used. (Threshold 4 is about 1.42 V)
D2 : THOLD[2] Threshold 3 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 3 is used. (Threshold 3 is about 1.30 V)
D1 : THOLD[1] Threshold 2 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 2 is used. (Threshold 2 is about 1.17 V)
D0 : THOLD[0] Threshold 1 is used as voltage detection.
[0] : Others (default)
[1] : Threshold 1 is used. (Threshold 1 is about 1.04 V)
When all bits are set zero, threshold is in auto-detection mode (default)
Do not set more than 1 register bit to logic "High" value at the same time.
If 2 bits are set to "High" at the same time, system will only recognize the first "High" bit threshold that is set.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
Doc No.
TA4-EA-06028
Revision.
3
Established
:
2011-10-07
Revised
:
2013-03-22
AN32183A
Page 28 of 56
Product Standards
D5 : X6 X6 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X6 is fixed as constant current mode. The LED A6’s current setting is used.
D4 : X5 X5 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X5 is fixed as constant current mode. The LED A5’s current setting is used.
D3 : X4 X4 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X4 is fixed as constant current mode. The LED A4’s current setting is used.
D2 : X3 X3 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X3 is fixed as constant current mode. The LED A3’s current setting is used.
D1 : X2 X2 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X2 is fixed as constant current mode. The LED A2’s current setting is used.
D0 : X1 X1 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X1 is fixed as constant current mode. The LED A1’s current setting is used.
Default
2Ch
Address
X1X2X3X4X5X6----R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
CONSTX6_1Register Name
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Please refer to Page.39 for details.
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Product Standards
D3 : X10 X10 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X10 is fixed as constant current mode. The LED I1’s current setting is used.
D2 : X9 X9 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X9 is fixed as constant current mode. The LED A9’s current setting is used.
D1 : X8 X8 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X8 is fixed as constant current mode. The LED A8’s current setting is used.
D0 : X7 X7 is fixed as constant current mode.
[0] : Normal matrix operation (default)
[1] : X7 is fixed as constant current mode. The LED A7’s current setting is used.
Default
2Dh
Address
X7X8X9X10--------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
CONSTX10_7Register Name
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Please refer to Page.39 for details.
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Product Standards
D5 : Y6 Z6 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z6 turns on (VCC level).
D4 : Y5 Z5 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z5 turns on (VCC level).
D3 : Y4 Z4 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z4 turns on (VCC level).
D2 : Y3 Z3 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z3 turns on (VCC level).
D1 : Y2 Z2 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z2 turns on (VCC level).
D0 : Y1 Z1 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z1 turns on (VCC level).
Default
2Eh
Address
Y1Y2Y3Y4Y5Y6----R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
CONSTY6_1Register Name
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Please refer to Page.39 for details.
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Product Standards
D2 : Y9 Z9 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z9 turns on (VCC level).
D1 : Y8 Z8 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z8 turns on (VCC level).
D0 : Y7 Z7 output is fixed to High (VCC level).
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z7 turns on (VCC level).
Default
2Fh
Address
Y7Y8Y9----------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
CONSTY9_7Register Name
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Please refer to Page.39 for details.
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Product Standards
Default
30h
Address
Y1MSKY2MSKY3MSKY4MSKY5MSKY6MSK----R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
MASKY6_1Register Name
D5 : Y6MSK Z6 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z6 turns off.
D4 : Y5MSK Z5 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z5 turns off.
D3 : Y4MSK Z4 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z4 turns off.
D2 : Y3MSK Z3 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z3 turns off.
D1 : Y2MSK Z2 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z2 turns off.
D0 : Y1MSK Z1 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z1 turns off.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Please refer to Page.39 for details.
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Product Standards
Default
31h
Address
Y7MSKY8MSKY9MSK----------R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
MASKY9_7Register Name
D2 : Y9MSK Z9 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z9 turns off.
D1 : Y8MSK Z8 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z8 turns off.
D0 : Y7MSK Z7 output is fixed to OFF.
[0] : Normal matrix operation (default)
[1] : Switch between VCC and Z7 turns off.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
• Please refer to Page.39 for details.
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Product Standards
--
Default
32h
Address
SLOPEEXTH[1:0]SLOPEEXTL[1:0]FADTIM----R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
SLPTIMERegister Name
D4 : FADTIM Fade out time control.
[0] : T3 = T1 (default)
[1] : T3 = T1 2
D3-2 : SLOPEEXTL T4 time extent control.
[00] : T4 = T1 (default)
[01] : T4 = T1 0.25
[10] : T4 = T1 0.5
[11] : T4 = T1 2
D1-0 : SLOPEEXTH T2 time extent control.
[00] : T2 = T1 (default)
[01] : T2 = T1 0.25
[10] : T2 = T1 0.5
[11] : T2 = T1 2
T1 T3T2 T4
This bit also affect in PWM fade out mode. Fade out time becomes 2 times of fade in time when FADTIM = 1.
T1 time is controlled by the register #91h to #E1h.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
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Product Standards
Default
33h
Address
MLDCOM[2:0]----------R/W
1100000003h
D0D1D2D3D4D5D6D7R/W
MLDCOMRegister Name
D2-0 : MLDCOM LED Turn on time compensation in melody mode
[000] : 0s
[001] : 1.94 µs
[010] : 3.87 µs
[011] : 5.80 µs (default)
[100] : 7.74 µs
[101] : 9.67 µs
[110] : 11.6 µs
[111] : 13.5 µs
Default
36h
Address
SCANSET[3:0]--------R/W
0001000008h
D0D1D2D3D4D5D6D7R/W
SCANSETRegister Name
D3-0 : SCANSET SCAN number control
[0000] : Only scan the first column.
[0001] : Only scan the first 2 column.
[0010] : Only scan the first 3 column.
[0011] : Only scan the first 4 column.
[0100] : Only scan the first 5 column.
[0101] : Only scan the first 6 column.
[0110] : Only scan the first 7 column.
[0111] : Only scan the first 8 column.
[1000] : Scan all column. (default)
All other values will scan all column.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
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Product Standards
D7-0 : DTA1 A1 PWM duty control.
[0000_0000] : 0%. (default)
[0000_0001] : 0.39%. (1/256)
[0000_0010] : 0.78%. (2/256)
[0000_0011] : 1.17%. (3/256)
…
[1111_1100] : 98.8%. (253/256)
[1111_1110] : 99.2%. (254/256)
[1111_1111] : 99.6%. (255/256)
Default
40h
Address
DTA1[7:0]R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
DTA1Register Name
This duty setting is only effective when PWMA1 is High.
The definition for register addresses #41h to #90h is the same as address #40h.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
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Product Standards
SDTA1[2:0]
Default
91h
Address
--BRTA1[3:0]R/W
0000000000h
D0D1D2D3D4D5D6D7R/W
A1Register Name
D7-4 : BRTA1 Luminance set up of LED A1 (in case of IMAX [2:0] == [011])
[0000] : 0 mA (default)
[0001] : 2 mA
[0010] : 4 mA
[0011] : 6 mA
[0100] : 8 mA
[0101] : 10 mA
…
[1010] : 20 mA
[1011] : 22 mA
[1100] : 24 mA
[1101] : 26 mA
[1110] : 28 mA
[1111] : 30 mA
D2-0 : SDTA1 (SCANSET == [11], default setting)
(1) Firefly Operation (PWMA1 == 0)
[000] : Constant current mode (default)
[001] : 0.248 s
[010] : 0.495 s
[011] : 0.99 s
[100] : 1.484 s
[101] : 1.979 s
[110] : 2.473 s
[111] : 2.968 s
(2) PWM Fade-in/out Operation (PWMA1 == 1)
[000] : Instant change mode (default)
[001] : 1.939 ms
[010] : 3.879 ms
[011] : 7.758 ms
[100] : 11.636 ms
[101] : 15.515 ms
[110] : 19.394 ms
[111] : 23.273 ms
T1 T3T2 T4
In case of PWM duty change from 0 to 255, the longest time is 255 23.273 ms = 5.957 s.
T1 time is also controlled by SCANSET in register #36h. The calculation method is as follow:
SCANSET == 0000 : T1 = 0.111 T_default
SCANSET == 0001 : T1 = 0.222 T_default
…
SCANSET == 0111 : T1 = 0.888 T_default
The definition for register addresses #92h to #E1h is the same as address #91h.
3. Register map Detailed Explanation (continued)
OPERATION ( continued )
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Product Standards
Blinking mode!=000001
PWM modex10001
0
0
1
x
x
Y*MSK
0
1
x
x
x
Y*
Constant current mode0001
Turn on with all A1, A2, A3, A4xx01
OFFxx01
X*CNT constant modexx11
OFFxxx0
Operation ModeSDT*PWM*X*MTXON
4. Operation Mode priority
OPERATION ( continued )
• * for X*, PWM*, SDT* == 1 ~ 10, * for Y*MSK, Y* == 1 ~ 9.
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Product Standards
START condition
SDA
SCL
STOP condition
START or
repetitive START
condition
STOP or
repetitive START
condition
SCL
SDA
MSB
ACK ACK
12 789 123 –89
Sr
or
P
Sr
P
S
or
Sr
ACK signal from slave ACK signal from receiver
Completion of Byte Transfer &
Slave interruption.
5.1 Basic Rules
5.2 START and STOP conditions
When SDA signal changes from "High" to "Low" while SCL is "High" will trigger START condition. Whereas,
STOP condition will be triggered when SDA signal changes from "Low" to "High" while SCL is "High".
START condition and STOP condition are always formed by the master. After the START condition occurs, the
bus becomes busy state. After STOP condition occurs, the bus becomes free again.
5.3 Data Transfer
Length of each byte output to SDA line is always 8 bits. There is no limitation in the number of bytes that can
be transmitted at 1 time. Many bytes can be sent. The acknowledge bit is necessary for each byte. Data is
sequentially transmitted from most significant bit (MSB).
This LSI, I2C-bus, is designed to correspond to the Standard-mode (100 kbps), Fast-mode(400 kbps) and
Fast-mode plus (1 000 kbps) devices in the version 03 of NXP's specification. However, it does not correspond to
the HS-mode (to 3.4 Mbps).
This LSI will operate as a slave device in the I2C-bus system. This LSI will not operate as a master device.
The program operation check of this LSI has not been conducted on the multi-master bus system and the mix-
speed bus system, yet. The connected confirmation of this LSI to the CBUS receiver also has not been checked.
Please confirm with our company if it will be used in these mode systems.
The I2C is the brand of NXP.
5. I2C Bus Interface
OPERATION ( continued )
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Product Standards
S Slave address Sub address
Stop condition
ACK : 0
Start condition Write mode : 0
Sub address
X data
Sub address
X+1 data
W A A Data byte A P
7-bit 8-bit 8-bit
ACK : 0 ACK : 0
S Slave address Sub address
ACK : 0
Start condition Write mode : 0
W A A Data byte A
7-bit 8-bit 8-bit
ACK : 0 ACK : 0
Data byte
8-bit
Sub address
X+m-1 data
Sub address
X+m data
Data byte A
8-bit
ACK : 0
Data byte
8-bit
ACK : 0
AP
A
ACK : 0
: Data transmission from Master
: Data transmission from Slave
Data byte can be written in Sub address by transmitting data byte continuously.
Sub address is incremented automatically.
Sub address is not incremented automatically.
The next data byte is written in the same Sub address by transmitting data byte continuously.
5.4 I2C Interface - Data Format
In this LSI, 4 different Slave address can be changed by selecting SLAVSEL ( "Low" or "High" or "SCL" or
"SDI"). The slave addresses of this LSI are as follow:
1011 110XSCL
1011 101XHigh
SDI
Low
SLAVSEL
1011 100X
1011 111X
Slave address
Write mode
Write mode (Auto increment mode)
5. I2C Bus Interface (continued)
OPERATION ( continued )
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Product Standards
S Slave address Data byte
Stop condition
ACK : 0
Start condition Read mode : 1
RA A P
7-bit 8-bit
NACK : 1
S Slave address Sub address
ACK : 0
Start condition Write mode : 0
W A Sr Slave address A
7-bit 8-bit 7-bit
ACK : 0
Data byte
8-bit
A
NACK : 1
A PR
Stop conditionRepeated start condition Read mode : 1
ACK : 0
Sub address
X+m–1 data
Sub address
X+m data
Data byte A
8-bit
ACK : 0
Data byte
8-bit
NACK : 1
AP
S Slave address Sub address
ACK : 0
Start condition
W A Sr Slave address A
7-bit 8-bit 7-bit
ACK : 0
Data byte
8-bit
A
ACK : 0
A R
Repeated start condition Read mode : 1
ACK : 0
Sub address
X data
Stop condition
Write mode : 0
: Data transmission from Master
: Data transmission from Slave
Sub address is not incremented automatically.
The next data byte reads the same Sub address by transmitting data byte continuously.
When Sub address 8 bit is not specified and data is read, this LSI allows to read the value of adjacent Sub
address specified in the last Write mode.
The next data byte reads the same Sub address by transmitting data byte continuously.
It is possible to read data byte in continuous Sub address by transmitting data byte continuously.
Sub address is incremented automatically.
5.4 I2C Interface - Data Format (continued)
Read mode (in case Sub address is not specified)
Read mode (in case Sub address is specified)
Read mode (Auto increment mode)
5. I2C Bus Interface (continued)
OPERATION ( continued )
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Product Standards
Oscillator 2.4 MHz
(PAD) CLKIO
(Register) EXTCLK
Logic block
(Matrix)
*Matrix operation, PWM control
1
0
6.2 Distribution diagram of control / clock system
VCC2
VLDO
VDD
PGND1
PGND2
LOGIC SCAN
SW I2C
BGR LED
Driver
Music
Sync
(Register) CLKOUT
TSD
VCC1
AGND
6.1 Distribution diagram of power supply
6. Signal distribution diagram
OPERATION ( continued )
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Product Standards
Connected
pin name
Z4
Z3
Z5
Z1
Z2
Z9
Z8
Z10
Z6
Z7
4321
D
C
B
A
87659
H
G
F
E
I
LED matrix driver circuit individually drives LED of 9 9 matrix. In total, the LSI can drive and light up 81 LED.
In this specification, LED's number controlled by each pin corresponds as follows.
The internal logic circuit is operated by using an internal clock or the external clock input to the terminal
CLKIO.
7. Block Configuration of Matrix LED
7.1 Matrix LED descriptions, Matrix LED’s numbers
OPERATION ( continued )
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Product Standards
Actual driver configuration is shown in the following figure.
The anodes and cathode of each LED are connected to different Z pin as shown in figure below.
Z10 pin consists of only Current Sink and Slope control timing driver. Thus, LED anode are not to be
connected to Z10 pin.
Please do not remove any of the LED inside the matrix if it is not used. If LED are to be removed, it is advised
to remove the entire row (e.g: all LED in row A) instead of removing only 1 LED. If only one LED in the row is
removed instead of the whole row, user needs to avoid using LED whose reverse breakdown voltage is lower
than the operating VCC level.
Internal control logic according to user register settings is used to control Y1 to Y9CNT(PMOS ON/Off Scan
Switches) as well as X1 to X10CNT (Current sink value as well as PWM/Slope timing for lighting effects)
VCC / External DCDC
PWM
PWM
PWM
Y3CNT
Y4CNT
Y2CNT
Y1CNT
PWM
PWM
X2CNT
X4CNT
X3CNT
X5CNT
Matrix SCAN Switches
Current Sink with
Slope control timing
Z5
Z4
Z3
Z2
Z1
Control
Logic
Y5CNT
X1CNT
1234
A
B
C
D
7. Block Configuration of Matrix LED (continued)
7.2 Driver Configuration
OPERATION ( continued )
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Product Standards
Scan period : 2,331 clks (approx 1.031 kHz @ 2.4 MHz Clock)
255 clks
Y1CNT
Y2CNT
Y3CNT
Y4CNT
Y5CNT
Y6CNT
Y7CNT
Y8CNT
Y9CNT
X1~
X10CNT
4 clks
Y4CNT
Y5CNT
X*CNT
Min Duty : 1clk (0.416 µs)Max Duty : 255clks (106.08 µs)
The figure below shows a timing chart when in operation.
Timing can be controlled according to the external clock frequency input to CLKIO pin.
In default condition, it is controlled by internal 2.4 MHz clock.
Y1 to Y9CNT are scan timing which is turned on one at a time. The ON period of each pin is constant 255 clks
(106.08 µs) and includes the interval of 4 clks (1.664 µs).
81 LED (9 9 matrix) are controlled by X1 to X10CNT according to below figure.
When Yx = Xx = Low, the actual waveform of Zx is set to Hi-Z.
Duty can be set using register DT*[7:0] from registers #40h to #90h. Additional brightness control is provided
through register BRT*[3:0] (registers #91h to #E1h).
7. Block Configuration of Matrix LED (continued)
7.3 Timing Chart when in operation
OPERATION ( continued )
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Product Standards
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Constant current mode1
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Group LED can synchronize with Music Input from CLKIO pin
Bar Meter Mode has more priority than Melody mode.
Bar Meter Mode5
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Each LED can synchronize with Music Input from CLKIO pin
Melody mode4
3
2
No.
Fixed Current at 100% Duty IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Adjustable detention Time for each step : (0.248 s to 2.968 s / step)
Firefly mode
IMAX Setting : 7.5 mA to 60 mA (max)
DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step
Adjustable detention Time for each step : (1.939 ms to 23.273 ms / step)
PWM mode and Fade-in/out
mode
Setting RangeFeatures
Maximum current setting value can be set up as 60mA using register IMAX[2:0] (register 05h). Brightness can
be set through the register BRT*[3:0] (register #91h to #E1h) for individual LED.
Example)
E.g. If user sets register IMAX[2:0](#05h) = 011 and BRT*[3:0](#91h to #E1h) = 1111, the current will be 30 mA.
E.g. If user sets register IMAX[2:0](#05h) = 111 and BRT*[3:0](#91h to #E1h) = 1111, the current will be 60 mA.
E.g. If user sets register IMAX[2:0](#05h) = 111 and BRT*[3:0](#91h to #E1h) = 0111, the current will be 28 mA.
8.1 Constant Current Mode
60 mA (max)
t
Current value
Functions Table for LED Driver
8. LED Driver Block Function
OPERATION ( continued )
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Product Standards
This operation is characterized by PWM signal having variable duty depending on register DT*[7:0]
(registers #40h to #90h). However, any changes in duty is not instantaneous, but rather it will step to the new
duty at time determined by register SDT*[2:0].
Example)
Case 1 : LED*DT(new) > LED*DT(old) (PWM Mode without Fade in/out control)
Case 2 : LED*DT(new) > LED*DT(old) (PWM Mode with Fade in control)
In Case 1, PWM duty has been changed from low to high duty. But the register SDT*[2:0] setting is [000]
indicating that there is no Fade in/out control. Therefore, PWM duty changes instantaneously. Users can see
that LED becomes brighter instantaneously once PWM duty has been changed.
In Case 2, PWM duty has also been changed from low to high duty. Unlike in case 1, the register SDT*[2:0]
setting is not [000] in case 2. Therefore, PWM duty has changed according to the register SDT*[2:0] setting.
This is called PWM mode with Fade in control. Users can see that LED becomes brighter slowly according to
the timing set in register SDT*[2:0].
t
SDT*[2:0] = [000]
LED*DT(new)
LED*DT(old)
Duty
t
SDT*[2:0] (not [000])
LED*DT(new)
LED*DT(old)
Duty
8. LED Driver Block Function (continued)
8.2 PWM Mode and Fade-in/out Mode
OPERATION ( continued )
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DT*[7:0] is set through register #40h to #90h. FADTIM is set through register #32h. SDT*[2:0] is set through
register #91h to #E1h.
Example) (continued)
Case 3 : LED*DT(new) < LED*DT(old), FADTIM = 0 (PWM Mode with Fade out control)
t
SDT*[2:0] (not [000])
LED*DT(old)
LED*DT(new)
Duty
In Case 3, PWM duty has been changed from high to low duty. Unlike in case 1, the register SDT*[2:0] setting
is not [000] in case 3. Therefore, PWM duty has changed according to the register SDT*[2:0] setting. This is
called PWM mode with Fade out control. Users can see that LED becomes dimmer slowly according to the
timing set in register SDT*[2:0].
Case 4 : LED*DT(new) < LED*DT(old), FADTIM = 1 (PWM Mode with Fade out control)
t
SDT*[2:0] 2 (not [000])
LED*DT(old)
LED*DT(new)
Duty
In Case 4, PWM duty has also been changed from high to low duty. Unlike in case 3, the register FADTIM is
not [0]. Again, the register SDT*[2:0] setting is also not [000] in case 4. PWM duty has changed according to
the register SDT*[2:0] setting. Users can see that LED becomes dimmer slowly. It is slower than Case3 as
FADTIM register is high (2 times slower than Case 3 Fade out control).
8. LED Driver Block Function (continued)
8.2 PWM Mode and Fade-in/out Mode (continued)
OPERATION ( continued )
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This operation is characterized by PWM signal cycling from minimum to maximum duty and vice versa with
auto repeat function at time step determined by register SDT*[2:0]. Unlike PWM Fade in/out mode, firefly is
auto repetition of the sequence and thus creating LED blinking function effect.
t
256/256
Duty
0/256
STATE = 0 STATE = 1 STATE = 2 STATE = 3
SDT
256 steps
SDTH
64 steps
128 steps
256 steps
512 steps
FADTIM
256 steps
SDTL
64 steps
128 steps
256 steps
512 steps
Example)
Example 1 : SDTH = 00 (SDT 1), SDTL = 00 (SDT 1), FADTIM = 0
Example 2 : SDTH = 00 (SDT 1), SDTL = 00 (SDT 1), FADTIM = 1 (SDT 2)
Example 3 : SDTH = 01 (SDT 0.25), SDTL = 11 (SDT 2), FADTIM = 0
The SDTH is controlled by SLOPEEXTH[1:0] register, SDTL is controlled by SLOPEEXTL[1:0] register. All
these register, SLOPEEXTH[1:0], SLOPEEXTL[1:0] and FADTIM can be set through register #32h.
SDT*[2:0] registers are set individually through register #91h to #E1h. All other combinations of SDTH, SDTL
and FADTIM is possible.
t
Duty
t
Duty
t
Duty
8. LED Driver Block Function (continued)
8.3 Firefly Control
OPERATION ( continued )
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8. LED Driver Block Function (continued)
8.4 Melody Mode Explanation
OPERATION ( continued )
Case 1 : CLKIO as output pin
CLKIO output internal frequency by using
CLKOUT register
Case 2 : CLKIO as input for external clock
CLKIO uses as external input by using
EXTCLK register
Case 3 : CLKIO as input for music signal during melody mode
CLKIO uses as music input when melody mode
is enabled by register MLDACT from register 04h.
Melody mode is to synchronize LED to external music signal. Melody mode can be set through register
MLDACT from register 04h. Each of the 16 LED matrix can be individually enabled for external music
synchronization through register data (address #08h to #09h when register address 04h is set as data 04h).
External Music Signal can be injected from CLKIO pin. CLKIO pin serve as both input and output. CLKIO pin
can output internal oscillator frequency by using CLKOUT register (register 04h).
CLKIO pin can be used as input for external signal by using EXTCLK register (register 04h). External clock
frequency is typically 2.4 MHz. It is advisable to use external clock frequency from 1.2 MHz to 4.8 MHz.
Please do not set MLDACT, EXTCLK and CLKOUT register to "High" at the same time. In such case, the
priority of operation will be EXTCLK then CLKOUT and then Melody Mode will have the least priority.
CLKIO
2.4 MHz
External
Signal
1.2 to 4.8MHz
CLKIO
AC music
signal
CLKIO
Note : If input CLKIO voltage is higher than VDD, there will be back flow current to VDD. It can be calculated as below :
(VCLKIO –0.7 V –VDD)
IBackFlow =
393 k
Cin
Note : Cin can be calculated as below : In case of that the applicable music frequency is 20 Hz.
1
Cin >= = 45.5 nF
( 20 Hz ) x 2 x 3.14 x 175 k
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AC music signal input from CLKIO pin will be compared with internal threshold setting. Based on the
comparison of music signal and threshold voltage, PWM driver control will change and control the LED
ON/OFF. Therefore, LED light on/off control will synchronize with music tempo while LED brightness will
synchronize with music loudness. There are two threshold mode, one is auto threshold and the other is fixed
threshold mode.
There are 8 threshold voltage levels in this LSI as defined in the register 2Bh (THOLD[7:0]). Auto threshold
mode means that the 8 threshold voltages will be scanned automatically from the lowest to highest threshold
voltages at a fixed frequency higher than audio frequency. Input music signal will be compared with these
scanning threshold voltages to control PWM Driver in order to have music synchronization effects. This mode
allows user to easily use music synchronize function without having the trouble of manually setting the
detection threshold. When melody mode is enabled, auto threshold mode will be the default mode.
Fixed threshold mode means that the threshold voltage is fixed at one threshold level. It can be set using
register 2Bh (THOLD[7:0]). Input music signal will be compared with this fixed threshold voltage set by the
user. During fixed threshold mode, do not set more than 1 register bit to logic "High" value at the same time. If
user set more register bits to logic "High" after setting 1 register bit to “High”, system will only recognise the
first "High" bit threshold that is set. In this mode, user can have the flexibility to configure different threshold
voltage levels to achieve the desired LED music synchronizing visual effect according to the system music
input level.
It is also advised that AC music signal peak to peak voltage to be at least 0.35 V and not more than 2.8 V.
Example of Fixed threshold mode
Additional brightness compensation in melody mode can be achieved by increasing or decreasing the turning
on period of LED. Using brightness compensation register MLDCOM[2:0] (#33h), LED turning on period can
be controlled and LED can become brighter or dimmer.
This additional brightness compensation will be effective only in auto threshold mode. If fixed threshold mode
is used, this register will not be able to control LED brightness.
PWM Driver
Constant current
AC music signal
& fixed
Threshold voltage
t
Brightness Compensation in Melody Mode
8. LED Driver Block Function (continued)
8.4 Melody Mode Explanation (continued)
OPERATION ( continued )
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In the above diagram, column 1 = group1, column 2 = group2, column 8 = group8 and column 9 = group9.
Each group can be enabled through register GRP9_1, 9_2, 9_8, 9_9 (address #2Ah). The LED in the all
groups will be synchronized to threshold signals as follow:
Bar Meter Mode operation is another method of external melody mode wherein a group of LEDs are used
instead of individual LED. Bar Meter Mode has higher priority than individual LED melody mode.
All other LEDs not in Bar Meter Mode can operate in individual external melody mode or other modes.
During Bar Meter Mode, auto threshold detection should be used. This LSI does not support Bar Meter Mode
with fixed threshold setting. It is also recommended not to use other modes together with Bar Meter Mode of
LED in group 1, 2, 8 & 9 (i.e. LED A to I1, 2, 8, 9)
Row's E, F, G, H, I
Threshold 5
Row's D, E, F, G, H, I
Threshold 6
Row's G, H, I
Threshold 3
Row's F, G, H, I
Threshold 4
Row's A, B, C, D, E, F, G, H, I
Threshold 8
Row's C, D, E, F, G, H, I
Threshold 7
Row's H, I
Threshold 2
Row's I
Threshold 1
Bar Meter Mode Group LED ONThreshold Signal
Threshold 4
Threshold 5
Threshold 6
Threshold 7
Threshold 8
Threshold 8
GRP9_1
GRP9_2
GRP9_8
GRP9_9
Threshold 1
Threshold 2
Threshold 3
A
B
C
D
E
F
G
H
I
12 3 4 56 7 89
8. LED Driver Block Function (continued)
8.5 Bar Meter Mode Explanation
OPERATION ( continued )
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Ghost images sometimes appear during LED matrix mode operation. Very dim light can appear in some LED
even during OFF condition. This is called Ghost Image. In this LSI, Ghost Image Prevention Function is
included to reduce Ghost Image effect. Ghost Image Prevention Function can be enabled through register
ZPDEN (register 04h).
• Ghost Image Prevention may not remove the ghost image perfectly. It depends on the LED color combination
and LED connection method.
During normal operation, ghost discharge signal will be always low. When ghost image prevention function is
enabled through register 04h, ghost discharge signal will turn on for 2 clks cycle during 4 clks dead time
between each YCNT. During on period of 2 clks cycle, output Z pin will be forced to half of VCC.
Y1CNT
Y2CNT
Y3CNT
Y4CNT
Ghost
discharge
Signals
4 clks
Y4CNT
Y5CNT
Y5CNT
Y6CNT
2 clks
Ghost
discharge
Signals
Ghost Discharge Disabled Ghost Discharge Enabled
Ghost discharge signal turns on for 2 clks
during dead time between Y*CNT.
9. Ghost Image Prevention Function
OPERATION ( continued )
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9. Ghost Image Prevention Function ( continued )
OPERATION ( continued )
Example of RGB LED connection
To minimize ghost image, it is recommended to use LED with same forward voltage drop in LED panel. If user
wants to use LED with different forward voltage drop in LED panel (e.g. RGB LED in LED panel), it is
recommended that all the cathodes of LED connected to the same pin must have same forward voltage drop.
(i.e. same colour LED sharing the same cathode). A recommended RGB LED connection to minimize ghost
image is shown in diagram below.
Connected
pin name
Z4
Z3
Z5
Z1
Z2
Z9
Z8
Z10
Z6
Z7
LED1-B LED1-G LED1-R LED2-RLED2-GLED2-B LED3-B LED3-RLED3-G
LED5-R
LED5-B LED5-G
1
2
3
4
8
5 6
7
10
12
11
9
21
2013
15
19
17
16
14
18
22
LED4-R
LED4-B LED4-G
LED6-R
LED6-B LED6-G LED7-R
LED7-B LED7-G
LED10-R
LED10-B LED10-G LED9-R
LED9-B LED9-G
LED8-B LED8-R LED8-G
LED11-R
LED11-B LED11-G LED12-R
LED12-B LED12-G
LED13-R
LED13-B LED13-G LED14-R
LED14-B LED14-G
LED15-R LED15-G
LED15-B
LED16-R
LED16-B LED16-G
LED18-R
LED18-B LED18-G
LED21-R
LED21-B LED21-G LED22-R
LED22-B LED22-G
LED19-R
LED19-B LED19-G
LED17-R
LED17-G LED17-B
LED20-R
LED20-B LED20-G
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Product Standards
PACKAGE INFORMATION ( Reference Data )
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IMPORTANT NOTICE
1. When using the LSI for new models, verify the safety including the long-term reliability for each product.
2. When the application system is designed by using this LSI, please confirm the notes in this book.
Please read the notes to descriptions and the usage notes in the book.
3. This LSI is intended to be used for general electronic equipment.
Consult our sales staff in advance for information on the following applications: Special applications in which exceptional
quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize life or harm the human
body.
Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automobile, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for
any special application, unless our company agrees to the use of such special application.
4. This LSI is neither designed nor intended for use in automotive applications or environments unless the specific product is
designated by our company as compliant with the ISO/TS 16949 requirements.
Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in
connection with the LSI being used in automotive application, unless our company agrees to such application in this book.
5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage
incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations.
6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might emit
smoke or ignite.
7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In
addition, refer to the Pin Description for the pin configuration.
8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as
solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality,
because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI
during transportation.
9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs
such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load
short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage
and smoke emission will depend on the current capability of the power supply..
10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work
during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily
exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be
damaged before the thermal protection circuit could operate.
11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the
pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated
during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.
12. Verify the risks which might be caused by the malfunctions of external components.
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Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for general applications (such as office equipment, communications
equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,
life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of
the products may directly jeopardize life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the products described in this book for any special application, unless our company agrees to your using the products in
this book for any special application.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or im-
provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
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