LTC6948
19
6948fa
For more information www.linear.com/LTC6948
operaTion
Changes in the internal ALC output can cause extremely
small jumps in the VCO frequency. These jumps may be
acceptable in some applications but not in others. Use the
above table to choose when the ALC is active. The ALCHI
and ALCLO flags, valid only when the ALC is active or the
ALCMON bit is set, may be used to monitor the resonator
amplitude.
The ALC must be allowed to operate during or after a
calibration cycle. At least one of the ALCCAL, ALCEN, or
ALCULOK bits must be set.
VCO (N) DIVIDER
The 10-bit N divider provides the feedback from the VCO to
the PFD. Its divide ratio N is restricted to any integer from
35 to 1019, inclusive, when in fractional mode. The divide
ratio may be programmed from 32 to 1023, inclusive, when
in integer mode. Use the ND[9:0] bits found in registers
h06 and h07 to directly program the N divide ratio. See
the Applications Information section for the relationship
between N and the fREF, fPFD, fVCO, and fRF frequencies.
∆∑ MODULATOR
The Δ∑ modulator changes the N divider’s ratio each PFD
cycle to achieve an average fractional divide ratio. The
fractional numerator NUM[17:0] is programmable from
1 to 262143, or 218 – 1. The fractional denominator is
fixed at 262144 (or 218), with the resulting fractional ratio
F given by Equation 4. See the Applications Information
section for the relationship between NUM, F, and the fREF,
fPFD, fVCO, and fRF frequencies.
The Δ∑ modulator uses digital signal processing (DSP)
techniques to achieve an average fractional divide ratio.
The modulator is clocked at the fPFD rate. This process
produces output modulation noise known as quantization
noise with a highpass frequency response. The external
lowpass loop filter is used to filter this quantization noise to
a level beneath the phase noise of the VCO. This prevents
the noise from contributing to the overall phase noise of
the system. The loop filter must be designed to adequately
filter the quantization noise.
The oversampling ratio OSR is defined as the ratio of the
Δ∑ modulator clock frequency fPFD to the loop bandwidth
BW of the PLL (see Equation 11). See the Applications
Information section for guidelines concerning the OSR
and the loop filter.
When the desired output frequency is such that the needed
NUM value is 0, the LTC6948 should be operated in integer
mode (INTN = 1). In integer mode, the modulator is placed
in standby, with all blocks still powered up, thus allowing
it to resume fractional operation immediately.
Enable numerator dither mode (DITHEN = 1) to further
reduce spurious produced by the modulator. Dither has no
measurable impact on in-band phase noise, and is enabled
by default. See Table 12 for a complete list of modulator
bit descriptions.
Modulator Reset
To achieve consistent spurious performance, the modulator
DSP circuitry should be re-initialized by setting RSTFN=1
whenever NUM[17:0] is changed. Setting AUTORST = 1
causes the RSTFN bit to be set automatically whenever
any of serial port registers h05 through h0A are written.
When AUTORST is enabled, there is no need for a sepa-
rate register write to set the RSTFN bit. See Table 12 for
a summary of the modulator bits.
Table 12. Fractional Modulator Bit Descriptions
BIT DESCRIPTION
AUTORST Automatically Reset Modulator when Registers h05 to h0A
Are Written
DITHEN Enable Fractional Numerator Dither
INTN Integer Mode; Fractional Modulator Placed in Standby
RSTFN Reset Modulator (Auto Clears)
SEED Seed Value for Pseudorandom Dither Algorithm