27C64/87C64 64K (8K x 8) CHMOS PRODUCTION AND UV ERASABLE PROMS mu CHMOS Microcontroller and mg High Performance Speeds Microprocessor Compatible 150 ns Maximum Access Time 87C64-Integrated Address Latch mw New Quick-Pulse Programming Universal 28 Pin Memory Site, 2-line Algorithm (1 second programming) Control gw Available in 28-Pin Cerdip and Plastic m Low Power Consumption DIP Package and 32-Lead PLCC 100 1A Maximum Standby Current Package. : a Noise Immunity Features (See Packaging Spec, Order #231369) +10% Vcc Tolerance Maximum Latch-up Immunity Through EPI Processing intels 27C64 and 87C64 CHMOS EPROMs are 64K bit 5V only memories organized as 8192 words of 8 bits. They employ advanced CHMO$S"II-E circuitry for systems requiring low power, high performance speeds, and immunity to noise. The 87C64 has been optimized for multiplexed bus microcontroller and microprocessor compatibility while the 27C64 has a non-multiplexed addressing interface and is plug compatible with the standard Intel 2764A (HMOS II-E). The 27C64 and 87C64 are offered in both a ceramic DIP, Plastic DIP, and Plastic Leaded Chip Carrier (PLCC) Packages. Cerdip packages provide flexibility in prototyping and R&D environments, whereas Plastic DIP and PLCC EPROMs provide optimum cost effectiveness in production environments. A new Quick-Pulse Program- ming Algorithm is employed which can speed up programming by as much as one. hundred times. The 87C64 incorporates an address latch on the address pins to minimize chip count in multiplexed bus systems. Designers can eliminate an external address latch by tieing address and data pins of the 87C64 directy to the processor's multiplexed address/data pins. On the falling edge of the ALE input (ALE/CE), address information at the address inputs (AgA12) of the 87C64 is latched internally. The address inputs are then ignored as data information is passed on the same bus. The highest degree of protection against !atch-up is achieved through Intels unique EPI processing. Preven- tion of latch-up is provided for stresses up to 100 mA on address and data pins from 1V to Voc + 1V. *HMOS and CHMOS are patented processes of Intel Corporation. DATA OUTPUTS 09-07 OUTPUT ENABLE PROG LOGIC CHIP ENABLE OUTPUT BUFFERS Y=GATING 65,536 BIT dom Aya CELL MATRIX ADDRESS WPUTS 290000-1 Shaded Areas {288355 represent the 87C64 version Figure 1. Block Diagram October 1989 4-28 Order Number: 290000-009j 27C64/87C64 27512 27256 | 27128A 270512 | 270256 | 27C128 2732A | 2716 Ais Vpp Vep Ay2 Ai2 At2 Az Ar Ay Az A; As Ag As Ag Ag As As Ag - As As Aa Ag Aq Ag Ag Ag Ag Ag Ag | Ag Ao Ao Ag Ag Ag Ay Ay Ay Ay Ay Ao Ao Ao Ao Ag Oo Oo Oo Qo Oo O, Oy Oy O71 O71 Og O2 Oz O2 O2 GND GND GND GND | GND NOTE: Pin Names Ag-Aig_| ADDRESSES Oo-07 | OUTPUTS OUTPUT ENABLE CHIP PGM PROGRAM STROBE NC. NO CONNECT DU. OON'T USE 27064/87C64 P27C64/P87C64 Vpp Ct 2812 Yoo Ay, 92 2713 Pow as 26F Nc. ag hs 25 Ag ag 5 24D hy ace 2D Ay as? 22 0 a6 21D Aw ads 2015 Ce, ae Ay Ch 10 wK 0, Opty 18D 0, 0, C12 17D og o, Cts 16, cup Ota 15 Fos 290000-2 27128A | 27256 | 27512 2716 | 2732A 276128 | 270256 | 27512 Voc Voc Veo PGM Ata Ata Veco | Voc Ai3 Ay3 Aig Ag Ag Ag Aa As Ag Ag Ag Ag Ag Vep Ay An Au Any OE | OE/Vpp OE OE/Vep Ato | Ato Ato Ato Ato ce CE cE CE CE O7 O7 O7 07 07 O6 O6 Os Os Os Os Os Os Os Os O4 O4 Os O4 O4 O3 Og Og O3 Og Intel Universal Site Compatible EPROM Pin Configurations are shown in the adjacent blocks to 27C64 Pins. Shaded Areas = Figure 2. Pin Configuration srepresent the 87C64 version Ag As Ms As Az Ay wc % LIL LILILIU N27/87C64-BKXB] Az] |Ar2] | Yep! | Dv | | Yoo | [PCM] | NC N27C128 16KX8 POM] Ars N27C256 S2KX8 Ma N27C512 6akX8 Ata 4 3 2 1 32 uN 30 CU] 5 29 | As Cs wl eee [ at | Ay | 8 32 PIN PLCC 26 | Ne 0.450" X 0.550 oy oe 9 25 | oe C (11.430 X 13.970) Yee MILLIMETERS, Cho its FEE TOP VIEW bo C] tt 23 | ae! CI] 12 22 | oy [| 13 21 | Og 14.15 16 17 18 19 20 Mi 0, 0, [ono] | ou |] 03 | | 04 O5 Figure 3. PLCC(N) Lead Configuration 4-29 290000-11OOS ES TS Ee de intel 27064/87C64 Extended Temperature (Express) EXPRESS EPROM Product Family EPROMs The Intel EXPRESS EPROM family is a series of PRODUCT DEFINITIONS electrically programmable read only memories which Operatin have received additional processing to enhance Type Temperature (c) Burn-in 125C (hr) product characteristics. EXPRESS processing is available for several densities of EPROM, allowing Q Oto +70 168 +8 the choice of appropriate memory size to match sys- T 40 to +85 NONE tem applications. L 40 to +85 168 +8 EXPRESS EPROM products are available with 168 +8 hour, 125C dynamic burn-in using intels stan- dard bias configuration. This process exceeds or EXPRESS Options meets most industry specifications of burn-in. The standard EXPRESS EPROM operating temperature 27C64/87C64 Versions range is 0C to 70C. Extended operating tempera- ture range (40C to +85C) EXPRESS products Packaging Options are also available. Like all Intel EPROMs, the EX- Speed Cerdip PLCC PRESS EPROM family is inspected to 0.1% electri- Versions cal AQL. This may allow the user to reduce or elimi- 4 Q (27) nate incoming inspection testing. -20 T,L,Q T READ OPERATION D.C. CHARACTERISTICS Electrical Parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for: 27C64 Symbol Parameter 87064 Test Conditions Min Max Isp Voc Standby Current (mA) {| CMOS 0.1 CE = Voc, OE = Vit TTL 1.0 CE = Vin, OE = Vit loo, Voc Active Current (mA) TTL 20,30 | OF = CE=Vi_ Vcc Active Current at TIL 20,30 | OF = CE=Vi High Temperature Vep = Voc. Tambient = 85C NOTE: 1. See notes 4 and 6 of Read Operation D.C. Characteristics. YY Vpp Ch! 28 Voc Ayg2 272 Pow a7 3 26D n/c 30 ys apts 25D Aa ie ag O95 24D Ag do j | j | j acs 23 Ay as]? 22 oF nde Bel pr. a on Adds 20/0 E, ave/cE : Yee Mot] 10 19 Eewed of A 290000-14 oO 1 18 ~ ane: 0 7 i Binary Sequence from Ag to Ay2 Oy 13 16 o, noc] 14 shew! 05 290000-13 OE=+5V R=1KN Voc= +5V Vpp= +5V. GND=O0V_ CE = 93.3 KHz PGM = +5V Burn-in Bias and Timing Diagrams| intel 4 27C64/87C64 ABSOLUTE MAXIMUM RATINGS* Operating Temperature During Read ...............065 OC to + 70C(2) Temperature Under Bias......... 10C to + 80C Storage Temperature .......... 65C to + 150C Voltage on Any Pin with Respect to Ground .............. 2.0V to 7V(1) Voltage on Pin Ag with Respect to Ground ......... 2.0V to + 13.5V(1) Vpp Supply Voltage with Respect to Ground During Programming ......... 2.0V to + 14V0) Voc Supply Voitage with Respect to Ground .........- 2.0V to +7.0V0) *Notice: Stresses above those listed under Abso- lute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect device reliability. READ OPERATION D.C. CHARACTERISTICS orc < Ta < +70C Symbol Parameter Notes| Min [Typ(3)| Max [Unit Test Condition ua Input Leakage Current 0.01 1.0 pA |Vin = OV to Voc ILo Output Leakage Current +10 | nA |Voutr = OV to Voc Ipp, Vpp Current Read 100 pA \Vpp = Voc Isp Vcc Current Standby CMOS 100 | pA |CE = Vcc with inputs TL | 4 1.0 |mA|CE = Vin Icc; |Vcc Current Active 4,6 20,30 |mAICE = Vit f = 5 MHz, loyt = OMA VIL Input Low Voltage (+ 10% Supply) ~0.5 0.8 am) V lVpp = V. Input Low Voltage -0.2 0.2 PP ~ CC (CMOS) Min Input High Voltage( + 10% Supply) 2.0 Voct 0.5 am) V |Vpp = V Input High Voltage Voo~0.2 Voc+ 0.2 pps nce (CMOS) VoL Output Low Voltage 0.45 V floL=2.1 mA. VOH Output High Voltage 3.5 V jlon= 2.5mA los Output Short Circuit Current 7 100 |mA Vpp Vpp Read Voltage 8 |Voc0.7 Voc Vv NOTES: 1. Minimum D.C. input voltage is 0.5V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. Maximum D.C. Voltage on output pins is Voc + 0.5V which may overshoot to Voc + 2V for periods less than 20 ns. 2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS and Military version. 3. Typical limits are at Voc = 5V, Ta = +25C. 4. 20 mA for STD and ~3 versions; 30 mA for 150 ns versions. Vit, Vin levels at TTL inputs. 2 and 4-31 5. ALE/CE or CE is Voc + 0.2V. All other inputs can have any value within spec. 6. Maximum Active power usage is the sum Ipp + icc. The maximum current value is with Outputs Op to O7 unloaded. 7. Output shorted for no more than one second. No more than one output shorted at a time. iog is sampled but not 400% tested. 8. Vpp may be one diode voltage drop below Vcc. It may be connected directly to Vcc.! intel 27C64/87C64 READ OPERATION A.C. CHARACTERISTICS 27C64(") 0C < Ta < +70C 27C64-1 27C64-2 Vec +5% N27C64-1 N27C64-2 oe oe 4 P27C64-1 P27C64-2 Versions (3) 27C64-20 Uni Init 27C64-15 Veco + 10% N nae 4-15 N27C64-20 27C64-25 P27C64-20 Symbol Characteristic Min Max Min | Max Min Max tacc Address to Output Delay 150 200 250 ns toe CE to Output Delay 150 200 250 ns toe OE to Output Delay 75 75 100 ns tor (2) OE High to Output High Z 35 55 60 ns ton) Output Hold from Addresses, CE 0 0 0 ns or OE Change-Whichever is First NOTES: 1. A.C. characteristics tested at V4 = 2.4V and Vi_ = 0.45V. Timing measurements made at Vo, = 0.8V and Voy = 2.0V. 2. Guaranteed and sampled. 3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC. A.C. WAVEFORMS 27C64 Vv eeoe tH \ ADDRESSES xX ADDRESS ve K veee ad SR CE / Vit esee / + tog I~ NS OE ve Peewee Ln ate tog tacc tox Vin pom cece output, won Ll VALID OUTPUT men te WAY... 4 290000-5 NOTES: 1. Typical values are for Ta = 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to tcg~toe after the falling edge of CE without impact on toe. 4-3227C64/87C64 A.C. CHARACTERISTICS 67 2 OC < Ta < +70C Voc 5% 87C64-1 87C64-2 87064 Versions (3) N87C64-1 N87C64-2 N87C64 87C64-20. 87C64-25 Unit Vec + 10% N87C64-20 N87C64-25 Symbol Parameter Min Max Min Max Min Max ti Chip Deselect Width 50 50 60 ns taL Address to CE-Latch Set-up 7 20 25 ns tla Address Hold from CE-LATCH 30 45 50 ns tac. CE-Latch Access Time 150 200 250 ns toe Output Enable to Output Valid 75 75 100 ns tcoe ALE/CE to Output Enable 30 45 50 ns tcHz(2) | Chip Deselect to Output in High Z 45 50 60 ns tonz@) Output Disable to Output 35 50 60 ns in High Z NOTES: 1. A.C. characteristics tested at Vix, = 2.4V and Vi_ = 0.45V. Timing measurements made at Vo_ = 0.8V and Voy = 2.0V. 2. Guaranteed and sampled. 3. Model Number Prefixes: No prefix = Cerdip; N = PLCC. A.C. WAVEFORMS ADDRESSES FRXXXMRA RAR _ tw ety, _-! ALE/CE kK . x ty. tree touz \. OUTPUTS coe oe touz OE 290000-6 CAPACITANCE(1) T, = 25C, f = 1.0 MHz Symbol Parameter Max | Unit | Conditions Cin Address/Control Capacitance| 6 | pF | Vin = OV Court | Output Capacitance 12 | pF | Vout = 0V NOTE: 1. Sampled. Not 100% tested. A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 1.3V. 24 2.0 5 2.0 were T OINTS OUTPUT nas INPU Xie sth INTs << os ama . DEVICE 290000-10 UNDER our Cy = 100 pF A.C. Testing: Inputs are driven at 2.4V for a Logic 1and 0.45V 1 for a Logic 0. Timing measurements are made at 2.0V for a - 290000-3 logic 1 and 0.8V for a Logic 0. CL = 100 pF C, Includes Jig Capacitance 4-33| intel 27C64/87C64 DEVICE OPERATION The modes of operation of the 27C64/87C64 are listed in Table 1. A single 5V power supply is re- quired in the read mode. All inputs are TTL levels except for Vpp and 12V on Ag for intgligent Identifier mode. Table 1. Mode Selection for 27C64 and 87C64 Pins oe | POM | ay | ag | Yer | Voc | Outputs Mode (7) (7) Read ViL Vir Vin x(1) Xx Voc 5.0V Dout Output Disable VIL Vin Vin Xx xX Voc 5.0V High Z Standby ViH X x xX xX Voc 5.0V High Z Programming Vit Vin Vit xX x (4) (4) Din Program Verify ViL Vit VIH X x (4) (4) Dout Program Inhibit Vin X Xx xX xX (4) (4) |. HIGHZ intgligent Identifier() ViL Vic ViH Vi(2) Vit Voc Voc 89 H (6) -Manufacturer 88 H (6) intgligent Identifier() Vit Vit Vin Vy (2) Vin Voc Voc 07H -27C64 intgligent Identifier(3, 5) Vit Vit Vin Vy(2) Vin Voc Voc 37H -87C64 NOTES: . X can be Vi_ or Vin. .VH = 12.0V + 0.5V. - Ai-Ag, Ato-12 = ViL- . ALE/CE has to be toggled in order to latch in the addresses and read the signature codes. . The Manufacturers identifier reads 89H for Cerdip devices; 88H for Plastic DiP and PLCC devices. 1 2 3 4. See Table 2 for Vcc and Vpp voltages. 5 6. 7 . In Read Mode tie PGM and Vpp to Vcc. Read Mode: 27C64 The 27C64 has two control functions, both. of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output enable (OE) is the output contro! and should be used to gate data from the output pins. Assuming that ad- dresses are stable, the address access time (tacc) is equal to the delay from CE to output (tc). Data is available at the outputs after a delay of tog from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc-toe. 4-34 Read Mode: 87C64 The 87C64 was designed to reduce the hardware interface requirements when incorporated in proces- sor systems with multiplexed address-data busses. Chip count (and therefore power and board space) can be minimized when the 87C64 is designed as shown in Figure 4. The processors multiplexed bus (ADo-7) is tied to both address and data pins. of the 87C64. All address inputs of the 87C64 are latched when ALE/CE is brought low, thus eliminating the need for a separate address tatch.| intel BO OEE ERE LR a oo af - 27C64/87C64 The 87C64 internal address latch is directly enabled through the use of the ALE/CE line. As the transition occurs on the ALE/CE from the TTL high to the low state, the last address presented at the address pins is retained. Data is then enabled onto the bus from the EPROM by the OE pin. Yss Voc RST Voc Yss 1 i f MTL!" p a7ces mS cs AomAy xTAL2 Op=07 e0cst KAS By otn i" Pa ALE ALE /CE a ASN x Ps 290000-4 Figure 4. 80C31 with 87C64 System Configuration Standby Mode The 27C64 and 87C64 have Standby modes which reduce the maximum Vcc current to 100 uA. Both are placed in the Standby mode when CE or ALE/CE are in the CMOS-high state. When in the Standby mode, the outputs are in a high impedance state, independent of the OE input. Two Line Output Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, CE (or ALE/CE) should be decoded and used as the primary device selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the sys- tem control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. 4-35 SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these tran- sient and inductive current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed by complying with Intel's Two-Line Control, and by properly selected decoupling capaci- tors. It is recommended that a 0.1 uF ceramic ca- pacitor be used on every device between Voc and GND. This should be a high frequency capacitor for low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7 uF bulk electrolytic capacitor should be used between Voc and GND for every eight devices. The buik ca- pacitor should be located near where the power sup- ply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces. PROGRAMMING MODES Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure. The device is in the programming mode when Vpp is raised to its programming voltage (See Table 2) and CE (or ALE/CE) and PGK are both at TTL low and OE = Vip. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program Inhibit Programming of multiple EPROMS in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE (or ALE/CE) or PGM input inhibits the other devices from being programmed.27C64/87C64 Except for CE (or ALE/CE), all like inputs (including OE) of the parallel EPROMs may be common. A TTL low-level pulse applied to the PGM input with Vpp at its programming voltage and CE (or ALE/CE) = Vit will program the selected device. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they have been cor- rectly programmed, The verify is performed with OE and CE (or ALE/CE) at Vi, at Vin, and Voc and Vpp at their programming voltages. Data should pe verified a minimum of tog after the falling edge of E. intgligent Identifier Mode The intgligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro- grammed with its corresponding programming aigo- rithm. This mode is functional in the 25C +5C am- bient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line AO from Vi to Viz. Al other address lines must be held at Vi, during the intgligent Identifier Mode. Byte 0 (AO = Vj.) represents the manufacturer code and byte 1 (AO = Vj) the device identifier code. These two identifier bytes are given in Table 1. ALE/CE of the 87C64 has to be toggled in order to latch in the addresses and read the Signature Codes. 4-36 ERASURE CHARACTERISTICS (FOR CERDIP EPROMS) The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data shows that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity < exposure time) for erasure should be a minimum of 15 Wsec/cm?. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 W/cm? power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 wW/ cm2). Exposure of the device to high intensity UV light for longer periods may cause permanent dam- age. CHMOS NOISE CHARACTERISTICS Special EP! processing techniques have enabled In- tel to build CHMOS with features adding to system reliability. These include input/output protection to latch-up. Each of the data and address pins will not latch-up with currents up to 100 mA and voltages from 1V to Voc + TV. Additionally, the Vpp (programming) pin is designed to resist latch-up to the 14V maximum device limit.] 27C64/87C64 INCREMENT LAST ADDRESS ADDRESS? COMPARE ALL BYTES TO ORIGINAL DATA PASS PROGRAM ONE 100 ys PULSE INCREMENT X Voc = Vpp = 5.0V START ADDRESS = FIRST LOCATION Voc = 6.25 Vp = 12.75V Vv DEVICE FAILED DEVICE PASSED 290000-12 Figure 5. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm Intels 27C64 and 87C64 EPROMs can now be pro- grammed using the Quick-Pulse Programming Algo- rithm, developed by Intel to substantially reduce the throughput time in the production environment. This algorithm allows these devices to be programmed in under one second, almost a hundred fold improve- ment over previous algorithms. Actual programming time is a function of the PROM programmer being used. The Quick-Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a byte veri- 4-37 fication to determine when the address byte has been successfully programmed. Up to 25 100 ps pulses per byte are provided before a failure is rec- ognized. A flowchart of the Quick-Pulse Program- ming Algorithm is shown in Figure 5. For the Quick Pulse Programming Algorithm, the en- tire sequence of programming pulses and byte verifi- cations is performed at Voc = 6.25V and Vpp at 12.75V. When programming of the EPROM has been completed, all bytes should be compared to the original data with Voc = Vpp = 5.0V.! | 27C64/87C64 D.C. PROGRAMMING CHARACTERISTICS (27064/87C64) Ta = 25C +5C Table 2 Symbol Parameter Limits Test Conditions Min Max Unit (Note 1) Ihe Input Current (All Inputs) 1.0 pA Vin = Vic or Vin VIL Input Low Level (All Inputs) 0.1 - 0.8 Vv Vin Input High Level 2.0 Veco + 0.5 v VoL Output Low Voltage During Verify 0.45 Vv lo. = 2.1 mA VoH Output High Voltage During Verify 3.6 Vv lon = 2.5mA Ioce(9) Vcc Supply Current 30 mA Ippo(3) Vpp Supply Current (Program) 30 mA CE = Vit Vip Ag intgligent Identifier Voltage 411.5 12.5 Vv Vpp Programming Voltage 12.5 13.0 Vv Voc Supply Voltage During Programming 6.0 6.5 Vv A.C. PROGRAMMING CHARACTERISTICS 27C64 Ta = 25C +5C, See Table 2 for Vcc and Vpp Voltages Symbol Parameter Limits Conditions Min Typ Max Unit (Note 1) tas Address Setup Time 2 ys toes GE Setup Time 2 ps tos Data Setup Time 2 ps taH Address Hold Time Qo ps toH Data Hold Time 2 ps torp GE High to Output Float Delay 0 130 ns (Note 2) tvps Vpp Setup Time 2 ps tycs Voc Setup Time 2 pS tces CE Setup Time 2 ps tpw PGM Program Pulse Width 95 100 105 ps Quick-Pulse toE Data Valid from OE 150 ns NOTES: A.C. CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%)...... 20 ns Input Pulse Levels .............-..45 0.45V to 2.4V Input Timing Reference Level ....... 0.8V and 2.0V Output Timing Reference Level...... 0.8V and 3.5V 4-38 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no long- er drivensee timing diagram. 3. The maximum current value is with outputs Op to O7 Un- loaded.intel 27C64/87C64 PROGRAMMING WAVEFORMS 27C64 - VERIFY > v, =e ADDRESSES x ADDRESS STABLE Vi mee t - = AH v iH [ HiGH2 f ve DATA DATA IN STABLE DATA OUT VALID =e Vit > ve tore(2) tos . lag POH eet 12.754 2. Vee ] 5.0 tues 6.25 > Vcc ] 5.0v ives Vin cE Vie ve tces . YY, vo PGM Vi x ' tow toes toe! Vin a | _ tor oe > PW fe \ Vi 290000-9 NOTES: 1. The Input Timing Reference Level is 0.8V for Vi_ and 2V for a Vin. 2. tog and tprp are characteristics of the device but must be accommodated by the programmer. 3. When programming the 27C64, a 0.1 uF capacitor is required across Vpp and ground to suppress spurious voitage transients which can damage the device. 4-39| intel 27064/87C64 A.C. PROGRAMMING CHARACTERISTICS - Ta = 25C +5C, See Table 2 for Voc and Vpp Voltages. Symbol |" Parameter Limits Unit Conditions Min Typ . Max tvps | Vpp Setup Time 2 ps tyvcs Voc Setup Time 2 ps ti Chip Deselect Width 2 ps taL Address to Chip Select Setup 1 ps tLa Address Hold from Chip Select 1 ps tpw PGM Pulse Width 95 100 105 us Quick-Pulse tos Data Setup Time ps tpFP OE High to Data Float 130 ns toes Output Enable Setup Time / ps toe Data Valid from Output Enable 150 ns tou Data Hold Time pS tces CE Setup Time BS NOTE: 1. Programming tolerances and test conditions are the same as 27C64. PROGRAMMING WAVEFORMS ADDRESS ADDRESSES tamte tay DATA ALE/CE PGM 290000-8 NOTE: 1. 12.75V Vpp & 6.25V Voc for Quick-Pulse Programming Algorithm. 4-40i | intel 27064/87C64 REVISION HISTORY Number Description 09 Revised DIP and PLCC pin configurations. Revised Express options. Deleted 3 and 30 speed bins. Deleted Plastic DIP 87C84 Option. 4-41