19-2419; Rev 6; 10/14
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX5048A/MAX5048B are high-speed MOSFET
drivers capable of sinking/sourcing 7.6A/1.3A peak cur-
rents. These devices take logic input signals and drive
a large external MOSFET. The MAX5048A/MAX5048B
have inverting and noninverting inputs that give the
user greater flexibility in controlling the MOSFET. They
feature two separate outputs working in complementary
mode, offering flexibility in controlling both turn-on and
turn-off switching speeds.
The MAX5048A/MAX5048B have internal logic circuitry,
which prevents shoot-through during output state
changes. The logic inputs are protected against volt-
age spikes up to +14V, regardless of V+ voltage.
Propagation delay time is minimized and matched
between the inverting and noninverting inputs. The
MAX5048A/MAX5048B have very fast switching times
combined with very short propagation delays (12ns
typ), making them ideal for high-frequency circuits.
The MAX5048A/MAX5048B operate from a +4V to +12.6V
single power supply and typically consume 0.95mA of
supply current. The MAX5048A has CMOS input logic
levels, while the MAX5048B has standard TTL input logic
levels. These devices are available in space-saving
6-pin SOT23 and TDFN packages.
Applications
Power MOSFET Switching
Switch-Mode Power Supplies
DC-DC Converters
Motor Control
Power-Supply Modules
Features
oIndependent Source-and-Sink Outputs for
Controllable Rise and Fall Times
o+4V to +12.6V Single Power Supply
o7.6A/1.3A Peak Sink/Source Drive Current
o0.23ΩOpen-Drain n-Channel Sink Output
o2ΩOpen-Drain p-Channel Source Output
o12ns (typ) Propagation Delay
oMatching Delay Time Between Inverting and
Noninverting Inputs
oVCC/2 CMOS (MAX5048A)/TTL (MAX5048B) Logic
Inputs
o1.6V Input Hysteresis
oUp to +14V Logic Inputs (Regardless of V+
Voltage)
oLow Input Capacitance: 2.5pF (typ)
o-40°C to +125°C Operating Temperature Range
o6-Pin SOT23 and TDFN Packages
P_OUT
GNDN_OUT
1
+
6 IN+
5 IN-
V+
MAX5048A
MAX5048B
SOT23
TOP VIEW
2
34
Pin Configurations
Typical Operating Circuit
Ordering Information
MAX5048A
MAX5048B
P_OUT
N_OUT
IN-
GND
IN+
V+
V+
N
PART TEMP RANGE PIN-
PACKAGE
LOGIC
INPUT
TOP
MARK
MAX5048AAUT-T -40°C to +125°C 6 SOT23 VCC/2
CMOS ABEC
MAX5048BAUT-T -40°C to +125°C 6 SOT23 TTL ABED
MAX5048AATT-T -40°C to +125°C 6 TDFN-EP* VCC/2
CMOS AKV
MAX5048BATT-T -40°C to +125°C 6 TDFN-EP* TTL AKW
Pin Configurations continued at end of data sheet.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*
EP = Exposed pad.
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
2Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = +12V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltages Referenced to GND
V+ ...........................................................................-0.3V to +13V
IN+, IN-...................................................................-0.3V to +14V
N_OUT, P_OUT ............................................-0.3V to (V+ + 0.3V)
N_OUT Continuous Output Current (Note 1) ....................390mA
P_OUT Continuous Output Current (Note 1).....................100mA
Continuous Power Dissipation* (TA= +70°C)
6-Pin SOT23 (derate 9.1mW/°C above +70°C)............727mW
6-Pin TDFN (derate 18.2mW/°C above +70°C) .........1454mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Continuous output current is limited by the power dissipation of the package.
*As per JEDEC51 standard.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
V+ Operating Range V+ 4.0 12.6 V
V+ Undervoltage Lockout UVLO V+ rising 3.25 3.6 4.00 V
V+ Undervoltage Lockout
Hysteresis 400 mV
V+ Undervoltage Lockout to
Output Delay Time V+ rising 300 ns
V+ Supply Current I+ IN+ = IN- = V+ 0.95 1.5 mA
n-CHANNEL OUTPUT
TA = +25°C 0.23 0.32
VV+ = +10V,
IN-OUT = -100mA TA = +125°C 0.38 0.43
TA = +25°C 0.24 0.34
Driver Output Resistance—
Pulling Down (MAX5048AAUT/
MAX5048BAUT)
RON-N VV+ = +4.5V,
IN-OUT = -100mA TA = +125°C 0.40 0.47
Ω
TA = +25°C 0.31 0.34
VV+ = +10V,
IN-OUT = -100mA TA = +125°C 0.46 0.51
TA = +25°C 0.32 0.36
Driver Output Resistance—
Pulling Down (MAX5048AATT/
MAX5048BATT)
RON-N
VV+ = +4.5V,
IN-OUT = -100mA TA = +125°C 0.48 0.55
Ω
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 2)
SOT23
Junction-to-Case Thermal Resistance (θJC)......................75°C/W
TDFN
Junction-to-Case Thermal Resistance (θJC).......................8.5°C/W
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
3
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Off Pulldown Resistance V+ = 0 or unconnected, IN-OUT = -10mA,
TA = +25°C 3.3 10 Ω
Power-Off Pulldown Clamp
Voltage
V+ = 0 or unconnected, IN-OUT = -10mA,
TA = +25°C 0.85 1.0 V
Output Leakage Current ILK-N N_OUT = V+ 6.85 20 µA
Peak Output Current (Sinking) IPK-N CL = 10,000pF 7.6 A
p-CHANNEL OUTPUT
TA = +25°C 2.00 3.00
VV+ = +10V,
IP-OUT = 50mA TA = +125°C 2.85 4.30
TA = +25°C 2.20 3.30
Driver Output Resistance—
Pulling Up (MAX5048AAUT/
MAX5048BAUT)
RON-P VV+ = +4.5V,
IP-OUT = 50mA TA = +125°C 3.10 4.70
Ω
TA = +25°C 2.08 3.08
VV+ = +10V,
IP-OUT = 50mA TA = +125°C 2.93 4.38
TA = +25°C 2.28 3.38
Driver Output Resistance—
Pulling Up (MAX5048AATT/
MAX5048BATT)
RON-P VV+ = +4.5V,
IP-OUT = 50mA TA = +125°C 3.18 4.78
Ω
Output Leakage Current ILK-P P_OUT = 0 0.001 10 µA
Peak Output Current (Sourcing) IPK-P CL = 10,000pF 1.3 A
LOGIC INPUT
MAX5048A 0.67 x V+
Logic 1 Input Voltage VIH MAX5048B 2.4 V
MAX5048A 0.33 x V+
Logic 0 Input Voltage VIL MAX5048B 0.8 V
MAX5048A 1.6
Logic-Input Hysteresis VHYS MAX5048B 0.68 V
Logic-Input Current VIN_ = V+ or 0 0.001 10 µA
Input Capacitance CIN 2.5 pF
SWITCHING CHARACTERISTICS FOR V+ = +10V
CL = 1000pF 8
CL = 5000pF 45
Rise Time tR
CL = 10,000pF 82
ns
CL = 1000pF 3.2
CL = 5000pF 7.5Fall Time tF
CL = 10,000pF 12.5
ns
Turn-On Propagation Delay Time tD-ON Figure 1, CL = 1000pF (Note 4) 7 12 25 ns
Turn-Off Propagation Delay Time tD-OFF Figure 1, CL = 1000pF (Note 4) 7 12 25 ns
Break-Before-Make Time 2.5 ns
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, TA= -40°C to +125°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Note 3: All DC specifications are 100% tested at TA= +25°C. Specifications over -40°C to +125°C are guaranteed by design.
Note 4: Guaranteed by design, not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SWITCHING CHARACTERISTICS FOR V+ = +4.5V
CL = 1000pF 12
CL = 5000pF 41
Rise Time tR
CL = 10,000pF 74
ns
CL = 1000pF 3.0
CL = 5000pF 7.0Fall Time tF
CL = 10,000pF 11.3
ns
Turn-On Propagation Delay Time tD-ON Figure 1, CL = 1000pF (Note 4) 8 14 27 ns
Turn-Off Propagation Delay Time tD-OFF Figure 1, CL = 1000pF (Note 4) 8 14 27 ns
Break-Before-Make Time 4.2 ns
Typical Operating Characteristics
(CL= 1000pF, TA = +25°C, unless otherwise noted.)
RISE TIME vs. SUPPLY VOLTAGE
MAX5048 toc01
SUPPLY VOLTAGE (V)
RISE TIME (ns)
1086
8
11
14
17
20
5
412
TA = +125°C
TA = 0°C
TA = +85°C
TA = +25°C
TA = -40°C
FALL TIME vs. SUPPLY VOLTAGE
MAX5048 toc02
SUPPLY VOLTAGE (V)
FALL TIME (ns)
1086
2.5
3.5
4.5
5.0
6.0
2.0
412
TA = +125°C
TA = -40°C
TA = 0°C
TA = +85°C
TA = +25°C
3.0
5.5
4.0
MAX5048 toc03
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
1086
12
14
16
18
20
10
412
TA = +125°C
TA = -40°C
TA = 0°C
TA = +85°C
TA = +25°C
PROPAGATION DELAY TIME, LOW-TO-HIGH
vs. SUPPLY VOLTAGE
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
5
Maxim Integrated
Typical Operating Characteristics (continued)
(CL= 1000pF, TA = +25°C, unless otherwise noted.)
MAX5048 toc04
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
1086
12
14
16
18
20
10
412
TA = +125°C
TA = -40°C
TA = 0°C
TA = +85°C
TA = +25°C
PROPAGATION DELAY TIME, HIGH-TO-LOW
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5048 toc05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
1086
2
4
6
8
10
12
0
412
DUTY CYCLE = 50%
V+ = +10V, CL = 0
1MHz
500kHz
40kHz
75kHz
100kHz
SUPPLY CURRENT vs. LOAD CAPACITANCE
MAX5048 toc06
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
16001200400 800
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0 2000
V+ = +10V
f = 100kHz
DUTY CYCLE = 50%
SUPPLY CURRENT vs. TEMPERATURE
MAX5048 toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
1007550250-25
1.3
1.4
1.5
1.6
1.7
1.8
1.2
-50 125
V+ = +10V
f = 100kHz, CL = 0
DUTY CYCLE = 50%
MAX5048A
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX5048 toc08
SUPPLY VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
1086
1
2
3
4
5
6
7
8
0
412
RISING
FALLING
MAX5048A
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX5048 toc09
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
108642
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0.8
012
INPUT
HIGH-TO-LOW
INPUT
LOW-TO-HIGH
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
6Maxim Integrated
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 5000pF)
MAX5048 toc10
IN+
2V/div
OUTPUT
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 10,000pF)
MAX5048 toc11
IN+
2V/div
OUTPUT
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 5000pF)
MAX5048 toc12
IN+
2V/div
OUTPUT
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 10,000pF)
MAX5048 toc13
IN+
2V/div
OUTPUT
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 5000pF)
MAX5048 toc14
IN+
5V/div
OUTPUT
5V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 10,000pF)
MAX5048 toc15
IN+
5V/div
OUTPUT
5V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 5000pF)
MAX5048 toc16
IN+
5V/div
OUTPUT
5V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 10,000pF)
MAX5048 toc17
IN+
5V/div
OUTPUT
5V/div
20ns/div
Typical Operating Characteristics (continued)
(CL= 1000pF, TA = +25°C, unless otherwise noted.)
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
7
Maxim Integrated
Detailed Description
Logic Inputs
The MAX5048A/MAX5048Bs’ logic inputs are protected
against voltage spikes up to +14V, regardless of the V+
voltage. The low 2.5pF input capacitance of the inputs
reduces loading and increases switching speed. These
devices have two inputs that give the user greater flexi-
bility in controlling the MOSFET. Table 1 shows all pos-
sible input combinations.
The difference between the MAX5048A and the
MAX5048B is the input threshold voltage. The
MAX5048A has VCC/2 CMOS logic-level thresholds,
while the MAX5048B has TTL logic-level thresholds (see
the
Electrical Characteristics
). For V+ above 5.5V, VIH
(typ) = 0.5x(V+) + 0.8V and VIL (typ) = 0.5x(V+) - 0.8V.
As V+ is reduced from 5.5V to 4V, VIH and VIL gradually
approach VIH (typ) = 0.5x(V+) + 0.65V and VIL (typ) =
0.5x(V+) - 0.65V. Connect IN+ to V+ or IN- to GND
when not used. Alternatively, the unused input can be
used as an ON/OFF pin (see Table 1).
Undervoltage Lockout (UVLO)
When V+ is below the UVLO threshold, the N-channel
is ON and the P-channel is OFF, independent of the
state of the inputs. The UVLO is typically 3.6V with
400mV typical hysteresis to avoid chattering.
Driver Outputs
The MAX5048A/MAX5048B provide two separate out-
puts. One is an open-drain P-channel, the other an
open-drain N-channel. They have distinct current sourc-
ing/sinking capabilities to independently control the rise
and fall times of the MOSFET gate. Add a resistor in
series with P_OUT/N_OUT to slow the corresponding
rise/fall time of the MOSFET gate.
Applications Information
Supply Bypassing, Device Grounding,
and Placement
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the V+
pin can approach 1.3A, while at the GND pin the peak
current can approach 7.6A. VCC drops and ground
shifts are forms of negative feedback for inverters and, if
excessive, can cause multiple switching when the IN-
input is used and the input slew rate is low. The device
driving the input should be referenced to the
MAX5048A/MAX5048B GND pin especially when the IN-
input is used. Ground shifts due to insufficient device
grounding may disturb other circuits sharing the same
AC ground return path. Any series inductance in the V+,
P_OUT, N_OUT and/or GND paths can cause oscilla-
tions due to the very high di/dt that results when the
MAX5048A/MAX5048B are switched with any capacitive
load. A 0.1µF or larger value ceramic capacitor is rec-
ommended bypassing V+ to GND and placed as close
to the pins as possible. When driving very large loads
(e.g., 10nF) at minimum rise time, 10µF or more of paral-
lel storage capacitance is recommended. A ground
plane is highly recommended to minimize ground return
resistance and series inductance. Care should be taken
to place the MAX5048A/MAX5048B as close as possi-
ble to the external MOSFET being driven to further mini-
mize board inductance and AC path resistance.
Power Dissipation
Power dissipation of the MAX5048A/MAX5048B con-
sists of three components, caused by the quiescent
current, capacitive charge and discharge of internal
nodes, and the output current (either capacitive or
resistive load). The sum of these components must be
kept below the maximum power-dissipation limit.
Pin Description
PIN NAME FUNCTION
1V+
Power Supply. Bypass to GND with a
0.1µF ceramic capacitor.
2 P_OUT p-Channel Open-Drain Output. Sources
current for MOSFET turn-on.
3 N_OUT n-Channel Open-Drain Output. Sinks
current for MOSFET turn-off.
4 GND Ground
5IN-
Inverting Logic Input Terminal. Connect
to GND when not used.
6 IN+ Noninverting Logic Input Terminal.
Connect to V+ when not used.
—EP
Exposed paddle. Connect to GND.
Solder EP to the GND plane for
improved thermal performance.
IN+ IN- p-CHANNEL n-CHANNEL
L L OFF ON
L H OFF ON
H L ON OFF
H H OFF ON
Table 1. Truth Table
L = Logic low
H = Logic high
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
8Maxim Integrated
The quiescent current is 0.95mA typical. The current
required to charge and discharge the internal nodes is
frequency dependent (see the
Typical Operating
Characteristics
). The MAX5048A/MAX5048B power dis-
sipation when driving a ground referenced resistive
load is:
P = D x RON(MAX) x ILOAD2
where D is the fraction of the period the MAX5048A/
MAX5048Bs’ output pulls high, RON (MAX) is the maxi-
mum on-resistance of the device with the output high
(P-channel), and ILOAD is the output load current of the
MAX5048A/MAX5048B.
For capacitive loads, the power dissipation is:
P = CLOAD x (V+)2x FREQ
where CLOAD is the capacitive load, V+ is the supply
voltage, and FREQ is the switching frequency.
Layout Information
The MOSFET drivers MAX5048A/MAX5048B source-
and-sink large currents to create very fast rise and fall
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. The
following PCB layout guidelines are recommended
when designing with the MAX5048A/MAX5048B:
• Place one or more 0.1µF decoupling ceramic capaci-
tor(s) from V+ to GND as close to the device as possi-
ble. At least one storage capacitor of 10µF (min)
should be located on the PC board with a low resis-
tance path to the V+ pin of the MAX5048A/MAX5048B.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from N_OUT of the
MAX5048A/MAX5048B to the MOSFET gate to the
MOSFET source and to GND of the MAX5048A/
MAX5048B. When the gate of the MOSFET is being
pulled high, the active current loop is from P_OUT of
the MAX5048A/MAX5048B to the MOSFET gate to
the MOSFET source to the GND terminal of the
decoupling capacitor to the V+ terminal of the
decoupling capacitor and to the V+ terminal of the
MAX5048A/MAX5048B. While the charging current
loop is important, the discharging current loop is crit-
ical. It is important to minimize the physical distance
and the impedance in these AC current paths.
• In a multilayer PCB, the component surface layer
surrounding the MAX5048A/MAX5048B should con-
sist of a GND plane containing the discharging and
charging current loops.
IN+
VIL
90%
10%
tD–OFF
P_OUT AND
N_OUT
TIED
TOGETHER
tD–ON
tFtR
IN+
IN-
V+
V+
CL
N_OUT
GND
P_OUT
TEST CIRCUIT
TIMING DIAGRAM
MAX5048A
MAX5048B
INPUT
OUTPUT
VIH
Figure 1. Timing Diagram and Test Circuit
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
9
Maxim Integrated
BREAK-
BEFORE-
MAKE
CONTROL
P
N
N_OUT
GND
IN-
IN+
P_OUT
V+
MAX5048A
MAX5048B
Figure 2. MAX5048A/MAX5048B Functional Diagram
MAX5048A
MAX5048B
P_OUT
N_OUT
IN-
GND
IN+
V+
VS
V+
(4V TO 12.6V)
Figure 3. Noninverting Application
MAX5048A
MAX5048B
P_OUT
N_OUT
IN-
GND
IN+
V+
VS
VOUT
FROM PWM
CONTROLLER
(BOOST)
V+
(4V TO 12.6V)
Figure 4. Boost Converter
MAX5048A
MAX5048B
P_OUT
N_OUT
IN-
GND
IN+ V+
MAX5048A/
MAX5048B
P_OUT
N_OUT
IN-
GND
IN+ V+
FROM PWM
CONTROLLER
(BUCK) VOUT
4V TO 12V
P
N
Figure 5. MAX5048A/MAX5048B in High-Power Synchronous
Buck Converter
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
10 Maxim Integrated
P_OUT
GNDN_OUT
1
+
6 IN+
5 IN-
V+
MAX5048A
MAX5048B
TDFN-EP
(3mm x 3mm)
TOP VIEW
2
3
EXPOSED PAD
4
Pin Configurations (continued) Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
6 SOT23 U6F+6 21-0058 90-0175
6 TDFN —21-0137 90-0058
Chip Information
PROCESS: BiCMOS
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________
11
© 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
5 11/12 Added “+” lead(Pb)-free/RoHS-compliant designations to Ordering Information 1, 9
6 10/14 Updated Driver Output Resistance—Pulling Down specifications 2
