Features
•Serial Peripheral Interface (SPI) Compatible
•Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
•Low-voltage and Standard-voltage Operation
–V
CC = 1.8V to 5.5V
•20 MHz Clock Rate (5V)
•8-byte Page Mode
•Block Write Protection
– Protect 1/4, 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
•Self-timed Write Cycle (5 ms max)
•High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
•Green (Pb/Halogen-free/Rohs Compliant) Packaging Options
•Die Sales: Wafer Form, Waffle Pack, Bumped Wafers
Description
The Atmel®AT25010B/020B/040B provides 1024/2048/4096 bits of serial electrically
erasable programmable read-only memory (EEPROM) organized as 128/256/512
words of 8 bits each. The device is optimized for use in many industrial and commer-
cial applications where low-power and low-voltage operation are essential. The
AT25010B/020B/040B is available in space saving, JEDEC SOIC, UDFN, TSSOP,
XDFN and VFBGA packages.
The AT25010B/020B/040B is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate Program Enable and Program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 0-1. Pin Configuration
Pin Name Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
SPI Serial
EEPROM
1K (128x8)
2K (256x8)
4K (512x8)
Atmel AT25010B
Atmel AT25020B
Atmel AT25040B
V
CC
HOLD
SCK
SI
CS
SO
WP
GND
4
3
2
1
5
6
7
8
8-lead UDFN, XDFN
Bottom View
V
CC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball VFBGA
Bottom View
1
2
3
4
8
7
6
5
SOIC, TSSOP
V
CC
HOLD
SCK
SI
CS
SO
WP
GND
8707C–SEEPR–6/11
2
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
1. Absolute Maximum Ratings*
Figure 1-1. Block Diagram
Operating Temperature  40°C to + 125°C *NOTICE: Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is
a stress rating only and functional opera-
tion of the device at these or any other
conditions beyond those indicated in the
operational sections of this specification
is not implied. Exposure to absolute max-
imum rating conditions for extended peri-
ods may affect device reliability.
Storage Temperature 65°C to + 150°C
Voltage on Any Pin
with Respect to Ground  1.0V to + 7.0V
Maximum Operating Voltage.................................... 6.25V
DC Output Current ................................................. 5.0 mA
MEMORY ARRAY
128/256/512 X 8
STATUS
REGISTER
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
ADDRESS
DECODER
VCC
3
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
Table 1-1. Pin Capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested.
Table 1-2. DC Characteristics(1)
Note: 1. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from TA= 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT =0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN =0V
Applicable over recommended operating range from: TAI =40Cto+85C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 20 MHz, SO = Open, Read 8.5 10.0 mA
ICC2 Supply Current VCC = 5.0V at 10 MHz, SO = Open, Read, Write 4.5 5.0 mA
ICC3 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read, Write 2.0 3.0 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 0.5 µA
ISB2 Standby Current VCC = 2.5V, CS = VCC 0.2 1.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 3.5 µA
IIL Input Leakage VIN =0VtoV
CC 3.0 µA
IOL Output Leakage VIN =0VtoV
CC,T
AC = 0°C to 70°C 3.0 3.0 µA
VIL(1) Input Low-voltage 0.6 VCC x 0.3 V
VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage 3.6V VCC 5.5V IOL = 3.0 mA 0.4 V
VOH1 Output High-voltage IOH =1.6 mA VCC 0.8 V
VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15 mA 0.2 V
VOH2 Output High-voltage IOH =100 µA VCC 0.2 V
4
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
Table 1-3. AC Characteristics
Applicable over recommended operating range from TAI =40 to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
20
10
5
MHz
tRI Input Rise Time
4.5 5.5
2.5 5.5
1.8 5.5
2
2
2
µs
tFI Input Fall Time
4.5 5.5
2.5 5.5
1.8 5.5
2
2
2
µs
tWH SCK High Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tWL SCK Low Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tCS CS High Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
ns
tCSS CS Setup Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
ns
tCSH CS Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
ns
tSU Data In Setup Time
4.5 5.5
2.5 5.5
1.85.5
20
40
80
ns
tHData In Hold Time
4.5 5.5
2.5 - 5.5
1.8 - 5.5
20
40
80
ns
tHD Hold Setup Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tCD Hold Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tVOutput Valid
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
20
40
80
ns
tHO Output Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
ns
tLZ Hold to Output Low Z
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
25
50
100
ns
5
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
Note: 1. This parameter is characterized and is not 100% tested.
2. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010B/020B/040B always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25010B/020B/040B has separate pins designated for data transmission (SO)
and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte con-
tains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both
the read and write instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010B/020B/040B, and
the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This
will reinitialize the serial communication.
CHIP SELECT: The AT25010B/020B/040B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010B/020B/040B. When the device
is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK
pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still
toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010B/020B/040B. If the internal write cycle has
already been initiated, WP going low will have no effect on any write operation.
tHZ Hold to Output High Z
4.5 5.5
2.5 5.5
1.8 5.5
25
50
100
ns
tDIS Output Disable Time
4.5 5.5
2.5 5.5
1.8 5.5
25
50
100
ns
tWC Write Cycle Time
4.5 5.5
2.5 5.5
1.8 5.5
5
5
5
ms
Endurance(1) 5.0V, 25C, Page Mode 1M Write Cycles
Table 1-3. AC Characteristics (Continued)
Applicable over recommended operating range from TAI =40 to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
6
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
Figure 2-1. SPI Serial Interface
AT25010B/020B/040B
7
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
3. Functional Description
The AT25010B/020B/040B is designed to interface directly with the synchronous serial peripheral interface (SPI) of
the 6805 and 68HC11 series of microcontrollers.
The AT25010B/020B/040B utilizes an 8-bit instruction register. The list of instructions and their operation codes
are contained in Figure 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low CS transition.
Note: “A” represents MSB address bit A8.
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during
a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The read/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-1. Instruction Set for the AT25010B/020B/040B
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 A011 Read Data from Memory Array
WRITE 0000 A010 Write Data to Memory Array
Table 3-2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
XXXXBP1BP0WEN
RDY
Table 3-3. Read Status Register Bit Definition
Bit Definition
Bit0(
RDY) Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN) Bit 1 = “0” indicates the device is not write enabled.
Bit 1 = “1” indicates the device is write enabled.
Bit 2 (BP0) See Table 3-4.
Bit 3 (BP1) See Table 3-4.
Bits 4–7 are “0”s when device is not in an internal write cycle.
Bits 0–7 are “1”s during an internal write cycle.
8
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec-
tion. The AT25010B/020B/040B is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4.
Bits BP1 and BP0 are nonvolatile cells that have the same properties and functions as the regular memory cells
(e.g., WREN, tWC, RDSR).
READ SEQUENCE (READ): Reading the AT25010B/020B/040B via the SO pin requires the following sequence.
After the CS line is pulled low to select a device, the read op-code (including A8) is transmitted via the SI line fol-
lowed by the byte address to be read (A7A0). Upon completion, any data on the SI line will be ignored. The data
(D7D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line
should be driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read
cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25010B/020B/040B, the Write Protect pin (WP) must be
held high and two separate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be
programmed must be outside the protected address field location selected by the block write protection level. Dur-
ing an internal write cycle, all commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE
op-code (including A8) is transmitted via the SI line followed by the byte address (A7A0) and the data (D7D0) to
be programmed. Programming will start after the CS pin is brought high. The low-to-high transition of the CSpin
must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The ready/busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If
Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is
enabled during the write programming cycle.
The AT25010B/020B/040B is capable of an 8-byte page write operation. After each byte of data is received, the
three low-order address bits are internally incremented by one; the six high-order bits of the address will remain
constant. If more than 8 bytes of data are transmitted, the address counter will roll over and the previously written
data will be overwritten. The AT25010B/020B/040B is automatically returned to the write disable state at the com-
pletion of a write cycle.
Note: If the WP pin is brought low or if the device is not write enabled (WREN), the device will ignore the Write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
Table 3-4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25010B AT25020B AT25040B
0 0 0 None None None
1 (1/4) 0 1 607F C0FF 180FF
2 (1/2) 1 0 407F 80FF 1001FF
3 (All) 1 1 007F 00FF 0001FF
9
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
4. Timing Diagrams
Figure 4-1. Synchronous Data Timing (for Mode 0)
Figure 4-2. WREN Timing
Figure 4-3. WRDI Timing
SO HI-Z HI-Z
t
V
VALID IN
SI
t
H
t
SU
t
DIS
SCK t
WH
t
CSH
CS
t
CSS
t
CS
t
WL
t
HO
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VOH
V
OL
SO
SI
SCK
CS
WREN OP-CODE
HI-Z
SO
SI
SCK
CS
WRDI OP-CODE
HI-Z
10
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
Figure 4-4. RDSR Timing
Figure 4-5. WRSR Timing
Figure 4-6. READ Timing
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
76543210
DATA OUT
HIGH IMPEDANCE
MSB
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
76543210
DATA IN
HIGH IMPEDANCE
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION BYTE ADDRESS
DATA OUT
HIGH IMPEDANCE
MSB
76543210
76543210
9th BIT OF ADDRESS
8
11
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
Figure 4-7. WRITE Timing
Figure 4-8. HOLD Timing
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION BYTE ADDRESS DATA IN
HIGH IMPEDANCE
7654321076543210
9th BIT OF ADDRESS
8
H
OLD
SO
SCK
CS
tCD tCD
tHD
tHD
t
LZ
tHZ
12
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
5. Ordering Code Detail
Atmel Designator
Product Family
Device Density
Device Revision
Shipping Carrier Option
Operating Voltage
010 = 1k
020 = 2k
040 = 4k
B or blank = Bulk (tubes)
T = Tape and reel
L = 1.8V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu lead finish,
Industrial Temperature Range
(-40˚C to +85˚C)
U = Green, matte Sn lead finish,
Industrial Temperature range
(-40˚C to +85˚C)
11 = 11mil wafer thickness
Package Option
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
ME = XDFN
C = VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
AT25010B-SSHL-B
13
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
6. Part Markings
AT25010B-SSHL
AT25010B-XHL
AT25010B-CUL
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 51B=AT25010B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 1 B L @
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 51B=AT25010B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
PIN 1 INDICATOR(DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 1 B L @
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: 51B=AT25010B, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=TRACE CODE
|---|---|---|---|
5 1 B U
|---|---|---|---|
Y M X X
|---|---|---|---|
|<-- PIN 1 THIS CORNER
14
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
AT25010B-MAHL
AT25010B-MEHL
AT25020B-SSHL
LINE 1: 51B=AT25010B
LINE 2: H=MATERIAL SET/GRADE, L=1.8 to 5.5V, @=COUNTRY OF ORIGIN
LINE 3: Y=DATE CODE, XX=TRACE CODE
|---|---|---|
5 1 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 51B=AT25010B
LINE 2: Y=DATE CODE, XX=TRACE CODE
|---|---|---|
5 1 B
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 52B=AT25020B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 2 B L @
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
15
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
AT25020B-XHL
AT25020B-CUL
AT25020B-MAHL
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 52B=AT25020B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 2 B L @
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: 52B=AT25020B, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=TRACE CODE
|---|---|---|---|
5 2 B U
|---|---|---|---|
Y M X X
|---|---|---|---|
|<-- PIN 1 THIS CORNER
LINE 1: 52B=AT25020B
LINE 2: H=MATERIAL SET/GRADE, L=1.8 to 5.5V, @=COUNTRY OF ORIGIN
LINE 3: Y=DATE CODE, XX=TRACE CODE
|---|---|---|
5 2 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
16
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
AT25020B-MEHL
AT25040B-SSHL
AT25040B-XHL
LINE 1: 52B=AT25020B
LINE 2: Y=DATE CODE, XX=TRACE CODE
|---|---|---|
5 2 B
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 54B=AT25040B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 4 B L @
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 54B=AT25040B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 4 B L @
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
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8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
AT25040B-CUL
AT25040B-MAHL
AT25040B-MEHL
LINE 1: 54B=AT25040B, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=TRACE CODE
|---|---|---|---|
5 4 B U
|---|---|---|---|
Y M X X
|---|---|---|---|
|<-- PIN 1 THIS CORNER
LINE 1: 54B=AT25040B
LINE 2: H=MATERIAL SET/GRADE, L=1.8 to 5.5V, @=COUNTRY OF ORIGIN
LINE 2: Y=DATE CODE, XX=TRACE CODE
|---|---|---|
5 4 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
PIN 1 INDICATOR (DOT)
LINE 1: 54B=AT25040B
LINE 2: Y=DATE CODE, XX=TRACE CODE
|---|---|---|
5 4 B
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
18
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
7. Ordering Codes
AT25010B Ordering Information(1)
Note: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube).
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel).
3. Contact Atmel Sales for Wafer sales.
Ordering Code Voltage Package Operation Range
AT25010B-SSHL-B(1) (NiPdAu Lead Finish)
AT25010B-SSHL-T(2) (NiPdAu Lead Finish)
AT25010B-XHL-B(1) (NiPdAu Lead Finish)
AT25010B-XHL-T(2) (NiPdAu Lead Finish)
AT25010B-MAHL-T(2) (NiPdAu Lead Finish)
AT25010B-MEHL-T(2) (NiPdAu Lead Finish)
AT25010B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8ME1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(40 to 85C)
AT25010B-WWU11L(3) 1.8V to 5.5V Die Sale Industrial Temperature
(40 to 85C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8ME1 8-lead (1.80x2.20mm body) Extra Thin DFN (XDFN)
8U3-1 8-ball die Ball Grid Array (VFBGA)
19
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
AT25020B Ordering Information(1)
Note: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube).
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel).
3. Contact Atmel Sales for Wafer sales.
Ordering Code Voltage Package Operation Range
AT25020B-SSHL-B(1) (NiPdAu Lead Finish)
AT25020B-SSHL-T(2) (NiPdAu Lead Finish)
AT25020B-XHL-B(1) (NiPdAu Lead Finish)
AT25020B-XHL-T(2) (NiPdAu Lead Finish)
AT25020B-MAHL-T(2) (NiPdAu Lead Finish)
AT25020B-MEHL-T(2) (NiPdAu Lead Finish)
AT25020B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8ME1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(40 to 85C)
AT25020B-WWU11L(3) 1.8V to 5.5V Die Sale Industrial Temperature
(40 to 85C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8ME1 8-lead (1.80x2.20mm body) Extra Thin DFN (XDFN)
8U3-1 8-ball die Ball Grid Array (VFBGA)
20
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
AT25040B Ordering Information
Note: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube).
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel).
3. Contact Atmel Sales for Wafer sales.
Ordering Code Voltage Package Operation Range
AT25040B-SSHL-B(1) (NiPdAu Lead Finish)
AT25040B-SSHL-T(2) (NiPdAu Lead Finish)
AT25040B-XHL-B(1) (NiPdAu Lead Finish)
AT25040B-XHL-T(2) (NiPdAu Lead Finish)
AT25040B-MAHL-T(2) (NiPdAu Lead Finish)
AT25040B-MEHL-T(2) (NiPdAu Lead Finish)
AT25040B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8ME1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(40 to 85C)
AT25040B-WWU11L(3) 1.8V to 5.5V Die Sale Industrial Temperature
(40 to 85C)
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8ME1 8-lead, 1.80mm x 2.20mm Body, Extra Thin DFN (XDFN)
8U3-1 8-ball die Ball Grid Array (VFBGA)
21
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
8. Packaging Information
8S1 – JEDEC SOIC
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
8S1 E
12/11/09
8S1, 8-lead, (0.150” Wide Body),
Plastic Gull Wing Outline (JEDEC SOIC) SWB
–
–
–
–
–
–
–
1.27 BSC
–
–
1.75
0.25
0.51
0.25
5.05
3.99
6.20
1.27
8˚
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.35
0.10
0.31
0.17
4.80
3.81
5.79
0.40
0˚
A
A1
b
C
D
E1
E
e
L
θ
Notes: 1. These drawings are for general information only. Refer
to JEDEC Drawing MS-012, Variation AA for proper
dimensions, tolerances, datums, etc.
E
1234
8765
GND NC NC NC
SDA SCL NC VCC
Ø
C
E1
L
A
b
A1
e
D
End ViewTop View
Side View
22
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
8A2 – TSSOP
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 E
5/19/10
8A2, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
23
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
8MA2 – UDFN
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
8MA2 A
4/15/08
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229 for proper dimensions,
tolerances, datums, etc.
2. The terminal #1 ID is a laser-marked feature.
3. Dimensions b applies to metalized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should not
be measured in that radius area.
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
YNZ
1.40
1.20
0.50
0.00
–
0.30
0.18
0.20
D
E
D2
E2
A
A1
A2
C
L
e
b
K
2.00 BSC
3.00 BSC
1.50
1.30
0.55
0.02
–
0.152 REF
0.35
0.50 BSC
0.25
–
1.60
1.40
0.60
0.05
0.55
0.40
0.30
–
3
C
E
A
A1
A2
Pin 1 ID
D
8
7
6
5
1
2
3
4
D2
E2
e (6x)
L (8x)
b (8x)
Pin#1 ID
(R0.10) 0.35
K
1
2
3
4
8
7
6
5
24
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
8ME1 – XDFN
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
8ME1 A
8/3/09
8ME1, 8-lead (1.80 x 2.20 mm Body)
Extra Thin DFN (XDFN) DTP
–
0.00
1.70
2.10
0.15
0.26
A
A1
D
E
b
e
e1
L
–
–
1.80
2.20
0.20
0.40 TYP
1.20 REF
0.30
0.40
0.05
1.90
2.30
0.25
0.35
Bottom ViewTop View Side View
8 7 6 5
1 2 3 4
D
E
PIN #1 ID
A1
A
PIN #1 ID
e1
b
L
eb
0.10
0.15
25
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
8U3-1 – VFBGA
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE
PO8U3-1 C
9/19/07
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
VFBGA Package (dBGA2)
0.73
0.09
0.40
0.20
A
A1
A2
b
D
E
e
e1
d
d1
0.79
0.14
0.45
0.25
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
0.85
0.19
0.50
0.30 2
Top View
End View
Notes: 1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder
ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu
E
D
PIN 1 BALL PAD CORNER
b
1.
A1
A
A2
8 7 6 5
1 2 3 4
Bottom View
(8 SOLDER BALLS)
PIN 1 BALL PAD CORNER
(d1)
d
(e1)
e
26
8707C–SEEPR–6/11
Atmel AT25010B/020B/040B
9. Revision History
Doc. Rev. Date Comments
8707C 06/2011 Correct AT25040B-SSHL marking detail
Replace 8A2 package drawing with version E
8707B 10/2010 Remove Preliminary
8707B 3/2010 Replace 8Y6 with 8MA2
8707A 2/2010 Initial document release
8707C–SEEPR–6/11
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