Semiconductor
MSC23436C-xxBS10/DS10
4,194, 304- word x 36- bit DY NAMIC RAM MO DULE : FAST PAGE MODE TY P E
This vers ion: Apr. 7. 1999
DESCRIPTION
The MSC23436C-xxBS10/DS10 is a 4,194,304-word x 36-bit CMOS dynamic random access memory module
which is com posed of ei ght 16Mb(4Mx4) DRAMs in SO J packages and two 8Mb(4Mx 2) DRAMs in SOJ packages
m ounted wit h ten decoupl i ng capaci t ors. Thi s i s a 72-pi n singl e in- li ne m em ory m odul e. Thi s modul e supports any
applicat ion where high density and l ar ge c apac ity of stor age memory ar e r equired.
FEATURES
· 4, 194,304-word x 36- bit or ganizat ion
· 72-pin Single In-Li ne M emory M odule
MSC23436C-xxBS10 : Gold tab
MSC23436C-xxDS10 : S older t ab
· Singl e 5V power supply, ±10% tolerance
· I nput : T TL compatible
· Output : TTL compatible, 3-state
· Refresh : 2048cycles/32ms
· / CA S befor e /RAS refr esh, hidden refresh, /RAS only refresh capability
· F ast page mode capability
· Multi-bit t est mode capability
PRODUCT FAMILY
Access Tim e (Max.) Power Di ssi pati on (Max.)
Family tRAC tAA tCAC
Cycle
Time
(Min.) Operating Standby
MSC23436C-60BS10/DS10 60ns 30ns 15ns 110ns 5720mW
MSC23436C-70BS10/DS10 70ns 35ns 20ns 130ns 5225mW 55mW
Semiconductor MSC23436C
MODULE OUTLINE
172
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
φ3.18
25.4±0.2
101.19Typ.
107.95±0.2
*1
3.38Typ.
3.17Min.
5.28Max.
1.27
(U nit : mm)
MSC23436C-xxBS10/DS10
*1 Tolerance over 14.5mm from bottom edge is ±0.5.
Semiconductor MSC23436C
PIN C ONFIGURATI ON
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1V
SS 19 A10 37DQ1755DQ12
2 DQ0 20 DQ4 38DQ3556DQ30
3 DQ1821DQ2239 V
SS 57 DQ13
4 DQ1 22 DQ5 40 /CAS0 58 DQ31
5 DQ1923DQ2341/CAS259 V
CC
6 DQ2 24 DQ6 42 /CAS3 60 DQ32
7 DQ2025DQ2443/CAS161DQ14
8 DQ3 26 DQ7 44 /RAS0 62 DQ33
9 DQ2127DQ2545 NC 63DQ15
10 VCC 28 A7 46 NC 64 DQ34
11 NC 29 NC 47 /WE 65 DQ16
12 A0 30 VCC 48 NC 66 NC
13 A1 31 A8 49 DQ9 67 PD1
14 A2 32 A9 50 DQ27 68 PD2
15 A3 33 NC 51 DQ10 69 PD3
16 A4 34 /RAS2 52 DQ28 70 PD4
17 A5 35 DQ26 53 DQ11 71 NC
18 A6 36 DQ8 54 DQ29 72 VSS
Presence Det ect P ins
Pin No. Pin Name -60 -70
67 PD1 VSS VSS
68 PD2 NC NC
69 PD3 NC VSS
70 PD4 NC NC
Semiconductor MSC23436C
BLOCK DIAGRAM
/WE
A0-A10
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ1
DQ2
/OE
V
CC
/RAS
/CAS1
/WE
V
SS
/CAS2
V
CC
V
SS
C1-C10
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ18
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ19
DQ20
DQ21
V
CC
V
SS
V
CC
V
SS
DQ22
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ23
DQ24
DQ25
V
CC
V
SS
DQ26
A0-A10
DQ1
DQ2
/OE
V
CC
/RAS
/CAS1
/WE
V
SS
DQ35
/CAS2
DQ27
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ28
DQ29
DQ30
V
CC
V
SS
DQ31
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ32
DQ33
DQ34
V
CC
V
SS
/CAS2
/RAS2
/CAS3
Semiconductor MSC23436C
ELECTRICAL CH ARACTERISTI CS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Vol t age on Any Pi n R el at i ve t o V SS VIN, VOUT -0.5 to 7.0 V
Vol tage on VCC Supply Rel ative to VSS VCC -0.5 to 7.0 V
Short Ci rcuit O utput Current IOS 50 mA
Power Dissipation PD *10W
Operating Temperature TOPR 0 t o 70 °C
Storage Temperature TSTG -40 to 125 °C
* Ta = 25°C
Recommen ded O perating Conditions ( Ta = 0°C to 70°C )
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Supply Voltage VSS 000V
Input H i gh Volt age VIH 2.4 - VCC + 0.5 V
Input Low Volt age VIL -0.5 - 0.8 V
Capacitance ( V CC = 5V ±10% , Ta = 25°C, f = 1 M H z )
Parameter Symbol Typ. Max. Unit
Input C apaci t ance (A0 - A10) CIN1 -70pF
Input C apaci t ance (/ W E ) C IN2 -80pF
Input Capaci tance (/RAS0, / R AS2) CIN3 -43pF
Input Capaci tance (/CAS0 - /CAS3) CIN4 -28pF
I/ O Capacitance (DQ0 - DQ 35) CI/O -16pF
Semiconductor MSC23436C
DC Characteristics (VCC = 5V ±10%, Ta = 0°C to 70°C )
-60 -70
Parameter Symbol Condition Min. Max. Min. Max. Unit Note
Output High Volt age VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V
Output Low Voltage VOL IOL = 4.2m A 0 0.4 0 0.4 V
Input Leakage C urrent ILI
0V ≤ VIN ≤ 6.5V;
All other pins not
under test = 0V -100 100 -100 100 µA
Output Leakage Current ILO D Q di sabl e
0V ≤ VOUT ≤ VCC -10 10 -10 10 µA
Average Power
Supply Current
(Operating) ICC1 / R AS, / CAS cycli ng,
tRC = Min. - 1040 - 950 mA 1, 2
/RAS, / C AS = VIH -20-20mA
Power supply current
(Standby) ICC2 /RAS, /CAS
≥ VCC -0.2V -10-10mA
1
Average Power
Supply Current
(/RAS only ref resh) ICC3
/RAS cycli ng,
/CAS = VIH,
tRC = Min. - 1040 - 950 mA 1, 2
Average Power
Supply Current
(/CAS before /R AS refresh) ICC6 /RAS cycling,
/CAS bef ore /R AS - 1040 - 950 mA 1, 2
Average Power
Supply Current
(Fast Page Mode) ICC7
/RAS = VIL,
/CAS cycli ng,
tPC = Min. - 860 - 770 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while /RAS = VIL.
3. The address can be changed once or less while /CAS = VIH.
Semiconductor MSC23436C
AC Characteristics (1/2) (VCC = 5V ±10%, Ta = 0°C to 70°C ) Not e: 1, 2, 3, 9, 10
-60 -70
Parameter Symbol Min. Max. Min. Max. Unit Note
Random R ead or Write C ycl e Time tRC 110 - 130 - ns
Fast Page M ode Cycl e Tim e t PC 40 - 45 - ns
Access Time f rom /RAS tRAC - 60 - 70 ns 4, 5, 6
Access Time f rom /CAS tCAC - 15 - 20 ns 4, 5
Access Time from C ol um n Address tAA - 30 - 35 ns 4, 6
Access Time from / CAS Precharge tCPA - 35 - 40 ns 4
Output Low Im pedance Time from /CAS t CLZ 0-0-ns4
/CAS to Data Output Buffer Turn-off Delay Time tOFF 0 15 0 20 ns 7
Transit i on Tim e tT3 50 3 50 ns 3
Refresh Period tREF -32-32ms
/RAS Precharge Time tRP 40 - 50 - ns
/RAS Pul se W i dt h tRAS 60 10K 70 10K ns
/RAS Pul se W i dth (Fast Page Mode) tRASP 60 100K 70 100K ns
/RAS Hold Time tRSH 15 - 20 - ns
/CAS Precharge Time (Fast Page Mode) tCP 10 - 10 - ns
/CAS Pul se W i dt h tCAS 15 10K 20 10K ns
/CAS Hold Time tCSH 60 - 70 - ns
/CAS t o / RAS Precharge Time tCRP 10 - 10 - ns
/RAS Hold Time from /CAS Precharge tRHCP 35 - 40 - ns
/RAS to /CAS Delay Time tRCD 20 45 20 50 ns 5
/RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6
Row Address Set-up Time tASR 0-0-ns
Row Address Hold Time tRAH 10 - 10 - ns
Colum n Address Set-up Time tASC 0-0-ns
Colum n Address Hol d Time tCAH 15 - 15 - ns
Colum n Address to / R AS Lead Time tRAL 30 - 35 - ns
Read Com m and Set -up Time t RCS 0-0-ns
Read Com m and Hold Tim e tRCH 0-0-ns8
Read Comm and H ol d Time referenced to / R AS tRRH 0-0-ns8
Semiconductor MSC23436C
AC Characteristics (2/2) (VCC = 5V ±10%, Ta = 0°C to 70°C ) Not e: 1, 2, 3, 9, 10
-60 -70
Parameter Symbol Min. Max. Min. Max. Unit Note
Write Com m and Set -up Time tWCS 0-0-ns
Write Com m and H ol d Time tWCH 10 - 15 - ns
Write Com m and Pul se Width tWP 10 - 10 - ns
Write Comm and to /RAS Lead Time tRWL 15 - 20 - ns
Write Comm and to /CAS Lead Time tCWL 15 - 20 - ns
Data-in Set -up Time tDS 0-0-ns
Data-in Hold Time tDH 15 - 15 - ns
/CAS Active Delay Time from /RAS Precharge tRPC 10 - 10 - ns
/RAS t o /C AS Set -up Time (/CAS before /RAS) tCSR 10 - 10 - ns
/RAS t o /C AS Hol d Time (/CAS before /RAS) tCHR 20 - 20 - ns
/W E t o / R AS Precharge Time (/CAS before /RAS) t WRP 10 - 10 - ns
/WE Hold Time from /RAS (/CAS before /RAS) tWRH 10 - 10 - ns
/RAS t o / W E Set-up Time (Test M ode) tWTS 10 - 10 - ns
/RAS t o / W E H ol d Time (Test M ode) tWTH 20 - 20 - ns
Semiconductor MSC23436C
Notes: 1. A start - up delay of 200µs is required after power-up, fol lowed by a minimum of eight initialization cycl es
(/RA S only refr esh or / CA S befor e /RAS refr esh) before pr oper devi c e oper ation is achieved.
2. The AC c har ac teri stics assume tT = 5ns.
3. VIH(Min.) and VIL(Max. ) are refer enc e levels for measuri ng input timing si gnals. Transition times (tT) are
m easured bet ween VIH and VIL.
4. This parameter i s measured wi th a load c ircuit equivalent to 2TT L loads and 100pF.
5. Operation within the tRCD(M ax. ) li mit ensures that t RAC(Max . ) can be met.
tRCD(Max.) is s pecified as a reference point only . If tRCD is greater than the s pecified tRCD(Max.) limit, then
the acc ess ti me is controlled by tCAC.
6. Operation within the tRAD(Max.) li mit ensures that tRAC(Max . ) can be met.
tRAD(Max.) is s pecified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, the n
the acc ess ti me is controlled by tAA.
7. tOFF(Max . ) defi ne t he ti m e at whi ch the out put ac hieves the open ci rc uit condi ti on and is not refer enced
to out put voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 4-bit paral l el t est f uncti on. CA0 and CA1 are not used. In a read cycl e, i f al l i nternal bi ts are equal,
th e DQ pin will ind ic ate a hig h level. I f any in t e r nal b it s ar e not equal, the DQ pin will indicate a low level.
The test m ode i s cleared and t he mem ory dev i ce r eturned t o i ts norm al operating stat e by a / RAS onl y
refresh or /CAS bef ore /RAS ref resh cycle.
10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the abov e value to the specified
value in this data sheet.