2015 Microchip Technology Inc. DS20005449A-page 1
HV2802/HV2902
Features
32-Channel SPST (Single-Pole, Single-Throw)
High-Voltage Analog Switch
3.3V or 5.0V CMOS Input Logic Level
20 MHz Data Shift Clock Frequency
High-Voltage CMOS (HVCMOS) Technology for
High Performance
Very Low Quiescent Power Dissipation (10 µA)
Low Parasitic Capacitance
DC to 50 MHz Analog Signal Frequency
-60 dB Typical OFF-Isolation at 5.0 MHz
CMOS Logic Circuitry for Low Power
Excellent Noise Immunity
Cascadable Serial Data Register with Latches
Flexible Operating Supply Voltages
Integrated Bleed Resistors on the Outputs
(HV2902 only)
Applications
Medical Ultrasound Imaging
Non-Destructive Testing (NDT) Metal Flaw
Detection
Piezoelectric Transducer Drivers
Inkjet Printer Heads
Optical MEMS Modules
General Description
The HV2802 and HV2902 are low-charge injection,
32-channel, high-voltage analog switches intended for
use in applications requiring high-voltage switching
controlled by low-voltage control signals, such as
medical ultrasound imaging, driving piezoelectric
transducers and printers. The HV2902 has integrated
bleed resistors which eliminate voltage build-up on
capacitive loads such as piezoelectric transducers.
Input data are shifted into a 32-bit shift register that can
then be retained in a 32-bit latch. To reduce any
possible clock feedthrough noise, the latch enable bar
should be left high until all bits are clocked in. Data are
clocked in during the rising edge of the clock. Using the
HVCMOS technology, this device combines
high-voltage bilateral DMOS switches and low-power
CMOS logic to provide efficient control of high-voltage
analog signals.
The device is suitable for various combinations of
high-voltage supplies, e.g., VPP/VNN: +40V/-160V,
+100V/-100V and +160V/-40V.
Package Type
*
See
Section 2.0 “Package Pin Configurations and
Fun c tions Desc ription”
HV2802/HV2902
9x9x1.0 mm VFBGA*
Top View
13121110987654321
A
B
C
D
E
F
G
H
J
K
L
M
N
Low Harmonic Distortion, 32-Channel SPST,
High-Voltage Analog Switch
HV2802/HV2902
DS20005449A-page 2 2015 Microchip Technology Inc.
Block Diagram
Level
Shifters
VPP
VNN
Latches
CLRLE
CLK
DIN
GND
VDD
Output
Switches
DOUT
SW0A
SW0B
SW1A
SW1B
SW2A
SW2B
SW30A
SW30B
SW31A
SW31B
D
LE
CLR
32-Bit
Shift
Register
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
Bleed
Resistors
RGND
HV2902 only
2015 Microchip Technology Inc. DS20005449A-page 3
HV2802/HV2902
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
VDD Logic Supply Voltage .......................................................................................................................... -0.5V to +6.5V
VPP-VNN Differential Supply ......................................................................................................................................220V
VPP Positive Supply ...........................................................................................................................-0.5V to VNN +200V
VNN Negative Supply ................................................................................................................................ +0.5V to -200V
Logic Input Voltage..............................................................................................................................-0.5V to VDD +0.3V
Analog Signal Range .......................................................................................................................................VNN to VPP
Peak Analog Signal Current/Channel ........................................................................................................................3.0A
Power Dissipation .................................................................................................................................................... 1.5W
†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Note 1 3)
Parameter Symbol Value
Logic Power Supply Voltage VDD +3.0V to +5.5V
Positive Voltage Supply VPP +40V to VNN+200V
Negative Voltage Supply VNN -40V to -160V
High-Level Input Voltage VIH 0.9VDD to VDD
Low-Level Input Voltage VIL 0V to 0.1VDD
Analog Signal Voltage Peak-to-Peak VSIG VNN +10V to VPP -10V
Note 1: Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2: VSIG must be VNN VSIG VPP or floating during power up/down transition.
3: Rise and fall times of power supplies VDD, VPP
, and VNN should not be less than 1.0 ms.
HV2802/HV2902
DS20005449A-page 4 2015 Microchip Technology Inc.
DC ELECTRIC AL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, VDD = 5.0V, VPP = +100V, VNN = -100V, Specification at 0°C
and 70°C based on characterization and not 100% tested.
Parameters Symbol 0°C +25°C +70°C Units Conditions
Min. Max. Min. Typ. Max. Min. Max.
Small Signal Switch
ON-Resistance
RONS —30—2638—48 ISIG =5.0mA,
VPP =+40V, V
NN = -160V
—25—2227—32 I
SIG = 200 mA,
VPP =+40V, V
NN = -160V
—25—2227—30 I
SIG =5.0mA,
VPP =+100V, V
NN = -100V
—18—1824—27 I
SIG = 200 mA,
VPP =+100V, V
NN = -100V
—23—2025—30 I
SIG =5.0mA,
VPP =+160V, V
NN = -40V
—22—1625—27 I
SIG = 200 mA,
VPP =+160V, V
NN = -40V
Small Signal Switch
ON-Resistance
Matching
RONS —20— 5 20—20 %I
SIG =5.0mA,
VPP =+100V, V
NN = -100V
Large Signal Switch
ON-Resistance
(
Note 1)
RONL ———15——— VSIG =V
PP -10V, ISIG =1A
Value of Output Bleed
Resistor
RINT 20 35 50 kOutput switch to RGND
IRINT =0.5mA
Switch off Leakage
per Switch
ISOL —5—11015µAV
SIG =V
PP -10V, VNN +10V
Switch DC Offset
VOS 300 100 300 300 mV Switch OFF,
RLOAD = 100 kfor HV2802
No load for HV2902
500 100 500 500 Switch ON
RLOAD = 100 kfor HV2802
No load for HV2902
Quiescent V
PP
Supply
Current
IPPQ 10 50 µA All switches off
Quiescent V
NN
Supply
Current
INNQ ——1050——
Quiescent V
PP
Supply
Current
IPPQ 10 50 µA All switches on,
ISW =5.0mA
Quiescent V
NN
Supply
Current
INNQ ——1050——
Switch Output Peak
Current (
Note 1)
ISW —— 2 3 ——— AV
SIG duty cycle < 0.1%
Output Switching
Frequency (
Note 1)
fSW ————50——kHzDuty cycle=50%
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Design guidance only.
2015 Microchip Technology Inc. DS20005449A-page 5
HV2802/HV2902
Average V
PP
Supply
Current
IPP —14——14—14mA
V
PP
= +40V, V
NN
= -160V
All output switches are turning
on and off at 50 kHz with no load
—14——14—14
V
PP
= +100V, V
NN
= -100V
All output switches are turning
on and off at 50 kHz with no load
—14——14—14
V
PP
= +160V, V
NN
= -40V
All output switches are turning
on and off at 50 kHz with no load
Average
V
NN
Supply
Current
INN —14——14—14mA
V
PP
= +40V, V
NN
= -160V
All output switches are turning
on and off at 50 kHz with no load
—14——14—14
V
PP
= +100V, V
NN
= -100V
All output switches are turning
on and off at 50 kHz with no load
—14——14—14
V
PP
= +160V, V
NN
= -40V
All output switches are turning
on and off at 50 kHz with no load
Average V
DD
Supply
Current
I
DD
—8—8—8mA
f
CLK
=5.0MHz, V
DD
=5.0V
Quiescent V
DD
Supply Current
I
DDQ
—10——10—1A
All logic inputs are static
Data Out Source
Current
I
SOR
0.45 0.45 0.70 0.40 mA
V
OUT
=V
DD
-0.7V
Data Out Sink Current
I
SINK
0.45 0.45 0.70 0.40 mA
V
OUT
=0.7V
Logic Input
Capacitance (Note 2)CIN —10——10—10pF
DC ELECTRICAL CHARACTERISTICS (CONTINUE D)
Electrical Specifications: Unless otherwise specified, VDD = 5.0V, VPP = +100V, VNN = -100V, Specification at 0°C
and 70°C based on characterization and not 100% tested.
Parameters Symbol 0°C +25°C +70°C Units Conditions
Min. Max. Min. Typ. Max. Min. Max.
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Design guidance only.
HV2802/HV2902
DS20005449A-page 6 2015 Microchip Technology Inc.
AC ELECTRIC AL CHARACTERISTICS
Electrical S pecifications: Unless otherwise specified, VDD =5.0V, V
PP = +100V, VNN = -100V, Specification at 0°C and
70°C based on characterization and not 100% tested.
Parameters Symbol 0°C +25°C +70°C Units Conditions
Min. Max. Min. Typ. Max. Min. Max.
Set Up Time Before LE Rises
(Note 1)
tSD 25—25——25— ns
Time Width of LE (Note 1)t
WLE 56—56——56— nsV
DD =3.0V
12—12——12— V
DD =5.0V
Clock Delay Time to Data Out
(Note 1)
tDO 84081940840nsV
DD =3.0V
83081530830 V
DD =5.0V
Time Width of CLR (Note 1)t
WCLR 55—55——55— ns
Set Up Time Data to Clock
(Note 1)
tSU 21—21——21— nsV
DD =3.0V
7—7—7— V
DD =5.0V
Hold Time Data from Clock
(Note 1)
tH5—5—5—nsV
DD =3.0V
7—7—7— V
DD =5.0V
Clock Frequency fCLK —8——8—8MHzV
DD =3.0V
—20——20—20 V
DD =5.0V
Clock Rise and Fall Times tR, tF—50——50—50ns
Turn ON Time tON —5——5—5µsV
SIG = VPP -10V,
RLOAD = 10 k
Turn OFF Time tOFF —5——5—5
Maximum VSIG Slew Rate
(Note 1)
dv/dt 20 V/ns
V
PP
= +40V, V
NN
= -160V
————20——
V
PP
= +100V, V
NN
= -100V
————20——
V
PP
= +160V, V
NN
= -40V
OFF Isolation (Note 1)K
O———-33-30——dBf=5.0MHz,
1.0 kǁ15 pF load
———-60-58—— f=5.0MHz,
50 load
Switch Crosstalk (Note 1)K
CR -70 -60 dB f = 5.0 MHz,
50 load
Output Switch Isolation Diode
Current (Note 1)
IID 300 mA 300 ns pulse width,
2.0% duty cycle
Off Capacitance SW to GND
(Note 1)
C
SG(OFF)
10 15 pF 0V, f = 1.0 MHz
On Capacitance SW to GND
(Note 1)
C
SG(ON)
———1318——
Output Voltage Spike SWA,
SWB (Note 1)
+VSPK ————
+150
——mV
V
PP
= +40V, V
NN
= -160V
R
LOAD
= 50
-VSPK ——
-150
————
+VSPK ————
+150
——
V
PP
= +100V, V
NN
= -100V
R
LOAD
= 50
-VSPK ——
-150
————
+VSPK ————
+150
——
V
PP
= +160V, V
NN
= -40V
R
LOAD
= 50
-VSPK ——
-150
————
Charge Injection
(per switch) (Note 1)
QC ———820———pC
V
PP
= +40V, V
NN
= -160V
———600———
V
PP
= +100V, V
NN
= -100V
———350———
V
PP
= +160V, V
NN
= -40V
Note 1: Specification is obtained by characterization and is not 100% tested.
2015 Microchip Technology Inc. DS20005449A-page 7
HV2802/HV2902
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature TA0—+70°C
Storage Temperature TA-65 +150 °C
Package Thermal Resistance
Thermal Resistance, 78-Ball VFBGA JA —32.2—°C/W
HV2802/HV2902
DS20005449A-page 8 2015 Microchip Technology Inc.
1.1 Logic Timing and Truth Table
FIGURE 1-1: Logic Timing Waveforms.
TABLE 1-1: TRUTH TABLE (Notes 1 6)
D0 D1 ••• D15 D16 •• D31 LE CLR SW0 SW1 ••• SW15 SW16 ••• SW31
L—
•••
——
•••
—L LOFF
•••
——
•••
H— L LON
—L —L L—OFF
—H L LON
——LL————
——LL————
L— —L L— OFF
—— H L L —— ON
—— L L L —— OFF
—— H L L —— ON
——LL————
——LL————
——LL————
——LL————
—— L L L —— —— OFF
—— H L L —— ON
X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X H ALL SWITCHES OFF
Legend: X = Do not care; L = Low; H = High.
Note 1: The 32 switches operate independently.
2: Serial data is clocked in on the L to H transition of the CLK.
3: All 32 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the
shift register’s data flow through the latch.
4: DOUT is high when data in register 31 is high.
5: Shift register’s clocking has no effect on the switch states if LE is high.
6: The CLR clear input overrides all other inputs.
50%
DNDN-1
DN+1
50%
50%50%
50%
50%
50% 50%
10%
50%
10%
DATA
IN
LE
CLOCK
DATA
OUT
OFF
ON
CLR
VOUT
(typical)
tWCL
tOFF
tWLE
tSU
tON
tDO
th
tSD
50%
2015 Microchip Technology Inc. DS20005449A-page 9
HV2802/HV2902
2.0 PACKAGE PIN CONFIGURATIONS
AND FUNCTIONS DESCRIPTION
This section details the pin designation for the 78-Ball
VFBGA package (Figure 2-1). The descriptions of the
pins are listed in Ta b l e 2 - 1 .
FIGURE 2-1: 78-Ball VFBGA Package - Top View.
12 34 56 78 910111213
A
B
C
D
E
F
G
H
J
K
L
M
N
SW2B
SW3A
SW4A
SW5A
SW6A
SW7A
SW8A
SW9A
SW10A
SW11A
SW12A
SW13A SW12B
SW8B
SW24B
SW25B SW26A
SW27ASW26B
SW28A
SW29A
SW29B
SW28B
SW27B
SW30A
SW30BSW31B
SW31A
CLRCLKDIN
SW1A SW0A
VDD LE
GNDDOUT
SW0BSW1B
SW11B
SW10B
SW9B
SW2A
SW3B
SW7B
SW6B
SW5B
SW4B
SW25A
SW24A
SW23B
SW22B
SW18B
VNN
VPP
SW17BSW16BSW15BSW14BSW13B VNN VPP
SW14A SW15A SW16A SW17A SW18A SW19A
SW19B SW20A
SW21ASW20B
SW22A
SW21B
SW23A
NC
RGND
NC
RGND
NC
RGND
Note: On pins B6, M10 and N5 the NC pin is available for
HV2802 only, while RGND pin is available for HV2902.
HV2802/HV2902
DS20005449A-page 10 2015 Microchip Technology Inc.
TABLE 2-1: PIN FUNCTION TABLE
Pin
Number
Symbol Description
9x9x1.0 VFBGA
HV2802 HV2902
A1 SW2B SW2B Analog switch 2 terminal B
A3 SW1B SW1B Analog switch 1 terminal B
A4 SW0B SW0B Analog switch 0 terminal B
A5 DOUT DOUT Data out logic output
A6 GND GND Ground
A7 VDD VDD Logic supply voltage
A8 LE LE Latch enable logic input, low active
A10 SW31A SW31A Analog switch 31 terminal A
A11 SW30A SW30A Analog switch 30 terminal A
A13 SW29B SW29B Analog switch 29 terminal B
B1 SW3A SW3A Analog switch 3 terminal A
B2 SW2A SW2A Analog switch 2 terminal A
B4 SW1A SW1A Analog switch 1 terminal A
B5 SW0A SW0A Analog switch 0 terminal A
B6 NC RGND No connect / Ground for bleed resistor
B7 DIN DIN Data in logic input
B8 CLK CLK Clock logic input for shift register
B9 CLR CLR Latch clear logic input
B10 SW31B SW31B Analog switch 31 terminal B
B11 SW30B SW30B Analog switch 30 terminal B
B12 SW28B SW28B Analog switch 28 terminal B
B13 SW29A SW29A Analog switch 29 terminal A
C1 SW4A SW4A Analog switch 4 terminal A
C2 SW3B SW3B Analog switch 3 terminal B
C12 SW27B SW27B Analog switch 27 terminal B
C13 SW28A SW28A Analog switch 28 terminal A
D1 SW5A SW5A Analog switch 5 terminal A
D2 SW4B SW4B Analog switch 4 terminal B
D12 SW26B SW26B Analog switch 26 terminal B
D13 SW27A SW27A Analog switch 27 terminal A
E1 SW6A SW6A Analog switch 6 terminal A
E2 SW5B SW5B Analog switch 5 terminal B
E12 SW25B SW25B Analog switch 25 terminal B
E13 SW26A SW26A Analog switch 26 terminal A
F1 SW7A SW7A Analog switch 7 terminal A
F2 SW6B SW6B Analog switch 6 terminal B
F12 SW24B SW24B Analog switch 24 terminal B
F13 SW25A SW25A Analog switch 25 terminal A
G1 SW8A SW8A Analog switch 8 terminal A
G2 SW7B SW7B Analog switch 7 terminal B
G12 SW23B SW23B Analog switch 23 terminal B
G13 SW24A SW24A Analog switch 24 terminal A
2015 Microchip Technology Inc. DS20005449A-page 11
HV2802/HV2902
H1 SW9A SW9A Analog switch 9 terminal A
H2 SW8B SW8B Analog switch 8 terminal B
H12 SW22B SW22B Analog switch 22 terminal B
H13 SW23A SW23A Analog switch 23 terminal A
J1 SW10A SW10A Analog switch 10 terminal A
J2 SW9B SW9B Analog switch 9 terminal B
J12 SW21B SW21B Analog switch 21 terminal B
J13 SW22A SW22A Analog switch 22 terminal A
K1 SW11A SW11A Analog switch 11 terminal A
K2 SW10B SW10B Analog switch 10 terminal B
K12 SW20B SW20B Analog switch 20 terminal B
K13 SW21A SW21A Analog switch 21 terminal A
L1 SW12A SW12A Analog switch 12 terminal A
L2 SW11B SW11B Analog switch 11 terminal B
L12 SW19B SW19B Analog switch 19 terminal B
L13 SW20A SW20A Analog switch 20 terminal A
M1 SW13A SW13A Analog switch 13 terminal A
M2 SW12B SW12B Analog switch 12 terminal B
M6 SW14A SW14A Analog switch 14 terminal A
M7 SW15A SW15A Analog switch 15 terminal A
M8 SW16A SW16A Analog switch 16 terminal A
M9 SW17A SW17A Analog switch 17 terminal A
M10 NC RGND No connect/Ground for bleed resistor
M12 SW18A SW18A Analog switch 18 terminal A
M13 SW19A SW19A Analog switch 19 terminal A
N1 SW13B SW13B Analog switch 13 terminal B
N2 VNN VNN Negative supply voltage
N4 VPP VPP Positive supply voltage
N5 NC RGND No connect/Ground for bleed resistor
N6 SW14B SW14B Analog switch 14 terminal B
N7 SW15B SW15B Analog switch 15 terminal B
N8 SW16B SW16B Analog switch 16 terminal B
N9 SW17B SW17B Analog switch 17 terminal B
N10 VPP VPP Positive supply voltage
N12 VNN VNN Negative supply voltage
N13 SW18B SW18B Analog switch 18 terminal B
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin
Number
Symbol Description
9x9x1.0 VFBGA
HV2802 HV2902
HV2802/HV2902
DS20005449A-page 12 2015 Microchip Technology Inc.
3.0 TE ST CIRCUIT EXAMPLES
This section details test circuit examples for a few electrical characteristics. The RGND pins are found only on the
HV2902 device. The Switch DC Offset of HV2802 needs 100 k external load.
FIGURE 3-1:
Switch Off Leakage per Switch.
FIGURE 3-2: Switch DC Offset.
FIGURE 3-3: TON/TOFF Test Circuit.
FIGURE 3-4: Off Isolation.
FIGURE 3-5: Output Switch Isolation
Diode Current.
FIGURE 3-6: Switch Crosstalk.
RGND* Open
5.0V
VPP
VNN
VDD
Open
GND
VNN
VPP
VPP-10V
ISOL
RGND*
VPP
VPP
VNN
VNN
VDD
GND
5.0V
VOUT
RLOAD
100k
(HV2802 only)
VPP
VPP
VNN
VNN
VDD
GND
5.0V
VPP-10V
RLOAD
VOUT
10k
RGND*
VPP
VPP
VNN
VNN
VDD
GND
5.0V
RLOAD
VOUT
VIN =10V
P-P
@5 MHz
Ko20LogVOUT
VIN
----------------=
RGND*
VPP
VPP
VNN
VNN
VDD
GND
5.0V
VNN
VSIG
IID
RGND*
VPP
VPP
VNN
VNN
VDD
GND
5.0V
50
50
VIN =10V
P-P
@5 MHz
NC
KCR 20LogVOUT
VIN
----------------=
RGND*
VOUT
2015 Microchip Technology Inc. DS20005449A-page 13
HV2802/HV2902
FIGURE 3-7: Charge Injection.
FIGURE 3-8: Output Voltage Spike.
VOUT
VOUT
1000pF
VSIG
VPP
VPP
VNN
VNN
VDD
GND
5.0V
Q 1000pF
VOUT
=
RGND*
RLOAD
50
1kRGND*
VPP
VNN
VNN
VDD
GND
5.0
V
VPP
+VSPK
-VSPK
VOUT
HV2802/HV2902
DS20005449A-page 14 2015 Microchip Technology Inc.
4.0 DETAILED DESCRIPTION AND
APPLICATION INFORMATION
The high-voltage analog switches are used for
multiplexing a piezoelectric transducer array in a probe
to multiple channel transmitters (Tx) arrays in a medical
ultrasound system.
Figure 4-1 shows a typical medical ultrasound image
system comprising 64-channels of transmit pulsers,
64-channels of receivers (LNA and ADC) and
64-channels of T/R switches connecting to 192
elements of an ultrasound transducer probe via a
high-voltage analog switch array.
FIGURE 4-1: Typical Med ical Ultrasou nd Imag ing Sys tem .
The HV2802/HV2902 devices are comprised of two
main circuitries:
A low-power CMOS digital serial interface
powered by VDD to control the high-voltage
analog switches
High-voltage bilateral analog switch.
High-voltage supplies VPP and VNN are needed by the
high-voltage level translation circuitry to control the
states of the output high-voltage analog switches. In
addition, each high-voltage analog switch can be
independently controlled because each switch is
controlled via a corresponding latch. A 32-bit shift
register and 32 latches allow the user to serially load
data into the registers, and after completion, to load the
data onto the latches that control the states of the
high-voltage analog switches.
The HV2802/HV2902 have a digital serial interface
consisting of logic signals, Data In (DIN), Clock (CLK),
Data Out (DOUT), Latch Enable (LE) and Clear (CLR).
The digital circuits are supplied by VDD and either a
3.3V or a 5V logic can be used. With a VDD = 5V supply,
the serial clock frequency can operate up to 20 MHz.
The data is shifted into the shift registers on the rising
edge (low-to-high transition) of the clock. The switch
configuration bit of SW31 is shifted in first and the
switch configuration bit of SW0 is shifted in last. To
avoid clock feedthrough, the latch enable input (LE)
should remain high while the 32-bit data-in signal is
shifted into the 32-bit register. After the valid 32-bit data
complete shifting into the shift registers, the high-to-low
transition of the LE signal transfers the contents of the
shift register into the latches. Finally, setting the LE high
again allows all the latches to keep the current state,
while new data can now be shifted into the shift
registers without upsetting the latches.
It is recommended to change all the latch states at the
same time through this method to avoid possible clock
feedthrough noise. See Figure 4-2 for details.
ADC
ADC
ADC
FPGA Ctrl Logic
VIDEO CPU MEMORY
Tx
Rx
T/R
Switch
T/R
Switch Rx
Tx
Tx
Rx
T/R
Switch
CH64
CH2
CH1
PZT Array
HV 2XXX SW Array
Tx / Rx Array
E1
E65
E192
E128
E129
E2
E66
E130
E64
2015 Microchip Technology Inc. DS20005449A-page 15
HV2802/HV2902
FIGURE 4-2: Latch Enable Timing Waveforms.
When the CLR input is set high, all 32 latches are
cleared of the data. Consequently, all the high-voltage
switches are set to off state. However, the CLR signal
does not affect the contents of the shift register, so the
shift register can operate independently of the CLR
signal. Hence, after the CLR input is set low, the shift
register would still retain the previous data.
The serial input interface of the HV2802/HV2902
allows multiple devices to daisy-chain together. In this
configuration, DOUT of a HV2802/HV2902 device is
connected to the DIN of the subsequent device, and so
forth. The last DOUT of the daisy-chained
HV2802/HV2902 can either be floating or fed back to
an FPGA to check the previously stored shift register
data. To control all the high-voltage analog switch
states in daisy-chained N devices, N times 32 clocks
and N times 32 bits of data are shifted into shift
registers, while LE remains high and CLR remains low.
After all N times 32 bits of data finish shifting in, the
high-to-low transition of the LE transfers the data from
all N times 32-bit shift registers to N times 32 latches
simultaneously. Consequently, all N times 32
high-voltage analog switches change states
simultaneously.
It is recommended that 0.1 uF ceramic decoupling
capacitors, with the appropriate voltage ratings, be
connected between GND and the other supplies (VDD,
VPP and VNN). These decoupling capacitors should be
placed as close as possible to the device.
The HV2802/HV2902 devices do not have a specific
power up/down sequence. During the power up/down
period, all the analog switch inputs should be within the
VPP and VNN range or floating. The rise time and fall
time of the power supplies, VDD, VPP and VNN, should
be greater than 1 ms. Violating the rise time or fall time
requirement on the power supplies may cause
malfunction such as latch-up or even permanent
damage of the device.
The HV2902 device has 35 k integrated bleed
resisters connected from all the analog switch
terminals A and B to RGND. These bleed resisters
eliminate voltage build-up on capacitive loads such as
piezoelectric transducers. The HV2802 device does
not have integrated bleed resistors.
DIN
LE
CLK
tWLE
tSD
tH
tSU
tDO
DOUT
DN31 DN30 DN29 DN1DN0
DN-131 DN-130 DN-129 DN-11DN-10DN31
*The previous data input in the shift register are shifted out
HV2802/HV2902
DS20005449A-page 16 2015 Microchip Technology Inc.
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
78-Ball VFBGA (9x9x1.0) Example
HV2802GA
1520256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015 Microchip Technology Inc. DS20005449A-page 17
HV2802/HV2902
A
0.10 C
0.10 C
C
SEATING
PLANE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Microchip Technology Drawing C04-371A Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
A3
A
e
D1
D/4
D
E/4
E
B
DETAIL A
78-Ball Very Thin Fine Pitch Ball Grid Array (5G) - 9x9x1.0 mm Body [VFBGA]
SEE DETAIL B
E1
HV2802/HV2902
DS20005449A-page 18 2015 Microchip Technology Inc.
Microchip Technology Drawing C04-371A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C
NX Øb
Ø0.15 C A B
Ø0.05 C
SOLDER BALL
DETAIL A
A1
0.10 C
0.08 C
DETAIL A
Number of Pins
Overall Height
Ball Diameter
Overall Width
Overall Length
Overall Ball Pitch
Overall Ball Pitch
Molded Cap Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
Øb
D
E1
D1
A3
e
E
N
0.65 BSC
0.50
0.25
-
0.15
0.30
9.00 BSC
7.80 BSC
7.80 BSC
-
0.20
9.00 BSC
MILLIMETERS
MIN NOM
78
0.35
1.00
0.25
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
0.45 0.55
78-Ball Very Thin Fine Pitch Ball Grid Array (5G) - 9x9x1.0 mm Body [VFBGA]
2015 Microchip Technology Inc. DS20005449A-page 19
HV2802/HV2902
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
Contact Pad Diameter (X78)
Contact Pitch
MILLIMETERS
0.65 BSC
MIN
E1
MAX
0.25
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2371A
NOM
C1
C2
E2
E1
Contact Pad Spacing
ØX
Contact Pitch 0.65 BSCE2
C2Contact Pad Spacing 7.80
X
C1Contact Pad Spacing 780
78-Ball Very Thin Fine Pitch Ball Grid Array (5G) - 9x9x1.0 mm Body [VFBGA]
HV2802/HV2902
DS20005449A-page 20 2015 Microchip Technology Inc.
NOTES:
2015 Microchip Technology Inc. DS20005449A-page 21
HV2802/HV2902
APPENDIX A: REVISION HISTORY
Revision A (October 2015)
Original release of this document.
HV2802/HV2902
DS20005449A-page 22 2015 Microchip Technology Inc.
NOTES:
2015 Microchip Technology Inc. DS20005449A-page 23
HV2802/HV2902
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX-X
Package
Device
Device HV2802: 32-Channel SPST, High-Voltage Analog Switch
HV2902: 32-Channel SPST, High-Voltage Analog Switch
with Bleed Resistors
Package GA-G = Very Thin Fine Pitch Ball Grid Array (5G) -
9x9x1.0 mm (VFBGA), 78-Ball
Examples:
a)
HV2802GA-G:
78-Ball VFBGA package
b)
HV2902GA-G:
78-Ball VFBGA package
HV2802/HV2902
DS20005449A-page 24 2015 Microchip Technology Inc.
NOTES:
2015 Microchip Technology Inc. DS20005449A-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-907-6
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005449A-page 26 2015 Microchip Technology Inc.
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