FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2001-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.3
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90495G Series
MB90497G/F497G/F498G/V495G
■DESCRIPTION
The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed for devices
like consumer electronics, which require high-speed, real-time process control. This series features an on-chip
full-CAN interface.
In addition to being backwards compatible with the F2MC* family architecture, the instruction set has been ex-
panded to add support for high-lev el language instructions, expanded addressing mode, and enhanced m ultiply/
divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long
word (32-bit) data.
The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit
PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller.
* : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■FEATURES
•Models that support operating temperature (TA) +125 °C
•Clock
•Built-in PLL clock multiplier circuit
•Choose 1/2 oscillation clock or ×1 to ×4 m ultiplied oscillation clock (f or a 4-MHz oscillation clock, 4 to 16 MHz)
machine (PLL) clock (Continued)
DS07-13713-6E
MB90495G Series
2DS07-13713-6E
(Continued)
•Select subclock behavior (8.192 kHz)
•Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and × 4 PLL clock)
• 16-Mbyte CPU memory space
•24-bit internal addressing
•External access possible through selection of 8/16-bit bus width (external bus mode)
• Optimum instruction set for controller applications
•Wealth of data types (Bit, Byte, Word, Long Word)
•Wealth of addressing modes (23 different modes)
•Enhanced signed multiply-divide instructions and RETI instruction functions
•Enhanced high-precision arithmetic employing 32-bit accumulator
• Instruction set supports high-level programming language (C) and multitasking
•Employs system stack pointer
•Enhanced indirect instructions with all pointer types
•Barrel shift instructions
• Improved execution speed
•4-byte instruction queue
• Powerful interrupt feature
•Powerful 8-level, 34-condition interrupt feature
• CPU-independent automated data forwarding
•Extended intelligent I/O service feature (EI2OS) : maximum 16 channels
• Low-power consumption (Standby) Mode
•Sleep mode (CPU operation clock stopped)
•Time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational)
•Watch mode (subclock and watch timer only operational)
•Stop mode (oscillation clock and subclock stopped)
•CPU intermittent operation mode
• Process
•CMOS technology
• I/O Ports
•Generic I/O ports (CMOS output) : 49
•Timer
•Time-base timer, watch timer, watchdog timer : 1 channel
•8/16-bit PPG timer : four 8-bit channels, or two 16-bit channels
•16-bit reload timer : 2 channels
•16-bit I/O timer
•16-bit free-run timer : 1 channel
•16-bit input capture (ICU) : 4 channels
Generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input
edge detection (Continued)
MB90495G Series
DS07-13713-6E 3
(Continued)
•CAN Controller : 1 channel
•CAN specifications conform to versions 2.0A and 2.0B
•8 on-chip message buffers
•Forwarding rate 10 kbps to 1 Mbps (with 16-MHz machine clock)
• UART0 (SCI) /UART1 (SCI) : 2 channels
•All with full duplex double buffer
•Use clock-asynchronous or clock-synchronous serial forwarding
• DTP/external interrupt : 8 channels
•A module for launching extended intelligent I/O service (EI2OS) and generating external interrupts through
external output
• Delayed interrupt generation module
•Generates interrupt requests for switching tasks
• 8/10-bit A/D converter : 8 channels
•Switch between 8-bit and 10-bit resolution
•Launch through external trigger input
•Conversion time : 6.13 μs (with 16-MHz machine clock, including sampling time)
• Program batch function
•2-address pointer ROM correction
• Clock output function
MB90495G Series
4DS07-13713-6E
■PRODUCT LINEUP
* : The S2 dipswitch setting when using the MB2145-507 emulation baud. For details, see the MB2145-507
hardware manual (2.7 Emulator Power Pin) . (Continued)
Parameter Part Number MB90F497G MB90497G MB90F498G MB90V495G
Feature Classification Flash ROM Mask ROM Flash ROM Product Evaluated
ROM Size 64 Kbytes 128 Kbytes ⎯
RAM Size 2 Kbytes 6 Kbytes
Process CMOS
Package LQFP64 (pin pitch 0.65 mm) , QFP64 (pin pitch 1.00 mm) PGA256
Operating Power 4.5 V to 5.5 V
Emulator power supply* ⎯None
CPU Functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
: 351
: 8-bit, 16-bit
: 1 to 7 bytes
: 1 bit, 8-bit, 16-bit
Minimum execution time : 62.5 ns (with 16-MHz machine clock)
Interrupt processing time : minimum 1.5 μs (with 16-MHz machine clock)
Low-power consumption
(Standby) Mode Sleep mode/watch mode/time-base timer mode/stop mode / CPU intermittent
mode
I/O Ports General-purpose I/O ports (CMOS output) : 49
Time-base timer 18-bit free-run counter
Interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms
(with 4-MHz oscillation clock)
Watchdog timer Reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(with 4-MHz oscillation clock)
16-bit
I/O Timer
16-bit
free-run timer Number of channels : 1
Interrupts from overflow generation
Input capture Number of channels : 4
Maintenance of free-run timer value through pin input (rising, falling or both edg-
es)
16-bit reload timer
Number of channels : 2
16-bit reload timer operation
Count clock interval : 0.25 μs, 0.5 μs, 2.0 μs
(with 16-MHz machine clock)
External event count enabled
Watch timer 15-bit free-run counter
Interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s
(with 8.192-kHz subclock)
8/16-bit PPG timer
Number of channels : 2 (two 8-bit channels can be used)
Two 8-bit or one 16-bit channel PPG operation possible
Free interval, free duty pulse output possible
Count clock : 62.5 ns to 1 μs (with 16-MHz machine clock)
MB90495G Series
DS07-13713-6E 5
(Continued)
■PACKAGES AND CORRESPONDING PRODUCTS
: available × : not available
Note : See “■ PACKAGE DIMENSIONS” for details.
■PRODUCT COMPARISON
Memory Size
When evaluating with evaluation chips and other means, take careful note of the different between the evaluation
chip and the chip actually used. Take particular note of the following.
• While the MB90V495G does not feature an on-chip ROM, the dedicated development tool can be used to
achieve operation equivalent to a product with built-in ROM. Therefore, the ROM size is configured by the
development tool.
• On the MB90V495G, the FF4000H to FFFFFFH image is only visible in the 00 bank, and the FE0000H to
FF3FFFH is only visible in the FE and FF banks (configurable on development tool) .
• On the MB90F497G/F498G/497G, the FF4000H to FFFFFFH image is visible in the 00 bank, and the FF0000H
to FF3FFFH is visible only in the FF bank.
Parameter Part Number MB90F497G MB90497G MB90F498G MB90V495G
Delayed interrupt generation
module Module for delayed interrupt generation switching tasks
Used in real-time OS
DTP/external interrupt circuit Number of inputs : 8
Starting by rising edge, falling edge, “H” level input, or “L” level input, external
interrupts or extended intelligent I/O service (EI2OS) can be used
8/10-bit A/D converter
Number of channels : 8
Resolution : set 10-bit or 8-bit
Conversion time : 6.13 μs (with 16-MHz machine clock, including sampling time)
Continuous conversion of multiple linked channels possible
(up to 8 channels can be set)
One-shot conversion mode : converts selected channel only once
Continuous conversion mode : converts selected channel continuously
Stop conversion mode : converts selected channel and suspends operation
repeatedly
UART0 (SCI)
Number of channels : 1
Clock-synchronous forwarding : 62.5 kbps to 2 Mbps
Clock-asynchronous forwarding : 1,202 bps to 62,500 bps
Transmission can be performed by two-way serial transmission or by master/
slave connection
UART1 (SCI)
Number of channels : 1
Clock-synchronous forwarding : 62.5 kbps to 2 Mbps
Clock-asynchronous forwarding : 9,615 bps to 500 kbps
Transmission can be performed by two-way serial transmission or by master/
slave connection
CAN Compliant with CAN specification versions 2.0A and 2.0B
Send/receive message buffers : 8
Forwarding bit rate : 10 kbps to 1 Mbps (with 16-MHz machine clock)
Package MB90F497G MB90497G MB90F498G
FPT-64P-M06
FPT-64P-M23
MB90495G Series
6DS07-13713-6E
■PIN ASSIGNMENTS
(TOP VIEW)
(FPT-64P-M06)
P44/RX
P61/INT1
P62/INT2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
X0A
X1A
P63/INT3
MD0
51
42
33
P30/SOT0/ALE
VSS
P27/INT7/A23
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOT1/A19
P22/TIN1/A18
P21/TOT0/A17
P20/TIN0/A16
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12/IN2/AD10
P11/IN1/AD09
P10/IN0/AD08
P07/AD07
1
10
19
52
58
64
P31/SCK0/RD
P32/SIN0/WRL
P33/WRH
P34/HRQ
P35/HAK
VCC
C
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOT1
P43/TX
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VSS
X1
X0
MD2
MD1
RST
32
26
20
QFP-64P
MB90495G Series
DS07-13713-6E 7
(TOP VIEW)
(FPT-64P-M23)
P61/INT1
P62/INT2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
X0A
X1A
48
40
33
P27/INT7/A23
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOT1/A19
P22/TIN1/A18
P21/TOT0/A17
P20/TIN0/A16
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12/IN2/AD10
P11/IN1/AD09
P10/IN0/AD08
1
8
16
49
57
64
VSS
P30/SOT0/ALE
P31/SCK0/RD
P32/SIN0/WRL
P33/WRH
P34/HRQ
P35/HAK
VCC
C
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOT1
P43/TX
P44/RX
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VSS
X1
X0
MD2
MD1
RST
MD0
P63/INT3
32
24
17
LQFP-64P
MB90495G Series
8DS07-13713-6E
■PIN DESCRIPTION
(Continued)
Pin No. Pin Name Circuit
Type Description
QFP-
64P *1 LQFP-
64P *2
21 P61 DGeneral-purpose I/O port
INT1 Functions as external interrupt input pin. Set this to input port.
32 P62 DGeneral-purpose I/O port
INT2 Functions as external interrupt input pin. Set this to input port.
4 to 11 3 to 10 P50 to P57 EGeneral-purpose I/O port
AN0 to
AN7 Functions as analog input port of A/D converter. This is enabled if analog
input configuration is permitted.
12 11 AVCC ⎯VCC power input pin of A/D converter.
13 12 AVR ⎯Reference voltage (+) input pin for the A/D converter.This voltage must
not exceed VCC and AVCC. Reference voltage (−) is fixed to AVSS.
14 13 AVSS ⎯VSS power input pin of A/D converter.
15 14 P60 DGeneral-purpose I/O port
INT0 Functions as external interrupt input pin. Set this to input port.
16 15 X0A A Low-speed oscillation pin.
Perform pull-down processing if not connected to an oscillator.
17 16 X1A A Low-speed oscillation pin.
Set to open if not connected to an oscillator.
18 17 P63 DGeneral-purpose I/O port
INT3 Functions as external interrupt input pin. Set this to input port.
19 18 MD0 C Input pin for specifying operation mode.
20 19 RST B External reset input pin.
21 20 MD1 C Input pin for specifying operation mode.
22 21 MD2 F Input pin for specifying operation mode.
23 22 X0 A High-speed oscillation pin.
24 23 X1 A High-speed oscillation pin.
25 24 VSS ⎯Power supply (0 V) input pin.
26 to
33 25 to
32
P00 to P07 D
General-purpose I/O port
Only enabled in single-chip mode.
AD00 to
AD07 I/O pin for the lower 8-bit of the external address data bus.
Only enabled during external bus mode.
34 to
37 33 to
36
P10 to P13
D
General-purpose I/O port. Only enabled in single-chip mode.
IN0 to IN3 Functions as trigger input pin for input capture channels ch.0 to ch.3. Set
this to input port.
AD08 to
AD11 I/O pin for upper 4-bit of external address data bus.
Only enabled during external bus mode.
MB90495G Series
DS07-13713-6E 9
(Continued)
(Continued)
Pin No. Pin Name Circuit
Type Description
QFP-
64P *1 LQFP-
64P *2
38 to
41 37 to
40
P14 to P17
D
General-purpose I/O port.
Only enabled in single-chip mode.
PPG0 to
PPG3 Functions as output pin of PPG timer 0/1, 2/3. Only valid if output config-
uration is enabled.
AD12 to
AD15 I/O pin for upper 4-bit of external address data bus.
Only enabled during external bus mode.
42 41
P20
D
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in ex-
ternal bus mode, these pins function as general purpose I/O ports.
TIN0 Functions as event input pin of TIN0 reload timer 0.
Set this to input port.
A16 Output pin of external address bus (A16) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
43 42
P21
D
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in ex-
ternal bus mode, these pins function as general purpose I/O ports.
TOT0 Functions as event output pin of TOT0 reload timer 0.
Only valid if output configuration enabled.
A17 Output pin of external address bus (A17) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
44 43
P22
D
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in ex-
ternal bus mode, these pins function as general purpose I/O ports.
TIN1 Functions as event input pin of TIN1 reload timer 1.
Set this to input port.
A18 Output pin of external address bus (A18) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
45 44
P23
D
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in ex-
ternal bus mode, these pins function as general purpose I/O ports.
TOT1 Functions as event output pin for TOT1 reload timer 1.
Only valid if output configuration enabled.
A19 Output pin for external address bus (A19) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
MB90495G Series
10 DS07-13713-6E
(Continued)
(Continued)
Pin No. Pin Name Circuit
Type Description
QFP-
64P *1 LQFP-
64P *2
46 to
49 45 to
48
P24 to P27
D
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in ex-
ternal bus mode, these pins function as general purpose I/O ports.
INT4 to INT7 Functions as external interrupt input pin. Set this to input port.
A20 to A23 Output pin for external address bus (A20 to A23) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
50 49 VSS ⎯Power supply (0 V) input pin.
51 50
P30
D
General-purpose I/O port.
Only enabled in single-chip mode.
SOT0 UART0 serial data output pin.
Only valid if UART0 serial data output configuration is enabled.
ALE Address latch authorization output pin.
Only enabled during external bus mode.
52 51
P31
D
General-purpose I/O port.
Only enabled in single-chip mode.
SCK0 UART0 serial clock I/O pin.
Only valid if UART0 serial clock I/O configuration is enabled.
RD Lead strobe output pin.
Only enabled during external bus mode.
53 52
P32
D
General-purpose I/O port.
SIN0 UART0 serial data input pin.
Set this to input port.
WRL Write strobe output pin for lower 8-bit of data bus.
Only valid if WRL pin output is enabled, in external bus mode.
54 53 P33 DGeneral-purpose I/O port.
WRH Write strobe output pin for upper 8-bit of data bus.
Only valid if external bus mode/16-bit bus mode/WRH pin output enabled.
55 54 P34 DGeneral-purpose I/O port.
HRQ Hold request input pin.
Only valid if hold input is enabled, in external bus mode.
56 55 P35 DGeneral-purpose I/O port.
HAK Hold addressing output pin.
Only valid if hold input is enabled, in external bus mode.
57 56 VCC ⎯Power supply (5 V) input pin.
58 57 C ⎯Capacity pin for power stabilization.
Please connect to an approximately 0.1 μF ceramic capacitor.
MB90495G Series
DS07-13713-6E 11
(Continued)
*1 : FPT-64P-M06
*2 : FPT-64P-M23
Pin No. Pin Name Circuit
Type Description
QFP-
64P *1 LQFP-
64P *2
59 58
P36
D
General-purpose I/O port.
FRCK Functions as an external clock input pin for a FRCK 16-bit free-run timer.
Set this to input port.
RDY External ready input pin.
Only valid if external ready input is enabled, in external bus mode.
60 59
P37
D
General-purpose I/O port.
ADTG Functions as A/D converter external trigger input pin. Set this to input port.
CLK External clock output pin.
Only valid if external clock output is enabled, in external bus mode.
61 60 P40 DGeneral-purpose I/O port.
SIN1 UART1 serial data input pin.
Set this to input port.
62 61 P41 DGeneral-purpose I/O port.
SCK1 UART1 serial clock I/O pin.
Only valid if UART1 clock I/O configuration is enabled.
63 62 P42 DGeneral-purpose I/O port.
SOT1 UART1 serial data output pin.
Only valid if UART1 serial data output configuration is enabled.
64 63 P43 DGeneral-purpose I/O port.
TX CAN transmission output pin.
Only valid if output configuration enabled.
164 P44 DGeneral-purpose I/O port.
RX CAN reception input pin.
Set this to input port.
MB90495G Series
12 DS07-13713-6E
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A • High speed oscillation feedback
resistor : 1 MΩ approx.
• Low speed oscillation feedback
resistor : 10 MΩ approx.
B • Hysteresis input with pull-up
• Pull-up Resistor : 50 kΩ approx.
C Hysteresis input
D • CMOS hysteresis input
• CMOS level output
• Standby control available
E • CMOS hysteresis input
• CMOS level output
• Doubles as analog input pin
• Standby control available
X1 Clock input
Standby control signal
X0
X1A
X0A
R
R
V
CC
Hysteresis input
RHysteresis input
R
VCC
P-ch
N-ch
VSS
IOL = 4 mA
Digital output
Digital output
Hysteresis input
Standby control
R
VCC
P-ch
N-ch
VSS
IOL = 4 mA
Digital output
Digital output
Hysteresis input
Standby control
Analog input
MB90495G Series
DS07-13713-6E 13
(Continued)
Type Circuit Remarks
F • Hysteresis input with pull-down
• Pull-down Resistor : 50 kΩ approx.
(except Flash device)
R
R
V
SS
Hysteresis input
MB90495G Series
14 DS07-13713-6E
■HANDLING DEVICES
• Make sure you do not exceed the maximum rated values (in order to prevent latch-up) .
• CMOS IC chips may suffer latch-up if a voltage higher than VCC or lower than VSS is applied to an input or
output pin with other than mid or high current resistance; or voltage exceeding the rating is applied across VCC
and VSS pins.
• Latch-ups can dramatically increase the power supply current, causing thermal breakdown of the device.
Make sure that you do not exceed the maximum rated v a lue of your device, in order to prevent a latch-up.
• When turning the analog po wer supply on or off, mak e sure that the analog po w er v oltage (AVCC, AVR) and
analog input voltages do not exceed the digital voltage (VCC) .
• Handling Unused Pins
Leaving unused input/output pins open may cause malfunctions and latch-ups, permanently damaging the
de vice. Pre v ent this b y connecting it to a pull-up or pull-do wn resistor of no less than 2 kΩ. Lea v e unused input/
output pins open in output mode, or if in input mode, handle them in the same as input pins.
• Notes on Using External Clock
When using the external clock, drive pin X0 only, and leave pin X1 unconnected. See below for an example of
external clock use.
Example External Clock Use
• Notes on Not Using Subclock
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
• Power Supply Pins
• If your product has m ultiple VCC or VSS pins, pins of the same potential are internally connected in the de vice
in order to av oid abnormal operation, including latch-up. However, you should make sure to connect the pins’
external power and ground lines, in order to lower unneeded emissions, prevent abnormal operation of strobe
signals due to a rise in ground levels, and maintain total output current within rated levels.
• Take care to connect the VCC and VSS pins of MB90495G Series devices to power lines via the lowest possible
impedance.
• It is recommended that you connect a bypass capacitor of approximately 0.1 μF between VCC and VSS pins near
MB90495G Series device pins.
• Crystal Oscillator Circuit
• Noise in the vicinity of X0 and X1 pins could cause abnormal operations in MB90495G Series devices. Mak e
sure to provide b ypass capacitors via the shortest possib le distance from X0 and X1 pins, crystal oscillators
(or ceramic resonators) , and ground lines. In addition, design your printed circuit boards so as to keep X0
and X1 wiring from crossing other wiring, if at all possible.
• It is strongly recommended that you pro vide printed circuit board artwork surrounding X0 and X1 pins within
a grand area, as this should stabilize operation.
X0
X1
Open MB90495G Series
MB90495G Series
DS07-13713-6E 15
• A/D Converter Power-up and Analog Input Initiation Sequence
• Make sure to power up the A/D converter and analog input (pins AN0 to AN7) after turning on digital pow er
(VCC) .
• Turn off digital power after turning off the A/D conv erter pow er supply and analog inputs. In this case, mak e
sure that the voltage of AVR does not exceed AVCC (it is permissible to turn off analog and digital power
simultaneously) .
• Connecting Unused A/D Converter Pins
If you are not using the A/D converter, set unused pins to AVCC = AVR = VCC, AVSS = VSS.
• Notes for Powering Up
Ensure that the voltage step-up time (between 0.2 V and 2.7 V) at power-up is no less than 50 μs, in order to
prevent malfunction in the built-in step-down circuit.
• Initialization
The device contains built-in registers which are only initialized by a power-on reset. Cycle the power supply to
initialize these registers.
• Stabilizing the Power Supply
Make sure that the VCC power supply voltage is stable. Even at the rated operating VCC power supply voltage,
large, sudden changes in the voltage could cause malfunctions. As a standard for stable power supply, keep
VCC ripples (peak-to-peak value) at commercial power frequencies (50 Hz / 60 Hz) to no more than 10% of the
power supply voltage, and momentary surges caused by switching the power supply and other events to more
than 0.1 V/ms.
• If Output from Ports 0/1 Becomes Undefined
After pow er is turned on, if the RST pin is set to “H” during step-down circuit stabilization standby (during power-
on reset) , por ts 0 and 1 output will be undefined. If the RST pin is set to “L”, por ts 0 and 1 will go into a high
impedance state. Take careful note of the timing of events outlined in figures 1 and 2.
MB90495G Series
16 DS07-13713-6E
•Figure 1 - Timing Chart of Undefined Output from Ports 0/1 (with RST pin set to “H”)
•Figure 2 - Timing Chart of High Impedance State for Ports 0/1 (when RST pin is “L”)
V
CC
(power supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Time in standby for oscillation to stabilize
*
2
Time in standby for step-
down circuit to stabilize
*
1
Time of undefined output
*1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 8.19 ms)
*2 : Oscillation stabilization standby time : 218/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 16.38 ms)
VCC (power supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Time in standby for oscillation to stabilize*2
Step-down circuit
stabilization standby time*1
High impedance
*1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 8.19 ms)
*2 : Oscillation stabilization standby time : 218/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 16.38 ms)
MB90495G Series
DS07-13713-6E 17
• Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to contin ue the operation using the free-
running frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
• Support for TA = + 125 °C
If used exceeding TA = +105 °C, be sure to contact us for reliability limitations.
MB90495G Series
18 DS07-13713-6E
■BLOCK DIAGRAM
RAM
ROM/Flash
CAN
UART1
UART0
X0, X1
RST
X0A, X1A
SOT1
SCK1
SIN1
SOT0
SCK0
SIN0
AVCC
AVSS
AN0 to AN7
AVR
ADTG
FRCK
IN0 to IN3
RX
TX
PPG0 to PPG3
INT0 to INT7
TIN0, TIN1
T OT0, T O T1
AD00 to AD15
A16 to A23
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
Clock
control circuit
Watch timer
Time-base timer
Prescaler
Prescaler
8/10-bit
A/D converter
(8 ch)
CPU
F2MC-16LX
Core
16-bit
free-run timer
Internal data bus
Input
capture
(4 ch)
16-bit
PPG timer
(2 ch)
DTP/external
interrupt circuit
16-bits
reload timer
(2 ch)
External bus
MB90495G Series
DS07-13713-6E 19
■MEMORY MAP
The memor y access modes of the MB90495G Ser ies can be set to single chip mode, internal ROM - external
bus mode, and external ROM - external bus mode.
1. Memory Allocation of the MB90495G
The MB90495G Series has 24-bit inter nal address bus and 24-bit external address bus output, enabling it to
access up to 16 Mbytes of external access memory . The enable/disable time of the ROM mirror function is shown
graphically in the memory map.
2. Memory Map
Note : When the internal R OM is operational, the R OM data in the upper address of bank 00 of the F2MC-16LX is
visible in an image. This is called the ROM mirror function, and takes advantage of the small C compiler model.
With the F2MC-16LX, the lower 16-bit address of bank FF and the lower 16-bit address of bank 00 are set
identical to one another . This allows the ROM-internal table to be ref erenced without specifying a far pointer .
F or e xample, sa y the address “00C000H” is accessed. In actuality, the “FFC000H ” address inside ROM will
be accessed. However, as the ROM space in bank FF exceeds 48 Kbytes, the entire space cannot be viewed
on bank 00’s image. And so, since “FF4000H” to “FFFFFFH” ROM data will be visible on the “004000H” to
“00FFFFH” image, save the ROM data table in the “FF4000H” to “FFFFFFH” space.
Address #3
000000H
0000C0H
000100H
003900H
010000H
FFFFFFH
Single chip mode
(ROM mirror function available)
Periphery Periphery Periphery
RAM space
Register RAM space
Register RAM space
Register
Extention
IO space Extention
IO space Extention
IO space
ROM space
(image of
bank FF)
ROM space
(image of
bank FF)
ROM space ROM space
Internal ROM
External bus mode External ROM
External bus mode
Address #1
Address #2
Internal access memory
External access memory
Access prohibited
003800H
002000H
* : Addresses #1 and #3 are product-specific.
Product Address #1*Address #2 Address #3*
MB90V495G 001900H004000H (FC0000H)
MB90F497G 000900H004000HFF0000H
MB90497G 000900H004000HFF0000H
MB90F498G 000900H004000HFE0000H
MB90495G Series
20 DS07-13713-6E
■I/O MAP
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
000000HPDR0 Port 0 data register R/W Port 0 XXXXXXXXB
000001HPDR1 Port 1 data register R/W Port 1 XXXXXXXXB
000002HPDR2 Port 2 data register R/W Port 2 XXXXXXXXB
000003HPDR3 Port 3 data register R/W Port 3 XXXXXXXXB
000004HPDR4 Port 4 data register R/W Port 4 XXXXXXXXB
000005HPDR5 Port 5 data register R/W Port 5 XXXXXXXXB
000006HPDR6 Port 6 data register R/W Port 6 XXXXXXXXB
000007H
to
00000FH (system-reserved area) *
000010HDDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0B
000011HDDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0B
000012HDDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0B
000013HDDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0B
000014HDDR4 Port 4 direction register R/W Port 4 XXX 0 0 0 0 0B
000015HDDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0B
000016HDDR6 Port 6 direction register R/W Port 6 XXXX 0 0 0 0B
000017H
to
00001AH
(system-reserved area) *
00001BHADER Analog input enable register R/W 8/10-bit
A/D converter 1 1 1 1 1 1 1 1B
00001CH
to
00001FH (system-reserved area) *
000020HSMR0 Serial mode register 0 R/W
UART0
0 0 0 0 0 0 0 0B
000021HSCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0B
000022HSIDR0/
SODR0 Serial input data register 0/
Serial output data register 0 R/W XXXXXXXXB
000023HSSR0 Serial status register 0 R/W 0 0 0 0 1 X 0 0B
000024HCDCR0 Communication prescaler control
register 0 R/W 0 XXX 1 1 1 1B
000025HSES0 Serial edge selection register 0 R/W XXXXXXX 0B
000026HSMR1 Serial mode register 1 R/W
UART1
0 0 0 0 0 0 0 0B
000027HSCR1 Serial control register 1 R/W 0 0 0 0 0 1 0 0B
000028HSIDR1/
SODR1 Serial input data register 1/
Serial output data register 1 R/W XXXXXXXXB
MB90495G Series
DS07-13713-6E 21
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
000029HSSR1 Serial status register 1 R/W UART1 0 0 0 0 1 0 0 0B
00002AH (system-reserved area) *
00002BHCDCR1 Communication prescaler control
register 1 R/W UART1 0 XXX 0 0 0 0B
00002CH
to
00002FH (system-reserved area) *
000030HENIR DTP/external interrupt enable register R/W
DTP/external
interrupt
0 0 0 0 0 0 0 0B
000031HEIRR DTP/external interrupt condition
register R/W XXXXXXXXB
000032HELVR Detection level configuration register R/W 0 0 0 0 0 0 0 0B
000033HR/W 0 0 0 0 0 0 0 0B
000034HADCS A/D control status register R/W
8/10-bit
A/D converter
0 0 0 0 0 0 0 0B
000035HR/W 0 0 0 0 0 0 0 0B
000036HADCR A/D data register R XXXXXXXXB
000037HR/W 0 0 1 0 1 XXXB
000038H
to
00003FH
(system-reserved area) *
000040HPPGC0 PPG0 operation mode control register R/W 8/16-bit
PPG timer 0/1
0 X 0 0 0 XX 1B
000041HPPGC1 PPG1 operation mode control register R/W 0 X 0 0 0 0 0 1B
000042HPPG01 PPG0/1 count clock selection register R/W 0 0 0 0 0 0 XXB
000043H (system-reserved area) *
000044HPPGC2 PPG2 operation mode control register R/W 8/16-bit
PPG timer 2/3
0 X 0 0 0 XX 1B
000045HPPGC3 PPG3 operation mode control register R/W 0 X 0 0 0 0 0 1B
000046HPPG23 PPG2/3 count clock selection register R/W 0 0 0 0 0 0 XXB
000047H
to
00004FH (system-reserved area) *
000050HIPCP0 Input capture data register 0 R
16-bit I/O timer
XXXXXXXXB
000051HXXXXXXXXB
000052HIPCP1 Input capture data register 1 R XXXXXXXXB
000053HXXXXXXXXB
000054HICS01 Input capture control status register R/W 0 0 0 0 0 0 0 0B
000055HICS23 0 0 0 0 0 0 0 0B
000056HTCDT Timer counter data register R/W 0 0 0 0 0 0 0 0B
000057H0 0 0 0 0 0 0 0B
MB90495G Series
22 DS07-13713-6E
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
000058HTCCS Timer counter control status register R/W
16-bit I/O timer
0 0 0 0 0 0 0 0B
000059H0 XXXXXXXB
00005AHIPCP2 Input capture data register 2 R XXXXXXXXB
00005BHXXXXXXXXB
00005CHIPCP3 Input capture data register 3 R XXXXXXXXB
00005DHXXXXXXXXB
00005EH
to
000065H (system-reserved area) *
000066HTMCSR0 Timer control status register
R/W 16-bit reload timer 0 0 0 0 0 0 0 0 0B
000067HR/W XXXX0 0 0 0B
000068HTMCSR1 R/W 16-bit reload timer 1 0 0 0 0 0 0 0 0B
000069HR/W XXXX0 0 0 0B
00006AH
to
00006EH (system-reserved area) *
00006FHROMM ROM mirror function selection register W ROM mirror function
selection module XXXXXXX 1B
000070H
to
00007FH (system-reserved area) *
000080HBVALR Message buffer valid register R/W CAN controller 0 0 0 0 0 0 0 0B
000081H (system-reserved area) *
000082HTREQR Send request register R/W CAN controller 0 0 0 0 0 0 0 0B
000083H (system-reserved area) *
000084HTCANR Send cancel register W CAN controller 0 0 0 0 0 0 0 0B
000085H (system-reserved area) *
000086HTCR Send complete register R/W CAN controller 0 0 0 0 0 0 0 0B
000087H (system-reserved area) *
000088HRCR Reception complete register R/W CAN controller 0 0 0 0 0 0 0 0B
000089H (system-reserved area) *
00008AHRRTRR Reception RTR register R/W CAN controller 0 0 0 0 0 0 0 0B
00008BH (system-reserved area) *
00008CHROVRR Reception overrun register R/W CAN controller 0 0 0 0 0 0 0 0B
00008DH (system-reserved area) *
00008EHRIER Reception complete interrupt enable
register R/W CAN controller 0 0 0 0 0 0 0 0B
MB90495G Series
DS07-13713-6E 23
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
00008FH
to
00009DH (system-reserved area) *
00009EHPACSR Address detection control register R/W ROM correction
function 0 0 0 0 0 0 0 0B
00009FHDIRR Delayed interrupt request generate/
cancel register R/W Delayed interrupt
generation module XXXXXXX 0B
0000A0HLPMCR Low power consumption mode control
register R/W Low-power
consumption modes 0 0 0 1 1 0 0 0B
0000A1HCKSCR Clock selection register R/W Clock 1 1 1 1 1 1 0 0B
0000A2H
to
0000A4H (system-reserved area) *
0000A5HARSR Auto ready function selection register W
External access
0 0 1 1 XX 0 0B
0000A6HHACR High address control register W 0 0 0 0 0 0 0 0B
0000A7HECSR Bus control signal selection register W 0 0 0 0 0 0 0 XB
or
0 0 0 0 1 0 0 XB
0000A8HWDTC Watchdog timer control register R/W Watchdog timer XXXXX 1 1 1B
0000A9HTBTC Time-base timer control register R/W Time-base timer 1 XX 0 0 1 0 0B
0000AAHWTC Watch timer control register R/W Watch timer 1 X 0 0 1 0 0 0B
0000ABH
to
0000ADH (system-reserved area) *
0000AEHFMCS Flash memory control status register R/W 512-Kbit
flash memory 0 0 0 X 0 0 0 0B
0000AFH (system-reserved area) *
0000B0HICR00 Interrupt control register 00 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
0000B1HICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1B
0000B2HICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1B
0000B3HICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1B
0000B4HICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1B
0000B5HICR05 Interrupt control register 05 R/W 0 0 0 0 0 1 1 1B
0000B6HICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1B
0000B7HICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1B
0000B8HICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1B
0000B9HICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1B
0000BAHICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1B
MB90495G Series
24 DS07-13713-6E
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
0000BBHICR11 Interrupt control register 11 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
0000BCHICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1B
0000BDHICR13 Interrupt control register 13 R/W 0 0 0 0 0 1 1 1B
0000BEHICR14 Interrupt control register 14 R/W 0 0 0 0 0 1 1 1B
0000BFHICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1B
0000C0H
to
0000FFH
(system-reserved area) *
001FF0H
PADR0
Detection address configuration
register 0 (lower) R/W
ROM correction
function
XXXXXXXXB
001FF1HDetection address configuration
register 0 (mid) R/W XXXXXXXXB
001FF2HDetection address configuration
register 0 (upper) R/W XXXXXXXXB
001FF3H
PADR1
Detection address configuration
register 1 (lower) R/W XXXXXXXXB
001FF4HDetection address configuration
register 1 (mid) R/W XXXXXXXXB
001FF5HDetection address configuration
register 1 (upper) R/W XXXXXXXXB
003900HTMR0/
TMRLR0 16-bit timer register 0/
16-bit reload register 0 R/W 16-bit reload timer 0 XXXXXXXXB
003901HXXXXXXXXB
003902HTMR1/
TMRLR1 16-bit timer register 1/
16-bit reload register 1 R/W 16-bit reload timer 1 XXXXXXXXB
003903HXXXXXXXXB
003904H
to
00390FH
(system-reserved area) *
003910HPRLL0 PPG0 reload register L R/W
8/16-bit PPG timer
XXXXXXXXB
003911HPRLH0 PPG0 reload register H R/W XXXXXXXXB
003912HPRLL1 PPG1 reload register L R/W XXXXXXXXB
003913HPRLH1 PPG1 reload register H R/W XXXXXXXXB
003914HPRLL2 PPG2 reload register L R/W XXXXXXXXB
003915HPRLH2 PPG2 reload register H R/W XXXXXXXXB
003916HPRLL3 PPG3 reload register L R/W XXXXXXXXB
003917HPRLH3 PPG3 reload register H R/W XXXXXXXXB
003918H
to
003BFFH
(system-reserved area) *
003C00H
to
003C0FH
RAM (general-purpose RAM)
MB90495G Series
DS07-13713-6E 25
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
003C10H
to
003C13HIDR0 ID register 0 R/W
CAN controller
XXXXXXXXB
to
XXXXXXXXB
003C14H
to
003C17HIDR1 ID register 1 R/W XXXXXXXXB
to
XXXXXXXXB
003C18H
to
003C1BHIDR2 ID register 2 R/W XXXXXXXXB
to
XXXXXXXXB
003C1CH
to
003C1FHIDR3 ID register 3 R/W XXXXXXXXB
to
XXXXXXXXB
003C20H
to
003C23HIDR4 ID register 4 R/W XXXXXXXXB
to
XXXXXXXXB
003C24H
to
003C27HIDR5 ID register 5 R/W XXXXXXXXB
to
XXXXXXXXB
003C28H
to
003C2BHIDR6 ID register 6 R/W XXXXXXXXB
to
XXXXXXXXB
003C2CH
to
003C2FHIDR7 ID register 7 R/W XXXXXXXXB
to
XXXXXXXXB
003C30H,
003C31HDLCR0 DLC register 0 R/W XXXXXXXXB
XXXXXXXXB
003C32H,
003C33HDLCR1 DLC register 1 R/W XXXXXXXXB
XXXXXXXXB
003C34H,
003C35HDLCR2 DLC register 2 R/W XXXXXXXXB
XXXXXXXXB
003C36H,
003C37HDLCR3 DLC register 3 R/W XXXXXXXXB
XXXXXXXXB
003C38H,
003C39HDLCR4 DLC register 4 R/W XXXXXXXXB
XXXXXXXXB
003C3AH,
003C3BHDLCR5 DLC register 5 R/W XXXXXXXXB
XXXXXXXXB
003C3CH,
003C3DHDLCR6 DLC register 6 R/W XXXXXXXXB
XXXXXXXXB
003C3EH,
003C3FHDLCR7 DLC register 7 R/W XXXXXXXXB
XXXXXXXXB
003C40H
to
003C47HDTR0 Data register 0 R/W XXXXXXXXB
to
XXXXXXXXB
MB90495G Series
26 DS07-13713-6E
(Continued)
Address Register
Abbreviation Register Name Access Resource Name Initial Value
003C48H
to
003C4FHDTR1 Data register 1 R/W
CAN controller
XXXXXXXXB
to
XXXXXXXXB
003C50H
to
003C57HDTR2 Data register 2 R/W XXXXXXXXB
to
XXXXXXXXB
003C58H
to
003C5FHDTR3 Data register 3 R/W XXXXXXXXB
to
XXXXXXXXB
003C60H
to
003C67HDTR4 Data register 4 R/W XXXXXXXXB
to
XXXXXXXXB
003C68H
to
003C6FHDTR5 Data register 5 R/W XXXXXXXXB
to
XXXXXXXXB
003C70H
to
003C77HDTR6 Data register 6 R/W XXXXXXXXB
to
XXXXXXXXB
003C78H
to
003C7FHDTR7 Data register 7 R/W XXXXXXXXB
to
XXXXXXXXB
003C80H
to
003CFFH
(system-reserved area) *
003D00H,
003D01HCSR Control status register R/W CAN controller 0 XXXX 0 0 1B
0 0 XXX 0 0 0B
003D02HLEIR Display last event register R/W 0 0 0 XX 0 0 0B
003D03H (system-reserved area) *
003D04H,
003D05HRTEC Receive/transmit error counter R
CAN controller
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
003D06H,
003D07HBTR Bit timing register R/W 1 1 1 1 1 1 1 1B
X 1 1 1 1 1 1 1B
003D08HIDER IDE register R/W XXXXXXXXB
003D09H (system-reserved area) *
003D0AHTRTRR Transmit RTR register R/W CAN controller 0 0 0 0 0 0 0 0B
003D0BH (system-reserved area) *
003D0CHRFWTR Remote frame reception standby
register R/W CAN controller XXXXXXXXB
003D0DH (system-reserved area) *
003D0EHTIER Transmit complete interrupt enable
register R/W CAN controller 0 0 0 0 0 0 0 0B
MB90495G Series
DS07-13713-6E 27
(Continued)
Explanation of reset values
0 : The reset value of this bit is 0.
1 : The reset value of this bit is 1.
X : The reset value of this bit is undefined.
* : System-reserved area contains system-internal addresses, and cannot be used.
Address Register
Abbreviation Register Name Access Resource Name Initial Value
003D0FH (system-reserved area) *
003D10H,
003D11HAMSR Acceptance mask selection register R/W CAN controller XXXXXXXXB
XXXXXXXXB
003D12H,
003D13H (system-reserved area) *
003D14H
to
003D17HAMR0 Acceptance mask register 0 R/W
CAN controller
XXXXXXXXB
to
XXXXXXXXB
003D18H
to
003D1BHAMR1 Acceptance mask register 1 R/W XXXXXXXXB
to
XXXXXXXXB
003D1CH
to
003FFFH (system-reserved area) *
MB90495G Series
28 DS07-13713-6E
■INTERRUPT CONDITIONS AND INTERRUPT VECTOR/REGISTER
(Continued)
Interrupt Condition EI2OS
Compatible Interrupt Vector Interrupt Register Priority
*3
Number Address ICR Address
Reset ×#08 08HFFFFDCH⎯⎯Highest
INT 9 instruction ×#09 09HFFFFD8H⎯⎯ ↑
Exception processing ×#10 0AHFFFFD4H⎯⎯
Can controller reception complete (RX) ×#11 0BHFFFFD0HICR00 0000B0H (*1)
Can controller reception complete
(
TX
) /
Node status transition (NS) ×#12 0CHFFFFCCH
Reserved ×#13 0DHFFFFC8HICR01 0000B1H
Reserved ×#14 0EHFFFFC4H
External interrupt (INT0/INT1) #15 0FHFFFFC0HICR02 0000B2H (*1)
Time-base timer ×#16 10HFFFFBCH
16-bit reload timer 0 #17 11HFFFFB8HICR03 0000B3H (*1)
8/10-bit A/D converter #18 12HFFFFB4H
16-bit free-run timer overflow #19 13HFFFFB0HICR04 0000B4H (*1)
External interrupt (INT2/INT3) #20 14HFFFFACH
Reserved ×#21 15HFFFFA8HICR05 0000B5H (*2)
PPG timer ch.0, ch.1 underflow ×#22 16HFFFFA4H
Input capture 0 load #23 17HFFFFA0HICR06 0000B6H (*1)
External interrupt (INT4/INT5) #24 18HFFFF9CH
Input capture 1 load #25 19HFFFF98HICR07 0000B7H (*1)
PPG timer ch.2, ch.3 underflow ×#26 1AHFFFF94H
External interrupt (INT6/INT7) #27 1BHFFFF90HICR08 0000B8H (*1)
Watch timer #28 1CHFFFF8CH
Reserved ×#29 1DHFFFF88HICR09 0000B9H (*1)
Input capture 2 load
Input capture 3 load ×#30 1EHFFFF84H
Reserved ×#31 1FHFFFF80HICR10 0000BAH (*1)
Reserved ×#32 20HFFFF7CH
Reserved ×#33 21HFFFF78HICR11 0000BBH (*1)
Reserved ×#34 22HFFFF74H
Reserved ×#35 23HFFFF70HICR12 0000BCH (*1)
16-bit reload timer 1 #36 24HFFFF6CH
UART1 reception complete #37 25HFFFF68HICR13 0000BDH (*1)
UART1 transmission complete #38 26HFFFF64H
MB90495G Series
DS07-13713-6E 29
(Continued)
: Available
× : Not available
: Available, EI2OS halt function supplied
: Available for interrupt conditions not shared by ICR
*1 : • The interrupt level is the same for peripheral devices sharing the ICR register.
• P eripheral devices that share the ICR register and use the extended intelligent I/O service only utilize one set.
• If one side of a peripheral device sharing the ICR register is set to extended intelligent I/O service, the other
side cannot use interrupts.
*2 : Only the 16-bit reload timer is compatible with EI2OS. Since PPG does not support EI2OS, if you use EI2OS
with the 16-bit reload timer, prohibit interrupts by PPG.
*3 : Priority if two or more interrupts with the same level are generated simultaneously.
Interrupt Condition EI2OS
Compatible Interrupt Vector Interrupt Register Priority
*3
Number Address ICR Address
UART0 reception complete #39 27HFFFF60HICR14 0000BEH (*1)
UART0 transmission complete #40 28HFFFF5CH
Flash memory ×#41 29HFFFF58HICR15 0000BFH (*1) ↓
Delayed interrupt generation module ×#42 2AHFFFF54HLowest
MB90495G Series
30 DS07-13713-6E
■PERIPHERAL RESOURCES
1. I/O Port
(1) Overview
General-purpose (parallel) I/O ports can be used as the I/O ports. The MB90495G Series has 7 ports (49) .
Each port doubles as a peripheral device I/O pin.
• I/O Port Features
I/O ports output data to I/O pins and load signals input to them, by means of the port data register (PDR) .
Additionally, the por t direction register (DDR) sets the I/O direction of the I/O pins at the bit level. Below is a
description of each pin’s function, and the peripheral device that shares it.
• Port 0 : general-purpose I/O port/doubles as external address data bus pin
• P ort 1 : general-purpose I/O port/doubles as PPG timer output, input capture input, and external address data
bus pin
• Port 2 : general-purpose I/O port/doubles as reload timer I/O, external interrupt input pin, and external address
bus pin
• P ort 3 : general-purpose I/O port/doubles as U AR T0 I/O, free-run timer, and A/D conv erter startup trigger pin
• Port 4 : general-purpose I/O port/doubles as UART1 I/O, and CAN controller transmit/receive pin
• Port 5 : general-purpose I/O port/doubles as analog input pin
• Port 6 : general-purpose I/O port/doubles as external interrupt input pin
MB90495G Series
DS07-13713-6E 31
•Pin Block Diagram for Port 0 (single chip mode)
• Port 0 register (single chip mode)
• The port 0 register contains the port 0 data register (PDR0) and the port 0 direction register (DDR0) .
• The bits making up the register are in a one-to-one relation to the port 0 pin.
Compatibility between port 0 register and pin
Port Name Related register bit and corresponding pin
Port 0 PDR0, DDR0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00
P-ch
N-ch
Internal data bus
PDR (port data register)
DDR (port direction register)
PDR read
PDR write
Output latch
Direction
latch
DDR write
DDR read
Pin
Standby control (SPL = 1)
Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) and watch mode (SPL = 1)
MB90495G Series
32 DS07-13713-6E
• Block Diagram for Pins of Ports 1, 2, 3 and 4 (single-chip mode)
• Port 1 register (single-chip mode)
• The port1 register contains the port 1 data register (PDR1) and the port 1 direction register (DDR1) .
• The bits making up the register are in a one-to-one relationship with the port 1 pins.
Port 1 Register and Corresponding Pins
Port Name Related register bit and corresponding pin
Port 1 PDR1, DDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10
P-ch
N-ch
Internal data bus
Peripheral device
inputPeripheral device
output
Port data register (PDR)
PDR read
PDR write
Output
latch
Peripheral device
output enabled
Pin
Port direction register (DDR)
Direction
latch
DDR write
DDR readStandby control (SPL = 1)
Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) and watch mode (SPL = 1)
MB90495G Series
DS07-13713-6E 33
• Port 2 register
• The port2 register contains the port 2 data register (PDR2) , the port 2 direction register (DDR2) and the high
address control register (HACR).
• The high address control register (HA CR) enab les or disab les the output of external addresses (A16 to A23).
When the register enables the output of the external addresses, the port can not be used as a peripheral
device and a general-purpose I/O port.
• The bits making up the register are in a one-to-one relationship with the port 2 pins.
Port 2 Register and Corresponding Pins
• Port 3 register
• The port3 register contains the port 3 data register (PDR3) and the port 3 direction register (DDR3) .
• The bus control signal selection register (ECSR) enables or disables the input and output of external bus
control signals (WRL / WRH, HRQ / HAK, RDY, CLK). When the register enables the input and output of the
e xternal bus control signals, the port can not be used as a peripheral device and a general-purpose I/O port.
• The bits making up the register are in a one-to-one relationship with the port 3 pins.
Port 3 Register and Corresponding Pins
• Port 4 register
• The port4 register contains the port 4 data register (PDR4) and the port 4 direction register (DDR4) .
• The bits making up the register are in a one-to-one relationship with the port 4 pins.
Port 4 Register and Corresponding Pins
Port Name Related register bit and corresponding pin
Port 2 PDR2, DDR2,
HACR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20
Port Name Related register bit and corresponding pin
Port 3
PDR3, DDR3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ECSR CKE RYE HDE WRE ⎯
Corresponding pin P37 P36 P35 P34 P33 P32 P31 P30
Port Name Related register bit and corresponding pin
Port 4 PDR4, DDR4 ⎯⎯⎯bit4 bit3 bit2 bit1 bit0
Corresponding pin ⎯⎯⎯P44 P43 P42 P41 P40
MB90495G Series
34 DS07-13713-6E
• Block Diagram of Port 5 Pins
• Port 5 register
• The port 5 register contains the port 5 data register (PDR5) , the por t 5 direction register (DDR5) and the
analog input enable register (ADER) .
• The analog data enable register (ADER) enables or disables the input of analog signals by the analog input pin.
• The bits making up the register are in a one-to-one correspondence with the pins of port 5.
Port 5 Register and Corresponding Pins
Port Name Related register bit and corresponding pin
Port 5
PDR5, DDR5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADER ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Corresponding pin P57 P56 P55 P54 P53 P52 P51 P50
ADER
P-ch
N-ch
Internal data bus
Port data register (PDR)
Port direction register (DDR)
PDR read
PDR write
Analog input
Output latch
Direction
latch
Pin
DDR write
DDR readStandby control (SPL = 1)
Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) , and watch mode (SPL = 1)
MB90495G Series
DS07-13713-6E 35
• Block Diagram of Port 6 Pins
• Port 6 register
• The port 6 register contains the port 6 data register (PDR6) and the port 6 direction register (DDR6) .
• The bits making up the register are in a one-to-one relationship with the port 6 pins.
Port 6 Register and Corresponding Pins
Port Name Related register bit and corresponding pin
Port 6 PDR6, DDR6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Corresponding pin ⎯⎯⎯⎯P63 P62 P61 P60
Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) , and watch mode (SPL = 1)
MB90495G Series
36 DS07-13713-6E
2. Time-base Timer
The time-base timer is an 18-bit free-run counter (time-base counter) for counting up in synchronization with the
main clock (1/2 main oscillation clock) .
• Four interval times are available, and interrupt requests can be generated for each interval time.
• The time-base timer also has a function for supplying timers for oscillation stabilize standby time and operating
clocks for peripheral devices.
• Interval timer feature
• When the time-base timer counter reaches the inter val set by the inter val time selection bits (TBTC : TBC1,
TBC0) , it generates an overflow (TBTC : TBOF = 1) and interrupt request.
• If the interrupts due to overflow generation are enabled (TBTC : TBIE = 1) , when an overflow is generated
(TBTC : TBOF = 1) , an interrupt is generated.
• Select from the following 4 time-base timer intervals :
Time-base timer interval times
HCLK : oscillation clock
The number in parentheses ( ) for 4-MHz oscillation clock operation
• Time-base Timer Block Diagram
See below for the actual interrupt request number of the time-base timer :
Interrupt request number : #16 (10H)
Count Clock Interval Time
2/HCLK (0.5 μs)
212/HCLK (approx. 1.0 ms)
214/HCLK (approx. 4.1 ms)
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
TBIE⎯⎯ TBOF TBR TBC1 TBC0
× 2
1
2
1/
HCLK × 2
2
× 2
3
× 2
8
× 2
9
× 2
10
× 2
11
× 2
12
× 2
13
× 2
14
× 2
15
× 2
16
× 2
17
× 2
18
OF OF OF OF
To PPG timer
Time-base timer counter
To watchdog timer
To clock controller
oscillation stabilize
standby time selector
Interval
Timer selector
Set TBOF
Clear TBOF
Clear counter
circuit
Power-on Reset
CKSCR : MCS = 1 → 0*
1
CKSCR : SCS = 0 → 1*
2
Stop Mode
Time-base timer control register
(TBTC)
Time-base timer interrupt signal
Re-
served
OF : overflow
HCLK : oscillation clock
*1 : Switch machine clock from main clock to PLL clock
*2 : Switch machine clock from subclock to main clock
MB90495G Series
DS07-13713-6E 37
3. Watchdog Timer
The watchdog timer is a 2-bit timer used as a count clock for the timer-based or watch timer.
If the counter is not cleared within the interval time, it resets the CPU.
• Watchdog Timer Function
• The watchdog timer is a timer counter used to deal with runaway programs. Once the watchdog timer is
launched, it is necessary to keep clearing its counter within the specified interval. If the specified interval
passes without the watchdog timer counter being cleared, the CPU will be reset. This feature is called the
watchdog timer.
• The watchdog timer interval traces back to the clock interval input as the count clock. A watchdog reset is
generated for the smallest to largest times.
• The clock source output destination is set by the watchdog clock selection bit of the watch timer control register
(WTC : WDCS) .
• The watchdog timer interval is set time-base timer output selection bit/watch timer ou tput selection bit of the
watchdog timer control register (WDTC : WT1, WT0) .
Watchdog Timer Intervals
HCLK : oscillation clock (4 MHz) ; SCLK : Subclock (8.192 kHz)
Notes: • If the count clock of the watchdog timer is set to time-base timer output (overflow signal) , then clearing the
time-base timer could make it take longer to reset the watchdog.
• If you are using a subclock as the machine clock, make sure to select watch timer output by setting the
watchdog timer clock source selection bit (WDCS) of the watch timer control register (WTC) to 0.
Minimum Maximum Clock Interval Minimum Maximum Clock Interval
Approx. 3.58 ms Approx. 4.61 ms 214 ± 211/
HCLK Approx. 0.457 s Approx. 0.576 s 212 ± 29/
SCLK
Approx. 14.33 ms Approx. 18.3 ms 216 ± 213/
HCLK Approx. 3.584 s Approx. 4.608 s 215 ± 212/
SCLK
Approx. 57.23 ms Approx. 73.73 ms 218 ± 215/
HCLK Approx. 7.168 s Approx. 9.216 s 216 ± 213/
SCLK
Approx. 458.75 ms Approx. 589.82 ms 221 ± 218/
HCLK Approx. 14.336 s Approx. 18.432 s 217 ± 214/
SCLK
MB90495G Series
38 DS07-13713-6E
• Watchdog Timer Block Diagram
PONR ⎯WRST ERST SRST WTE WT1 WT0 WDCS
× 2
1
× 2
2
× 2
8
× 2
9
× 2
10
× 2
11
× 2
12
× 2
13
× 2
14
× 2
15
× 2
16
× 2
17
× 2
18
2
4
× 2
1
× 2
2
× 2
5
× 2
6
× 2
7
× 2
8
× 2
9
× 2
10
× 2
11
× 2
12
× 2
13
× 2
14
× 2
15
4
Watchdog timer control register (WDTC)
Watchdog timer
Counter
clear control
circuit
(Time-base timer counter)
(Clock counter)
Counter
clock
selector
Launch
2-bit
counter
Clear
Watch timer control register (WTC)
Watchdog
reset
generation circuit
To internal reset
generation circuit
Reset generation
Go to sleep mode
Go to time-base
timer mode
Go to watch mode
Go to stop mode
Main clock
(1/2 HCLK)
Subclock
SCLK
HCLK : Oscillation clock
SCLK : Subclock
MB90495G Series
DS07-13713-6E 39
4. 16-bit I/O Timer
The 16-bit I/O timer is a complex module compr ising one 16-bit free-run timer, and two input capture units (4
input pins) . Clock interval input signals and pulse widths can be measured based on the 16-bit free-run timer.
• 16-bit I/O Timer Configuration
The 16-bit I/O timer is made up of the following modules :
• One 16-bit free-run timer
• Two input capture units (each unit having 2 input pins)
• 16-bit I/O Timer Function
(1) 16-bit free-run timer function
The 16-bit free-run timer consists of a 16-bit up counter, a time counter control status register, and prescaler.
The 16-bit up counter counts up in synchronization with a fraction of the machine clock.
• The count clock can be set to one of eight fractions of the machine clock. The external clock signals input to
the 16-bit free-run timer clock input pin (FRCK) can be used as the count clock.
• Interrupts can be generated in response to counter value overflows.
• Interrupts launch the extended intelligent I/O service (EI2OS) .
• The count value of the 16-bit free-r un timer can be cleared to “0000 H” by either a reset, or software clear via
the timer count clear bit (TCCS : CLR) .
• The count value of the 16-bit free-run timer is output to the input capture, and used as the base time for capture
operation.
(2) Input Capture Function
When the input capture detects that an external signal edge has been input to an input pin, it stores the count
v alue of the 16-bit free-run timer in the input capture data register, f or the point at which the edge was detected.
The input capture consists of an input capture register corresponding to four I/O pins, an input capture control
status register, and an edge detection circuit.
• When an edge is detected, either rising, falling, or both can be selected.
• An interrupt request can be generated to the CPU when an input signal edge is detected.
• Interrupts launch the extended intelligent I/O service (EI2OS) .
• Since the input capture has four pairs of input pins and input capture data registers, it can measure up to 4
phenomena.
• Block Diagram of 16-bit I/O Timer
Internal data bus
Input capture Dedicated
bus
16-bit
free-run timer
16-bit free-run timer: The counter value of the 16-bit free-run timer is used as the base time of the input capture.
Input capture: Input capture detects rising, falling and both edges for external signals input to input pins, and stores
the counter value of the 16-bit free-run timer. Interrupts can be generated in response to input signal
edge detection.
MB90495G Series
40 DS07-13713-6E
•Block Diagram of 16-bit Free-run Timer
IVF IVFE STOP CLR CLK2 CLK1 CLK0
OF
FRCK
2
φ
STOP
CLK CLR
Pin
Prescaler
Timer counter control
status register
(TCCS)
Timer counter data register (TCDT)
16-bit free-run timer
Re-
served
Output count value
to input capture
Internal data bus
Free-run timer
interrupt request
Note: The 16-bit I/O timer contains one 16-bit free-r un timer.
The interrupt request number of the 16-bit free-r un timer is as follows :
Interrupt request number : 19 (13H)
Prescaler: Takes a fraction of the machine clock, and supplies a count clock to the 16-bit up-counter. One of
four machine clock fractions can be selected by setting the timer counter control status register
(TCCS) .
Timer Counter Register (TCDT) :
This is a 16-bit up-counter. It is possible to read the current counter value of the 16-bit free-run timer
by reading this counter. The counter can be set to an arbitrary value by writing to it while stopped.
Timer Counter Control Status Register (TCCS) :
TCCS selects the divide ratio of a machine clock, executes software clear of counter values. and
enables or disables counter operation. Also TCCS confirms and clears an overflow generation flag,
and enables or disables interruption.
φ : Machine clock
OF : overflow
MB90495G Series
DS07-13713-6E 41
• Input Capture Block Diagram
ICP1 ICP0 ICE1 ICE0 EG11EG10EG01EG00
2
2
IN3
IN2
ICP1 ICP0 ICE1 ICE0 EG11EG10EG01EG00
2
2
IN1
IN0
Edge detection circuit
Pin
Pin
Pin
Pin
Input capture
control status register
(ICS23)
Input capture
control status register
(ICS01)
Edge detection circuit
16-bit free-run timer
Input capture data register 3 (IPCP3)
Input capture data register 2 (IPCP2)
Input capture
interrupt request
Input capture data register 1 (IPCP1)
Input capture data register 0 (IPCP0)
Internal data bus
MB90495G Series
42 DS07-13713-6E
5. 16-bit Reload Timer
The functions of the 16-bit reload timer are as follows :
• Choose one of three internal clocks or an external event clock as the count clock.
• Choose a software or external launch trigger.
• An interrupt can be sent to the CPU in response to an underflow generated by the 16-bit timer register. Interrupts
can be used to utilize the timer as an interval timer.
• When an underflow is generated by the 16-bit timer register (TMR) , select one-shot mode, where TMR counter
operation is halted, or reload mode, where the 16-bit reload register value is reloaded, and TMR count operation
continues.
• Supports extended intelligent I/O service (EI2OS) .
• The MB90495G Series features two on-chip 16-bit reload timer channels.
•16-bit Reload Timer Operation Mode
• Internal Clock Mode
• Set the count clock selection bits of the timer control status register (TMCSR : CSL1, CSL0) to “00B”, “01B” or
“10B” to set the 16-bit reload timer to internal clock mode.
• In internal clock mode, the timer counts down in synchronization with the internal clock.
• Set the count clock selection bits of the timer control status register (TMCSR : CSL1, CSL0) to select one of
three count clock intervals.
• Select software-triggered or externally triggered (edge detection) launch.
Count Clock Launch Trigger Operation in Case of Underflow
Internal clock mode Software trigger
External trigger One-shot mode
Reload mode
Event count mode Software trigger One-shot mode
Reload mode
MB90495G Series
DS07-13713-6E 43
• 16-bit Reload Timer Block Diagram
TMRLR
TMR
CLK
TIN
UF
EN TOT
CLK
3
32
⎯⎯⎯⎯
CSL1 CSL0 MOD2MOD1 MOD0 OUTE OUTL RELD UFINTE CNTE TRG
Count clock generation circuit
Machine
clock
φ
Pin Pin
16-bit timer register
Prescaler
Clear
16-bit reload register
Gate
input
Internal
clock
External
clock
Internal data bus
Valid clock
determination
circuit
Clock
selector
Select
signal
Reload signal
Wait signal
Output control circuit
Output signal
generation
circuit
Reload
control circuit
Output to on-chip
peripheral functions
Operation
control circuit
Timer control status register (TMCSR)
Select function
I/O control
circuit
Output interrupt request
MB90495G Series
44 DS07-13713-6E
6. Watch Timer
The watch timer is a 15-bit free-run counter that counts up in synchronization with the subclock.
• Eight different intervals can be selected, and interrupt requests generated for each interval time.
• Supplies a timer f or subclock oscillation stabilization standby, and an operational cloc k for the w atchdog timer .
• The subclock is always the count clock, regardless of the clock selection register (CKSCR) setting.
• Interval timer feature
• When the inter val time set by the interval time selection bits (WTC : WTC2 to WTC0) is reached, the clock
timer generates an overflow in the bits corresponding to the interval time of the w atch timer counter, and sets
the overflow flag bit (WTC : WTOF = 1) .
• Interrupts ar ising from overflows are enabled (WTC : WTIE = 1) , an interrupt request is generated when the
overflow flag bit is set (WTC : WTOF = 1) .
• Select from one of the following 8 watch timer intervals :
Clock Timer Interval Times
SCLK : Subclock frequency
Figures in parentheses ( ) are a sample calculation with the subclock running at 8.192 kHz.
Subclock Frequency Interval Time
1/SCLK (122 μs)
28/SCLK (31.25 ms)
29/SCLK (62.5 ms)
210/SCLK (125 ms)
211/SCLK (250 ms)
212/SCLK (500 ms)
213/SCLK (1.0 s)
214/SCLK (2.0 s)
215/SCLK (4.0 s)
MB90495G Series
DS07-13713-6E 45
• Watch Timer Block Diagram
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
× 21× 22× 23× 24× 25× 26× 27× 28× 29× 210 × 211 × 212 × 213 × 215
× 214
OF OF OF OF OF OF OF
OF
SCLK
Watch timer counter
Watch timer control register (WTC)
Power-on reset
Go to hardware standby
Go to stop mode
Watch timer interrupt
Counter
clear circuit
Interval
timer selector
To watchdog timer
To subclock oscillation
stabilization standby time
OF : Overflow
SCLK : Subclock
Notes: The actual interrupt request number generated by the watch timer is as follows :
Interrupt request number : #28 (1CH)
Watch timer counter: 15-bit up counter using the subclock (SCLK) as its count clock.
Counter clear circuit: This circuit clears the watch timer counter.
MB90495G Series
46 DS07-13713-6E
7. 8/16-Bit PPG
The 8/16-bit PPG timer is a 2-channel reload timer module (PPG0, PPG1) capable of arbitrary synchronization
and pulse output of duty ratio. Combining the 2 channel module can yield the following behavior :
• 8-bit PPG output, 2-channel independent operation mode
• 16-bit PPG output operation mode
• 8 + 8-bit PPG output operation mode
The MB90495G Series features two on-chip, 8/16-bit PPG timers. This section describes the functions of PPG0/
1. PPG2/3 has the same functions as PPG0/1.
• 8/16-bit PPG Timer Functions
The 8/16-bit PPG timer is made up of f our 8-bit reload registers (PRLH0/PRLL0, PRLH1/PRLL1) , and two PPG
down counters (PCNT0, PCNT1) .
• Since you can set each output pulse to “H” or “L” width independently, the interval and duty ratio of each
pulse can be set to an arbitrary value.
• Select one of 6 internal clocks as the count clock.
• Interrupt requests can be generated f or each interval time, allo wing the timer to be used as an interv al timer .
• The use of an external circuit allows the timer to be used as a D/A converter.
MB90495G Series
DS07-13713-6E 47
• Block Diagram of 8/16-Bit PPG Timer 0
PPG0
CLK
R
SQ
PEN0 PE0 PIE0
PUF0
⎯⎯⎯
PCS2PCS0 PCM2
PCM1 PCM0
⎯⎯PCS1
3
2
PPG0
reload
register
PRLH0
("H" level side)
PPG0 temporary
buffer 0 (PRLBH0)
Reload register
L/H selector
Initial
count value
PPG0 down counter
(PCNT0)
PRLL0
("L" level side)
Select signal
Reload
Underflow
Time-base timer output
(512/HCLK)
Clear
Invert PPG0
output latch
Count
clock
selector
Select signal
PPG0/1 count clock selection register (PPG01)
PPG0 operation mode control register
(PPGC0)
Pulse selector
"H" level side data bus
"L" level side data bus
PPG output control circuit
Re-
served
Output
interrupt
request*
Operation mode
control signal
PPG0 underflow
PPG1 underflow
(to PPG1)
Pin
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
⎯ : Undefined
Reserved : Reserved bit
HCLK : Oscillation clock frequency
φ : Machine clock frequency
* : Interrupt output from 8/16-bit PPG timer 0 is merged with interrupt request output from PPG
timer 1 into a single interrupt via an OR circuit.
MB90495G Series
48 DS07-13713-6E
• Block Diagram of 8/16-Bit PPG Timer1
PPG1
CLK
MD0
R
SQ
PEN1 PE1 PIE1 PUF1 MD1 MD0⎯
PCS2PCS0 PCM2
PCM1 PCM0
⎯⎯PCS1
3
2
PPG1 reload
register
Operation
mode control signal
PPG1 underflow
(to PPG0)
PPG0 underflow
(from PPG0)
PRLH1
("H" side)
PPG1 temporary
buffer (PRLBH1)
Reload selector
L/H selector
Initial count value
PPG1 down counter
(PCNT1)
PRLL1
("L" side)
Reload
Underflow
Time-base timer output
(512/HCLK)
Peripheral clock (1/φ)
Peripheral clock (2/φ)
Peripheral clock (4/φ)
Peripheral clock (8/φ)
Peripheral clock (16/φ)
Select signal
Clear
Invert PPG1
output latch
PPG output control circuit
Select signal
Counter
clock
selector
PPG0/1 count clock selection register (PPG01)
"H" level side data bus
"L" level side data bus
PPG1 operation mode control register
(PPGC1)
Re-
served
Output
interrupt
request*
Pin
⎯ : Undefined
Reserved : Reserved bit
HCLK : Oscillation clock frequency
φ : Machine clock frequency
* : Interrupt output from 8/16-bit PPG timer 1 is merged with interrupt request output from
PPG timer 0 into a single interrupt via an OR circuit.
MB90495G Series
DS07-13713-6E 49
8. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks.
This module can be used to generate hardware interrupts from the software.
•Overview of the Delayed Interrupt Generation Module
Use the delayed interrupt generation module to generate or cancel hardware interrupts from the software.
Overview of the Delayed Interrupt Generation Module
• Delayed Interrupt/Generation Module Block Diagram
•Interrupt number
Below is the interrupt number used by the delayed interrupt generation module.
Interrupt number : #42 (2AH)
Functions and Control
Interrupt Condition
When the R0 bit of the delayed interrupt request generation/cancel register is
set to 1 (DIRR : R0 = 1) : Generate interrupt request
When the R0 bit of the delayed interrupt request generation/cancel register is
set to 0 (DIRR : R0 = 0) : Cancel interrupt request
Interrupt number #42 (2AH)
Interrupt control There is no enable setting from the register
Interrupt flag Stored in bit DIRR : R0
EI2OS Does not support extended intelligent I/O service
⎯⎯⎯⎯⎯⎯⎯R0 S
R
Internal data bus
Delayed interrupt request generation/cancel register
(DIRR)
Interrupt
request latch Interrupt
request signal
⎯ : Undefined
Interrupt request latch:This latch stores the delayed interrupt request generation/cancel register setting
(generates/cancels delayed interrupt requests) .
Delayed interrupt request generation/cancel register (DIRR) :
Generates or cancels delayed interrupt requests.
MB90495G Series
50 DS07-13713-6E
9. DTP/External Interrupts
The DTP/external interrupt transmits interrupt requests or data transfer requests generated by peripheral devices
to the CPU, generates external interrupt request, and starts the extended intelligent I/O service (EI2OS) .
• DTP/External Interrupt Functions
Outputs interrupt requests from external peripheral devices to the CPU using the same procedure as f or periph-
eral functions, and generates external interrupts, or starts the extended intelligent I/O service (EI2OS) .
If the interrupt control register is configured to prohibit the extended intelligent I/O service (EI2OS) (ICR : ISE =
0) , then the external interrupt feature becomes valid, and the process branches into interrupt processing.
If the EI2OS is enabled (ICR : ISE = 1) , then the DTP function becomes valid, and the EI2OS automatically
transmits data, and after transmitting data a specified number of times, branches into interrupt processing.
Overview of DTP/External Interrupts
External interrupt DTP functions
Input pins 8 (INT0 to INT7)
Interrupt condition Each pin sets individually in the detection level configuration register (ELVR)
“H” / “L” level/rising edge/falling edge input “H” / “L” level input
Interrupt numbers #15 (0FH) , #20 (14H) , #24 (18H) , #27 (1BH)
Interrupt control The DTP/external interrupt enable register (ENIR) enables or prohibits interrupt request
output
Interrupt flag Interrupt conditions stored by DTP/external interrupt condition register (EIRR)
Process selection Set EI2OS to be prohibited (ICR : ISE = 0) Set EI2OS to be enabled (ICR : ISE = 1)
Processing Branch to external interrupt process After the EI2OS conducts automatic data
forwarding the specified number of times,
branches to interrupt processing.
MB90495G Series
DS07-13713-6E 51
• DTP/External Interrupt Block Diagram
INT7
INT6
INT5
INT4
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
ER7 ER6 ER5 ER4 ER3 ER2
INT3
INT2
INT1
INT0
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
ER1 ER0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
Internal data bus
Detection level configuration register (ELVR)
Pin
Pin
Pin
Pin
DTP/external interrupt
input detection circuit
Interrupt request
signal
Level/
edge
selector
Level/
edge
selector
Level/
edge
selector
Level/
edge
selector
Level/
edge
selector
Level/
edge
selector
Level/
edge
selector
Level/
edge
selector
Pin
Pin
Pin
Pin
DTP/external interrupt condition
register (EIRR)
Interrupt request
signal
DTP/external interrupt enable
register (ENIR)
MB90495G Series
52 DS07-13713-6E
10. 8/10-bit A/D Converter
The 8/10-bit A/D converter converts analog voltage to 8 or 10-bit digital values, by means of RC successive
approximation conversion.
• The input signal can be selected from an 8-channel analog input pin set.
• Select a software trigger, internal timer output, or external trigger as the start trigger.
• Functions of the 8/10-bit A/D Converter
Converts analog voltage (input voltage) input to the analog input pins to 8-bit or 10-bit digital values. (A/D
conversion)
The 8/10-bit A/D converter has the fo llowing features :
• Single-channel A/D conversion time is a minimum of 6.12 μs, including sampling time.*
• Single-channel sampling time is a minimum of 2.0 μs.*
• RC-type successive approximation with sampling and hold circuits is used for conversion.
• Select 8 or 10-bit resolution.
• Analog input pins can use up to 8 channels.
• A/D conversion results are stored in the A/D data register, allowing them to be used to generate interrupts.
• Interrupt requests launch the EI2OS. Use the EI2OS to prevent dropped data even with continuous A/D con-
version.
• Select software, internal timer output, or external trigger (falling edge) as the start trigger.
* : With machine clock operating at 16 MHz
•Conversion Modes of the 8/10-bit A/D Converter
Conversion Mode Description
Single conversion mode Conducts A/D conversion for each channel in turn, from the start channel to the end
channel. When A/D conversion of the end channel is completed, the A/D conversion
function halts.
Continuous conversion
mode
Conducts A/D conversion for each channel in turn, from the start channel to the end
channel. When A/D conversion of the end channel is completed, the function returns
to the start channel and continues A/D conversion.
Stop conversion mode Suspends each channel and conducts A/D conversion, one at a time. When A/D
conversion of the end channel is completed, the function returns to the start channel
and repeats the A/D conversion and channel stop.
MB90495G Series
DS07-13713-6E 53
• 8/10-bit A/D Converter Block Diagram
BUSY INT INTE PAUSSTS1 STS0 STAT MD1 MD0 ANS2ANS1ANS0ANE2ANE1ANE0
AN7
AN6
ADTG
TO
AN5
AN4
AN3
AN2
AN1
AN0 AVR
AVCC
AVSS
26
2
2
2
φ
S10 ST1 ST0 CT1 CT0 ⎯D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A/D control
status register
(ADCS)
A/D data register
(ADCR)
Launch
Selector
Analog
channel
selector
Output interrupt request
Re-
served
Sample and
hold circuit
Decoder
Comparator
Control circuit
D/A converter
Internal data bus
TO : Internal timer output
⎯ : Undefined
Reserved : Make sure this is always set to “01”
φ : Machine clock
MB90495G Series
54 DS07-13713-6E
11. UART0/1
The UART is a general-pur pose serial data communications interface for synchronous or asynchronous com-
munication with external devices.
• The UAR T has a clock-synchronous/clock-asynchronous two-way communications feature .
• Also supplies a master/slave communications feature (multi-processor mode) . (It can be used only master
side.)
• Interrupts can be generated upon send complete, receive complete, or reception error detection.
• Supports extended intelligent I/O service (EI2OS) .
•UART0/1 Functions
Note : During clock-synchronous forwarding, just the data is forwarded, with no stop or start bit appended.
Functions
Data Buffer Full-duplex double buffer
Transfer mode • Clock-synchronous (no start, stop, or parity bit)
• Clock-asynchronous (start-stop synchronization)
Baud Rate • Select from 8 dedicated baud rate generators
• External clock input possible
• Clock supplied from internal timer (16-bit reload timer) available
Data length • 7-bit (asynchronous normal mode only)
•8-bit
Signal method Non Return to Zero (NRZ)
Reception Error Detection • Framing error
• Overrun error
• Parity error (not available in operation mode 1 (multi processor mode) )
Interrupt Requests • Receive interrupt (reception complete, reception error detected)
• Send interrupt (send complete)
• Both send and receive support extended intelligent I/O service (EI2OS)
Master/Slave Communications
Function
(In multiprocessor mode) 1-to-n (master to slave) communication available (can only be used as master)
MB90495G Series
DS07-13713-6E 55
• UART0 Block Diagram
SCK0
SIN0
SOT0
MD1
MD0
CS2
CS1
CS0
SOE
SCKE
MD
DIV3
DIV2
DIV0
DIV1
PEN
P
SBL
CL
A/D
REC
TXE
RXE
PE
ORE
FRE
RDRF
TDRE
TIE
RIE
NEG
Dedicated baud rate
generator
16-bit reload timer0
Pin
Pin
Serial
edge
selection
register
Clock
selector
Reception status
determination circuit
Reception clock
Communi-
cations
prescaler
control
register
Control bus
Reception
control circuit
Start bit
detection circuit
Reception
bit counter
Reception
parity counter
Reception
shift register
Serial input
data register0
Internal data bus
Serial
mode
register0
Send clock
Re-
ception
end
Send
control circuit
Send start
circuit
Send bit
counter
Send parity
counter
Send
shift register
Serial output
data register0
Serial
control
register0
Reception
interrupt
request output
Send interrupt
request output
Pin
Send start
EI2OS
receive error
generation signal
(to CPU)
Serial
status
register0
MB90495G Series
56 DS07-13713-6E
• UART1 Block Diagram
SCK1
SIN1
SOT1
Dedicated baud rate
generator
16-bit reload timer1
Pin
Pin
Clock
selector
Reception status
determination circuit
Reception clock
Communi-
cations
prescaler
control
register
Control bus
Reception
control circuit
Start bit
detection circuit
Reception
bit counter
Reception
parity counter
Reception
shift register
Serial input
data register1
Internal data bus
Serial
mode
register1
Send clock
Re-
ception
end
Send
control circuit
Send start
circuit
Send bit
counter
Send parity
counter
Send
shift register
Serial output
data register1
Serial
control
register1
Reception
interrupt
request output
Send interrupt
request output
Pin
Send start
EI2OS
receive error
generation signal
(to CPU)
Serial
status
register1
PE
ORE
FRE
RDRF
TDRE
TIE
RIE
PEN
P
SBL
CL
A/D
REC
TXE
RXE
MD
DIV2
DIV0
DIV1
MD1
MD0
CS2
CS1
CS0
SOE
SCKE BDS
RST
MB90495G Series
DS07-13713-6E 57
12. CAN Controller
CAN (Controller Area Network) is a serial communications protocol conforming to CAN version 2.0 A and B.
Sending and receiving is available in standard and extended frame form at.
• Can Controller Features
• The CAN controller format conforms to CAN versions 2.0 A and B.
• Sending and receiving is available in standard and extended frame format.
• Supports automatic data frame formatting through remote frame reception.
• Baud rate : 10 kbps to 1 Mbps . When using at 1 Mbps, the machine clock must be oper ated at 8 MHz or more.
Data Transmission Baud Rates
• Supplies 8 send/receive message buffers.
• Sending and receiving av ailab le in standard fr ame f ormat (ID 11-bit) , and e xtended frame f ormat (ID 29-bit) .
• Message data can be set to 0 to 8 bytes.
• Possible to configure a multi-level message bu ffer.
• The CAN controller has two built-in acceptance masks, each of which can be set to a different mask for
reception message IDs.
• The two acceptance masks can receive in standard or extended frame format.
• Configure four types of partial masks with full-bit compare, full-bit mask, and acceptance mask register 0/1.
Machine clock Baud rate (Max)
16 MHz 1 Mbps
12 MHz 1 Mbps
8 MHz 1 Mbps
4 MHz 500 kbps
2 MHz 250 kbps
MB90495G Series
58 DS07-13713-6E
• CAN Controller Block Diagram
BTR
PSC
TS1
TS2
RSJ
TOE
NS1,0
NT
NIE
HALT
RS
TS
CSR
RTEC
BVALR
TREQR
TCANR
TRTRR
RFWTR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
AMSR
AMR0
AMR1
IDER
LEIR
IDR0 to IDR7
DLCR0 to
DLCR7
DTR0 to DTR7
RAM
0
1
RX
TX
EI2OS -16LX Bus
CPU
operation
clock Prescaler
(1:1 to 1:64)
Node status
transition interrupt
generation circuit
Clear send
buffer Send buffer
determination
circuit
Send buffer
Set/clear send buffer
Send complete interrupt
generation circuit
Set reception buffer
Reception complete
interrupt generation circuit
Reception buffer
Set/clear send buffer
Set reception
buffer Select ID
Acceptance
filter
RAM address
generation circuit
Bit timing
generation circuit
Node status
transition
interrupt signal Error
control
circuit
Send
buffer
Send
complete
interrupt
signal
Reception
complete
interrupt
signal
Reception buffer
determination
circuit
Reception buffer
Reception buffer/
Send buffer/
Receive DLC/Send DLC/
Select ID
Operation clock (TQ)
Sink segment
Timer segment 1
Timer segment 2
Send/receive
sequence
Data
counter
Acceptance
filter control
circuit
Send
DLC Re-
ception
DLC
ID
selection
Bit error/
Staff error/
CRC error/
Frame error/
ACK error
Send shift
register
Receive
DLC
Reception
shift register
Arbitration
lost
Bit error
ACK error
Frame
error
CRC
generation
circuit
CRC error
CRC generation
circuit/error check
Bus status
determina-
tion circuit
Error
frame
generation
circuit
Overload
frame
generation
circuit
Arbitration lost
Staffing
ACK
generation
circuit
Staff
error
Destaffing/
staffing error
check
Arbitration check
Bit error check
Acknowledgement
error check
Form error check
Idle/
interrupt/
suspend/
send/
receive/
error/
overload
Output
driver Pin
Input
latch Pin
Send DLC
MB90495G Series
DS07-13713-6E 59
13. ROM Correction Function
In the case that the address of the instruction after the one that a progr am is currently processing matches the
address configured in the detection address configuration register, the progr am fo rces the next instruction to be
processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be
conducted using INT9 interrupts, programs can be repaired using batch processing.
• Overview of the ROM Correction Function
• The address of the instruction after the one that a program is currently processing is always stored in an
address latch via the internal data bus. ROM correction constantly compares the address stored in the address
latch with the one configured in the detection address configuration register. If the two compared addresses
match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing
program.
• There are two detection address configuration registers : PADR0 and PADR1. Each register provides an
interrupt enable bit. This allows y ou to individually configure each register to enab le/prohibit the generation of
interrupts when the address stored in the address latch matches the one configured in the detection address
configuration register.
• ROM Correction Block Diagram
• Address latch
Stores value of address output to internal data bus.
• Address detection control register (PACSR)
Set this register to enable/prohibit interrupt output when an address match is detected.
• Detection address configuration register (PADR0, PADR1)
Configure an address with which to compare the address latch value.
AD1E AD0E
PADR1 (24-bit)
PADR0 (24-bit)
PACSR
Internal data bus
Address latch
Detection address configuration register 0
Detection address configuration register 1
Re-
served Re-
served Re-
served Re-
served Re-
served Re-
served
Address detection control register (PACSR)
Comparator
INT9 instruction
(INT9 interrupt generation)
Reserved : Make sure this is always set to “01”
MB90495G Series
60 DS07-13713-6E
14. ROM Mirror Function Selection Module
The ROM mirror function selection module configures R OM-internal data arra yed inside bank FF to be readable
by accessing bank 00.
• ROM Mirror Function Selection Module Block Diagram
• Accessing Bank FF through ROM Mirror Function
ROM
Internal data bus
Address
Data
Bank FF
ROM mirror function selection register (ROMM)
Address area
Bank 00
MI
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
004000H
00FFFFH
FEFFFFH
FF0000H
FF4000H
FFFFFFH
MB90F497G
MB90497G
Bank 00
Bank FF
(Area corresponding
to ROM mirror)
ROM mirror area
FC0000H
FE0000H
MB90F498G
MB90V495G
MB90495G Series
DS07-13713-6E 61
15. 512-K/1-M bit Flash Memory
• Overview
There are three methods available for writing/deleting data to/from flash memory :
1. Parallel writer
2. Serial dedicated writer
3. Program runtime write/delete
• Overview of 512-K/1-M bit flash memory
512-Kbit flash memory is arra yed in bank FFH on the CPU memory map , 1-Mbit flash memory is array ed in bank
FEH to FFH on the CPU memory map. The flash memory interface circuit provides read and program access
from the CPU.
Since instructions from the CPU are carried out via the flash memory interface circuit, flash memory can be
overwritten at the implementation level. This allows you to efficiently improve programs and data.
• Features of 512-K/1-M bit Flash Memory
• 512-Kbit flash memory : 64 KWords × 8-bit/32 KW ords × 16-bit (16-Kbyte + 8-Kbyte + 8-Kbyte + 32-Kbyte)
sector architecture
• 1-Mbit flash memory : 128 KWords × 8-bit/64 KW ords × 16-bit (16-Kbyte + 8-Kbyte + 8-Kb yte + 32-Kbyte +
64-Kbyte) sector architecture
• Auto program algorithm (Embedded Algorithm : same as MBM29LV200)
• On-chip delete suspend/delete resume functions
• Data polling, write/delete completion detection through toggle bit
• Write/delete completion detection from CPU overwrite
• Sector-specific deletion available (sectors can be combined as desired)
• Write/delete iterations (minimum) : 10,000
Notes : There is no function to read the manufacture or device code.
These codes also cannot be accessed through commands.
• Flash memory write/delete
• It is not possible to simultaneously write to and read from flash memory.
• When writing to or deleting from flash memory, first copy the program residing in flash memory into RAM,
then execute the program copied into RAM. This will allow you to write to flash memory.
MB90495G Series
62 DS07-13713-6E
•List of Flash Memory Registers and Reset Values
• Sector Architecture of 512-K/1-M bit Flash memory
• Sector architecture
512-Kbit flash memory : When accessing from the CPU, SA0 to SA3 are arrayed in the Bank FF register.
1-Mbit flash memory : When accessing from the CPU , SA0 is arra y ed in the Bank FE register, SA1 to SA4
are arrayed in the Bank FF register.
Sector Architecture of 512-K/1-M bit Flash Memory
7bit 6543210
000X0000
× : Undefined
Flash memory control
status register (FMCS)
FF0000H
FF7FFFH
FF8000H
FF9FFFH
FFA000H
FFBFFFH
FFC000H
FFFFFFH
70000H
77FFFH
78000H
79FFFH
7A000H
7BFFFH
7C000H
7FFFFH
SA0 (32 Kbytes)
SA1 (8 Kbytes)
SA2 (8 Kbytes)
SA3 (16 Kbytes)
512-Kbit
Flash Memory CPU Addresses Writer Address*
* : If a parallel write is writing data to Flash memory, the write address corresponds to the CPU address.
If a general-purpose writer is used to write/delete, this address is written to/over.
FE0000H
FEFFFFH
FF0000H
FF7FFFH
FF8000H
FF9FFFH
60000H
6FFFFH
70000H
77FFFH
78000H
79FFFH
FFA000H
FFBFFFH
7A000H
7BFFFH
SA0 (64 Kbytes)
SA1 (32 Kbytes)
SA2 (8 Kbytes)
SA3 (8 Kbytes)
1-Mbit
Flash Memory CPU Addresses Writer Address*
FFC000H
FFFFFFH
7C000H
7FFFFH
SA4 (16 Kbytes)
MB90495G Series
DS07-13713-6E 63
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings (VSS = AVSS = 0 V)
*1 : AVCC and AVR shall never exceed VCC. Also, AVR shall never exceed AVCC.
*2 : VI and VO shall nev er e xceed VCC + 0.3 V. Howe v er, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*3 : The rating for the maximum output current is the peak value of one of the corresponding pins.
*4 : The standard for computing average output current is the av erage current output from one of the corresponding
pins over a period of 100 ms (the av er age v a lue is tak en b y multiplying oper ating current by operational rate) .
*5 : The standard for computing average total output current is the average current output from all of the corre-
sponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational
rate) .
*6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P44, P50 to P57, P60 to P63
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices. (Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1
AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR *1
Input voltage VIVSS − 0.3 VSS + 6.0 V *2
Output voltage VOVSS − 0.3 VSS + 6.0 V *2
Maximum clamp current ICLAMP − 2.0 + 2.0 mA *6
Total maximum clamp current Σ| ICLAMP | ⎯20 mA *6
“L” level maximum output current IOL ⎯15 mA *3
“L” level average output current IOLAV ⎯4mA *
4
“L” level maximum total output current ΣIOL ⎯100 mA
“L” level average total output current ΣIOLAV ⎯50 mA *5
“H” level maximum output current IOH ⎯−15 mA *3
“H” level average output current IOHAV ⎯−4mA *
4
“H” level maximum total output current ΣIOH ⎯−100 mA
“H” level average total output current ΣIOHAV ⎯−50 mA *5
Power consumption PD⎯315 mW
Operating temperature TA−40 +105 °C
−40 +125 °C*
7
Storage temperature Tstg −55 +150 °C
MB90495G Series
64 DS07-13713-6E
(Continued)
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits:
*7 : If used exceeding TA = +105 °C, be sure to contact us for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
+B input (0 V to 16 V)
Limiting
resistance
Protective diode
MB90495G Series
DS07-13713-6E 65
2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)
*1 : Use a ceramic capacitor, or one with approximately the same frequency characteristics. The b ypass capacitor
of the VCC pin should have a greater capacity than CS.
See the figure below for details about connecting a smooth capacitor to the CS.
*2 : If used exceeding TA = +105 °C, be sure to contact us for reliability limitations.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage VCC,
AVCC
4.5 5.0 5.5 V During normal operation,
TA = −40 °C to +105 °C
4.75 5.0 5.25 V During normal operation,
+105 °C < TA ≤ +125 °C
3.0 ⎯5.5 V Maintaining stop operation state
Smoothing capacitor CS0.022 0.1 1.0 μF*1
Operating temperature TA−40 ⎯+105 °C
−40 ⎯+125 °C*2
C
CS
• C Pin Connection Diagram
MB90495G Series
66 DS07-13713-6E
3. DC Characteristics (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(Continued)
Parameter Sym-
bol Pin Name Condition Value Unit Remarks
Min Typ Max
“H” level
input
voltage
VIHS CMOS
hysteresis
input pin ⎯0.8 VCC ⎯VCC + 0.3 V
VIHM MD input pin ⎯VCC − 0.3 ⎯VCC + 0.3 V
“L” level
input
voltage
VILS CMOS
hysteresis
input pin ⎯VSS − 0.3 ⎯0.2 VCC V
VILM MD input pin ⎯VSS − 0.3 ⎯VSS + 0.3 V
“H” level
output voltage VOH All output
pins
VCC = 4.5 V,
IOH = −4.0 mA VCC − 0.5 ⎯⎯VTA = −40 °C to +105 °C
VCC = 4.75 V VCC − 0.5 ⎯⎯V+105 °C < TA ≤ +125 °C
“L” level
output voltage VOL All output
pins
VCC = 4.5 V,
IOL = 4.0 mA ⎯⎯0.4 V TA = −40 °C to +105 °C
VCC = 4.75 V ⎯⎯0.4 V +105 °C < TA ≤ +125 °C
Input leakage
current IIL All output
pins
VCC = 5.5 V,
VSS < VI < VCC −5⎯ + 5 μATA = −40 °C to +105 °C
VCC = 5.25 V,
VSS < VI < VCC −5⎯ + 5 μA+105 °C < TA ≤ +125 °C
Power
supply
current*
ICC
VCC
VCC = 5.0 V
Internal 16-MHz
operation,
Normal mode
⎯30 40 mA MB90497G
MB90F497G
MB90F498G
VCC = 5.0 V
Internal 16-MHz
operation,
Flash memory
write mode
⎯45 50 mA MB90F497G
MB90F498G
VCC = 5.0 V
Internal 16-MHz
operation,
Flash memory
delete mode
⎯45 50 mA MB90F497G
MB90F498G
ICCS
VCC = 5.0 V
Internal 16-MHz
operation,
Sleep mode
⎯11 18 mA MB90497G
MB90F497G
MB90F498G
MB90495G Series
DS07-13713-6E 67
(Continued) (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
* : This is when using the external clock as the power supply current test condition.
Parameter Sym-
bol Pin Name Condition Value Unit Remarks
Min Typ Max
Power
supply
current*
ICTS
VCC
VCC = 5.0 V
Internal 2-MHz operation,
Timer mode ⎯0.6 1.2 mA MB90497G
MB90F497G
MB90F498G
ICCL
VCC = 5.0 V
Internal 8-kHz operation,
Subclock operation mode
TA = + 25 °C
⎯30 50 μA MB90497G
⎯300 500 μAMB90F497G
MB90F498G
ICCLS
VCC = 5.0 V
Internal 8-kHz operation,
Subclock sleep mode
TA = + 25 °C
⎯10 30 μAMB90497G
MB90F497G
MB90F498G
ICCT
VCC = 5.0 V
Internal 8-kHz operation,
Clock mode
TA = + 25 °C
⎯825μAMB90497G
MB90F497G
MB90F498G
Power
supply
current* ICCH VCC VCC = 5.0 V
Stop mode, TA = + 25 °C⎯520μAMB90497G
MB90F497G
MB90F498G
Input
Capacity CIN
Other than
AVCC,
AVSS,
AVR, C,
VCC, or VSS
⎯⎯515pF
Pull up
Resistor RUP RST ⎯25 50 100 kΩ
Pull down
Resistor RDOWN MD2 ⎯25 50 100 kΩ
MB90495G Series
68 DS07-13713-6E
4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Par ameter Symbol Pin Name Value Unit Remarks
Min Typ Max
Clock frequency fCX0, X1 3 ⎯16 MHz
fCL X0A, X1A ⎯32.768 ⎯kHz
Clock Cycle Time tHCYL X0, X1 62.5 ⎯333 ns
tLCYL X0A, X1A ⎯30.5 ⎯μs
Input clock pulse width PWH, PWL X0 10 ⎯⎯ns Duty ratio should be around
30 % to 70 %
PWLH, PWLL X0A ⎯15.2 ⎯μs
Input clock rising/falling
time tCR, tCF X0 ⎯⎯ 5 ns When external clock used
Internal operation clock
frequency fCP ⎯1.5 ⎯16 MHz When oscillation circuit used
fLCP ⎯⎯8.192 ⎯kHz When subclock used
Internal operation clock
cycle time tCP ⎯62.5 ⎯666 ns When using oscillation circuit
tLCP ⎯⎯122.1 ⎯μs When subclock used
X0
t
HCYL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WH
P
WL
X0A
t
LCYL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WLH
P
WLL
• X0/X1 Clock Timing
MB90495G Series
DS07-13713-6E 69
AC characteristics are specified by the following reference voltage values.
5.5
4.5
3.0
3.3
81.5 312 16
PLL guaranteed operation range
MB90F497G/MB90F498G/MB90497G guaranteed operation range (TA = -40°C to +105°C)
Power supply voltage VCC (V)
Internal clock fCP (MHz)
5.25
4.75
MB90F497G/MB90F498G/MB90497G guaranteed operation range
( = +105°C < TA < +125°C)
16
12
8
9
4
34 8 16
×1/2
(no multiplication)
×4×3×2×1
Internal clock f
CP
(MHz)
External clock f
C
(MHz)
Relationship between external clock frequency and internal operation clock frequency
Relationship between internal operating clock frequency and power supply voltage
• PLL guaranteed operation range
0.8 VCC
0.2 VCC
2.4 V
0.8 V
• Input Signal Waveform
Hysteresis Input Pin
• Output Signal Waveform
Output Pin
MB90495G Series
70 DS07-13713-6E
(2) Clock Output Timing (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(3) Reset Input Timing
* : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several
dozen ms; for a ceramic oscillator, this is se v e ral hundred μs to a fe w ms, and f or an external clock this is 0 ms.
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Max
Cycle time tCYC CLK ⎯62.5 ⎯ns
CLK ↑ → CLK ↓tCHCL 20 ⎯ns
Parameter Symbol Pin
Name Condition Value Unit Remarks
Min Max
Reset input time tRSTL RST ⎯
16 tCP ⎯ns Normal mode
Oscillator oscillation time*
+ 16 tCP ⎯ms
Stop mode,
Watch mode,
Subclock mode,
Subsleep mode
CLK
tCYC
2.4 V 2.4 V
0.8 V
tCHCL
tRSTL
0.2 VCC 0.2 VCC
16 tCP
RST
X0
90% of
amplitude
Instruction execution
Oscillation stabilize standby time
Oscillator
oscillation time
Internal operation
clock
Internal reset
• Stop mode, Watch mode, Subclock mode, Subsleep mode
MB90495G Series
DS07-13713-6E 71
(4) Power-on Reset (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin
Name Condition Value Unit Remarks
Min Max
Power supply rising time tRVCC ⎯0.05 30 ms
Power supply cutoff time tOFF VCC 1⎯ms Due to repeated operations
VCC
VCC
VSS
3 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
RAM data hold period
It is recommended that you keep the rising
speed to no more than 50 mV/ms.
Sudden changes in the power supply voltage may cause a power-on reset. To change the power
supply voltage while the device is in operation, it is recommended that you raise the voltage at a
steady rate, in order to suppress fluctuations (see figure below). In this case, perform this operation
when the PLL clock is not being used. If, however, the voltage falling speed is no more than 1 V/s,
it is permissible to perform this operation while using the PLL clock.
MB90495G Series
72 DS07-13713-6E
(5) Bus Read Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin Name Value Unit Remarks
Min Max
ALE pulse width tLHLL ALE tCP/2 − 20 ⎯ns
Valid address → ALE ↓ time tAVLL ALE, A23 to A16,
AD15 to AD00 tCP/2 − 20 ⎯ns
ALE ↓ → address valid time tLLAX ALE, AD15 to
AD00 tCP/2 − 15 ⎯ns
Valid address → RD ↓ time tAVRL A23 to A16,
AD15 to AD00, RD tCP − 15 ⎯ns
Valid address → Valid data input tAVDV A23 to A16,
AD15 to AD00 ⎯5 tCP/2 − 60 ns
RD pulse width tRLRH RD 3 tCP/2 − 20 ⎯ns
RD ↓ → valid data input tRLDV RD, AD15 to AD00 ⎯3 tCP/2 − 60 ns
RD ↑ → data hold time tRHDX RD, AD15 to AD00 0 ⎯ns
RD ↑ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 ⎯ns
RD ↑ → address valid time tRHAX RD, A23 to A16 tCP/2 − 10 ⎯ns
Valid address → CLK ↑ time tAVCH A23 to A16,
AD15 to AD00,
CLK tCP/2 − 20 ⎯ns
RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 20 ⎯ns
ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 ⎯ns
MB90495G Series
DS07-13713-6E 73
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.2 V
CC
0.8 V
CC
CLK
ALE
RD
A23 to A16
AD15 to AD00
t
RHLH
t
AVRL
t
AVLL
t
LLAX
t
LHLL
t
RLRH
t
RHAX
t
RHDX
t
RLCH
2.4 V
2.4 V
0.8 V
t
AVCH
0.2 V
CC
0.8 V
CC
t
AVDV
t
RLDV
2.4 V
t
LLRL
Address Read data
• Bus read timing
MB90495G Series
74 DS07-13713-6E
(6) Bus Write Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin Name Value Unit Remarks
Min Max
Valid Address → WR ↓ time tAVWL A23 to A16,
AD15 to AD00, WR tCP − 15 ⎯ns
WR pulse width tWLWH WR 3 tCP/2 − 20 ⎯ns
Valid data output → WR ↑ time tDVWH AD15 to AD00, WR 3 tCP/2 − 20 ⎯ns
WR ↑ → data hold time tWHDX AD15 to AD00, WR 20 ⎯ns
WR ↑ → address valid time tWHAX A23 to A16, WR tCP/2 − 10 ⎯ns
WR ↑ → ALE ↑ time tWHLH WR, ALE tCP/2 − 15 ⎯ns
WR ↑ → CLK ↑ time tWLCH WR, CLK tCP/2 − 20 ⎯ns
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
CLK
ALE
WR (WRL, WRH)
A23 to A16
AD15 to AD00
tWHLH
tAVWL tWLWH
tWHAX
tWHDX
tWLCH
tDVWH
Address Write data
MB90495G Series
DS07-13713-6E 75
(7) Ready Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
Note : Use the automatic ready function if the setup time for the falling edge of the RDY signal is not sufficient.
(8) Hold Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
Note : It will take at least 1 cycle from the time the HRQ pin is loaded until the HAK changes.
Parameter Symbol Pin Name Value Unit Remarks
Min Max
RDY setup time tRYHS RDY 45 ⎯ns
RDY hold time tRYHH RDY 0 ⎯ns
Parameter Symbol Pin Name Value Unit Remarks
Min Max
Pin in floating status → HAK ↓ time tXHAL HAK 30 tCP ns
HAK ↑ → pin valid time tHAHV HAK tCP 2 tCP ns
tRYHS tRYHH
2.4 V
0.8 VCC
0.2 VCC
0.8 VCC
CLK
ALE
RD/WR
RDY
Unweighted
RDY
Weighted
(1 cycle)
• Ready Input timing
HAK
t
XHAL
t
HAHV
2.4 V
0.8 V 2.4 V
2.4 V
0.8 V
0.8 V
Each pin High-Z
• Hold Timing
MB90495G Series
76 DS07-13713-6E
(9) UAR T Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
* : See “ (1) Clock Timing” for details about tCP (internal operating clock cycle time).
Notes : • AC characteristics are for CLK synchronous mode.
• CL is the load capacitor value connected to pins while testing.
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Max
Serial clock cycle time tSCYC SCK1 Internal shift clock
mode output pin :
CL = 80 pF + 1 TTL
8 tCP*⎯ns
SCK ↓ → SOT delay time tSLOV SCK1, SOT1 −80 + 80 ns
Valid SIN → SCK ↑tIVSH SCK1, SIN1 100 ⎯ns
SCK ↑ → valid SIN hold time tSHIX SCK1, SIN1 60 ⎯ns
Serial clock “H” pulse width tSHSL SCK1
External shift clock
mode output pin :
CL = 80 pF + 1 TTL
4 tCP ⎯ns
Serial clock “L” pulse width tSLSH SCK1 4 tCP ⎯ns
SCK ↓ → SOT delay time tSLOV SCK1, SOT1 ⎯150 ns
Valid SIN → SCK ↑tIVSH SCK1, SIN1 60 ⎯ns
SCK ↑ → valid SIN hold time tSHIX SCK1, SIN1 60 ⎯ns
MB90495G Series
DS07-13713-6E 77
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
MB90495G Series
78 DS07-13713-6E
(10) Timer Input Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
(11) Timer Output Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
(12) Trigger Input Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Max
Input pulse width tTIWH TIN0, TIN1, FRCK ⎯4 tCP ⎯ns
tTIWL IN0 to IN3, FRCK
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Max
CLK ↑ → TOUT change time tTO TOT0, TOT1,
PPG0 to PPG3 ⎯30 ⎯ns
Parameter Symbol Pin Name Condition Value Unit Remarks
Min Max
Input pulse width tTRGH
tTRGL INT0 to INT7,
ADTG ⎯5 tCP ⎯ns Normal mode
1⎯μs Stop mode
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
TIN0, TIN1,
IN0 to IN3,
FRCK
• Timer Input Timing
2.4 V
tTO
2.4 V
0.8 V
CLK
TOT0, TOT1,
PPG0 to PPG3
• Timer Output Timing
0.8 V
CC
0.8 V
CC
0.2 V
CC
0.2 V
CC
t
TRGH
t
TRGL
INT0 to INT7,
ADTG
• Trigger Input Timing
MB90495G Series
DS07-13713-6E 79
5. A/D Converter (VCC = AVCC = 5.0 V±5%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR − AVSS, TA = −40 °C to +125 °C)
(VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR − AVSS, TA = −40 °C to +105 °C)
* : Current (VCC = AVCC = AVR = 5.0 V) when A/D converter is not operating and CPU is halted.
Parameter Symbol Pin Name Value Unit Remarks
Min Typ Max
Resolution ⎯⎯ ⎯ 10 bit
Total error ⎯⎯ ⎯ ⎯±5.0 LSB
Nonlinearity error ⎯⎯ ⎯ ⎯±2.5 LSB
Differential linearity error ⎯⎯ ⎯ ⎯±1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVSS −
3.5 LSB AVSS +
0.5 LSB AVSS +
4.5 LSB V1 LSB =
(AVR - AVSS) /
1024
Full-scale transition voltage VFST AN0 to AN7 AVR −
6.5 LSB AVR −
1.5 LSB AVR +
1.5 LSB V
Conversion time ⎯⎯66 tCP ⎯⎯ns Machine clock
of 16 MHz
Sampling period ⎯⎯32 tCP ⎯⎯ns
Analog port input current IAIN AN0 to AN7 ⎯⎯10 μA
Analog input voltage VAIN AN0 to AN7 AVSS ⎯AVR V
Reference voltage ⎯AVR AVSS + 3.0 ⎯AVCC V
Power supply current IAAVCC ⎯27mA
IAH AVCC ⎯⎯ 5μA*
Reference voltage supply
current IRAVR ⎯0.9 1.3 mA
IRH AVR ⎯⎯ 5μA*
Inter-channel variation ⎯AN0 to AN7 ⎯⎯ 4LSB
MB90495G Series
80 DS07-13713-6E
6. A/D Converter Glossary
(Continued)
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero tr ansition point
( “00 0000 0000” ←→ “00 0000 0001” ) with the full-scale transition point
( “11 1111 1110” ←→ “11 1111 1111” ) from actual conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
ideal value.
Total error : The difference between the actual v alue and the theoretical v alue, which includes
zero-transition error/full-scale tr ansition error, linearity error, and differential linear-
ity error.
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVSS AVR
VNT
1.5 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
Actual conversion
characteristics
(actual measurement)
Actual conversion
characteristics
Ideal characteristics
Digital output
Analog input
Total error
Total error of digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
1 LSB = (ideal value) AVR − AVSS
1024 [V]
VOT (ideal value) = AVSS + 0.5 LSB [V]
VFST (ideal value) = AVR − 1.5 LSB [V]
VNT : The voltage to transition digital output from (N − 1) to N.
MB90495G Series
DS07-13713-6E 81
(Continued)
7. Notes on Using A/D Converter
Select the output impedance v alue for the e xternal circuit of analog input according to the follo wing conditions :
External circuit output impedance values of about 5 kΩ or lower are recommended.
If external capacitors are used, a capacitance of several thousand times the internal capacitor value is recom-
mended in order to minimize the effect of vo ltage distrib ution between the external and internal capacitor.
If the output impedance of the external circuit is too high, the sampling time for analog voltages may not be
sufficient (sampling period = 2.00 μs @ machine clock of 16 MHz) .
•About Error
The smaller the absolute value of | AVR - AVSS |, the greater the relative error.
3FF
3FE
3FD
004
003
002
001
AVSS AVR AVSS AVR
N + 1
N
N − 1
N − 2
VNT
VOT (actual measurement)
VFST
{1 LSB × (N − 1)
+ VOT }
Actual conversion
characteristics
(actual
measurement)
(actual
measurement)
Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Digital output
Digital output
Analog inputAnalog input
VNT (actual measurement)
V (N + 1) T
(actual
measurement)
Linearity error Differential linearity error
Linearity error of digital output N = VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
Differential linearity error of digital output N = V (N + 1) T − VNT
1 LSB − 1 LSB [LSB]
VFST − VOT
1022 [V]
1 LSB =
VOT : Voltage for transition from digital output 000H to 001H.
VFST : Voltage for transition from digital output 3FEH to 3FFH.
C
Comparator
Analog input R
Note : The figures given here are the suggested values.
MB90F497G, MB90F498G, MB90V495G R 3.2 kΩ, C 30 pF
MB90497G R 2.6 kΩ, C 28 pF
• Model Analog Input Circuit
MB90495G Series
82 DS07-13713-6E
8. Flash Memory Program/Erase Characteristics
Parameter Condition Value Unit Remarks
Min Typ Max
Sector erase time
TA = + 25 °C
VCC = 5.0 V
⎯115s
Excludes 00H programming prior
erasure
Chip erase time ⎯5⎯sExcludes 00H programming prior
erasure
Word (16-bit width)
programming time ⎯16 3,600 μs Excludes system-level overhead
Erase/Program cycle ⎯10,000 ⎯⎯cycle
MB90495G Series
DS07-13713-6E 83
■EXAMPLE CHARACTERISTICS
• MB90F497G/F498G
(Continued)
3.0 4.0 5.0
V
CC
(V)
I
CC
(mA)
6.0 7.0
45
40
35
30
25
20
15
10
5
0
f = 16 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
3.0 4.0 5.0
V
CC
(V)
I
CCS
(mA)
6.0 7.0
16
14
12
10
8
6
4
2
0
f = 16 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICC − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
ICCS − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
MB90495G Series
84 DS07-13713-6E
(Continued)
(Continued)
3.0 4.0 5.0
V
CC
(V)
I
CCL
(μA)
6.0 7.0
180
f = 8 kHz
160
140
120
100
80
60
40
20
0
3.0 4.0 5.0
V
CC
(V)
I
CCLS
(μA)
6.0 7.0
10
9
8
7
6
5
4
3
2
1
0
f = 8 kHz
ICCL − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
ICCLS − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
MB90495G Series
DS07-13713-6E 85
(Continued)
3.0 4.0 5.0
V
CC
(V)
I
CCT
(μA)
6.0 7.0
7
6
5
4
3
2
1
0
f = 8 kHz
0123456
I
OH (mA)
7 8 9 10 11 12
VCC - VOH (mV)
1000
900
800
700
600
500
400
300
200
100
00123456
IOL (mA)
7 8 9 10 11 12
VOL (V)
1000
900
800
700
600
500
400
300
200
100
0
ICCT − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
(VCC − VOH) − IOH
TA = + 25 °C, VCC = 4.5 V VOL − IOL
TA = + 25 °C, VCC = 4.5 V
MB90495G Series
86 DS07-13713-6E
• MB90497G
(Continued)
3.0 4.0 5.0
VCC (V)
ICC (mA)
6.0 7.0
45
40
35
30
25
20
15
10
5
0
f = 16 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
3.0 4.0 5.0
VCC (V)
ICCS (mA)
6.0 7.0
16
14
12
10
8
6
4
2
0
f = 16 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICC − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
ICCS − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
MB90495G Series
DS07-13713-6E 87
(Continued)
(Continued)
3.0 4.0 5.0
V
CC
(V)
I
CCL
(μA)
6.0 7.0
25
20
15
10
5
0
f = 8 kHz
3.0 4.0 5.0
V
CC
(V)
I
CCLS
(μA)
6.0 7.0
10
9
8
7
6
5
4
3
2
1
0
f = 8 kHz
ICCL − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
ICCLS − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
MB90495G Series
88 DS07-13713-6E
(Continued)
3.0 4.0 5.0
V
CC
(V)
I
CCT
(μA)
6.0 7.0
7
6
5
4
3
2
1
0
f = 8 kHz
0123456
I
OH (mA)
7 8 9 10 11 12
VCC - VOH (mV)
1000
900
800
700
600
500
400
300
200
100
00123456
IOL (mA)
7 8 9 10 11 12
VOL (V)
1000
900
800
700
600
500
400
300
200
100
0
ICCT − VCC
TA = + 25 °C, external clock operation
f = internal operation frequency
(VCC − VOH) − IOH
TA = + 25 °C, VCC = 4.5 V VOL − IOL
TA = + 25 °C, VCC = 4.5 V
MB90495G Series
DS07-13713-6E 89
■ORDERING INFORMATION
Part Number Package Remarks
MB90F497GPF
MB90497GPF
MB90F498GPF
64-pin plastic QFP
(FPT-64P-M06)
MB90F497GPMC
MB90497GPMC
MB90F498GPMC
64-pin plastic LQFP
(FPT-64P-M23)
MB90495G Series
90 DS07-13713-6E
■PACKAGE DIMENSIONS
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic QFP Lead pitch 1.00 mm
Package width ×
package length 14 × 20 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 3.35 mm MAX
Code
(Reference) P-QFP64-14×20-1.00
64-pin plastic QFP
(FPT-64P-M06)
(FPT-64P-M06)
C
2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6
0.20(.008)
M
18.70±0.40
(.736±.016)
14.00±0.20
(.551±.008)
1.00(.039)
INDEX
0.10(.004)
119
20
32
52
64
3351
20.00±0.20(.787±.008)
24.70±0.40(.972±.016)
0.42±0.08
(.017±.003)
0.17±0.06
(.007±.002)
0~8°
1.20±0.20
(.047±.008)
3.00 +0.35
–0.20 (Mounting height)
.118+.014
–.008
0.25 +0.15
–0.20
.010 +.006
–.008
(Stand off)
Details of "A" part
"A" 0.10(.004)
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB90495G Series
DS07-13713-6E 91
(Continued)
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
64-pin plastic LQFP Lead pitch 0.65 mm
Package width ×
package length 12.0 × 12.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference) P-LFQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M23)
(FPT-64P-M23)
C
2003 FUJITSU LIMITED F64034S-c-1-1
0.65(.026)
0.10(.004)
116
17
3249
64
3348
*12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002) M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059 –
.004
+.008
–
0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB90495G Series
92 DS07-13713-6E
■MAIN CHANGES IN THIS EDITION
The vertical lines marked in the left side of the page show the changes.
Page Section Change Results
18 ■ BLOCK DIAGRAM
16-bit reload timer Corrected the direction of arrow for TIN0, TIN1 signal.
“→ (output)”→ “← (input)”
23 ■ I/O MAP
Address : 0000AAHCorrected the Initial Value of “Watch timer control register”.
10001000B → 1X001000B
MB90495G Series
DS07-13713-6E 93
MEMO
MB90495G Series
94 DS07-13713-6E
MEMO
MB90495G Series
DS07-13713-6E 95
MEMO
MB90495G Series
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