HD74HC563/HD74HC573
Octal Transparent Latches (with 3-state outputs)
ADE-205-509 (Z)
1st. Edition
Sep. 2000
Description
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D
inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements.
Features
High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Outputs
Output Control Latch Enable Data HD74HC563 HD74HD573
LHHLH
LHLHL
LL XQ
0Q
0
HX XZZ
Q
0
: level of Q before the indicated Steady-sate input conditions were established.
Q0: complement of Q0 or level of Q before the indicated Steady-state input conditions were established.
HD74HC563/HD74HC573
2
Pin Arrangement
HD74HC563
1
2
3
4
5
6
7
8
9
10
(Top view)
11
12
13
14
15
16
17
18
19
20
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
DQ
Latch
Enable
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
HD74HC563/HD74HC573
3
HD74HC573
1
2
3
4
5
6
7
8
9
10
(Top view)
11
12
13
14
15
16
17
18
19
20
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
DQ
Latch
Enable
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
DQ
OE
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage range VCC –0.5 to +7.0 V
Input voltage VIN –0.5 to VCC + 0.5 V
Output voltage VOUT –0.5 to VCC + 0.5 V
Output current IOUT ±35 mA
DC current drain per VCC , GND ICC, IGND ±75 mA
DC input diode current IIK ±20 mA
DC output diode current IOK ±20 mA
Power Dissipation per package PT500 mW
Storage temperature Tstg –65 to +150 °C
HD74HC563/HD74HC573
4
Block Diagram
HD74HC563
1D D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
2D
3D
4D
5D
6D
7D
8D 8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
LE
OC
HD74HC563/HD74HC573
5
HD74HC573
1D D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
D
C
C
Q
2D
3D
4D
5D
6D
7D
8D 8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
LE
OC
HD74HC563/HD74HC573
6
DC Characteristics
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Input voltage VIH 2.0 1.5 1.5 V
4.5 3.15 3.15
6.0 4.2 4.2
VIL 2.0 0.5 0.5 V
4.5 1.35 1.35
6.0 1.8 1.8
Output voltage VOH 2.0 1.9 2.0 1.9 V Vin = VIH or VIL IOH = –20 µA
4.5 4.4 4.5 4.4
6.0 5.9 6.0 5.9
4.5 4.18 4.13 IOH = –6 mA
6.0 5.68 5.63 IOH = –7.8 mA
VOL 2.0 0.0 0.1 0.1 V Vin = VIH or VIL IOL = 20 µA
4.5 0.0 0.1 0.1
6.0 0.0 0.1 0.1
4.5 0.26 0.33 IOL = 6 mA
6.0 0.26 0.33 IOL = 7.8 mA
Off-state output
current IOZ 6.0 ±0.5 ±5.0 µA Vin = VIH or VIL,
Vout = VCC or GND
Input current Iin 6.0 ±0.1 ±1.0 µA Vin = VCC or GND
Quiescent supply
current ICC 6.0 4.0 40 µA Vin = VCC or GND, Iout = 0 µA
HD74HC563/HD74HC573
7
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Propagation delay tPLH 2.0 110 140 ns Data to Q
time tPHL 4.5 11 22 28
6.0 19 24
tPLH 2.0 115 145 ns Clock to Q
tPHL 4.5 13 23 29
6.0 20 25
Output enable tZH 2.0 150 190 ns
time tZL 4.5 14 30 38
6.0 26 33
Output disable tHZ 2.0 150 190 ns
time tLZ 4.5 15 30 38
6.0 26 33
Setup time tsu 2.0 75 90 ns
4.5 15 2 19
6.0 13 16
Hold time th2.0 5 5 ns
4.5 5 –1 5
6.0 5 5
Pulse width tw2.0 80 100 ns
4.5 16 4 20
6.0 14 17
Output rise/fall tTLH 2.0 60 75 ns
time tTHL 4.5 4 12 15
6.0 10 13
Input capacitance Cin 5 10 10 pF
HD74HC563/HD74HC573
8
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DP-20N
Conforms
1.26 g
Unit: mm
0.51 Min
2.54 Min 5.08 Max
7.62
0.25
+ 0.11
– 0.05
2.54 ± 0.25 0.48 ± 0.10
24.50
25.40 Max
0.89 1.30
6.30
7.00 Max
110
1120
0° – 15°
1.27 Max
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-20DA
Conforms
0.31 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
*0.42 ± 0.08
0.12
0.15
M
20
10
1
*0.22 ± 0.05
0.80 Max
11
12.6
5.5
2.20 Max
13 Max
0° – 8°
0.70 ± 0.20
+ 0.20
– 0.30
7.80
1.27
0.10 ± 0.10
1.15
0.40 ± 0.06
0.20 ± 0.04
HD74HC563/HD74HC573
9
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-20DB
Conforms
0.52 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.12
0.15
0° – 8°
M
20 11
0.20 ± 0.10
1
1.27
10
12.8
13.2 Max
7.50
2.65 Max
*0.27 ± 0.05
*0.42 ± 0.08
+ 0.57
– 0.30
0.70
+ 0.25
– 0.40
10.40
1.45
0.935 Max
0.40 ± 0.06
0.25 ± 0.04
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
TTP-20DA
0.07 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.50 ± 0.10
0° – 8°
*0.17 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
110
20 11
4.40
6.50
6.80 Max
*0.22
+0.08
–0.07
0.07
+0.03
–0.04
1.0
0.65 Max
0.20 ± 0.06
0.15 ± 0.04
HD74HC563/HD74HC573
10
Cautions
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of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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5. This product is not designed to be radiation resistant.
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