1. General description
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the dat a input is transferred to the Q-ou tput on the LOW -to-HIGH transition
of the clock pulse. The D-input must be stab le one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 Vand 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the outpu t, preventing the damaging ba ckflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 200 V
24 mA output drive (VCC =3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Spe cified from 40 Cto+85C and 40 Cto+125C.
74LVC1G79
Single D-type flip-flop; positive-edge trigger
Rev. 12 — 5 December 2016 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 2 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lo wer left corner of the device, below the marking code.
5. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G79GW 40 Cto+125C TSSOP5 plastic thin shrink small outline package;
5 leads; body width 1.25 mm SOT353-1
74LVC1G79GV 40 Cto+125C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G79GM 40 Cto+125C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm SOT886
74LVC1G79GF 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 10.5 mm SOT891
74LVC1G79GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74LVC1G79GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
74LVC1G79GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5
terminals; body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking codes
Type number Marking[1]
74LVC1G79GW VP
74LVC1G79GV V79
74LVC1G79GM VP
74LVC1G79GF VP
74LVC1G79GN VP
74LVC1G79GS VP
74LVC1G79GX VP
Fig 1. Logic symbol Fig 2. IEC logic symbol
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© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 3 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
6. Pinning information
6.1 Pinning
Fig 3. Logic diagra m
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Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886
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Fig 6. Pin configuration SOT891, SOT1115 and
SOT1202 Fig 7. Pin co nfiguration SOT1226 (X2SON5)
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© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 4 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
Table 3. Pin description
Symbol Pin Description
TSSOP5 and X2SON5 XSON6
D 1 1 data input
CP 2 2 clock pulse inp ut
GND 3 3 ground (0 V)
Q 4 4 data output
n.c. - 5 not connected
VCC 5 6 supply voltage
Table 4. Function table[1]
Input Output
CP D Q
LL
HH
LXq
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 5 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VOoutput voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V
IOoutput current VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125 C[3] -250mW
Tstg storage temperature 65 +150 C
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temp erature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 6 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb =40 C to +85 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC --V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC --V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V
IO=4mA; V
CC = 1.65 V 1.2 - - V
IO=8mA; V
CC = 2.3 V 1.9 - - V
IO=12 mA; VCC = 2.7 V 2.2 - - V
IO=24 mA; VCC = 3.0 V 2.3 - - V
IO=32 mA; VCC = 4.5 V 3.8 - - V
VOL LOW-level output voltage VI=V
IH or VIL
IO=100A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.45 V
IO=8mA; V
CC = 2.3 V - - 0.3 V
IO=12mA; V
CC = 2.7 V - - 0.4 V
IO=24mA; V
CC = 3.0 V - - 0.55 V
IO=32mA; V
CC = 4.5 V - - 0.55 V
IIinput leakage current VI= 5.5 V or GND; VCC =0Vto5.5V - 0.1 1A
IOFF power-off leakage current VCC = 0 V; VIor VO=5.5V - 0.1 2A
ICC supply current VI= 5.5 V or GND;
VCC =1.65Vto5.5V; I
O=0A -0.14A
ICC additional supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC 0.6 V; IO=0A - 5 500 A
CIinput capacitance V CC = 3.3 V; VI = GND to VCC -5-pF
Tamb =40 C to +125 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC --V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC --V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 7 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
[1] All typical values are measured at VCC = 3.3 V and Tamb =25C.
11. Dynamic characteristics
VOH HIGH-level output voltage VI=V
IH or VIL
IO=100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V
IO=4mA; V
CC = 1.65 V 0.95 - - V
IO=8mA; V
CC = 2.3 V 1.7 - - V
IO=12 mA; VCC = 2.7 V 1.9 - - V
IO=24 mA; VCC = 3.0 V 2.0 - - V
IO=32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI=V
IH or VIL
IO=100A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.70 V
IO=8mA; V
CC = 2.3 V - - 0.45 V
IO=12mA; V
CC = 2.7 V - - 0.60 V
IO=24mA; V
CC = 3.0 V - - 0.80 V
IO=32mA; V
CC = 4.5 V - - 0.80 V
IIinput leakage current VI= 5.5 V or GND; VCC =0Vto5.5V - - 1A
IOFF power-off leakage current VCC = 0 V; VIor VO=5.5V - - 2A
ICC supply current VI= 5.5 V or GND;
VCC =1.65Vto5.5V; I
O=0A --4A
ICC additional supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC 0.6 V; IO=0A - - 500 A
Table 7. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay CP to Q; see Figure 8 [2]
VCC = 1.65 V to 1.95 V 1.0 3.6 9.9 1.0 12.5 ns
VCC = 2.3 V to 2.7 V 0.5 2.3 7.0 0.5 9.0 ns
VCC = 2.7 V 0.5 2.6 6.0 0.5 8.0 ns
VCC = 3.0 V to 3.6 V 0.5 2.2 5.0 0.5 6.5 ns
VCC = 4.5 V to 5.5 V 0.5 1.7 3.8 0.5 5.0 ns
tsu set-up time D to CP; see Figure 9
VCC = 1.65 V to 1.95 V 2.5 1.4 - 2.5 - ns
VCC = 2.3 V to 2.7 V 1.7 0.9 - 1.7 - ns
VCC = 2.7 V 1.7 0.9 - 1. 7 - ns
VCC = 3.0 V to 3.6 V 1.3 0.6 - 1.2 - ns
VCC = 4.5 V to 5.5 V 1.2 0.6 - 1.2 - ns
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 8 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
[1] Typical values are measured at Tamb =25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time D to CP; see Figure 9
VCC = 1.65 V to 1.95 V 0 0.7 - 0 - ns
VCC = 2.3 V to 2.7 V 0 0.4 - 0 - ns
VCC = 2.7 V +0.5 0.3 - 0.5 - ns
VCC = 3.0 V to 3.6 V +0.5 0.3 - 0.5 - ns
VCC = 4.5 V to 5.5 V +0.5 0.2 - 0.5 - ns
tWpulse width CP HIGH or LOW;
see Figure 9
VCC = 1.65 V to 1.95 V 3.0 1.1 - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 0.7 - 2.5 - ns
VCC = 2.7 V 2.5 0.6 - 2.5 - ns
VCC = 3.0 V to 3.6 V 2.5 0.6 - 2.5 - ns
VCC = 4.5 V to 5.5 V 2.0 0.5 - 2.0 - ns
fmax maximum
frequency CP; see Figure 9
VCC = 1.65 V to 1.95 V 160 250 - 160 - MHz
VCC = 2.3 V to 2.7 V 160 300 - 160 - MHz
VCC = 2.7 V 160 350 - 160 - MHz
VCC = 3.0 V to 3.6 V 160 450 - 160 - MHz
VCC = 4.5 V to 5.5 V 200 500 - 200 - MHz
CPD power dissipation
capacitance VI = GND to VCC;
VCC = 3.3 V [3] -17---pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 9 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
12. Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
Fig 8. Clock (CP) to output (Q) propagation delay times
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Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
Fig 9. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold
times and maximum clock pu lse frequency
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© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 10 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Table 9. Measurement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 VCC 0.5 VCC
2.3 V to 2.7 V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5 V 0.5 VCC 0.5 VCC
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr=t
fCLRLtPLH, tPHL
1.65 V to 1.95 V VCC 2.0ns 30pF 1kopen
2.3 V to 2.7 V VCC 2.0ns 30pF 500open
2.7V 2.7V 2.5ns 50pF 500open
3.0V to 3.6V 2.7V 2.5ns 50pF 500open
4.5 V to 5.5 V VCC 2.5ns 50pF 500open
© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 11 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
13. Package outline
Fig 11. Package outline SOT353-1 (TSSOP5)
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© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 12 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Fig 12. Package outline SOT753 (SC-74A)
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© Nexperia B.V. 2017. All rights reserved
74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 13 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Fig 13. Package outline SOT886 (XSON6)
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Product data sheet Rev. 12 — 5 December 2016 14 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Fig 14. Package outline SOT891 (XSON6)
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74LVC1G79 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 12 — 5 December 2016 15 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Fig 15. Package outline SOT1115 (XSON6)
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Product data sheet Rev. 12 — 5 December 2016 16 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Fig 16. Package outline SOT1202 (XSON6)
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Product data sheet Rev. 12 — 5 December 2016 17 of 21
Nexperia 74LVC1G79
Single D-type flip-flop; positive-edge trigger
Fig 17. Package outline SOT1226 (X2SON5)
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