LTC4267CGN-1#PBF - ANALOG DEVICES

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Typical applicaTion

FeaTures DescripTion

Power over Ethernet

IEEE 802.3af PD Interface with

Integrated Switching Regulator

The LT C

4267-1 combines an IEEE 802.3af compliant

Powered Device (PD) interface with a current mode switch-

ing regulator, providing a complete power solution for PD

applications. The LTC4267-1 integrates the 25k signature

resistor, classification current source, thermal overload

protection, signature disable and power good signal along

with an undervoltage lockout optimized for use with the

IEEE-required diode bridge. The LTC4267-1 provides an

increased operational current limit, maximizing power

available for class 3 applications.

The current mode switching regulator is designed for

driving a 6V rated N-channel MOSFET and features pro-

grammable slope compensation, soft-start, and constant

frequency operation, minimizing noise even with light

loads. The LTC4267-1 includes an onboard error amplifier

and voltage reference allowing use in both isolated and

nonisolated configurations.

The LTC4267-1 is available in a space saving, low profile

16-pin SSOP package.

Class 2 PD with 3.3V Isolated Power Supply

applicaTions

n Complete Power Interface Port for IEEE 802

.3af

Powered Device (PD)

n Onboard 100V, UVLO Switch

n Precision Dual Level Inrush Current Limit

n Integrated Current Mode Switching Regulator

n Onboard 25k Signature Resistor with Disable

n Programmable Classification Current (Class 0-4)

n Thermal Overload Protection

n Power Good Signal

n Integrated Error Amplifier and Voltage Reference

n Low Profile 16-Pin SSOP Package

n IP Phone Power Management

n Wireless Access Points

n Security Cameras

n Power over Ethernet

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

LTPoE++ is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

PVCC

PWRGD

NGATE

SENSE

ITH/RUN

VFB

PGND

POUT

VPORTP

RCLASS

SIGDISA

VPORTN

LTC4267-1

RCLASS

68.1Ω

5µF

MIN

10k

470Ω

100k

60.4k

PVCC

4.7µF

320µF

MIN

22nF

•

PA1133

PS2911

BAS516

TLV431

SBM1040

SMAJ58A

3.3V

1.5A

CHASSIS

HD01

–

HD01

–48V

FROM

DATA PAIR

–48V

FROM

SPARE PAIR

42671 TA01

Si3440

0.1Ω

6.8k

10k

0.1µF

LTC4267-1

42671fa

For more information www.linear.com/4267-1

pin conFiguraTionabsoluTe MaxiMuM raTings

VPORTN with Respect to VPORTP Voltage .. 0.3V to –100V

POUT, SIGDISA, PWRGD

Voltage .....................VPORTN + 100V to VPORTN –0.3V

PVCC to PGND Voltage (Note 2)

Low Impedance Source ........................... –0.3V to 8V

Current Fed .......................................... 5mA into PVCC

RCLASS Voltage ................VPORTN + 7V to VPORTN – 0.3V

PWRGD Current .....................................................10mA

RCLASS Current ....................................................100mA

NGATE to PGND Voltage ...........................–0.3V to PVCC

VFB, ITH/RUN to PGND Voltages ...............–0.3V to 3.5V

SENSE to PGND Voltage .............................. –0.3V to 1V

NGATE Peak Output Current (<10μs) ...........................1A

Operating Ambient Temperature Range

LTC4267C-1 ............................................. 0°C to 70°C

LTC4267I-1 ..........................................–40°C to 85°C

Junction Temperature ........................................... 150°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

(Note 1)

TOP VIEW

GN PACKAGE

16-LEAD NARROW PLASTIC SSOP

PGND

ITH/RUN

NGATE

PVCC

RCLASS

VPORTN

PGND

VFB

SENSE

VPORTP

SIGDISA

PWRGD

POUT

PGND

TJMAX = 150°C, θJA = 90°C/W

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4267CGN-1#PBF LTC4267CGN-1#TRPBF 4267-1 16-Lead Narrow Plastic SSOP 0°C to 70°C

LTC4267IGN-1#PBF LTC4267IGN-1#TRPBF 4267I-1 16-Lead Narrow Plastic SSOP –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4267CGN-1 LTC4267CGN-1#TR 4267-1 16-Lead Narrow Plastic SSOP 0°C to 70°C

LTC4267IGN-1 LTC4267IGN-1#TR 4267I-1 16-Lead Narrow Plastic SSOP –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC4267-1

42671fa

For more information www.linear.com/4267-1

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VPORTN Supply Voltage

Maximum Operating Voltage

Signature Range

Classification Range

UVLO Turn-On Voltage

UVLO Turn-Off Voltage

Voltage with Respect to VPORTP Pin

(Notes 4, 5, 6)

–1.5

–12.5

–34.8

–29.3

–36.0

–30.5

–57

–9.5

–21

–37.2

–31.5

VTURNON PVCC Turn-On Voltage Voltage with Respect to PGND l7.8 8.7 9.2 V

VTURNOFF PVCC Turn-Off Voltage Voltage with Respect to PGND l4.6 5.7 6.8 V

VHYST PVCC Hysteresis VTURNON – VTURNOFF l1.5 3.0 V

VCLAMP1mA PVCC Shunt Regulator Voltage IPVCC = 1mA, VITH/RUN = 0V,

Voltage with Respect to PGND

l8.3 9.4 10.3 V

VMARGIN VCLAMP1mA – VTURNON Margin l0.05 0.6 V

IVPORTN_ON VPORTP Supply Current when ON VPORTN = –48V, POUT, PWRGD, SIGDISA Floating l3 mA

IPVCC_ON PVCC Supply Current

Normal Operation

Start-Up

(Note 7)

VITH/RUN – PGND = 1.3V

PVCC – PGND = VTURNON – 100mV

240

350

µA

IVPORTN_CLASS VPORTN Supply Current During

Classification

VPORTN = –17.5V, POUT Tied to VPORTP, RCLASS,

SIGDISA Floating (Note 8)

l0.35 0.5 0.65 mA

ΔICLASS Current Accuracy During Classification 10mA < ICLASS < 40mA, –12.5V ≤ VPORTN ≤ –21V

(Note 9)

l±3.5 %

RSIGNATURE Signature Resistance –1.5V ≤ VPORTN ≤ – 9.5V, POUT Tied to VPORTP,

IEEE 802.3af 2-Point Measurement (Notes 4, 5)

l23.25 26.00 kΩ

RINVALID Invalid Signature Resistance –1.5V ≤ VPORTN ≤ –9.5V, SIGDISA and POUT Tied to

VPORTP, IEEE 802.3af 2-Point Measurement

(Notes 4, 5)

l9 11.8 kΩ

VIH Signature Disable

High Level Input Voltage

With Respect to VPORTN

High Level Invalidates Signature (Note 10)

l3 57 V

VIL Signature Disable

Low Level Input Voltage

With Respect to VPORTN

Low Level Enables Signature

l0.45 V

RINPUT Signature Disable, Input Resistance With Respect to VPORTN l100 kΩ

VPG_OUT Power Good Output Low Voltage I = 1mA VPORTN = –48V,

PWRGD Referenced to VPORTN

l0.5 V

VPG _FALL

VPG_RISE

Power Good Trip Point VPORTN = –48V, Voltage between VPORTN and POUT

POUT Falling

POUT Rising

1.3

2.7

1.5

3.0

1.7

3.3

IPG_LEAK Power Good Leakage Current VPORTN = 0V, PWRGD FET Off, VPWRGD = 57V l1 µA

RON On-Resistance I = 300mA, VPORTN = –48V, Measured from

VPORTN to POUT

1.0 1.6

VITHSHDN Shutdown Threshold (at ITH/RUN) PVCC – PGND = VTURNON + 100mV l0.15 0.28 0.45 V

ITHSTART Start-Up Current Source at ITH/RUN VITH/RUN – PGND = 0V, PVCC – PGND = 8V 0.2 0.3 0.4 µA

VFB Regulated Feedback Voltage Referenced to PGND, PVCC – PGND = 8V (Note 11) l0.780 0.800 0.812 V

IFB VFB Input Current PVCC – PGND = 8V (Note 11) 10 50 nA

gmError Amplifier Transconductance ITH/RUN Pin Load = ±5µA (Note 11) 200 333 500 µA/V

ΔVO(LINE) Output Voltage Line Regulation VTURNOFF < PVCC < VCLAMP (Note 11) 0.05 mV/V

ΔVO(LOAD) Output Voltage Load Regulation ITH/RUN Sinking 5µA, PVCC – PGND = 8V (Note 11)

ITH/RUN Sourcing 5µA, PVCC – PGND = 8V (Note 11)

mV/µA

IPOUT_LEAK POUT Leakage VPORTN = 0V, Power MOSFET Off,

POUT = 57V (Note 12)

l150 µA

LTC4267-1

42671fa

For more information www.linear.com/4267-1

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ILIM_HI Input Current Limit, High Level VPORTN = –48V, POUT = –43V (Note 13, 14) l350 450 mA

ILIM_LO Input Current Limit, Low Level VPORTN = –48V, POUT = –43V (Note 13, 14) l90 205 mA

fOSC Oscillator Frequency VITH/RUN – PGND = 1.3V, PVCC – PGND = 8V 180 200 240 kHz

DCON(MIN) Minimum Switch On Duty Cycle VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V,

PVCC – PGND = 8V

6 8 %

DCON(MAX) Maximum Switch On Duty Cycle VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V,

PVCC – PGND = 8V

70 80 90 %

tRISE NGATE Drive Rise Time CLOAD = 3000pF, PVCC – PGND = 8V 40 ns

tFALL NGATE Drive Fall Time CLOAD = 3000pF, PVCC – PGND = 8V 40 ns

VIMAX Peak Current Sense Voltage RSL = 0, PVCC – PGND = 8V (Note 15) l90 100 115 mV

ISLMAX Peak Slope Compensation Output Current PVCC – PGND = 8V (Note 16) 5 µA

tSFST Soft-Start Time PVCC – PGND = 8V 1.4 ms

TSHUTDOWN Thermal Shutdown Trip Temperature (Notes 13, 17) 140 °C

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: PVCC internal clamp circuit self regulates to 9.4V with respect to

PGND.

Note 3: The LTC4267-1 operates with a negative supply voltage in the

range of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface

are always referred to in terms of absolute magnitude. Terms such as

“maximum negative voltage” refer to the largest negative voltage and

a “rising negative voltage” refers to a voltage that is becoming more

negative.

Note 4: The LTC4267-1 is designed to work with two polarity protection

diode drops between the PSE and PD. Parameter ranges specified in the

Electrical Characteristics section are with respect to this product pins and

are designed to meet IEEE 802.3af specifications when these diode drops

are included. See the Application Information section.

Note 5: Signature resistance is measured via the two-point ∆V/∆I method

as defined by IEEE 802.3af. The PD signature resistance is offset from

the 25k to account for diode resistance. With two series diodes, the total

PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af

specifications. The minimum probe voltages measured at the LTC4267-1

pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and

–9.5V.

Note 6: The PD interface includes hysteresis in the UVLO voltages to

preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD

will power up from a voltage source with 20Ω series resistance on the first

trial.

Note 7: Dynamic Supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 8: IVPORTN_CLASS does not include classification current

programmed at the RCLASS pin. Total current in classification mode will be

IVPORTN_CLASS + ICLASS (See Note 9).

Note 9: ICLASS is the measured current flowing through RCLASS. ∆ICLASS

accuracy is with respect to the ideal current defined as ICLASS = 1.237/

RCLASS. The current accuracy does not include variations in RCLASS

resistance. The total classification current for a PD also includes the IC

quiescent current (IVPORTN_CLASS). See Applications Information.

Note 10: To disable the 25k signature, tie SIGDISA to VPORTP or hold

SIGDISA high with respect to VPORTN. See Applications Information.

Note 11: The switching regulator is tested in a feedback loop that servos

VFB to the output of the error amplifier while maintaining ITH/RUN at the

midpoint of the current limit range.

Note 12: IPOUT_LEAK includes current drawn through POUT by the power

good status circuit. This current is compensated for in the 25k signature

resistance and does not affect PD operation.

Note 13: The LTC4267-1 PD Interface includes thermal protection. In

the event of an overtemperature condition, the PD interface will turn off

the switching regulator until the part cools below the overtemperature

limit. The LTC4267-1 is also protected against thermal damage from

incorrect classification probing by the PSE. If the LTC4267-1 exceeds the

overtemperature threshold, the classification load current is disabled.

Note 14: The PD interface includes dual level input current limit. At turn-

on, before the POUT load capacitor is charged, the PD current level is set

to a low level. After the load capacitor is charged and the POUT – VPORTN

voltage difference is below the power good threshold, the PD switches to

high level current limit. The PD stays in high level current limit until the

input voltage drops below the UVLO turn-off threshold.

Note 15: Peak current sense voltage is reduced dependent on duty cycle

and an optional external resistor in series with the SENSE pin (RSL). For

details, refer to the programmable slope compensation feature in the

Applications Information section.

Note 16: Guaranteed by design.

Note 17: The PD interface includes overtemperature protection that is

intended to protect the device from momentary overload conditions.

Junction temperature will exceed 125°C when overtemperature protection

is active. Continuous operation above the specified maximum operating

junction temperature may impair device reliability.

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Typical perForMance characTerisTics

Input Current vs Input Voltage

25k Detection Range Input Current vs Input Voltage Input Current vs Input Voltage

Input Current vs Input Voltage

Signature Resistance vs

Input Voltage

Normalized UVLO Threshold vs

Temperature

Power Good Output Low Voltage

vs Current POUT Leakage Current Current Limit vs Input Voltage

VPORTN VOLTAGE (V)

INPUT CURRENT (mA)

0.1

0.2

0.3

0.4

0.5

–2 –4 –6 –8

42671 G01

–10

TA = 25°C

VPORTN VOLTAGE (V)

INPUT CURRENT (mA)

–10 –20 –30 –40

42671 G02

–50 –60

CLASS 4

CLASS 3

CLASS 2

CLASS 1

CLASS 0

TA = 25°C

VPORTN VOLTAGE (V)

–12

9.0

INPUT CURRENT (mA)

9.5

10.5

11.0

11.5

–14 –16

42671 G03

10.0

–18 –20 –22

12.0

85°C

–40°C

CLASS 1 OPERATION

VPORTN VOLTAGE (V)

INPUT CURRENT (mA)

–45 –55

42671 G04

–60–40 –50

EXCLUDES ANY LOAD CURRENT

TA = 25°C

VPORTN VOLTAGE (V)

–1

V1:

V2:

SIGNATURE RESISTANCE (kΩ)

–3 –5

42671 G05

–7 –9

–6 –10

–2 –4 –8

RESISTANCE =

DIODES: S1B

TA = 25°C

∆V

ΔI

V2 – V1

I2 – I1

IEEE UPPER LIMIT

IEEE LOWER LIMIT

LTC4267-1 + 2 DIODES

LTC4267-1 ONLY

TEMPERATURE (°C)

–40

–2

NORMALIZED UVLO THRESHOLD (%)

–1

–20 0 20 40

42671 G06

60 80

APPLICABLE TO TURN-ON

AND TURN-0FF THRESHOLDS

CURRENT (mA)

VPG_OUT (V)

42671 G07

024610

4TA = 25°C

POUT PIN VOLTAGE (V)

VOUT CURRENT (µA)

120

20 40

42671 G08

VIN = 0V

TA = 25°C

VPORTN VOLTAGE (V)

–40

CURRENT LIMIT (mA)

200

–60

42671 G09

100 –45 –50 –55

400

300

85°C

– 40°C

HIGH CURRENT MODE

LOW CURRENT MODE

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Typical perForMance characTerisTics

Reference Voltage vs

Temperature

Reference Voltage vs

Supply Voltage

Oscillator Frequency vs

Temperature

Oscillator Frequency vs

Supply Voltage

PVCC Undervoltage Lockout

Thresholds vs Temperature

PVCC Shunt Regulator Voltage vs

Temperature

IPVCC Supply Current vs

Temperature

TEMPERATURE (°C)

–50

VFB VOLTAGE (mV)

70 90

42671 G10

–10 10–30 30 50 110

812

808

804

800

796

792

788

PVCC = 8V

PVCC SUPPLY VOLTAGE (V)

799.0

VFB VOLTAGE (mV)

799.2

799.6

799.8

800.0

801.0

800.4

788.5

42671 G11

799.4

800.6

800.8

800.2

6.5 7.5 99.5

TA = 25°C

PVCC ≤ VCLAMP1mA

TEMPERATURE (°C)

–50

OSCILLATOR FREQUENCY (kHz)

–10 30 70 110

42671 G12

–30 10 50 90

PVCC = 8V

(WITH RESPECT TO PGND)

240

230

220

210

200

190

180

PVCC SUPPLY VOLTAGE (V)

190

OSCILLATOR FREQUENCY (kHz)

194

198

202

6.5 77.5 8

42671 G13

8.5

206

210

192

196

200

204

208

TA = 25°C

TEMPERATURE (°C)

–50

5.0

PVCC UNDERVOLTAGE LOCKOUT (V)

5.5

6.5

7.0

7.5

10.0

8.5

–10 30 50

42671 G14

6.0

9.0

9.5

8.0

–30 10 80 90 110

VTURNON

VTURNOFF

TEMPERATURE (°C)

–50

9.0

PVCC (V)

9.1

9.3

9.4

9.5

10.0

9.7

–10 30 50

42671 G15

9.2

9.8

9.9

9.6

–30 10 70 90 110

IPVCC = 1mA

TEMPERATURE (°C)

–50

215

SUPPLY CURRENT (µA)

220

230

235

240

265

250

–10 30 50

42671 G16

225

255

260

245

–30 10 70 90 110

PVCC = 8V

VITH/RUN = 1.3V

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Typical perForMance characTerisTics

Peak Current Sense Voltage vs

Temperature Soft-Start Time vs Temperature

Start-Up IPVCC Supply Current vs

Temperature

ITH/RUN Shutdown Threshold vs

Temperature

ITH/RUN Start-Up Current Source

vs Temperature

TEMPERATURE (°C)

–50

START-UP SUPPLY CURRENT (µA)

–10 30 70 110

42671 G17

–30 10 50 90

PVCC = VTURNON – 0.1V

TEMPERATURE (°C)

–50

SHUTDOWN THRESHOLD (mV)

300

350

400

70 90

42671 G18

250

200

–10 10–30 30 50 110

150

100

450

TEMPERATURE (°C)

–50

ITH/RUN PIN CURRENT SOURCE (nA)

100

200

300

400

–10 30 70 110

42671 G19

500

600

–30 10 50 90

PVCC = VTURNON + 0.1V

VITH/RUN = 0V

TEMPERATURE (°C)

–50

SENSE PIN VOLTAGE (mV)

100

110

42671 G20

80 –10 30 70

–30 10 50 90

120

105

115

PVCC = 8V

TEMPERATURE (°C)

–50

SOFT-START TIME (ms)

2.0

3.0

110

42671 21

1.0

0–10 30 70

–30 10 50 90

4.0

1.5

2.5

0.5

3.5

LTC4267-1

42671fa

For more information www.linear.com/4267-1

pin FuncTions

PGND (Pin 1, 8, 9, 16): Switching Regulator Negative

Supply. This pin is the negative supply rail for the switching

regulator controller and must be tied to POUT.

ITH/RUN (Pin 2): Current Threshold/Run Input. This pin

performs two functions. It serves as the switching regula-

tor error amplifier compensation point as well as the run/

shutdown control input. Nominal voltage range is 0.7V to

1.9V. Forcing the pin below 0.28V with respect to PGND

causes the controller to shut down.

NGATE (Pin 3): Gate Driver Output. This pin drives the

regulator’s external N-Channel MOSFET and swings from

PGND to PVCC.

PVCC (Pin 4): Switching Regulator Positive Supply. This

pin is the positive supply rail for the switching regulator

and must be closely decoupled to PGND.

RCLASS (Pin 5): Class Select Input. Used to set the current

value the PD maintains during classification. Connect a

resistor between RCLASS and VPORTN (see Table 2).

NC (Pin 6): No Internal Connection.

VPORTN (Pin 7): Negative Power Input. Tie to the –48V

input port through the input diodes.

POUT (Pin 10): Power Output. Supplies –48V to the switch-

ing regulator PGND pin and any additional PD loads through

an internal power MOSFET that limits input current. POUT

is high impedance until the voltage reaches the turn-on

UVLO threshold. The output is then current limited. See

the Application Information section.

PWRGD (Pin 11): Power Good Output, Open-Drain.

Indicates that the PD MOSFET is on and the switching

regulator can start operation. Low impedance indicates

power is good. PWRD is high impedance during detec-

tion, classification and in the event of a thermal overload.

PWRD is referenced to VPORTN.

SIGDISA (Pin 12): Signature Disable Input. SIGDISA al-

lows the PD to present an invalid signature resistance and

remain inactive. Connecting SIGDISA to VPORTP lowers

the signature resistance to an invalid value and disables

all functions of the LTC4267-1. If unused, tie SIGDISA

to VPORTN.

VPORTP (Pin 13): Positive Power Input. Tie to the input

port power return through the input diodes.

SENSE (Pin 14): Current Sense. This pin performs two

functions. It monitors the regulator switch current by read-

ing the voltage across an external sense resistor. It also

injects a current ramp that develops a slope compensation

voltage across an optional external programming resistor.

See the Applications Information section.

VFB (Pin 15): Feedback Input. Receives the feedback volt-

age from the external resistor divider across the output.

(DFN/MSOP)

LTC4267-1

42671fa

For more information www.linear.com/4267-1

block DiagraM

42671 BD

VPORTN

BOLD LINE INDICATES HIGH CURRENT PATH

POUT

–

PGND

RCLASS

PWRGD

CONTROL

CIRCUITS

INPUT

CURRENT

LIMIT

POWER GOOD

CLASSIFICATION

CURRENT LOAD

1.237V

375mA

140mA

16k

–

EN 25k

SIGNATURE

RESISTOR

VPORTP SIGDISA

–

SLOPE

COMP

CURRENT

RAMP

PVCC

GATE

DRIVER

NGATE

SENSE

200kHz

OSCILLATOR

UNDERVOLTAGE

LOCKOUT

CURRENT

COMPARATOR

SHUTDOWN

COMPARATOR

SHUTDOWN

20mV

ITH/RUN

ERROR

AMPLIFIER

VFB

SOFT-

START

CLAMP

VCC

SHUNT

REGULATOR

SWITCHING

LOGIC AND

BLANKING

CIRCUIT

0.28V PVCC <

VTURNON

0.3µA

PVCC

–

1.2V

800mV

REFERENCE

applicaTions inForMaTion

OVERVIEW

The LTC4267-1 is partitioned into two major blocks: a

Powered Device (PD) interface controller and a current

mode flyback switching regulator. The Powered Device

(PD) interface is intended for use as the front end of a

PD adhering to the IEEE 802.3af standard, and includes

a trimmed 25k signature resistor, classification current

source, and an input current limit circuit. With these

functions integrated into the LTC4267-1, the signature

and power interface for a PD can be built that meets all

the requirements of the IEEE 802.3af specification with a

minimum of external components.

The switching regulator portion of the LTC4267-1 is a

constant frequency current mode controller that is opti-

mized for Power over Ethernet applications. The regulator

is designed to drive a 6V N-channel MOSFET and features

soft-start and programmable slope compensation. The

integrated error amplifier and precision reference give the

PD designer the option of using a nonisolated topology

without the need for an external amplifier or reference. The

LTC4267-1 has been specifically designed to interface with

both IEEE compliant Power Sourcing Equipment (PSE)

and legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af specification. By setting

the initial inrush current limit to a low level, a PD using

the LTC4267-1 minimizes the current drawn from the PSE

during start-up. After powering up, the LTC4267-1 switches

to the high level current limit, thereby allowing the PD to

consume up to 13W if an IEEE 802.3af PSE is present.

This low level current limit also allows the LTC4267-1 to

charge arbitrarily large load capacitors without exceeding

the inrush limits of the IEEE 802.3af specification. This

dual level current limit provides the system designer with

flexibility to design PDs which are compatible with legacy

PSEs while also being able to take advantage of the higher

power available in an IEEE 802.3af system.

LTC4267-1

42671fa

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Using an LTC4267-1 for the power and signature inter-

face functions of a PD provides several advantages. The

LTC4267-1 current limit circuit includes an onboard 100V

power MOSFET. This low leakage MOSFET is specified to

avoid corrupting the 25k signature resistor while also sav-

ing board space and cost. In addition, the inrush current

limit requirement of the IEEE 802.3af standard can cause

large transient power dissipation in the PD. The LTC4267-1

is designed to allow multiple turn-on sequences without

overheating the miniature 16-lead package. In the event of

excessive power cycling, the LTC4267-1 provides thermal

overload protection to keep the onboard power MOSFET

within its safe operating area.

OPERATION

The LTC4267-1 PD interface has several modes of opera-

tion depending on the applied input voltage as shown in

Figure 1 and summarized in Table 1. These modes satisfy

the requirements defined in the IEEE 802.3af specification.

The input voltage is applied to the VPORTN pin and must

be negative relative to the VPORTP pin. Voltages in the data

sheet for the PD interface portion of the LTC4267-1 are

with respect to VPORTP while the voltages for the switch-

ing regulator are referenced to PGND. It is assumed that

PGND is tied to POUT. Note the use of different ground

symbols throughout the data sheet.

Table 1. LTC4267-1 Operational Mode

as a Function of Input Voltage

INPUT VOLTAGE

(VPORTN with RESPECT to VPORTP) LTC4267-1 MODE OF OPERATION

0V to –1.4V Inactive

–1.5V to –9.5V** 25k Signature Resistor Detection

–9.8V to –12.4V Classification Load Current Ramps up

from 0% to 100%

–12.5V to UVLO* Classification Load Current Active

UVLO* to –57V Power Applied to Switching Regulator

* VPORTN UVLO includes hysteresis.

Rising input threshold ≅ –36.0V

Falling input threshold ≅ –30.5V

** Measured at LTC4267-1 pin. The LTC4267-1 meets the IEEE 802.3af

10V minimum when operating with the required diode bridges.

Figure 1. Output Voltage, PWRGD and PD

Current as a Function of Input Voltage

DETECTION V1

CLASSIFICATION

UVLO

TURN-ON

UVLO

OFF

POWER

BAD

UVLO

OFF

UVLO

TURN-OFF

τ = RLOAD C1

PWRGD TRACKS

VPORTN

DETECTION V2

–10

TIME

–20

–30

VPORTN (V)

–40

–50

–10

TIME

–20

–30

POUT (V)

–40

–50

–10

TIME

–20

–30

PWRGD (V)

–40

–50

ICLASS

PD CURRENT

ILIM_LO

POWER

BAD

POWER

GOOD

DETECTION I1

CLASSIFICATION

ICLASS

DETECTION I2

LOAD, ILOAD (UP TO ILIM_HI)

CURRENT

LIMIT, ILIM_LO

42671 F01

ICLASS DEPENDENT ON RCLASS SELECTION

ILIM_LO = 140mA (NOMINAL), ILIM_HI = 375mA (NOMINAL)

I1 = V1 – 2 DIODE DROPS

25kΩ

ILOAD = (UP TO ILIM_HI)

VOUT

RLOAD

I2 = V2 – 2 DIODE DROPS

25kΩ

VPORTP

PSE

IIN

LTC4267-1

RCLASS

RLOAD

VOUT

RCLASS

PWRGD

POUT

PGND

VPORTN

VIN

TIME

VOLTAGES WITH RESPECT TO VPORTP

LTC4267-1

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Series Diodes

The IEEE 802.3af-defined operating modes for a PD refer-

ence the input voltage at the RJ45 connector on the PD.

The PD must be able to accept power of either polarity

at each of its inputs, so it is common to install diode

bridges (Figure 2). The LTC4267-1 takes this into account

by compensating for these diode drops in the threshold

points for each range of operation. A similar adjustment

is made for the UVLO voltages.

Detection

During detection, the PSE will apply a voltage in the range

of –2.8V to –10V on the cable and look for a 25k signature

resistor. This identifies the device at the end of the cable as

a PD. With the terminal voltage in this range, the LTC4267-1

connects an internal 25k resistor between the VPORTP and

VPORTN pins. This precision, temperature compensated

resistor presents the proper signature to alert the PSE

that a PD is present and desires power to be applied. The

internal low-leakage UVLO switch prevents the switching

regulator circuitry from affecting the detection signature.

The LTC4267-1 is designed to compensate for the voltage

and resistance effects of the IEEE required diode bridge.

The signature range extends below the IEEE range to ac-

commodate the voltage drop of the two diodes. The IEEE

specification requires the PSE to use a ∆V/∆I measurement

technique to keep the DC offset of these diodes from af-

fecting the signature resistance measurement. However,

the diode resistance appears in series with the signature

resistor and must be included in the overall signature

resistance of the PD. The LTC4267-1 compensates for

the two series diodes in the signature path by offsetting

the resistance so that a PD built using the LTC4267-1 will

meet the IEEE specification.

In some applications it is necessary to control whether

or not the PD is detected. In this case, the 25k signature

resistor can be enabled and disabled with the use of the

SIGDISA pin (Figure 3). Disabling the signature via the

SIGDISA pin will change the signature resistor to 9k

(typical) which is an invalid signature per the IEEE 802.3af

specification. This invalid signature is present for PD input

voltages from –2.8V to –10V. If the input rises above –10V,

the signature resistor reverts to 25k to minimize power

dissipation in the LTC4267-1. To disable the signature,

tie SIGDISA to VPORTP. Alternately, the SIGDISA pin can

be driven high with respect to VPORTN. When SIGDISA is

high, all functions of the PD interface are disabled.

RX–

RX+

TX–

TX+

RJ45 T1

POWERED DEVICE (PD)

INTERFACE

AS DEFINED

BY IEEE 802.3af

42671 F02

SPARE–

SPARE+

TO PHY

BR2

BR1

VPORTP

LTC4267-1

VPORTN

Figure 2. LTC4267-1 PD Front End Using

Diode Bridges on Main and Spare Inputs

LTC4267-1

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Classification

Once the PSE has detected a PD, the PSE may option-

ally classify the PD. Classification provides a method for

more efficient allocation of power by allowing the PSE

to identify lower power PDs and allocate less power for

these devices. The IEEE 802.3af specification defines five

classes (Table 2) with varying power levels. The designer

selects the appropriate classification based on the power

consumption of the PD. For each class, there is an as-

sociated load current that the PD asserts onto the line

during classification probing. The PSE measures the PD

load current to determine the proper classification and PD

power requirements.

During classification (Figure 4), the PSE presents a fixed

voltage between –15.5V and –20.5V to the PD. With the

input voltage in this range, the LTC4267-1 asserts a load

current from the VPORTP pin through the RCLASS resistor.

The magnitude of the load current is set by the RCLASS

resistor. The resistor values associated with each class

are shown in Table 2. Note that the switching regulator

will not interfere with the classification measurement since

the LTC4267-1 has not passed power to the regulator.

Table 2. Summary of IEEE 802.3af Power Classifications and

LTC4267-1 RCLASS Resistor Selection

Class Usage

Maximum

Power Levels

at Input of PD

(W)

Nominal

Classification

Load Current

(mA)

LTC4267-1

RCLASS

Resistor

(Ω, 1%)

0 Default 0.44 to 13.0 <5 Open

1 Optional 0.44 to 3.84 10.5 124

2 Optional 3.84 to 6.49 18.5 68.1

3 Optional 6.49 to 13.0 28 45.3

4 Reserved Reserved* 40 30.9

*Class 4 is currently reserved and should not be used.

The IEEE 802.3af specification limits the classification

time to 75ms because a significant amount of power is

dissipated in the PD. The LTC4267-1 is designed to handle

the power dissipation for this time period. If the PSE prob-

ing exceeds 75ms, the LTC4267-1 may overheat. In this

situation, the thermal protection circuit will engage and

disable the classification current source in order to protect

the part. The LTC4267-1 stays in classification mode until

the input voltage rises above the UVLO turn-on voltage.

VPORTN Undervoltage Lockout

The IEEE specification dictates a maximum turn-on voltage

of 42V and a minimum turn-off voltage of 30V for the PD.

In addition, the PD must maintain large on-off hysteresis to

prevent resistive losses in the wiring between the PSE and

the PD from causing start-up oscillation. The LTC4267-1

incorporates an undervoltage lockout (UVLO) circuit that

monitors the line voltage at VPORTN to determine when

to apply power to the integrated switching regulator

(Figure 5). Before the power is applied to the switching

regulator, the POUT pin is high impedance and sitting at

the ground potential since there is no charge on capacitor

C1. When the input voltage rises above the UVLO turn-on

threshold, the LTC4267-1 removes the detection and clas-

sification loads and turns on the internal power MOSFET.

C1 charges up under the LTC4267-1 current limit control

and the POUT pin transitions from 0V to VPORTN. This

sequence is shown in Figure 1. The LTC4267-1 includes

a hysteretic UVLO circuit on VPORTN that keeps power

applied to the load until the input voltage falls below the

UVLO turn-off threshold. Once the input voltage drops

below –30V, the internal power MOSFET is turned off and

Figure 4. IEEE 802.3af Classification Probing

Figure 3. 25k Signature Resistor with Disable

VPORTP

VPORTN

LTC4267-1

42671 F03

25k SIGNATURE

RESISTOR

SIGNATURE DISABLE

SIGDISA

16k

PSE VPORTP

RCLASS

VPORTN

LTC4267-1

CONSTANT

LOAD

CURRENT

INTERNAL

TO LTC4267-1

42671 F04

RCLASS

CURRENT PATH

PDPSE

PSE CURRENT MONITOR

PSE

PROBING

VOLTAGE

SOURCE

–15.5V TO –20.5V

LTC4267-1

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the classification current is reenabled. C1 will discharge

through the PD circuitry and the POUT pin will go to a high

impedance state.

limit because the load capacitor is charged with a current

below the IEEE inrush current limit specification.

As the LTC4267-1 switches from the low to high level

current limit, the current will increase momentarily. This

current spike is a result of the LTC4267-1 charging the

last 1.5V at the high level current limit. When charging a

10µF capacitor, the current spike is typically 100µs wide

and 125% of the nominal low level current limit.

The LTC4267-1 stays in the high level current limit mode

until the input voltage drops below the UVLO turn-off

threshold. This dual level current limit provides the sys-

tem designer with the flexibility to design PDs which are

compatible with legacy PSEs while also being able to take

advantage of the higher power allocation available in an

IEEE 802.3af system.

During the current limited turn on, a large amount of power

is dissipated in the power MOSFET. The LTC4267-1 PD

interface is designed to accept this thermal load and is

thermally protected to avoid damage to the onboard power

MOSFET. Note that in order to adhere to the IEEE 802.3af

standard, it is necessary for the PD designer to ensure the

PD steady state power consumption falls within the limits

shown in Table 2. In addition, the steady state current

must be less than ILIM_HI.

Power Good

The LTC4267-1 PD Interface includes a power good circuit

(Figure 6) that is used to indicate that load capacitor C1

is fully charged and that the switching regulator can start

operation. The power good circuit monitors the voltage

across the internal UVLO power MOSFET and PWRGD is

asserted when the voltage falls below 1.5V. The power

good circuit includes hysteresis to allow the LTC4267-1 to

operate near the current limit point without inadvertently

disabling PWRGD. The MOSFET voltage must increase to

3V before PWRGD is disabled.

If a sudden increase in voltage appears on the input line,

this voltage step will be transferred through capacitor C1

and appear across the power MOSFET. The response of

the LTC4267-1 will depend on the magnitude of the volt-

age step, the rise time of the step, the value of capacitor

C1 and the switching regulator load. For fast rising inputs,

Input Current Limit

IEEE 802.3af specifies a maximum inrush current and

also specifies a minimum load capacitor between the

VPORTP and POUT pins. To control turn-on surge current

in the system, the LTC4267-1 integrates a dual level cur-

rent limit circuit with an onboard power MOSFET and

sense resistor to provide a complete inrush control circuit

without additional external components. At turn-on, the

LTC4267-1 will limit the input current to the low level,

allowing the load capacitor to ramp up to the line voltage

in a controlled manner.

The LTC4267-1 has been specifically designed to interface

with legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af specification. At turn-on

the LTC4267-1 current limit is set to the lower level. After

C1 is charged up and the POUT – VPORTN voltage difference

is below the power good threshold, the LTC4267-1 switches

to the high level current limit. The dual level current limit

allows legacy PSEs with limited current sourcing capability

to power up the PD while also allowing the PD to draw full

power from an IEEE 802.3af PSE. The dual level current

limit also allows use of arbitrarily large load capacitors.

The IEEE 802.3af specification mandates that at turn-on

the PD not exceed the inrush current limit for more than

50ms. The LTC4267-1 is not restricted to the 50ms time

Figure 5. LTC4267-1 VPORTN Undervoltage Lockout

5µF

MIN

VPORTN

VPORTP

POUT

PGND

LTC4267-1

42671 F05

PSE UNDERVOLTAGE

LOCKOUT

CIRCUIT

CURRENT-LIMITED

TURN ON

INPUT LTC4267-1

VOLTAGE POWER MOSFET

0V TO UVLO* OFF

>UVLO* ON

*UVLO INCLUDES HYSTERESIS

RISING INPUT THRESHOLD ≅ –36V

FALLING INPUT THRESHOLD ≅ –30.5V

LTC4267-1

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the LTC4267-1 will attempt to quickly charge capacitor C1

using an internal secondary current limit circuit. In this

scenario, the PSE current limit should provide the overall

limit for the circuit. For slower rising inputs, the 375mA

current limit in the LTC4267-1 will set the charge rate of

the capacitor C1. In either case, the PWRGD signal may

go inactive briefly while the capacitor is charged up to the

new line voltage. In the design of a PD, it is necessary

to determine if a step in the input voltage will cause the

PWRGD signal to go inactive and how to respond to this

event. In some designs, it may be desirable to filter the

PWRGD signal so that intermittent power bad conditions

are ignored. Figure 7 demonstrates a method to insert a

lowpass filter on the power good interface.

For PD designs that use a large load capacitor and also con-

sume a lot of power, it is important to delay activation of the

switching regulator with the PWRGD signal. If the regulator

is not disabled during the current-limited turn-on sequence,

the PD circuitry will rob current intended for charging up

the load capacitor and create a slow rising input, possibly

causing the LTC4267-1 to go into thermal shutdown.

The

PWRGD pin connects to an internal open drain,

100V transistor capable of sinking 1mA. Low impedance

to VPORTN indicates power is good.

PWRGD is high

impedance during signature and classification probing

and in the event of a thermal overload. During turn-off,

PWRGD is deactivated when the input voltage drops below

30V. In addition, PWRGD may go active briefly at turn-on

for fast rising input waveforms. PWRGD is referenced to

the VPORTN pin and when active, will be near the VPORTN

potential. Connect the PWRGD pin to the switching regula-

tor circuitry as shown in Figure 7.

PD Interface Thermal Protection

The LTC4267-1 PD Interface includes thermal overload

protection in order to provide full device functionality in

a miniature package while maintaining safe operating

temperatures. Several factors create the possibility of

significant power dissipation within the LTC4267-1. At

turn-on, before the load capacitor has charged up, the

instantaneous power dissipated by the LTC4267-1 can be

as much as 10W. As the load capacitor charges up, the

power dissipation in the LTC4267-1 will decrease until it

reaches a steady-state value dependent on the DC load

current. The size of the load capacitor determines how fast

the power dissipation in the LTC4267-1 will subside. At

room temperature, the LTC4267-1 can typically handle load

capacitors as large as 800µF without going into thermal

shutdown. With large load capacitors, the LTC4267-1 die

temperature will increase by as much as 50°C during a

single turn-on sequence. If for some reason power were

removed from the part and then quickly reapplied so that

the LTC4267-1 had to charge up the load capacitor again,

the temperature rise would be excessive if safety precau-

tions were not implemented.

The LTC4267-1 PD interface protects itself from thermal

damage by monitoring the die temperature. If the die

temperature exceeds the overtemperature trip point, the

Figure 6. LTC4267-1 Power Good

Figure 7. Power Good Interface Examples

42671 F07

LTC4267-1

VPORTN POUT

PGND

VPORTP

ITH/RUN

PSE

–48V

+C1

5µF

100V

ALTERNATE ACTIVE-HIGH ENABLE FOR PVCC PIN

C15 OPTIONAL

SEE APPLICATIONS INFORMATION SECTION

ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP

10k

100k

0.047µF

PWRGD

PGND

LTC4267-1

VPORTN POUT

PGND

VPORTP

PVCC

PSE

–48V

+C1

5µF

100V

10k

100k

0.047µF

PWRGD

PGND

RSTART

CPVCC

PWRGD

5µF

MIN

VPORTN POUT

1.125V

300k 300k

100k

LTC4267-1

THERMAL SHUTDOWN

UVLO

42671 F06

PSE

–+

–

ITH/RUN

PGND

LTC4267-1

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current is reduced to zero and very little power is dissi-

pated in the part until it cools below the overtemperature

set point. Once the LTC4267-1 has charged up the load

capacitor and the PD is powered and running, there will

be minor residual heating due to the DC load current of

the PD flowing through the internal MOSFET.

During classification, excessive heating of the LTC4267-1

can occur if the PSE violates the 75ms probing time limit.

To protect the LTC4267-1, thermal overload circuitry will

disable classification current if the die temperature exceeds

the overtemperature trip point. When the die cools down

below the trip point, classification current is reenabled.

The PD is designed to operate at a high ambient tem-

perature and with the maximum allowable supply (57V).

However, there is a limit to the size of the load capacitor

that can be charged up before the LTC4267-1 reaches the

overtemperature trip point. Hitting the overtemperature trip

point intermittently does not harm the LTC4267-1, but it

will delay the completion of capacitor charging. Capacitors

up to 200µF can be charged without a problem over the

full operating temperature range.

Switching Regulator Main Control Loop

Due to space limitations, the basics of current mode

DC/DC conversion will not be discussed here. The reader

is referred to the detail treatment in Application Note 19

or in texts such as Abraham Pressman’s Switching Power

Supply Design.

In a Power over Ethernet System, the majority of applica-

tions involve an isolated power supply design. This means

that the output power supply does not have any DC elec-

trical path to the PD interface or the switching regulator

primary. The DC isolation is achieved typically through a

transformer in the forward path and an opto-isolator in

the feedback path or a third winding in the transformer.

The typical application circuit shown on the front page

of the data sheet represents an isolated design using an

opto-isolator. In applications where a nonisolated topol-

ogy is desired, the LTC4267-1 features a feedback port

and an internal error amplifier that can be enabled for this

specific application.

In the typical application circuit (Figure 11), the isolated

topology employs an external resistive voltage divider to

present a fraction of the output voltage to an external er-

ror amplifier. The error amplifier responds by pulling an

analog current through the input LED on an opto-isolator.

The collector of the opto-isolator output presents a cor-

responding current into the ITH/RUN pin via a series diode.

This method generates a feedback voltage on the ITH/RUN

pin while maintaining isolation.

The voltage on the ITH/RUN pin controls the pulse-width

modulator formed by the oscillator, current comparator,

and RS latch. Specifically, the voltage at the ITH/RUN pin

sets the current comparator’s trip threshold. The current

comparator monitors the voltage across a sense resistor

in series with the source terminal of the external N-Channel

MOSFET. The LTC4267-1 turns on the external power

MOSFET when the internal free-running 200kHz oscillator

sets the RS latch. It turns off the MOSFET when the cur-

rent comparator resets the latch or when 80% duty cycle

is reached, whichever happens first. In this way, the peak

current levels through the flyback transformer’s primary

and secondary are controlled by the ITH/RUN voltage.

In applications where a nonisolated topology is desir-

able (Figure 11), an external resistive voltage divider can

present a fraction of the output voltage directly to the

VFB pin of the LTC4267-1. The divider must be designed

so when the output is at its desired voltage, the VFB pin

voltage will equal the 800mV onboard internal reference.

The internal error amplifier responds by driving the ITH/

RUN pin. The LTC4267-1 switching regulator performs in

a similar manner as described previously.

Regulator Start-Up/Shutdown

The LTC4267-1 switching regulator has two shutdown

mechanisms to enable and disable operation: an un-

dervoltage lockout on the PVCC supply pin and a forced

shutdown whenever external circuitry drives the ITH/RUN

pin low. The LTC4267-1 switcher transitions into and out

of shutdown according to the state diagram (Figure 8).

It is important not to confuse the undervoltage lockout

of the PD interface at VPORTN with that of the switching

regulator at PVCC. They are independent functions.

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The undervoltage lockout mechanism on PVCC prevents

the LTC4267-1 switching regulator from trying to drive

the external N-Channel MOSFET with insufficient gate-to-

source voltage. The voltage at the PVCC pin must exceed

VTURNON (nominally 8.7V with respect to PGND) at least

momentarily to enable operation. The PVCC voltage must

fall to VTURNOFF (nominally 5.7V with respect to PGND)

before the undervoltage lockout disables the switching

regulator. This wide UVLO hysteresis range supports

applications where a bias winding on the flyback trans-

former is used to increase the efficiency of the LTC4267-1

switching regulator.

The ITH/RUN can be driven below VITHSHDN (nominally 0.28V

with respect to PGND) to force the LTC4267-1 switching

regulator into shutdown. An internal 0.3µA current source

always tries to pull the ITH/RUN pin towards PVCC. When

the ITH/RUN pin voltage is allowed to exceed VITHSHDN and

PVCC exceeds VTURNON, the LTC4267-1 switching regulator

begins to operate and an internal clamp immediately pulls

the ITH/RUN pin to about 0.7V. In operation, the ITH/RUN

pin voltage will vary from roughly 0.7V to 1.9V to represent

current comparator thresholds from zero to maximum.

Internal Soft-Start

An internal soft-start feature is enabled whenever the

LTC4267-1 switching regulator comes out of shutdown.

Specifically, the ITH/RUN voltage is clamped and is pre-

vented from reaching maximum until 1.4ms have passed.

This allows the input current of the PD to rise in a smooth

and controlled manner on start-up and stay within the cur-

rent limit requirement of the LTC4267-1 interface.

Adjustable Slope Compensation

The LTC4267-1 switching regulator injects a 5µA peak

current ramp out through its SENSE pin which can be

used for slope compensation in designs that require it.

This current ramp is approximately linear and begins at

zero current at 6% duty cycle, reaching peak current at

80% duty cycle. Programming the slope compensation

via a series resistor is discussed in the External Interface

and Component Selection section.

EXTERNAL INTERFACE AND COMPONENT SELECTION

Input Interface Transformer

Nodes on an Ethernet network commonly interface to the

outside world via an isolation transformer (Figure 9). For

PoE devices, the isolation transformer must include a

center tap on the media (cable) side. Proper termination

is required around the transformer to provide correct

impedance matching and to avoid radiated and conducted

emissions. Transformer vendors such as Bel Fuse, Coil-

craft, Pulse and Tyco (Table 3) can provide assistance with

selection of an appropriate isolation transformer and proper

termination methods. These vendors have transformers

specifically designed for use in PD applications.

Table 3. Power over Ethernet Transformer Vendors

VENDOR CONTACT INFORMATION

Bel Fuse Inc. 206 Van Vorst Street

Jersey City, NJ 07302

Tel: 201-432-0463

FAX: 201-432-9542

http://www.belfuse.com

Coilcraft, Inc. 1102 Silver Lake Road

Cary, IL 60013

Tel: 847-639-6400

FAX: 847-639-1469

http://www.coilcraft.com

Pulse Engineering 12220 World Trade Drive

San Diego, CA 92128

Tel: 858-674-8100

FAX: 858-674-8262

http://www.pulseeng.com

Tyco Electronics 308 Constitution Drive

Menlo Park, CA 94025-1164

Tel: 800-227-7040

FAX: 650-361-2508

http://www.circuitprotection.com

Figure 8. LTC4267-1 Switching Regulator

Start-Up/Shutdown State Diagram

LTC4267-1

PWM

SHUTDOWN

LTC4267-1

PWM

ENABLED

VITH/RUN

< VITHSHDN

(NOMINALLY

0.28V)

VITH/RUN > VITHSHDN

AND PVCC > VTURNON

(NOMINALLY 8.7V)

PVCC < VTURNOFF

42671 F08

ALL VOLTAGES WITH

RESPECT TO PGND

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Diode Bridge

IEEE 802.3af allows power wiring in either of two configu-

rations: on the TX/RX wires or via the spare wire pairs in

the RJ45 connector. The PD is required to accept power in

either polarity on either the main or spare inputs; therefore

it is common to install diode bridges on both inputs in

order to accommodate the different wiring configurations.

Figure 9 demonstrates an implementation of these diode

bridges. The IEEE 802.3af specification also mandates

that the leakage back through the unused bridge be less

than 28µA when the PD is powered with 57V.

The LTC4267-1 has several different modes of operation

based on the voltage present between VPORTN and VPORTP

pins. The forward voltage drop of the input diodes in a

PD design subtracts from the input voltage and will af-

fect the transition point between modes. When using the

LTC4267-1, it is necessary to pay close attention to this

forward voltage drop. Selection of oversized diodes will help

keep the PD thresholds from exceeding IEEE specifications.

The input diode bridge of a PD can consume over 4% of

the available power in some applications. It may be de-

sirable to use Schottky diodes in order to reduce power

loss. However, if the standard diode bridge is replaced

with a Schottky bridge, the transition points between the

modes will be affected. Figure 10 shows a technique for

using Schottky diodes while maintaining proper threshold

points to meet IEEE 802.3af compliance. D13 is added

to compensate for the change in UVLO turn-on voltage

caused by the Schottky diodes and consumes little power.

Input Capacitor

The IEEE 802.3af/at standard includes an impedance

requirement in order to implement the AC disconnect

function. A 0.1µF capacitor (C14 in Figure 9) is used to

meet the AC impedance requirement.

Input Series Resistance

Linear Technology has seen the customer community cable

discharge requirements increase by nearly 500,000 times

the original test levels. The PD must survive and operate

reliably not only when an initially charged cable connects

and dissipates the energy through the PD front end, but

also when the electrical power system grounds are subject

to very high energy events (e.g. lightning strikes).

In these high energy events, adding 10Ω series resistance

into the VPORTP pin greatly improves the robustness of

the LTC4267-1 based PD. (See Figure 9.) The TVS limits

the voltage across the port while the 10Ω and 0.1µF ca-

pacitance reduces the edge rate the LT4267-1 encounters

across its pin. The added 10Ω series resistance does not

operationally affect the LTC4267-1 PD Interface nor does

it affect its compliance with the IEEE802.3 standard.

Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor

RX–

RX+

TX–

TX+

RJ45

PULSE H2019

42671 F09

SMAJ58A

TVS

BR1

HD01

BR2

HD01

TO PHY

SPARE–

SPARE+

C14

0.1µF

100V

LTC4267-1

10Ω

VPORTN

VPORTP

LTC4267-1

42671fa

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Transient Voltage Suppressor

The LTC4267-1 specifies an absolute maximum voltage of

100V and is designed to tolerate brief overvoltage events.

However, the pins that interface to the outside world can

routinely see excessive peak voltages. To protect the

LTC4267-1, install a transient voltage suppressor (D3)

between the input diode bridge and the LTC4267-1 as

shown in Figure 9. A SMAJ58A is recommended for typical

PD applications. However, a SMBJ58A may be preferred in

applications where the PD front-end must absorb higher

energy discharge events.

Classification Resistor Selection (RCLASS)

The IEEE specification allows classifying PDs into four

distinct classes with class 4 being reserved for future use

(Table 2). An external resistor connected from RCLASS to

VPORTN (Figure 4) sets the value of the load current. The

designer should determine which power category the PD

falls into and then select the appropriate value of RCLASS

from Table 2. If a unique load current is required, the value

of RCLASS can be calculated as:

RCLASS = 1.237V/(IDESIRED – IIN_CLASS)

where IIN_CLASS is the LTC4267-1 IC supply current during

classification and is given in the electrical specifications.

The RCLASS resistor must be 1% or better to avoid de-

grading the overall accuracy of the classification circuit.

Resistor power dissipation will be 50mW maximum and

is transient so heating is typically not a concern. In order

to maintain loop stability, the layout should minimize

capacitance at the RCLASS node. The classification circuit

Figure 10. PD Front End with Isolation Transformer, Tw o Schottky Diode Bridges

RX–

SPARE–

RX+

TX–

TX+

FROM

PSE

RJ45

TXOUT+

OUT

TO PHY

TXOUT–

SPARE+

RXOUT+

RXOUT–

NOTES: UNLESS OTHERWISE SPECIFIED

1. ALL RESISTORS ARE 5%

2. SELECT RCLASS FOR CLASS 1-4 OPERATION. REFER

TO DATA SHEET APPLICATIONS INFORMATION SECTION

C2: AVX 1808GC102MAT

D9 TO D12, D14 TO D17: DIODES INC., B1100

T1: PULSE H2019

RCLASS

VPORTN

D13

MMSD4148

C11

0.1µF

100V

SMAJ58A

R30

75Ω

C24

0.01µF

200V

R31

75Ω

C25

0.01µF

200V

75Ω

0.01µF

200V

75Ω

0.01µF

200V

1000pF

2kV

D10

B1100

D12

B1100

10Ω

B1100

D11

B1100

D17

B1100

D16

B1100

D15

B1100

D14

B1100

VPORTP

LTC4267-1

42671 F10

LTC4267-1

42671fa

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applicaTions inForMaTion

can be disabled by floating the RCLASS pin. The RCLASS

pin should not be shorted to VPORTN as this would force

the LTC4267-1 classification circuit to attempt to source

very large currents and quickly go into thermal shutdown.

Power Good Interface

The PWRGD signal is controlled by a high voltage, open-

drain transistor. The designer has the option of using this

signal to enable the onboard switching regulator through

the ITH/RUN or the PVCC pins. Examples of active-high

interface circuits for controlling the switching regulator

are shown in Figure 7.

In some applications, it is desirable to ignore intermittent

power bad conditions. This can be accomplished by includ-

ing capacitor C15 in Figure 7 to form a lowpass filter. With

the components shown, power bad conditions less than

about 200µs will be ignored. Conversely, in other applica-

tions it may be desirable to delay assertion of PWRGD to

the switching regulator using CPVCC as shown in Figure 7.

It is recommended that the designer use the power good

signal to enable the switching regulator. Using PWRGD

ensures the capacitor C1 has reached within 1.5V of the

final value and is ready to accept a load. The LTC4267-1

is designed with wide power good hysteresis to handle

sudden fluctuations in the load voltage and current without

prematurely shutting off the switching regulator. Please

refer to the Power-Up Sequencing of the Application

Information section.

Signature Disable Interface

To disable the 25k signature resistor, connect SIGDISA pin

to the VPORTP pin. Alternately, SIGDISA pin can be driven

high with respect to VPORTN. An example of a signature

disable interface is shown in Figure 16, option 2. Note that

the SIGDISA input resistance is relatively large and the

threshold voltage is fairly low. Because of high voltages

present on the printed circuit board, leakage currents from

the VPORTP pin could inadvertently pull SIGDISA high. To

ensure trouble-free operation, use high voltage layout

techniques in the vicinity of SIGDISA. If unused, connect

SIGDISA to VPORTN.

Load Capacitor

The IEEE 802.3af specification requires that the PD main-

tain a minimum load capacitance of 5µF (provided by C1

in Figure 11). It is permissible to have a much larger load

capacitor and the LTC4267-1 can charge very large load

capacitors before thermal issues become a problem. The

load capacitor must be large enough to provide sufficient

energy for proper operation of the switching regulator.

However, the capacitor must not be too large or the PD

design may violate IEEE 802.3af requirements.

If the load capacitor is too large, there can be a problem

with inadvertent power shutdown by the PSE. Consider

the following scenario. If the PSE is running at –57V

(maximum allowed) and the PD has detected and powered

up, the load capacitor will be charged to nearly –57V. If

for some reason the PSE voltage is suddenly reduced to

–44V (minimum allowed), the input bridge will reverse bias

and the PD power will be supplied by the load capacitor.

Depending on the size of the load capacitor and the DC load

of the PD, the PD will not draw any power for a period of

time. If this period of time exceeds the IEEE 802.3af 300ms

disconnect delay, the PSE will remove power from the PD.

For this reason, it is necessary to ensure that inadvertent

shutdown cannot occur.

Very small output capacitors (≤10µF) will charge very

quickly in current limit. The rapidly changing voltage at

the output may reduce the current limit temporarily, caus-

ing the capacitor to charge at a somewhat reduced rate.

Conversely, charging a very large capacitor may cause the

current limit to increase slightly. In either case, once the

output voltage reaches its final value, the input current

limit will be restored to its nominal value.

The load capacitor can store significant energy when fully

charged. The design of a PD must ensure that this energy

is not inadvertently dissipated in the LTC4267-1. The

polarity-protection diode(s) prevent an accidental short on

the cable from causing damage. However, if the VPORTN

pin is shorted to VPORTP inside the PD while the capacitor

is charged, current will flow through the parasitic body

diode of the internal MOSFET and may cause permanent

damage to the LTC4267-1.

LTC4267-1

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Maintain Power Signature

In an IEEE 802.3af system, the PSE uses the maintain

power signature (MPS) to determine if a PD continues to

require power. The MPS requires the PD to periodically

draw at least 10mA and also have an AC impedance less

than 26.25kΩ in parallel with 0.05µF. If either the DC

current is less than 10mA or the AC impedance is above

26.25kΩ, the PSE may disconnect power. The DC current

must be less than 5mA and the AC impedance must be

above 2MΩ to guarantee power will be removed.

Selecting Feedback Resistor Values

The regulated output voltage of the switching regulator is

determined by the resistor divider across VOUT (R1 and

R2 in Figure 11) and the error amplifier reference voltage

VREF. The ratio of R2 to R1 needed to produce the desired

voltage can be calculated as:

R2 = R1 • (VOUT – VREF)/VREF

In an isolated power supply application, VREF is determined

by the designer’s choice of an external error amplifier.

Commercially available error amplifiers or programmable

shunt regulators may include an internal reference of

1.25V or 2.5V. Since the LTC4267-1 internal reference

and error amplifier are not used in an isolated design, tie

the VFB pin to PGND.

In a nonisolated power supply application, the LTC4267-1

onboard internal reference and error amplifier can be

used. The resistor divider output can be tied directly to

the VFB pin. The internal reference of the LTC4267-1 is

0.8V nominal.

Choose resistance values for R1 and R2 to be as large as

possible to minimize any efficiency loss due to the static

current drawn from VOUT, but just small enough so that

when VOUT is in regulation, the error caused by the nonzero

input current from the output of the resistor divider to the

error amplifier pin is less than 1%.

Error Amplifier and Opto-Isolator Considerations

In an isolated topology, the selection of the external error

amplifier depends on the output voltage of the switching

regulator. Typical error amplifiers include a voltage refer-

ence of either 1.25V or 2.5V. The output of the amplifier

and the amplifier upper supply rail are often tied together

internally. The supply rail is usually specified with a wide

upper voltage range, but it is not allowed to fall below the

reference voltage. This can be a problem in an isolated

switcher design if the amplifier supply voltage is not prop-

erly managed. When the switcher load current decreases

and the output voltage rises, the error amplifier responds

by pulling more current through the LED. The LED voltage

can be as large as 1.5V, and along with RLIM, reduces the

supply voltage to the error amplifier. If the error amp does

not have enough headroom, the voltage drop across the

LED and RLIM may shut the amplifier off momentarily,

causing a lock-up condition in the main loop. The switcher

will undershoot and not recover until the error amplifier

releases its sink current. Care must be taken to select the

reference voltage and RLIM value so that the error amplifier

always has enough headroom. An alternate solution that

avoids these problems is to utilize the LT1431 or LT4430

where the output of the error amplifier and amplifier supply

rail are brought out to separate pins.

The PD designer must also select an opto-isolator such

that its bandwidth is sufficiently wider than the bandwidth

of the main control loop. If this step is overlooked, the

main control loop may be difficult to stabilize. The output

collector resistor of the opto-isolator can be selected for

an increase in bandwidth at the cost of a reduction in gain

of this stage.

Output Transformer Design Considerations

Since the external feedback resistor divider sets the

output voltage, the PD designer has relative freedom in

selecting the transformer turns ratio. The PD designer

can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)

which yields more freedom in setting the total turns and

mutual inductance and may allow the use of an off the

shelf transformer.

Transformer leakage inductance on either the primary or

secondary causes a voltage spike to occur after the output

switch (Q1 in Figure 11) turns off. The input supply volt-

age plus the secondary-to-primary referred voltage of the

LTC4267-1

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flyback pulse (including leakage spike) must not exceed

the allowed external MOSFET breakdown rating. This spike

is increasingly prominent at higher load currents, where

more stored energy must be dissipated. In some cases,

a “snubber” circuit will be required to avoid overvoltage

breakdown at the MOSFET’s drain node. Application

Note 19 is a good reference for snubber design.

Current Sense Resistor Consideration

The external current sense resistor (RSENSE in Figure 11)

allows the designer to optimize the current limit behavior

for a particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak swing current goes from a fraction of an ampere to

several amperes. Care must be taken to ensure proper

circuit operation, especially for small current sense resis-

tor values.

Choose RSENSE such that the switching current exercises

the entire range of the ITH/RUN voltage. The nominal voltage

range is 0.7V to 1.9V and RSENSE can be determined by

experiment. The main loop can be temporarily stabilized by

connecting a large capacitor on the power supply. Apply

the maximum load current allowable at the power sup-

ply output based on the class of the PD. Choose RSENSE

such that ITH/RUN approaches 1.9V. Finally, exercise the

output load current over the entire operating range and

ensure that ITH/RUN voltage remains within the 0.7V to

1.9V range. Layout is critical around the RSENSE resistor.

For example, a 0.020Ω sense resistor, with one milliohm

(0.001Ω) of parasitic resistance will cause a 5% reduction

in peak switch current. The resistance of printed circuit

copper traces cannot necessarily be ignored and good

layout techniques are mandatory.

Programmable Slope Compensation

The LTC4267-1 switching regulator injects a ramping

current through its SENSE pin into an external slope

compensation resistor (RSL in Figure 11). This current

ramp starts at zero after the NGATE pin has been high for

the LTC4267-1’s minimum duty cycle of 6%. The current

rises linearly towards a peak of 5µA at the maximum duty

cycle of 80%, shutting off once the NGATE pin goes low.

A series resistor (RSL) connecting the SENSE pin to the

current sense resistor (RSENSE) develops a ramping volt-

age drop. From the perspective of the LTC4267-1 SENSE

pin, this ramping voltage adds to the voltage across the

sense resistor, effectively reducing the current comparator

threshold in proportion to duty cycle. This stabilizes the

control loop against subharmonic oscillation. The amount

of reduction in the current comparator threshold (ΔVSENSE)

can be calculated using the following equation:

∆VSENSE = 5µA • RSL • [(Duty Cycle – 6%)/74%]

Note: The LTC4267-1 enforces 6% < Duty Cycle < 80%.

Designs not needing slope compensation may replace RSL

with a short-circuit.

Applications Employing a Third Transformer Winding

A standard operating topology may employ a third wind-

ing on the transformer’s primary side that provides power

to the LTC4267-1 switching regulator via its PVCC pin

(Figure 11). However, this arrangement is not inherently

self-starting. Start-up is usually implemented by the use of

an external “trickle-charge” resistor (RSTART) in conjunc-

tion with the internal wide hysteresis undervoltage lockout

circuit that monitors the PVCC pin voltage.

RSTART is connected to VPORTP and supplies a current,

typically 100µA, to charge CPVCC. After some time, the

voltage on CPVCC reaches the PVCC turn-on threshold. The

LTC4267-1 switching regulator then turns on abruptly and

draws its normal supply current. The NGATE pin begins

switching and the external MOSFET (Q1) begins to deliver

power. The voltage on CPVCC begins to decline as the

switching regulator draws its normal supply current,

which

exceeds the delivery from RSTART. After some time, typically

tens of milliseconds, the output voltage approaches the

desired value. By this time, the third transformer winding

is providing virtually all the supply current required by the

LTC4267-1 switching regulator.

One potential design pitfall is under-sizing the value of

capacitor CPVCC. In this case, the normal supply current

drawn through PVCC will discharge CPVCC rapidly before the

third winding drive becomes effective. Depending on the

particular situation, this may result in either several off-on

cycles before proper operation is reached or permanent

relaxation oscillation at the PVCC node.

LTC4267-1

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Figure 11. Typical LTC4267-1 Application Circuits

PVCC

VPORTP

RCLASS

SIGDISA

VPORTN

ITH/RUN

LTC4267-1

NGATE

SENSE

VFB

•

COUT

PGND

POUT

C1 LSEC

LPRI

LBIAS

CPVCC

VOUT

42671 F11

RSENSE

RSL

RSTART

•

RCLASS

PVCC

VPORTP

RCLASS

SIGDISA

VPORTN

ITH/RUN

LTC4267-1

NGATE

SENSE

VFB

•

COUT

0.1µF

100V

0.1µF

100V

PGND

POUT

C1 LSEC

LPRI

CPVCC

VOUT

RSENSE

RSL

RSTART

RLIM

–48V

FROM

DATA PAIR

–48V

FROM

SPARE PAIR

RCLASS

VPORTP

VPORTN

CISO

OPTOISOLATOR

ERROR

AMPLIFIER

ISOLATED DESIGN EXAMPLE

NONISOLATED DESIGN EXAMPLE

–

–48V

FROM

DATA PAIR

–48V

FROM

SPARE PAIR

–

LTC4267-1

42671fa

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Resistor RSTART should be selected to yield a worst-case

minimum charging current greater that the maximum rated

LTC4267-1 start-up current to ensure there is enough cur-

rent to charge CPVCC to the PVCC turn-on threshold. RSTART

should also be selected large enough to yield a worst-case

maximum charging current less than the minimum-rated

PVCC supply current, so that in operation, most of the

PVCC current is delivered through the third winding. This

results in the highest possible efficiency.

Capacitor CPVCC should then be made large enough to avoid

the relaxation oscillation behavior described previously.

This is difficult to determine theoretically as it depends on

the particulars of the secondary circuit and load behavior.

Empirical testing is recommended.

The third transformer winding should be designed so

that its output voltage, after accounting for the forward

diode voltage drop, exceeds the maximum PVCC turn-off

threshold. Also, the third winding’s nominal output voltage

should be at least 0.5V below the minimum rated PVCC

clamp voltage to avoid running up against the LTC4267-1

shunt regulator, needlessly wasting power.

PVCC Shunt Regulator

In applications including a third transformer winding,

the internal PVCC shunt regulator serves to protect the

LTC4267-1 switching regulator from overvoltage transients

as the third winding is powering up.

If a third transformer winding is undesirable or unavail-

able, the shunt regulator allows the LTC4267-1 switching

regulator to be powered through a single dropping resistor

from VPORTP as shown in Figure 12. This simplicity comes

at the expense of reduced efficiency due to static power

dissipation in the RSTART dropping resistor.

The shunt regulator can sink up to 5mA through the PVCC

pin to PGND. The values of RSTART and CPVCC must be

selected for the application to withstand the worst-case

load conditions and drop on PVCC, ensuring that the PVCC

turn-off threshold is not reached. CPVCC should be sized

sufficiently to handle the switching current needed to drive

NGATE while maintaining minimum switching voltage.

External Preregulator

The circuit in Figure 13 shows a third way to power the

LTC4267-1 switching regulator circuit. An external series

preregulator consists of a series pass transistor Q1, zener

diode D1, and a bias resistor RB. The preregulator holds

PVCC at 7.6V nominal, well above the maximum rated PVCC

turn-off threshold of 6.8V. Resistor RSTART momentarily

charges the PVCC node up to the PVCC turn-on threshold,

enabling the switching regulator. The voltage on CPVCC

begins to decline as the switching regulator draws its

normal supply current, which exceeds the delivery of

RSTART. After some time, the output voltage approaches

the desired value. By this time, the pass transistor Q1

catches the declining voltage on the PVCC pin, and provides

virtually all the supply current required by the LTC4267-1

switching regulator. CPVCC should be sized sufficiently to

handle the switching current needed to drive NGATE while

maintaining minimum switching voltage.

Figure 12. Powering the LTC4267-1 Switching

Regulator via the Shunt Regulator

Figure 13. Powering the LTC4267-1 Switching

Regulator with an External Preregulator

VPORTP

PVCC

PGND

POUT

VPORTN

LTC4267-1

–48

FROM

PSE

RSTART

CPVCC

–

PGND

42671 F14

VPORTP

PVCC

PGND

POUT

VPORTN

LTC4267-1

–48

FROM

PSE

RSTART

CPVCC

–

PGND

8.2V

42671 F15

LTC4267-1

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The external preregulator has improved efficiency over

the simple resistor-shunt regulator method mentioned

previously. RB can be selected so that it provides a small

current necessary to maintain the zener diode voltage and

the maximum possible base current Q1 will encounter. The

actual current needed to power the LTC4267-1 switching

regulator goes through Q1 and PVCC sources current on

an “as-needed” basis. The static current is then limited

only to the current through RB and D1.

Compensating the Main Loop

In an isolated topology, the compensation point is typically

chosen by the components configured around the external

error amplifier. Shown in Figure 14, a series RC network

is connected from the compare voltage of the error am-

plifier to the error amplifier output. In PD designs where

transient load response is not critical, replace RZ with a

short. The product of R2 and CC should be sufficiently large

to ensure stability. When fast settling transient response

is critical, introduce a zero set by RZCC. The PD designer

must ensure that the faster settling response of the output

voltage does not compromise loop stability.

In a nonisolated design, the LTC4267-1 incorporates an

internal error amplifier where the ITH/RUN pin serves as

a compensation point. In a similar manner, a series RC

network can be connected from ITH/RUN to PGND as

shown in Figure 15. CC and RZ are chosen for optimum

load and line transient response.

Selecting the Switching Transistor

With the N-channel power MOSFET driving the primary of

the transformer, the inductance will cause the drain of the

MOSFET to traverse twice the voltage across VPORTP and

PGND. The LTC4267-1 operates with a maximum supply

of – 57V; thus the MOSFET must be rated to handle 114V

or more with sufficient design margin. Typical transis-

tors have 150V ratings while some manufacturers have

developed 120V rated MOSFETs specifically for Power-

over-Ethernet applications.

The NGATE pin of the LTC4267-1 drives the gate of the

N-channel MOSFET. NGATE will traverse a rail-to-rail volt-

age from PGND to PVCC. The designer must ensure the

MOSFET provides a low “ON” resistance when switched

to PVCC as well as ensure the gate of the MOSFET can

handle the PVCC supply voltage.

For high efficiency applications, select an N-channel

MOSFET with low total gate charge. The lower total gate

charge improves the efficiency of the NGATE drive circuit

and minimizes the switching current needed to charge

and discharge the gate.

Auxiliary Power Source

In some applications, it may be desirable to power the

PD from an auxiliary power source such as a wall trans-

former. The auxiliary power can be injected into the PD

at several locations and various trade-offs exist. Power

can be injected at the 3.3V or 5V output of the isolated

power supply with the use of a diode ORing circuit. This

method accesses the internal circuits of the PD after the

isolation barrier and therefore meets the 802.3af isola-

tion safety requirements for the wall transformer jack on

the PD. Power can also be injected into the PD interface

portion of the LTC4267-1. In this case, it is necessary to

ensure the user cannot access the terminals of the wall

Figure 14. Main Loop Compensation for an Isolated Design

TO OPTO-

ISOLATOR

42671 F14

VOUT

LTC4267-1

CCRZ

ITH/RUN PGND

42671 F15

Figure 15. Main Loop Compensation for a Nonisolated Design

LTC4267-1

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transformer jack on the PD since this would compromise

the 802.3af isolation safety requirements.

Figure 16 demonstrates three methods of diode ORing

external power into a PD. Option 1 inserts power before

the LTC4267-1 interface controller while options 2 and

3 bypass the LTC4267-1 interface controller section and

power the switching regulator directly.

If power is inserted before the LTC4267-1 interface con-

troller, it is necessary for the wall transformer to exceed

the LTC4267-1 UVLO turn-on requirement and include a

transient voltage suppressor (TVS) to limit the maximum

voltage to 57V. This option provides input current limit

for the transformer, provides a valid power good signal,

and simplifies power priority issues. As long as the wall

transformer applies power to the PD before the PSE, it

will take priority and the PSE will not power up the PD

because the wall power will corrupt the 25k signature. If

the PSE is already powering the PD, the wall transformer

power will be in parallel with the PSE. In this case, prior-

ity will be given to the higher supply voltage. If the wall

transformer voltage is higher, the PSE should remove the

line voltage since no current will be drawn from the PSE.

On the other hand, if the wall transformer voltage is lower,

the PSE will continue to supply power to the PD and the

wall transformer will not be used. Proper operation should

occur in either scenario.

If auxiliary power is applied directly to the LTC4267-1

switching regulator (bypassing the LTC4267-1 PD inter-

face), a different set of trade-offs arise. In the configuration

shown in option 2, the wall transformer does not need

to exceed the LTC4267-1 turn-on UVLO requirement;

however, it is necessary to include diode D9 to prevent

the transformer from applying power to the LTC4267-1

interface controller. The transformer voltage requirement

will be governed by the needs of the onboard switching

regulator. However, power priority issues require more

intervention. If the wall transformer voltage is below

the PSE voltage, then priority will be given to the PSE

power. The LTC4267-1 interface controller will draw power

from the PSE while the transformer will sit unused. This

configuration is not a problem in a PoE system. On the

other hand, if the wall transformer voltage is higher than

the PSE voltage, the LTC4267-1 switching regulator will

draw power from the transformer. In this situation, it is

necessary to address the issue of power cycling that may

occur if a PSE is present. The PSE will detect the PD and

apply power. If the switcher is being powered by the wall

transformer, then the PD will not meet the minimum load

requirement and the PSE will subsequently remove power.

The PSE will again detect the PD and power cycling will

start. With a transformer voltage above the PSE voltage,

it is necessary to either disable the signature, as shown

in option 2, or install a minimum load on the output of the

LTC4267-1 interface to prevent power cycling.

The third option also applies power directly to the

LTC4267-1 switching regulator, bypassing the LTC4267-1

interface controller and omitting diode D9. With the

diode omitted, the transformer voltage is applied to the

LTC4267-1 interface controller in addition to the switching

regulator. For this reason, it is necessary to ensure that

the transformer maintain the voltage between 38V and 57V

to keep the LTC4267-1 interface controller in its normal

operating range. The third option has the advantage of

automatically disabling the 25k signature resistor when

the external voltage exceeds the PSE voltage.

Power-Up Sequencing the LTC4267-1

The LTC4267-1 consists of two functional cells, the PD

interface and the switching regulator, and the power up

sequencing of these two cells must be carefully considered.

The PD designer should ensure that the switching regulator

does not begin operation until the interface has completed

charging up the load capacitor. This will ensure that the

switcher load current does not compete with the load

capacitor charging current provided by the PD interface

current limit circuit. Overlooking this consideration may

result in slow power supply ramp up, power-up oscillation,

and possibly thermal shutdown.

The LTC4267-1 includes a power good signal in the PD

interface that can be used to indicate to the switching regu-

lator that the load capacitor is fully charged and ready to

handle the switcher load. Figure 7 shows two examples of

ways the PWRGD signal can be used to control the switch-

ing regulator. The first example employs an N-channel

MOSFET to drive the ITH/RUN port below the shutdown

threshold (typically 0.28V). The second example drives

LTC4267-1

42671fa

For more information www.linear.com/4267-1

RX–

RX+

TX–

TX+

RJ45 T1

SPARE–

–

SPARE+

ISOLATED

WALL

TRANSFORMER

TO PHY

VPORTP

OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267-1 PD

OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267-1 PD WITH SIGNATURE DISABLED

VPORTN POUT

PGND

38V TO 57V

S1B

SMAJ58A

TVS

PGND

C14

0.1µF

100V

RX–

RX+

TX–

TX+

RJ45 T1

SPARE–

–

SPARE+

ISOLATED

WALL

TRANSFORMER

TO PHY

VPORTP

SIGDISA

LTC4267-1

BR2

HD01

–

BR1

HD01

–

BR1

HD01

–

VPORTN POUT

42671 F16

D10

S1B

SMAJ58A

TVS

100k

S1B

OPTION 3: AUXILIARY POWER APPLIED TO LTC4267-1 PD AND SWITCHING REGULATOR

RX–

RX+

TX–

TX+

RJ45 T1

SPARE–

–

SPARE+

ISOLATED

WALL

TRANSFORMER

TO PHY

38V TO 57V

VPORTP

LTC4267-1

VPORTN POUT

D10

S1B

SMAJ58A

TVS

C14

0.1µF

100V

C14

0.1µF

100V

BR2

HD01

–

BR1

HD01

–

BR2

HD01

–

100k

BSS63

RSTART

CPVCC

RSTART

CPVCC

RSTART

CPVCC

PGND

PVCC

PGND

PVCC

applicaTions inForMaTion

Figure 16. Auxiliary Power Source for PD

LTC4267-1

42671fa

For more information www.linear.com/4267-1

applicaTions inForMaTion

PVCC below the PVCC turn-off threshold. Employing the

second example has the added advantage of adding delay

to the switching regulator start-up beyond the time the

power good signal becomes active. The second example

ensures additional timing margin at start-up without the

need for added delay components. In applications where it

is not desirable to utilize the power good signal, sufficient

timing margin can be achieved with RSTART and CPVCC.

RSTART and CPVCC should be set to a delay of two to three

times longer than the duration needed to charge up C1.

Layout Considerations for the LTC4267-1

The most critical layout considerations for the LTC4267-1

are the placement of the supporting external components

associated with the switching regulator. Efficiency, stabil-

ity, and load transient response can deteriorate without

good layout practices around critical components.

For the LTC4267-1 switching regulator, the current loop

through C1, T1 primary, Q1, and RSENSE must be given

careful layout attention. (Refer to Figure 11.) Because of

the high switching current circulating in this loop, these

components should be placed in close proximity to each

other. In addition, wide copper traces or copper planes

should be used between these components. If vias are

necessary to complete the connectivity of this loop, placing

multiple vias lined perpendicular to the flow of current is

essential for minimizing parasitic resistance and reducing

current density. Since the switching frequency and the

power levels are substantial, shielding and high frequency

layout techniques should be employed. A low current,

low impedance alternate connection should be employed

between the PGND pins of the LTC4267-1 and the PGND

side of RSENSE, away from the high current loop. This

Kelvin sensing will ensure an accurate representation of

the sense voltage is measured by the LTC4267-1.

The placement of the feedback resistors R1 and R2 as

well as the compensation capacitor CC is very important

in the accuracy of the output voltage, the stability of the

main control loop, and the load transient response. In

an isolated design application, R1, R2, and CC should be

placed as close as possible to the error amplifier’s input

with minimum trace lengths and minimum capacitance. In

a nonisolated application, R1, and R2 should be placed as

close as possible to the VFB pin of the LTC4267-1 and CC

should be placed close to the ITH/RUN pin of the LTC4267-1.

In essence, a tight overall layout of the high current loop

and careful attention to current density will ensure suc-

cessful operation of the LTC4267-1 in a PD.

Place C14 (Figure 9) as close as physically possible to the

LTC4267-1 across VPORTP and VPORTN. Place the series

10Ω resistor close to C14. Excessive parasitic capacitance

on the RCLASS pin should be avoided. The SIGDISA pin is

adjacent to the VPORTP pin and any coupling, whether resis-

tive or capacitive may inadvertently disable the signature

resistance. To ensure consistent behavior, the SIGDISA

pin should be electrically connected and not left floating.

Voltages in a PD can be as large as –57V, so high voltage

layout techniques should be employed.

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Class 3 PD with 5V Nonisolated Power Supply

PVCC

NGATE

PWRGD

SENSE

VFB

ITH/RUN

VPORTP

RCLASS

SIGDISA

VPORTN

LTC4267-1

45.3Ω

100k

1µF

300µF**

•

COILTRONICS

CTX-02-15242

BAS516

UPS840

SMAJ

58A

1.8A

HD01

–

–48V

FROM

DATA PAIR

–48V

FROM

SPARE PAIR

42671 TA02

FDC2512

0.04Ω

10k

220k

220Ω

42.2k

27k

150pF

200V

9.1V

22nF

0.1µF

5µF*

MIN

PGND

POUT

MMBTA42

8.06k

*1µF CERAMIC + 4.7µF TANTALUM

** THREE 100µF CERAMICS

10Ω

Typical applicaTions

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Synchronous Class 3 PD with Triple Output Isolated Power Supplies

Typical applicaTions

PVCC

NGATE

PWRGD

ITH/RUN

VFB

VPORTP

SIGDISA

VPORTN

LTC4267-1

45.3Ω

SMAJ

58A

PVCC

6.8k

0.1µF

5µF***

MIN

POUT PGND

0.1µF

6.8nF

•

2.2nF

250VAC

PS2911

42671 TA03

J1 HALO HFJ11 RP28E-L12 INTEGRATED JACK

T1 COILCRAFT D1766-AL

T2 PULSE PA0184

* TWO 100µF CAPACITORS IN PARALLEL

** 47µF AND 220µF IN PARALLEL

*** 1µF CERAMIC + 4.7µF TANTALUM

BAS516

220k

4.7µF

PVCC

220k

8.2V

8.2k

BCX5616

MMBT3904

51Ω

10Ω

10p

BAS516

0.068

10k

0.47µF

20Ω

0.033µF 4.7μF

49.9k

PH7030DL

BAT54SLT1

ZRL431

10Ω

2.2k

Si3440DV

Si3442DV

•

RCLASS SENSE

PHY

LTC4267-1

42671fa

For more information www.linear.com/4267-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN16 REV B 0212

1 2 345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ±.004

(0.38 ±0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

LTC4267-1

42671fa

For more information www.linear.com/4267-1

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 1/13 Changed 12.95W IEEE 802.3af reference to 13.0W.

Updated maximum power levels for class 0 and class 3 to 13.0W.

Optional circuit removed for clarification from Figure 7.

Added a 10Ω resistor to the VPORTP pin in Figures 9 and 10. Added Input Capacitor, Input Series Resistance and

Transient Voltage Suppressor sections.

Added C14 and 10Ω resistor layout recommendation.

Added a 10Ω resistor to the VPORTP pin.

17, 18

28, 29, 32

LTC4267-1

42671fa

For more information www.linear.com/4267-1

 LINEAR TECHNOLOGY CORPORATION 2007

LT 0113 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/4267-1

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC4265 IEEE 802.3at High Power PD Interface

Controller with 2-Event Classification

2-Event Classification Recognition, 100mA Inrush Current, Single-Class Programming

Resistor, Full Compliance to 802.3at

LTC4267 IEEE 802.3af PD Interface with Integrated

Switching Regulator

100V 400mA Internal Switch, Programmable Classification, 200kHz Constant

Frequency PWM

LTC4269-1 IEEE 802.3at PD Interface with Integrated

Flyback Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback

Controller, 50kHz to 250kHz, Auxiliary Support

LTC4269-2 IEEE802.3at PD Interface with Integrated

Forward Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback

Controller, 100kHz to 500kHz, Auxiliary Support

LTC4278 IEEE 802.3at PD Interface with Integrated

Flyback Switching Regulator

2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback

Controller, 50kHz to 250kHz, Auxiliary Support

LT4275A LTPoE++ ™ PD Controller Provides Up to 90W, External MOSFET for Lowest Power Dissipation and Highest

System Efficiency, 2-Event Classification, Programmable Classification

LT4275B IEEE 802.3at PD Controller External MOSFET for Lowest Power Dissipation and Highest System Efficiency,

2-Event Classification, Programmable Classification

LT4275C IEEE 802.3af PD Controller External MOSFET for Lowest Power Dissipation and Highest System Efficiency,

Programmable Classification

LTC4274 Single PoE PSE Controller Provides Up to 90W, 2-Event Classification, and Port Current and Voltage Monitoring

LTC4266 Quad PoE PSE Controller Provides Up to 90W, 2-Event Classification, and Port Current and Voltage Monitoring

High-Efficiency Class 3 PD with 3.3V Isolated Power Supply

PVCC

NGATE

SENSE

ITH/RUN

PWRGD

VFB

VPORTP

RCLASS

SIGDISA

VPORTN

LTC4267-1

45.3Ω

220k 330Ω220k

PVCC

4.7µF

SMAJ

58A

PULSE

PA1136

MMSD4148

BAS516

MMTBA42

–48V

FROM

DATA PAIR

–48V

FROM

SPARE PAIR

Si3440

2N7002

PVCC

100k

PVCC

6.8k

10k

0.1µF

5µF*

MIN

B1100

(8 PLACES)

POUT PGND

10Ω

9.1V 150pF

510Ω

500Ω

0.068Ω

100k

60.4k

570µF**

33nF

•

10Ω 470pF

2200pF

“Y” CAP

250VAC

PS2911

TLV431

SBM1040

3.3V

2.6A

CHASSIS

42671 TA04

*1µF CERAMIC + 4.7µF TANTALUM

**100µF CERAMIC + 470µF TANTALUM

BAS516

MMSD4148