W83176R-735 W83176G-735 Winbond 3 DIMM DDR ZERO DELAY BUFFER Date: Mar/31/2006 Revision: 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET W83176R-735/W83176G-735 Data Sheet Revision History PAGES 1 n.a. 2 3.7 DATES VERSION VERSION ON WEB MAIN CONTENTS n.a. All of the versions before 0.50 are for internal use. 12/18/03 0.5 n.a. Correction IC version, add register default value and correction some description and default value 3 05/03/04 1.0 1.0 Update to web 4 03/31/06 1.1 1.1 Add lead-free part number W83176G-735 5 6 7 8 9 1 0 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: March 31, 2006 Revision 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 1 2. PRODUCT FEATURES .............................................................................................................. 1 3. PIN CONFIGURATION ............................................................................................................... 1 3.1 4. 5. 6. 7. Block diagram ................................................................................................................. 2 PIN DESCRIPTION..................................................................................................................... 3 4.1 Clock Outputs ................................................................................................................. 3 4.2 Power Pins...................................................................................................................... 3 REGISTER 0 ~ REGISTER 4 RESERVED.............................................................................. 4 5.1 Register 5 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH).......................... 4 5.2 Register 6 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH).......................... 4 ACCESS INTERFACE ................................................................................................................ 5 6.1 Block Write protocol........................................................................................................ 5 6.2 Block Read protocol........................................................................................................ 5 6.3 Byte Write protocol ......................................................................................................... 5 6.4 Byte Read protocol ......................................................................................................... 5 SPECIFICATIONS ...................................................................................................................... 6 7.1 ABSOLUTE MAXIMUM RATINGS ................................................................................. 6 7.2 AC CHARACTERISTICS................................................................................................ 6 7.3 DC CHARACTERISTICS................................................................................................ 7 8. ORDERING INFORMATION ...................................................................................................... 8 9. HOW TO READ THE TOP MARKING........................................................................................ 8 10. PACKAGE DRAWING AND DIMENSIONS................................................................................ 9 - II - W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 1. GENERAL DESCRIPTION The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735 can support 3 D.D.R. DRAM DIMMs. The W83176R-735 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply. 2. PRODUCT FEATURES * * * * * * * Zero-delay clock outputs Feedback pins for synchronous Supports up to 3 D.D.R. DIMMs One pairs of additional outputs for feedback Low Skew outputs (< 100ps) Supports 400MHz D.D.R. SDRAM I2C 2-Wire serial interface and supports Byte or Block Date RW * 48-pin SSOP package 3. PIN CONFIGURATION C G N C L K C C L K T V D C L K T C L K C G N G N C L K C C L K T V D * S C L L K _ I N N / V D A V D A G N G N C L K C C L K T V D C L K T C L K C G N D 0 0 D 1 1 D D 2 2 D K T C D D D D 3 3 D 4 4 D 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 G C C V C C G G C C V S N F V F N G C C V C C G N D L K C L K T D D L K T L K C N D N D L K C L K T D D D A T / C B _ I N D D B _ O C N D L K C L K T D D L K T L K C N D 5 5 6 6 7 7 A * T U T T 8 8 9 9 *: Internal pull-up resistor 120K to VDD -1- Publication Release Date: March 31, 2006 Revision 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 3.1 Block diagram -2- W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 4. PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin *- 4.1 4.2 Internal 120k pull-up Clock Outputs SYMBOL PIN I/O CLKC[9:0] 26,30,40,43,4 7,23,19,9,6,2 OUT Complementory Clocks of differential pair outputs CLKT[9:0] 27,29,39,44,4 6,22,20,10,5,3 OUT True Clocks of differential pair outputs SDATA * 37 I/O SCLK * 12 IN CLK_INT 13 IN NC 14, 32,36 FB_OUTT 33 OUT FB_INT 35 IN FUNCTION Serial data of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd Serial clock of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd True reference clock input, 3.3V tolerant input NONE Not connected True Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. True Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. Power Pins SYMBOL PIN FUNCTION GND 1,7,8,18,24,25,31,41,42,48 VDD 4,11,15,21,28,34,38,45 Power Supply 2.5V AVDD 16 Analog power supply, 2.5V AGND 17 Analog ground -3- Ground Publication Release Date: March 31, 2006 Revision 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 5. REGISTER 0 ~ REGISTER 4 5.1 RESERVED Register 5 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH) BIT @POWERUP PIN 7 1 2,3 CLKC0,CLKT0 output control 6 1 6,5 CLKC1,CLKT1 output control 5 1 9,10 CLKC2,CLKT2 output control 4 1 19,20 CLKC3,CLKT3 output control 3 1 23,22 CLKC4,CLKT4 output control 2 1 26,27 CLKC9,CLKT9 output control 1 1 - Reserved 0 1 - Reserved 5.2 DESCRIPTION Register 6 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH) BIT @POWERUP PIN DESCRIPTION 7 1 - Reserved 6 1 - Reserved 5 1 - Reserved 4 1 30,29 CLKC8,CLKT8 output control 3 1 40,39 CLKC7,CLKT7 output control 2 1 43,44 CLKC6,CLKT6 output control 1 1 47,46 CLKC5,CLKT5 output control 0 1 - Reserved -4- W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 6. ACCESS INTERFACE The W83176R-735 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83176R-735 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C write address is defined at 0xD4. The I2C read address is defined at 0xD5. Block Read and Block Write Protocol 6.1 Block Write protocol 6.2 Block Read protocol ## In block mode, the command code must filled 00H 6.3 Byte Write protocol 6.4 Byte Read protocol -5- Publication Release Date: March 31, 2006 Revision 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 7. SPECIFICATIONS 7.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). SYMBOL PARAMETER VDD , AVDD Voltage on any pin with respect to GND TSTG Storage Temperature - 65C to + 150C TB Ambient Temperature - 55C to + 125C TA Operating Temperature 0C to + 70C 7.2 VDD RATING - 0.5 V to + 3.6 V AC CHARACTERISTICS = AVDD = 2.5V ( 5 % , TA = 0(C to +70(C, Test load = 10 pF PARAMETER SYMBOL MIN Operating clock frequency FIN Input Clock Duty Cycle Dtin Dynamic Supply Current Cycle to Cycle Jitter Output to Output Skew Output clock Rise time Output clock Fall time Output clock Duty Cycle Output differential-pair crossing voltag TYP MAX UNITS TEST CONDITIONS 100 200 MHz 40 60 % Idd 300 mA Fin=100 to 200Mhz C-Cjitter 200 ps Fout=100 to 200Mhz Tskew 100 ps Fout=100 to 200Mhz Tor 650 950 ps Fout=100 to 200Mhz Tof 650 950 ps Fout=100 to 200Mhz Dtot 45 55 % Fout=100 to 200Mhz Voc (Vdd/2)0.2 (Vdd/2) + 0.2 V Fout=100 to 200Mhz -6- Vdd/ 2 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 7.3 DC CHARACTERISTICS Vdd = AVDD= 2.5V ( 5 %, TA = 0(C to +70(C PARAMETER SYMBOL SDATA, SCLK Input Low Voltage SVIL SDATA, SCLK Input High Voltage SVIH MIN TYP MAX UNITS 1.0 Vdc 2.2 Vdc CLKIN, FBIN Input Voltage Low VIL CLKIN, FBIN Input Voltage High VIH Input Pin Capacitance CIN 5 pF COUT 6 pF LIN 7 nH Output Pin Capacitance Input Pin Inductance TEST CONDITIONS 0.4 2.1 Vdc Vdc -7- Fin=100 to 200Mhz Fin=100 to 200Mhz Publication Release Date: March 31, 2006 Revision 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 8. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83176R-735 48 PIN SSOP Commercial, 0C to +70C W83176G-735 48 PIN SSOP (Pb-free package) Commercial, 0C to +70C 9. HOW TO READ THE TOP MARKING W83176R-735 28051234 342GB W83176G-735 28051234 342GB 1st line: Winbond logo and the type number: W83176R-735/W83176G-735. 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G B 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. -8- W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET 10. PACKAGE DRAWING AND DIMENSIONS Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. -9- Publication Release Date: March 31, 2006 Revision 1.1 W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 10 -