STL8N65M2 Datasheet N-channel 650 V, 1 typ., 4 A MDmesh M2 Power MOSFET in a PowerFLAT 5x6 HV package Features 1 2 3 4 PowerFLAT 5x6 HV D(5, 6, 7, 8) 8 7 Order code VDS RDS(on ) max. ID STL8N65M2 650 V 1.25 4A * * Extremely low gate charge Excellent output capacitance (COSS) profile * * 100% avalanche tested Zener-protected 5 6 Applications * Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) AM15540v1 This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STL8N65M2 Product summary Order code STL8N65M2 Marking 8N65M2 Package PowerFLAT 5x6 HV Packing Tape and reel DS13016 - Rev 1 - May 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL8N65M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Value Unit 25 V Drain current (continuous) at TC = 25 C 4 A Drain current (continuous) at TC = 100 C 2.6 A Drain current pulsed 16 A Total power dissipation at TC = 25 C 48 W Avalanche current, repetitive or non-repetitive (pulse width limited by Tj max) 0.9 A Single pulse avalanche energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) 95 mJ Peak diode recovery voltage slope 15 MOSFET dv/dt ruggedness 50 Gate-source voltage ID IDM PTOT IAR EAS dv/dt Parameter (2) dv/dt (3) Tj Operating junction temperature range Tstg V/ns -55 to 150 C Value Unit Thermal resistance junction-case 2.6 C/W Thermal resistance junction-pcb 59 C/W Value Unit 0.5 C/W 88 C/W Storage temperature range 1. Pulse width is limited by safe operating area. 2. ISD 4 A, di/dt 400 A/s; VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS 480 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on 1 inch FR-4, 2 Oz copper board Table 3. Thermal data Symbol IAR EAS DS13016 - Rev 1 Parameter Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) Single pulse avalanche energy (starting Tj = 25 C, ID = IAR; VDD = 50 V) page 2/15 STL8N65M2 Electrical characteristics 2 Electrical characteristics TC = 25 C unless otherwise specified Table 4. On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 1 mA Min. Typ. 650 IDSS 1 A 100 A 10 A 3 4 V 1 1.25 Min. Typ. Max. Unit - 270 - pF - 14.5 - pF - 0.8 - pF VGS = 0 V, VDS = 650 V TC = 125 C (1) IGSS Gate-body leakage current VDS = 0 V, VGS = 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2 A Unit V VGS = 0 V, VDS = 650 V Zero gate voltage drain current Max. 2 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss eq. (1) Equivalent capacitance energy related VDS = 0 to 520 V, VGS = 0 V - 108 - pF Rg Intrinsic gate resistance f = 1 MHz open drain - 7 - Qg Total gate charge VDD = 520 V, ID = 5 A - 9 - nC Qgs Gate-source charge VGS = 0 to 10 V - 2.3 - nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior ) - 4.3 - nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS. Table 6. Switching times Symbol td(on) tr td(off) tf DS13016 - Rev 1 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 325 V, ID = 2.5 A, RG = 4.7 , VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) Min. Typ. Max. Unit - 7.7 - ns - 20 - ns - 19.5 - ns - 30 - ns page 3/15 STL8N65M2 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 4 A ISDM (1) Source-drain current (pulsed) - 16 A VSD (2) Forward on voltage ISD = 4 A, VGS = 0 V - 1.6 V trr Reverse recovery time ISD = 5 A, di/dt = 100 A/s, - 275 ns Qrr Reverse recovery charge - 1.62 C IRRM Reverse recovery current VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 11.8 A trr Reverse recovery time ISD = 5 A, di/dt = 100 A/s, - 430 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 C - 2.54 C IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 11.9 A 1. Pulse width is limited by safe operating area 2. Pulsed: pulse duration = 300 s, duty cycle 1.5% DS13016 - Rev 1 page 4/15 STL8N65M2 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GIPD080520191143SOA ZthPowerFlat_5x6_19 K d=0.5 0.2 tp =10 s 10 0.1 -1 0.05 0.02 0.01 S( on ) tp =100 s D 100 O lim pe ite rati d on by in R th is ar ea is 101 10-1 tp =1 ms tp =10 ms 10-2 Single pulse Single pulse,TC = 25 C TJ 150 C, VGS = 10 V 10-2 10 -1 10 0 10 1 VDS (V) 10 2 Figure 3. Output characteristics GIPG060820141159FSR ID (A) 10-5 10-4 10-3 10-2 10-1 100 tp(s) Figure 4. Transfer characteristics GIPG060820141210FSR ID (A) VDS=20V VGS=7, 8, 9, 10V 8 8 6V 6 6 4 4 5V 2 2 4V 0 0 10-3 -6 10 5 10 15 20 2 4 6 8 VGS(V) VDS(V) Figure 5. Normalized V(BR)DSS vs temperature V(BR)DSS 0 0 GADG270520190908MT (norm) Figure 6. Source-drain diode forward characteristics RDS(on) () GIPD220520191021RID ID=1mA 1.08 1.10 1.04 VGS = 10 V 1.05 1.00 1.00 0.96 0.95 0.92 0.88 -75 DS13016 - Rev 1 -25 0 25 75 125 TJ(C) 0.90 0 1 2 3 4 ID (A) page 5/15 STL8N65M2 Electrical characteristics curves Figure 7. Gate charge vs gate-source voltage GIPG060820141216FSR VDS VGS (V) VDS (V) VDD=520V ID=5A 12 600 10 500 8 400 6 300 4 200 2 100 Figure 8. Capacitance variations GIPG060820141238FSR C (pF) 1000 Ciss 0 0 2 4 8 6 0 Qg(nC) 10 Figure 9. Normalized gate threshold voltage vs temperature VGS(th) GADG270520190910MT (norm) ID=250A 1.1 10 Coss 1 Crss 0.1 0.1 1 100 10 VDS(V) Figure 10. Normalized on-resistance vs temperature GADG270520190911MT RDS(on) (norm) ID=2.5A VGS=10V 2.2 1.8 1.0 1.4 0.9 1.0 0.8 0.6 0.7 0.6 -75 100 25 0 25 75 125 TJ(C) Figure 11. Source-drain diode forward characteristics VSD (V) GIPD220520191023SDF 1.1 Tj = -50 C 0.2 -75 -25 0 25 125 TJ(C) 75 Figure 12. Output capacitance stored energy EOSS (J) GIPD080520191142EOS 2.4 1.0 Tj = 25 C 0.9 1.8 0.8 1.2 Tj = 150 C 0.7 0.6 0.6 0.5 0 DS13016 - Rev 1 1 2 3 4 ISD (A) 0.0 0 100 200 300 400 500 600 VDS (V) page 6/15 STL8N65M2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + F 3.3 F VDD VD VGS 1 k 100 nF RL IG= CONST VGS RG 47 k + pulse width D.U.T. 2.7 k 2200 F pulse width D.U.T. 100 VG 47 k 1 k AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 A L A B B 3.3 F D G + VD 100 H fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + F 2200 + F VDD 3.3 F VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS13016 - Rev 1 page 7/15 STL8N65M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS13016 - Rev 1 page 8/15 STL8N65M2 PowerFLAT 5x6 HV package information 4.1 PowerFLAT 5x6 HV package information Figure 19. PowerFLAT 5x6 HV package outline 8368143_Rev_4 DS13016 - Rev 1 page 9/15 STL8N65M2 PowerFLAT 5x6 HV package information Table 8. PowerFLAT 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 20. PowerFLATTM 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS13016 - Rev 1 page 10/15 STL8N65M2 PowerFLAT 5x6 packing information 4.2 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is 0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS13016 - Rev 1 page 11/15 STL8N65M2 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS13016 - Rev 1 page 12/15 STL8N65M2 Revision history Table 9. Document revision history DS13016 - Rev 1 Date Revision 30-May-2019 1 Changes First release page 13/15 STL8N65M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 PowerFLAT 5x6 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS13016 - Rev 1 page 14/15 STL8N65M2 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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(c) 2019 STMicroelectronics - All rights reserved DS13016 - Rev 1 page 15/15