1
2
34
PowerFLAT 5x6 HV
AM15540v1
5
6
7
8
1 2 3 4
Top View
D(5, 6, 7, 8)
G(4)
S(1, 2, 3)
Features
Order code VDS RDS(on ) max. ID
STL8N65M2 650 V 1.25 Ω 4 A
• Extremely low gate charge
• Excellent output capacitance (COSS) profile
• 100% avalanche tested
• Zener-protected
Applications
• Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh M2
technology. Thanks to its strip layout and an improved vertical structure, the device
exhibits low on-resistance and optimized switching characteristics, rendering it
suitable for the most demanding high efficiency converters.
Product status link
STL8N65M2
Product summary
Order code STL8N65M2
Marking 8N65M2
Package PowerFLAT 5x6 HV
Packing Tape and reel
N-channel 650 V, 1 Ω typ., 4 A MDmesh M2 Power MOSFET
in a PowerFLAT 5x6 HV package
STL8N65M2
Datasheet
DS13016 - Rev 1 - May 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
1Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VGS Gate-source voltage ±25 V
ID
Drain current (continuous) at TC = 25 °C 4 A
Drain current (continuous) at TC = 100 °C 2.6 A
IDM Drain current pulsed 16 A
PTOT Total power dissipation at TC = 25 °C 48 W
IAR Avalanche current, repetitive or non-repetitive (pulse width limited by Tj max) 0.9 A
EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 95 mJ
dv/dt (2) Peak diode recovery voltage slope 15
V/ns
dv/dt (3) MOSFET dv/dt ruggedness 50
TjOperating junction temperature range
-55 to 150 °C
Tstg Storage temperature range
1. Pulse width is limited by safe operating area.
2. ISD ≤ 4 A, di/dt ≤ 400 A/μs; VDS(peak) < V(BR)DSS, VDD = 400 V
3. VDS ≤ 480 V
Table 2. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 2.6 °C/W
Rthj-pcb (1) Thermal resistance junction-pcb 59 °C/W
1. When mounted on 1 inch² FR-4, 2 Oz copper board
Table 3. Thermal data
Symbol Parameter Value Unit
IAR
Avalanche current, repetetive or not
repetetive (pulse width limited by Tjmax)0.5 °C/W
EAS
Single pulse avalanche energy (starting
Tj = 25 °C, ID = IAR; VDD = 50 V) 88 °C/W
STL8N65M2
Electrical ratings
DS13016 - Rev 1 page 2/15
2Electrical characteristics
TC = 25 °C unless otherwise specified
Table 4. On/off-state
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown
voltage VGS = 0 V, ID = 1 mA 650 V
IDSS Zero gate voltage drain
current
VGS = 0 V, VDS = 650 V 1 µA
VGS = 0 V, VDS = 650 V
TC = 125 °C (1) 100 µA
IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V
RDS(on) Static drain-source
on-resistance VGS = 10 V, ID = 2 A 1 1.25 Ω
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
- 270 - pF
Coss Output capacitance - 14.5 - pF
Crss Reverse transfer capacitance - 0.8 - pF
Coss eq. (1) Equivalent capacitance
energy related VDS = 0 to 520 V, VGS = 0 V - 108 - pF
RgIntrinsic gate resistance f = 1 MHz open drain - 7 - Ω
QgTotal gate charge VDD = 520 V, ID = 5 A
VGS = 0 to 10 V
(see Figure 14. Test circuit for
gate charge behavior )
- 9 - nC
Qgs Gate-source charge - 2.3 - nC
Qgd Gate-drain charge - 4.3 - nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDS.
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 325 V, ID = 2.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13. Test circuit for
resistive load switching times
and Figure 18. Switching time
waveform)
- 7.7 - ns
trRise time - 20 - ns
td(off) Turn-off delay time - 19.5 - ns
tfFall time - 30 - ns
STL8N65M2
Electrical characteristics
DS13016 - Rev 1 page 3/15
Table 7. Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD Source-drain current - 4 A
ISDM (1) Source-drain current (pulsed) - 16 A
VSD (2) Forward on voltage ISD = 4 A, VGS = 0 V - 1.6 V
trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs,
VDD = 60 V (see
Figure 15. Test circuit for
inductive load switching and
diode recovery times)
- 275 ns
Qrr Reverse recovery charge - 1.62 µC
IRRM Reverse recovery current - 11.8 A
trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs,
VDD = 60 V, Tj = 150 °C
(see Figure 15. Test circuit for
inductive load switching and
diode recovery times)
- 430 ns
Qrr Reverse recovery charge - 2.54 µC
IRRM Reverse recovery current - 11.9 A
1. Pulse width is limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
STL8N65M2
Electrical characteristics
DS13016 - Rev 1 page 4/15
2.1 Electrical characteristics curves
Figure 1. Safe operating area
GIPD080520191143SOA
101
100
10-1
10 -1 10 0 10 1 10 2
ID
(A)
VDS (V)
Operation in this area is
limited by R DS(on)
tp =10 µs
tp =100 µs
tp =1 ms
tp =10 ms
Single pulse,TC = 25 °C
TJ ≤ 150 °C, VGS = 10 V
10-2
Figure 2. Thermal impedance
Single pulse
0.05
0.02
0.01
d=0.5
0.1
0.2
K
tp(s)
10-5 10-4 10-3
10-2
10-1
10-6
10-3
10-2
ZthPowerFlat_5x6_19
10-1 100
Figure 3. Output characteristics
ID
6
2
005VDS(V)
10
(A)
15
4V
5V
VGS=7, 8, 9, 10V
4
8
20
6V
GIPG060820141159FSR
Figure 4. Transfer characteristics
I
D
6
4
2
0
0 4 V
GS
(V)
8
(A)
2 6
8
V
DS
=20V
GIPG060820141210FSR
Figure 5. Normalized V(BR)DSS vs temperature
V
(BR)DSS
-75 0 T
J
(°C)
(norm)
-25 75
25 125
0.88
0.92
0.96
1.00
1.04
1.08
I
D
=1mA
GADG270520190908MT
Figure 6. Source-drain diode forward characteristics
GIPD220520191021RID
1.10
1.05
1.00
0.95
0.900 1 2 3 4
RDS(on)
(Ω)
ID (A)
VGS = 10 V
STL8N65M2
Electrical characteristics curves
DS13016 - Rev 1 page 5/15
Figure 7. Gate charge vs gate-source voltage
VGS
6
4
2
004Qg(nC)
(V)
8
68
10
VDD=520V
ID=5A
300
200
100
0
400
500
VDS
210
VDS
(V)
12 600
GIPG060820141216FSR
Figure 8. Capacitance variations
C
100
10
1
0.1
0.1 10 VDS(V)
(pF)
1100
Ciss
Coss
Crss
1000
GIPG060820141238FSR
Figure 9. Normalized gate threshold voltage vs
temperature
V
GS(th)
0.9
0.8
0.7
0.6
-75 0 T
J
(°C)
(norm)
25
1.0
75
25 125
I
D
=250μA
1.1
GADG270520190910MT
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
1.8
1.0
0.2
-75 0 T
J
(°C)
(norm)
-25 75
25 125
0.6
1.4
2.2
I
D
=2.5A
V
GS
=10V
GADG270520190911MT
Figure 11. Source-drain diode forward characteristics
GIPD220520191023SDF
1.1
1.0
0.9
0.8
0.7
0.6
0.50 1 2 3 4
VSD
(V)
ISD (A)
Tj = -50 °C
Tj = 25 °C
Tj = 150 °C
Figure 12. Output capacitance stored energy
GIPD080520191142EOS
2.4
1.8
1.2
0.6
0.00 100 200 300 400 500 600
EOSS
(µJ)
VDS (V)
STL8N65M2
Electrical characteristics curves
DS13016 - Rev 1 page 6/15
3Test circuits
Figure 13. Test circuit for resistive load switching times
AM01468v1
VD
RG
RL
D.U.T.
2200
μF VDD
3.3
μF
+
pulse width
VGS
Figure 14. Test circuit for gate charge behavior
AM01469v1
47 kΩ 1 kΩ
47 kΩ
2.7 kΩ
1 kΩ
12 V
IG= CONST 100 Ω
100 nF
D.U.T.
+
pulse width
VGS
2200
μF
VG
VDD
Figure 15. Test circuit for inductive load switching and
diode recovery times
AM01470v1
A
D
D.U.T.
SB
G
25 Ω
AA
BB
RG
G
D
S
100 µH
µF
3.3 1000
µF VDD
D.U.T.
+
_
+
fast
diode
Figure 16. Unclamped inductive load test circuit
AM01471v1
VD
ID
D.U.T.
L
VDD
+
pulse width
Vi
3.3
µF
2200
µF
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STL8N65M2
Test circuits
DS13016 - Rev 1 page 7/15
4Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
STL8N65M2
Package information
DS13016 - Rev 1 page 8/15
4.1 PowerFLAT 5x6 HV package information
Figure 19. PowerFLAT 5x6 HV package outline
8368143_Rev_4
STL8N65M2
PowerFLAT 5x6 HV package information
DS13016 - Rev 1 page 9/15
Table 8. PowerFLAT 5x6 HV mechanical data
Dim.
mm
Min. Typ. Max.
A 0.80 1.00
A1 0.02 0.05
A2 0.25
b 0.30 0.50
C 5.60 5.80 6.00
D 5.10 5.20 5.30
D2 4.30 4.40 4.50
D4 4.60 4.80 5.00
E 6.05 6.15 6.25
E1 3.50 3.60 3.70
E2 3.10 3.20 3.30
E4 0.40 0.50 0.60
E5 0.10 0.20 0.30
E7 0.40 0.50 0.60
e 1.27
L 0.50 0.55 0.60
K 1.90 2.00 2.10
Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm)
8368143_Rev_4_footprint
STL8N65M2
PowerFLAT 5x6 HV package information
DS13016 - Rev 1 page 10/15
4.2 PowerFLAT 5x6 packing information
Figure 21. PowerFLAT 5x6 tape (dimensions are in mm)
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
8234350_Tape_rev_C
Figure 22. PowerFLAT 5x6 package orientation in carrier tape
Pin 1
identification
STL8N65M2
PowerFLAT 5x6 packing information
DS13016 - Rev 1 page 11/15
Figure 23. PowerFLAT 5x6 reel
STL8N65M2
PowerFLAT 5x6 packing information
DS13016 - Rev 1 page 12/15
Revision history
Table 9. Document revision history
Date Revision Changes
30-May-2019 1 First release
STL8N65M2
DS13016 - Rev 1 page 13/15
Contents
1Electrical ratings ..................................................................2
2Electrical characteristics...........................................................3
2.1 Electrical characteristics curves ..................................................5
3Test circuits .......................................................................7
4Package information...............................................................8
4.1 PowerFLAT 5x6 HV package information ..........................................8
4.2 PowerFLAT 5x6 packing information .............................................10
Revision history .......................................................................13
STL8N65M2
Contents
DS13016 - Rev 1 page 14/15
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© 2019 STMicroelectronics – All rights reserved
STL8N65M2
DS13016 - Rev 1 page 15/15