CY62137CV30LL-70BAXE - Cypress Semiconductor Corp.

2M (128K x 16) Static RAM

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05201 Rev. *E Revised April 4, 2005

Features

• Very high speed: 55 ns and 70 n s

•Temperature Ranges

—Industrial: –40°C to +85°C

—Automotive: –40°C to +125°C

• Pin-compatible with the CY62137V

• Ultra-low active power

—Typical active current: 1.5 mA @ f = 1 MHz

—Typical active current: 5.5 mA @ f = fmax (70-ns

speed)

• Low and ultra-low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down wh en deselected

• CMOS for optimum speed/power

• Packages offered in a Lead-Free and Non-Lead Free

48-ball FBGA

Functional Description[1]

The CY62137CV25/30/33 and CY62137CV are high-perfor-

mance CMOS static RAMs organized as 128K words by 16

bits. These devices feature advanced circuit design to provide

ultra-low active current. This is ideal for providing More Battery

Life™ (MoBL®) in portable applications such as cel lular tele-

phones. The devices also has an automatic power-dow n fea-

ture that significantly reduces power consumption by 80%

when addresses are not toggling. T he devi ce can al so be put

into standby mode reducing power consumption by more than

99% when deselected (CE HIGH or both BLE and BHE are

HIGH). The input/output pins (I/O0 through I/O15) are placed

in a high-impedance state when: deselected (CE HIGH), out-

puts are disabled (OE HIGH), both Byte High Enable and Byte

Low Enable are disab led (BHE , BLE HIGH), or during a write

operation (CE LOW, and WE LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O 7), is

written into the location specified on the address pins (A0

through A16). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8 through I/O15) is written into the location

specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O0 to I/O7. If Byte High Ena ble (BHE) is

LOW , then data from memory will appear on I/O8 to I/O15. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Note:

1. For best practice recommendation s, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

128K x 16

RAM Array I/O0–I/O7

ROW DECODER

COLUMN DECODER

A11

A12

A13

A14

A15

2048 x 1024

SENSE AMPS

DATA IN DRIVERS

A3I/O8–I/O15

BLE

BHE

A16

Power-down BHE

BLE

A10

Circuit

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 2 of 12

Pin Configuration[2, 3]

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential –0.5V to VCCMAX + 0.5V

DC Voltage Applied to Outputs

in High-Z State[4]....................................–0.5V to VCC + 0.3V

DC Input Voltage[4].................................... −0.5V to VCC + 0.3V

Output Current into Output s (LO W).......... .............. ... ..20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current ................................................... > 200 mA

Notes:

2. NC pins are not connected to the die.

3. E3 (DNU) can be left as NC or VSS to ensure proper application.

4. VIL(min.) = –2.0V for pulse durations less than 20 ns.

5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.

A11

A10

A3CE

I/O10

I/O8

I/O9

I/O11

I/O13

I/O12

I/O14

I/O15

VSS

I/O0

BHE

BLE

VCC

I/O2

I/O1

I/O3

I/O4

I/O5I/O6

I/O7

A15

A14

A13

A12

NC NC

FBGA (Top View)

A16

DNU

VCC

Operating Range

Device Range Ambient

Temperature TAVCC

CY62137CV25 Industrial –40°C to +85 °C 2.2V to 2.7V

CY62137CV30 2.7V to 3.3V

CY62137CV33 3.0V to 3.6V

CY62137CV 2.7V to 3.6V

CY62137CV30 Automotive –40°C to +125°C 2.7V to 3.3V

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating, ICC (mA) Standby, I SB2 (µA)f = 1 MHz f = fmax

Range Min. Typ.[5] Max. Typ.[5] Max. Typ.[5] Max. Typ.[5] Max.

CY62137CV25LL Industrial 2.2 2.5 2.7 55 1.5 3 7 15 2 10

70 1.5 3 5.5 12

CY62137CV30LL Industrial 2.7 3.0 3.3 55 1.5 3 7 15 2 10

70 1.5 3 5.5 12

CY62137CV30LL Automotive 2.7 3.0 3.3 70 1.5 3 5.5 15 2 15

CY62137CV33LL Industrial 3.0 3.3 3.6 55 1.5 3 7 15 5 15

70 1.5 3 5.5 12

CY62137CVLL Industrial 2.7V 3.3 3.6 70 1.5 3 5.5 12 5 15

CY62137CVSL Industrial 2.7V 3.3 3.6 70 1.5 3 5.5 12 1 5

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 3 of 12

Electrical Characteristics Over the Operating Range

Parameter Description Tes t Co nditions

CY62137CV25-55 CY62137CV25-70

UnitMin. Typ.[5] Max. Min. Typ.[5] Max.

VOH Output HIGH Voltage IOH = –0.1 mA VCC = 2.2V 2.0 2.0 V

VOL Output LOW Voltage IOL = 0.1 mA VCC = 2.2V 0.4 0.4 V

VIH Input HIGH Voltage 1.8 VCC +

0.3V 1.8 VCC +

0.3V V

VIL Input LOW Voltage –0.3 0.6 –0.3 0.6 V

IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA

IOZ Output Leakage

Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA

ICC VCC Operating Supply

Current f = fMAX = 1/t RC VCC = 2.7V

IOUT = 0 mA

CMOS Levels

715 5.5 12 mA

f = 1 MHz 1.5 31.5 3

ISB1 Automatic CE

Power-down Current—

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = fmax (Address and Data Only),

f=0 (OE, WE, BHE, and BLE)

210 210 µA

ISB2 Automatic CE

Power-down Current—

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = 2.7V

Parameter Description Test Conditions

CY62137CV30-55 CY62137CV30-70

UnitMin. Typ.[5] Max. Min. Typ.[5] Max.

VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.3V 2.2 VCC +

0.3V V

VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V

IIX Input Leakage Current GND < VI < VCC Ind’l –1 +1 –1 +1 µA

Auto –2 +2

IOZ Output Leakage

Current GND < VO < VCC,

Output Disabled Ind’l –1 +1 –1 +1 µA

Auto –2 +2

ICC VCC Operating Supply

Current f = fMAX = 1/tRC VCC =

3.3V

IOUT =

0 mA

CMOS

Levels

Ind’l 715 5.5 12 mA

Auto 5.5 15

f = 1 MHz 1.5 31.5 3

ISB1 Automatic CE

Power-down Current—

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V

or VIN < 0.2V,

f = fmax (Address

and Data Only),

f=0 (OE, WE,

BHE, and BLE)

Ind’l 210 210 µA

Auto 215

ISB2 Automatic CE

Power-down Current—

CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V

or VIN < 0.2V

f = 0, VCC = 3.3V

Ind’l 210 210

Auto 215

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 4 of 12

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY62137CV33-55 CY62137CV33-70

CY62137CV-70

UnitMin. Typ.[5] Max. Min. Typ.[5] Max.

VOH Output HIGH Voltage IOH = –1.0 mA VCC = 3.0V 2.4 2.4 V

VCC = 2.7V 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA VCC = 3.0V 0.4 0.4 V

VCC = 2.7V 0.4 V

VIH Input HIGH Voltage 2.2 VCC +

0.3V 2.2 VCC +

0.3V V

VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V

IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA

IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA

ICC VCC Operating Supply Cur-

rent f = fMAX = 1/tRC VCC = 3.6V

IOUT = 0 mA

CMOS Levels

715 5.5 12 mA

f = 1 MHz 1.5 31.5 3

ISB1 Automatic CE

Power-down Current

—CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = fmax (Address and Data Only),

f=0 (OE, WE, BHE, and BLE)

515 515 µA

ISB2 Automatic CE

Power-down Current

—CMOS Inputs

CE > VCC – 0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = 3.6V

LL 515 515

SL 1 5

Capacitance[6]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = VCC(typ.) 6pF

COUT Output Capacitance 8pF

Thermal Resistance

Parameter Description Test Condition s BGA Unit

ΘJA Thermal Resistance

(Junction to Ambient)[6] Still Air, soldered on a 3 x 4.5 inch, two-layer printed

circuit board 55 °C/W

ΘJC Thermal Resistance

(Junction to Case)[6] 16 °C/W

AC Test Loads and Waveforms

VCC Typ

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

OUTPUT VTH

Equivalent to: THÉ VENINEQUIVALENT

ALL INPUT PULSES

RTH

Rise TIme: 1 V /ns Fall Time: 1 V/ns

Parameters 2.5V 3.0V 3.3V Unit

R1 16600 1105 1216 Ω

R2 15400 1550 1374 Ω

RTH 8000 645 645 Ω

VTH 1.20 1.75 1.75 V

Note:

6. Tested initially and after any design or process changes that may affect these parameters.

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 5 of 12

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Typ.[5] Max. Unit

VDR VCC for Data Retention 1.5 Vccmax V

ICCDR Data Retention Current VCC= 1.5V

CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V

LL Ind’l 1 6

µAAuto 8

SL Ind’l 4

tCDR[6] Chip Deselect to Data Retention Time 0ns

tR[7] Operation Recovery Time tRC ns

Data Retention Waveform[8]

Switching Characteristics Over the Operating Range[9]

Parameter Description

55 ns 70 ns

UnitMin Max Min Max

Read Cycle

tRC Read Cycle Time 55 70 ns

tAA Address to Data Valid 55 70 ns

tOHA Data Hold from Address Change 10 10 ns

tACE CE LOW to Data Valid 55 70 ns

tDOE OE LOW to Data Va lid 25 35 ns

tLZOE OE LOW to Low-Z[10] 5 5 ns

tHZOE OE HIGH to High-Z[10, 12] 20 25 ns

tLZCE CE LOW to Low-Z[10] 10 10 ns

tHZCE CE HIGH to High-Z[10, 12] 20 25 ns

tPU CE LOW to Power-up 0 0 ns

tPD CE HIGH to Power-down 55 70 ns

tDBE BHE/BLE LOW to Data Valid 55 70 ns

tLZBE[11] BHE/BLE LOW to Low-Z[10] 5 5 ns

tHZBE BHE/BLE HIGH to High-Z[10, 12] 20 25 ns

Write Cycle[13]

tWC Wr it e C ycle Time 55 70 ns

tSCE CE LOW to W rite End 45 60 ns

tAW Address Set-up to Write End 45 60 ns

Notes:

7. Full-device AC operation requires line ar VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.

8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

9. Test conditions assume signal transit ion time of 5 ns or less, timing ref erence levels of V CC(typ.)/2, inp ut pulse levels of 0 to V CC(typ.), and output loa ding of th e

specified IOL/IOH and 30-pF load capacit ance.

10. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any

given device.

11. If both byte enables are toggled together this value is 10 ns.

12. tHZOE, tHZCE, tHZBE, and tHZWE tra nsitions are measured when the outputs enter a high impedance state.

13. The internal writ e time o f th e memory is de fin ed by the o verlap of WE , CE = VIL, BHE and/or BLE = VIL. A ll sig nals mu st b e ACTIVE to ini tiate a wri te and any

of these signals can terminate a writ e by going INACTIVE. The d ata input set- up and hold timin g should be referenced to t he edge of the signa l that terminates

the write.

VCC(min.)

tCDR

VDR >1.5 V

DATA RETENTION MODE

CE or

VCC

BHE.BLE

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 6 of 12

tHA Address Hold from Write End 0 0 ns

tSA Address Set-up to Write Start 0 0 ns

tPWE WE Pulse Width 40 45 ns

tBW BHE/BLE Pulse Width 50 60 ns

tSD Data Set-up to Write End 25 30 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High-Z[10, 12] 20 25 ns

tLZWE WE HIGH to Low-Z[10] 10 10 ns

Switching Characteristics Over the Operating Range[9] (continued)

Parameter Description

55 ns 70 ns

UnitMin Max Min Max

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[14, 15]

Read Cycle No. 2 (OE Controlled)[15, 16]

Notes:

14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.

15. WE is HIGH for read cycle.

16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

ACE

LZBE

LZCE

DATA OUT HIGH IMPEDANCE IMPEDANCE

HZOE

HZCE

HIGH

SUPPLY

CURRENT

HZBE

BHE/BLE t

LZOE

ADDRESS

DOE

LZOE

DBE

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 7 of 12

Write Cycle N o. 1 (WE Controlled)[13, 17, 18]

Write Cycle N o. 2 (CE Controlled)[13, 17, 18]

Notes:

17. Data I/O is high-impedance if OE = VIH.

18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

19. During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

ADDRESS

DATA I/O

NOTE 19

BHE/BLE tBW

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

ADDRESS

DATA I/O

NOTE 19

BHE/BLE tBW

tSA

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 8 of 12

Write Cycle N o. 3 (WE Controlled, OE LOW) [18]

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [18]

Switching Waveforms (continued)

DATAIN VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATAI/O NOTE 19

tBW

BHE/BLE

DATA I/O

ADDRESS

tWC

DATA

VALID

NOTE 19

BHE/BLE

tSCE

PWE

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 9 of 12

Truth Table

CE WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X High-Z Deselect/Power-down Standby (ISB)

X X X H H High-Z Deselect/Power-down Standby (ISB)

L H L L L Data Out (I/OO–I/O15)Read Active (ICC)

L H L H L Data Out (I/OO–I/O7);

I/O8–I/O15 in High-Z Read Active (ICC)

L H L L H Dat a Out (I/O8–I/O15);

I/O0–I/O7 in High-Z Read Active (ICC)

L H H L L High-Z Output Disabled Active (ICC)

L H H H L High-Z Output Disabled Active (ICC)

L H H L H High-Z Output Disabled Active (ICC)

L L X L L Data In (I/OO–I/O15)Write Active (ICC)

L L X H L Data In (I/OO–I/O7);

I/O8–I/O15 in High-Z Write Active (ICC)

L L X L H Data In (I/O8–I/O15);

I/O0–I/O7 in High-Z Write Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Voltage

Range (V) Package

Name Package Type Operating

Range

70 CY62137CV25LL-70BAI 2.2–2.7 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) Industrial

CY62137CV25LL-70BVI 2.2–2.7 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

CY62137CV30LL-70BAI 2.7–3.3 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

CY62137CV30LL-70BVI 2.7–3.3 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

CY62137CV30LL-70BAXE 2.7–3.3 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

(Pb-Free) Automotive

CY62137CV30LL-70BVXE 2.7–3.3 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

(Pb-Free)

CY62137CV33LL-70BAI 3.0–3.6 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) Industrial

CY62137CV33LL-70BVI 3.0–3.6 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

CY62137CVLL-70BAI 2.7–3.6 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

CY62137CVLL-70BVI 2.7–3.6 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

CY62137CVSL-70BAI 2.7–3.6 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

CY62137CVSL-70BVI 2.7–3.6 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

55 CY62137CV25LL-55BAI 2.2–2.7 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

CY62137CV25LL-55BVI 2.2–2.7 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

CY62137CV30LL-55BAI 2.7–3.3 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

CY62137CV30LL-55BVI 2.7–3.3 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

CY62137CV33LL-55BAI 3.0–3.6 BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)

CY62137CV33LL-55BVI 3.0–3.6 BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 10 of 12

Package Diagrams

48-ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A

51-85096-*E

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 11 of 12

© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is su bject to change without notice. C ypr ess S em i con duct or Corpo ration assu me s no resp onsib ility for th e u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and

company names mentioned in this document may be the trademarks of their respective hol ders.

Package Diagrams (continued)

48-Lead VFBGA (6 x 8 x 1 mm) BV48A

51-85150-*B

CY62137CV25/30/33 MoBL®

CY62137CV MoBL®

Document #: 38-05201 Rev. *E Page 12 of 12

Document History Page

Document Title: CY62137CV25/30/33 MoBL® and CY62137CV MoBL® 2M (128K x 16) Static RAM

Document Number: 38-05201

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 112393 02/19/02 GAV New Data Sheet (advance information)

*A 114015 04/25/02 JUI Added BV package diagram

Changed from Advance Information to Preliminary

*B 117064 07/12/02 MGN Changed from Preliminary to Final

*C 118122 09/10/02 MGN A dded new part number: CY62137CV with wider voltage (2.7V – 3.6V).

Added new SL power bin for new part number.

For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns.

For TAA = 70 ns, improved tPWE min. from 50 ns to 45 ns.

For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns.

*D 118761 09/23/02 MGN Improved Typ. ICC spec to 7 mA (for 55 ns) and 5.5 mA (for 70 ns).

Improved Max ICC spec to 15 mA (for 55 ns) and 12 mA (for 70 ns).

For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns.

Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX + 0.5V.

Changed upper spec. for DC Vol tage Applied to Outpu ts in High-Z State and DC

Input Voltage to VCC + 0.3V.

*E 343877 See ECN PCI Added Automotive Information in Operating Range, DC and Ordering Information

Table