EP7312 Data Sheet FEATURES High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface ARM(R)720T Processor -- ARM7TDMI CPU operating at speeds of 74 and 90 MHz -- 8 KBytes of four-way set-associative cache -- MMU with 64-entry TLB -- Thumb code support enabled Ultra low power -- 90 mW at 74 MHz typical -- 108 mW at 90 MHz typical -- <.03 mW in the Standby State Advanced audio decoder/decompression capability -- Supports bit streams with adaptive bit rates -- Allows for support of multiple audio decompression algorithms (MP3, WMA, AAC, Audible, etc.) OVERVIEW The Cirrus LogicTM EP7312 is designed for ultra-lowpower portable and line-powered applications such as portable consumer entertainment devices, home and car audio juke box systems, and general purpose industrial control applications, or any device that features the added capability of digital audio compression & decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 KBytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft(R) Windows(R) CE and Linux(R). ORDERING INFORMATION: See list of available parts with legend on page 63. (cont.) (cont.) BLOCK DIAGRAM Serial Interface EPB Bus Power Management ARM720T ICE-JTAG Interrupts, PWM & GPIO ARM7TDMI CPU Core 8 KB Cache (2) UARTs w/ IrDA Clocks & Timers Boot ROM Write Buffer Bus Bridge MMU Keypad& Touch Screen I/F Internal Data Bus Memory Controller MaverickKeyTM SRAM I/F SDRAM I/F On-chip SRAM 48 KB USER INTERFACE SERIAL PORTS Digital Audio Interface LCD Controller MEMORY and STORAGE Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com MAY '02 DS508PP5 1 EP7312 High-Performance, Low-Power System on Chip FEATURES (cont) 48 KBytes of on-chip SRAM MaverickKeyTM IDs -- 32-bit unique ID can be used for DRM compliance 128-bit random ID Available in 74 and 90 MHz clock speeds LCD controller -- Interfaces directly to a single-scan panel monochrome STN LCD -- Interfaces to a single-scan panel color STN LCD with minimal external glue logic Full JTAG boundary scan and Embedded ICE support Integrated Peripheral Interfaces -- 32-bit SDRAM Interface up to 2 external banks -- 8/32/16-bit SRAM/FLASH/ROM Interface -- Digital Audio Interface providing glueless interface to low-power DACs, ADCs and CODECs -- Two Synchronous Serial Interfaces (SSI1, SSI2) -- CODEC Sound Interface -- 8x8 Keypad Scanner -- 27 General Purpose Input/Output pins -- Dedicated LED flasher pin from the RTC Internal Peripherals -- Two 16550 compatible UARTs -- IrDA Interface -- Two PWM Interfaces -- Real-time Clock -- Two general purpose 16-bit timers -- Interrupt Controller -- Boot ROM Package -- 208-Pin LQFP -- 256-Ball PBGA -- 204-Ball TFBGA The fully static EP7312 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process OVERVIEW (cont.) The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. The device has three basic power states: operating, idle and standby. MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. 2 The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, high quality ADCs, DACs, or CODECs such as the Cirrus Logic CS53L32A, CS43L42, and CS42L50 are easily added to an EP73xx design via the DAI. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Simply by adding desired memory and peripherals to the highly integrated EP7312 completes a low-power system solution. All necessary interface logic is integrated onchip. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table of Contents FEATURES ...........................................................................................................................................1 OVERVIEW ...........................................................................................................................................1 FEATURES (cont) .......................................................................................................................................................2 OVERVIEW (cont.) ......................................................................................................................................................2 Description of the EP7312's Components, Functionality, and Interfaces ....................................6 Processor Core - ARM720T ..................................................................................................................................6 Power Management ..............................................................................................................................................6 MaverickKeyTM Unique ID ......................................................................................................................................6 Memory Interfaces .................................................................................................................................................6 Digital Audio Capability .........................................................................................................................................7 Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7 Digital Audio Interface (DAI) ..................................................................................................................................7 CODEC Interface ..................................................................................................................................................8 SSI2 Interface ........................................................................................................................................................8 Synchronous Serial Interface ................................................................................................................................8 LCD Controller .......................................................................................................................................................8 64-Key Keypad Interface .......................................................................................................................................9 Interrupt Controller ................................................................................................................................................9 Real-Time Clock ....................................................................................................................................................9 PLL and Clocking ..................................................................................................................................................9 DC-to-DC Converter Interface (PWM) .................................................................................................................10 Timers .................................................................................................................................................................10 General Purpose Input/Output (GPIO) ................................................................................................................10 Hardware Debug Interface ..................................................................................................................................10 LED Flasher ........................................................................................................................................................10 Internal Boot ROM ...............................................................................................................................................10 Packaging ............................................................................................................................................................10 Pin Multiplexing ...................................................................................................................................................11 System Design ....................................................................................................................................................12 Contacting Cirrus Logic Support For a com plete listing of D irect Sales, D istributor, and S ales R epresentative contacts, visit the C irrus Logic w eb site at: http://www.cirrus.com /corporate/contacts/sales.cfm IM PO RTA NT N O TIC E "Prelim inary" product inform ation describes products that are in production, but for w hich full characterization data is not yet available. "Advance" product inform ation describes products that are in developm ent and subject to developm ent changes. C irrus Logic, Inc. and its subsidiaries ("C irrus") believe that the inform ation contained in this docum ent is accurate and reliable. H ow ever, the inform ation is subject to change w ithout notice and is provided "AS IS" without w arranty of any kind (express or im plied). C ustom ers are advised to obtain the latest version of relevant inform ation to verify, before placing orders, that inform ation being relied on is current and com plete. A ll products are sold subject to the term s and conditions of sale supplied at the tim e of order acknowledgm ent, including those pertaining to w arranty, patent infringem ent, and lim itation of liability. No responsibility is assum ed by Cirrus for the use of this inform ation, including use of this inform ation as the basis for m anufacture or sale of any item s, or for infringem ent of patents or other rights of third parties. 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A n export license and/or quota needs to be obtained from the com petent authorities of the C hinese G overnm ent if any of the products or technologies described in this m aterial is subject to the P R C Foreign Trade Law and is to be exported or taken out of the PR C . C E R TA IN AP P LIC A TIO N S U SING SE M IC O N D U C TO R P R O D UC TS M AY IN V O LV E P O TEN TIAL RISK S O F D E ATH , PE R SO NA L IN JU R Y , O R SE V ER E P RO PE R TY O R E N V IR O N M E NTAL D A M A G E ("C R ITIC A L AP P LIC A TIO N S "). C IR R U S P R O D U CTS A R E N O T D E SIG NE D , AU TH O R IZE D , O R W AR R A N TE D TO B E S U ITAB LE FO R U S E IN LIFE -S U PP O R T D E V IC ES O R SY S TE M S O R O TH E R CR ITIC A L AP P LIC A TIO N S . IN C LU S IO N O F C IR R U S P R O D U CTS IN S U C H AP P LIC A TIO N S IS U N D E R S TO O D TO B E FU LLY A T TH E C US TO M E R'S R IS K . C irrus Logic, C irrus, and the C irrus Logic logo designs are tradem arks of C irrus Logic, Inc. A ll other brand and product nam es in this docum ent m ay be tradem arks or service m arks of their respective ow ners. DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 3 EP7312 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS ...................................................................................................... 13 Absolute Maximum Ratings ................................................................................................................................ 13 Recommended Operating Conditions ................................................................................................................. 13 DC Characteristics .............................................................................................................................................. 13 Timings .............................................................................................................................................. 15 Timing Diagram Conventions .................................................................................................................... 15 Timing Conditions ..................................................................................................................................... 15 SDRAM Interface ................................................................................................................................................ 16 SDRAM Load Mode Register Cycle .......................................................................................................... 17 SDRAM Burst Read Cycle ........................................................................................................................ 18 SDRAM Burst Write Cycle ........................................................................................................................ 19 SDRAM Refresh Cycle .............................................................................................................................. 20 Static Memory ..................................................................................................................................................... 21 Static Memory Single Read Cycle ............................................................................................................ 22 Static Memory Single Write Cycle ............................................................................................................. 23 Static Memory Burst Read Cycle .............................................................................................................. 24 Static Memory Burst Write Cycle .............................................................................................................. 25 SSI1 Interface ..................................................................................................................................................... 26 SSI2 Interface ..................................................................................................................................................... 27 LCD Interface ...................................................................................................................................................... 28 JTAG Interface .................................................................................................................................................... 29 Packages ............................................................................................................................................ 30 208-Pin LQFP Package Characteristics ............................................................................................................. 30 208-Pin LQFP Pin Diagram ................................................................................................................................ 31 208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32 204-Ball TFBGA Package Characteristics .......................................................................................................... 38 204-Ball TFBGA Pinout (Top View) ..................................................................................................................... 39 204-Ball TFBGA Ball Listing ............................................................................................................................... 40 256-Ball PBGA Package Characteristics ............................................................................................................ 47 256-Ball PBGA Pinout (Top View) ....................................................................................................................... 49 256-Ball PBGA Ball Listing ................................................................................................................................. 50 JTAG Boundary Scan Signal Ordering ............................................................................................................... 55 CONVENTIONS ................................................................................................................................. 61 Acronyms and Abbreviations .............................................................................................................................. 61 Units of Measurement ......................................................................................................................................... 61 General Conventions .......................................................................................................................................... 62 Pin Description Conventions ............................................................................................................................... 62 Ordering Information ........................................................................................................................ 63 Ordering Information Legend .............................................................................................................................. 63 4 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip List of Figures Figure 1. A Fully-Configured EP7312-Based System ...................................................................................................12 Figure 2. Legend for Timing Diagrams .........................................................................................................................15 Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17 Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18 Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19 Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20 Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22 Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23 Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24 Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25 Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26 Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27 Figure 13. LCD Controller Timing Measurement ..........................................................................................................28 Figure 14. JTAG Timing Measurement .........................................................................................................................29 Figure 15. 208-Pin LQFP Package Outline Drawing ....................................................................................................30 Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................31 Figure 17. 204-Ball TFBGA Package ............................................................................................................................38 Figure 18. 256-Ball PBGA Package ..............................................................................................................................47 List of Tables Table 1. Power Management Pin Assignments ..............................................................................................................6 Table 2. Static Memory Interface Pin Assignments ........................................................................................................6 Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7 Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7 Table 5. DAI Interface Pin Assignments .........................................................................................................................7 Table 6. CODEC Interface Pin Assignments ..................................................................................................................8 Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8 Table 8. Serial Interface Pin Assignments ......................................................................................................................8 Table 9. LCD Interface Pin Assignments ........................................................................................................................8 Table 10. Keypad Interface Pin Assignments .................................................................................................................9 Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9 Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9 Table 13. PLL and Clocking Pin Assignments ................................................................................................................9 Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10 Table 15. General Purpose Input/Output Pin Assignments ..........................................................................................10 Table 16. Hardware Debug Interface Pin Assignments ................................................................................................10 Table 17. LED Flasher Pin Assignments ......................................................................................................................10 Table 18. DAI/SSI2/CODEC Pin Multiplexing ...............................................................................................................11 Table 19. Pin Multiplexing .............................................................................................................................................11 Table 20. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................32 Table 21. 204-Ball TFBGA Ball Listing .........................................................................................................................40 Table 22. 256-Ball PBGA Ball Listing ...........................................................................................................................50 Table 23. JTAG Boundary Scan Signal Ordering .........................................................................................................55 Table 24. Acronyms and Abbreviations ........................................................................................................................61 Table 25. Unit of Measurement .....................................................................................................................................61 Table 26. Pin Description Conventions .........................................................................................................................62 DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 5 EP7312 High-Performance, Low-Power System on Chip Description of the EP7312's Components, Functionality, and Interfaces The following sections describe the EP7312 in more detail. Processor Core - ARM720T The EP7312 incorporates an ARM 32-bit RISC micro controller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include: * ARM (32-bit) and Thumb (16-bit compressed) instruction sets * Enhanced MMU for Microsoft Windows CE and other operating systems * 8 KB of 4-way set-associative cache. * Translation Look Aside Buffers with 64 Translated Entries Power Management The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. The device has three basic power states: * Operating -- This state is the full performance state. All the clocks and peripheral logic are enabled. * Idle -- This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. * Standby -- This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor. Table 1 shows the power management pin assignments. Table 1. Power Management Pin Assignments Pin Mnemonic I/O Pin Description BATOK I Battery ok input nEXTPWR I External power supply sense input nPWRFL I Power fail sense input nBATCHG I Battery changed sense input MaverickKeyTM Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly 6 becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances. Memory Interfaces There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burstmode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industryleading code density. shows the Static Memory Interface pin assignments. Table 2. Static Memory Interface Pin Assignments Pin Mnemonic I/O Pin Description nCS[5:0] O Chip select out A[27:0] O Address output D[31:0] I/O Data I/O nMOE/nSDCAS (Note) O ROM expansion OP enable nMWE/nSDWE (Note) O ROM expansion write enable HALFWORD O Halfword access select output WORD O Word access select output O Transfer direction WRITE/nSDRAS Note: (Note) Pins are multiplexed. See Table 19 on page 11 for more information. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip The second is the programmable 16- or 32-bit-wide SDRAM interface that allows direct connection of up to two banks of SDRAM, totaling 512 Mb. To assure the lowest possible power consumption, the EP7312 supports self-refresh SDRAMs, which are placed in a low-power state by the device when it enters the lowpower Standby State. Table 3 shows the SDRAM Interface pin assignments. drive an infrared communication interface directly. Table 4 shows the UART pin assignments. Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments Pin Mnemonic I/O Pin Description TXD[1] O UART 1 transmit RXD[1] I UART 1 receive CTS I UART 1 clear to send Table 3. SDRAM Interface Pin Assignments Pin Mnemonic I/O Pin Description DCD I UART 1 data carrier detect SDCLK O SDRAM clock output DSR I UART 1 data set ready SDCKE O SDRAM clock enable output TXD[2] O UART 2 transmit nSDCS[1:0] O SDRAM chip select out RXD[2] I UART 2 receive WRITE/nSDRAS (Note 2) O SDRAM RAS signal output LEDDRV O Infrared LED drive output nMOE/nSDCAS (Note 2) O SDRAM CAS control signal PHDIN I Photo diode input nMWE/nSDWE (Note 2) O SDRAM write enable control signal A[27:15]/DRA[0:12] (Note 1) O SDRAM address O SDRAM internal bank select I/O SDRAM byte lane mask SDQM[3:2] O SDRAM byte lane mask D[31:0] I/O Data I/O A[14:13]/DRA[12:14] PD[7:6]/SDQM[1:0] Note: (Note 2) 1. Pins A[27:13] map to DRA[0:14] respectively. (i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to balance the load for large memory systems. 2. Pins are multiplexed. See Table 19 on page 11 for more information. Digital Audio Interface (DAI) The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal CS43L41/42/43 low-power audio DACs and the Crystal CS53L32 low-power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Table 5 shows the DAI Interface pin assignments. Table 5. DAI Interface Pin Assignments Pin Mnemonic Digital Audio Capability The EP7312 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7312 Universal Asynchronous Receiver/Transmitters (UARTs) I/O Pin Description SCLK O Serial bit clock SDOUT O Serial data out SDIN I Serial data in LRCK O Sample clock MCLKIN I Master clock input MCLKOUT O Master clock output Note: See Table 18 on page 11 for information on pin multiplexes. The EP7312 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the RX/TX signals to/from UART 1 to enable these signals to DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 7 EP7312 High-Performance, Low-Power System on Chip CODEC Interface Synchronous Serial Interface The EP7312 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the DAI and SSI2. Table 6 shows the CODEC Interface Pin Assignments. The EP7312 Synchronous Serial Interface has these features: Table 6. CODEC Interface Pin Assignments Pin Mnemonic I/O Pin Description PCMCLK O Serial bit clock PCMOUT O Serial data out PCMIN I Serial data in PCMSYNC O Frame sync Note: See Table 18 on page 11 for information on pin multiplexes. SSI2 Interface An additional SPI/Microwire1-compatible interface is available for both master and slave mode communications. The SSI2 unit shares the same pins as the DAI and CODEC interfaces through a multiplexer. The SSI2 Interface has these features: * * * * Synchronous clock speeds of up to 512 kHz Separate 16 entry TX and RX half-word wide FIFOs Half empty/full interrupts for FIFOs Separate RX and TX frame sync signals for asymmetric traffic Table 7 shows the SSI2 Interface pin assignments. Table 7. SSI2 Interface Pin Assignments Pin Mnemonic I/O Pin Description SSICLK I/O Serial bit clock SSITXDA O Serial data out SSIRXDA I Serial data in SSITXFR I/O Transmit frame sync SSIRXFR I/O Receive frame sync Note: 8 * ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation) * Selectable serial clock polarity Table 8 shows the Synchronous Serial Interface pin assignments. See Table 18 on page 11 for information on pin multiplexes. Table 8. Serial Interface Pin Assignments Pin Mnemonic I/O Pin Description ADCLK O SSI1 ADC serial clock ADCIN I SSI1 ADC serial input ADCOUT O SSI1 ADC serial output nADCCS O SSI1 ADC chip select SMPCLK O SSI1 ADC sample clock LCD Controller A DMA address generator is provided that fetches video display data for the LCD controller from memory. The display frame buffer start address is programmable, allowing the LCD frame buffer to be in SDRAM, internal SRAM or external SRAM. The LCD controller has these features: * Interfaces directly to a single-scan panel monochrome STN LCD * Interfaces to a single-scan panel color STN LCD with minimal external glue logic * Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments * Video frame buffer size programmable up to 128 KB * Bits per pixel of 1, 2, or 4 bits Table 9 shows the LCD Interface pin assignments. Table 9. LCD Interface Pin Assignments Pin Mnemonic I/O Pin Description CL1 O LCD line clock CL2 O LCD pixel clock out DD[3:0] O LCD serial display data bus FRM O LCD frame synchronization pulse M O LCD AC bias drive Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 64-Key Keypad Interface . Table 11. Interrupt Controller Pin Assignments Matrix keyboards and keypads can be easily read by the EP7312. A dedicated 8-bit column driver output generates strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR'ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state. The Keypad Interface has these features: * Column outputs can be individually set high with the remaining bits left at high-impedance * Column outputs can be driven all-low, all-high, or allhigh-impedance * Keyboard interrupt driven by OR'ing together all Port A bits * Keyboard interrupt can be used to wake up the system * 8x8 keyboard matrix usable with no external logic, extra keys can be added with minimal glue logic Table 10 shows the Keypad Interface Pin Assignments. Pin Mnemonic I/O Pin Description nEINT[2:1] I External interrupt EINT[3] I External interrupt nEXTFIQ I External Fast Interrupt input I Media change interrupt input nMEDCHG/nBROM Note: (Note) Pins are multiplexed. See Table 19 on page 11 for more information. Real-Time Clock The EP7312 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. * Driven by an external 32.768 kHz crystal oscillator Table 12 shows the Real-Time Clock pin assignments. Table 10. Keypad Interface Pin Assignments Table 12. Real-Time Clock Pin Assignments Pin Mnemonic I/O Pin Description O Keyboard scanner column drive Pin Mnemonic COL[7:0] Pin Description RTCIN Real-Time Clock Oscillator Input Interrupt Controller RTCOUT Real-Time Clock Oscillator Output When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. The EP7312 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. The Interrupt controller has these features: VDDRTC Real-Time Clock Oscillator Power VSSRTC Real-Time Clock Oscillator Ground * Supports 22 interrupts from a variety of sources (such as UARTs, SSI1, and key matrix.) * Routes interrupt sources to the ARM720T's IRQ or FIQ (Fast IRQ) inputs * Five dedicated off-chip interrupt lines operate as level sensitive interrupts Table 11 shows the interrupt controller pin assignments. PLL and Clocking The EP7312 processor and peripheral clocks have these features: * Processor and peripheral clocks operate from a single 3.6864 MHz crystal or external 13 MHz clock * Programmable clock speeds allow the peripheral bus to run at 18 MHz when the processor is set to 18 MHz and at 36 MHz when the processor is set to 36, 49 or 74 MHz, and at 45 MHz when the processor is set to 90 MHz. Table 13 shows the PLL and clocking pin assignments. Table 13. PLL and Clocking Pin Assignments Pin Mnemonic DS508PP5 Pin Description MOSCIN Main Oscillator Input MOSCOUT Main Oscillator Output VDDOSC Main Oscillator Power VSSOSC Main Oscillator Ground Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 9 EP7312 High-Performance, Low-Power System on Chip DC-to-DC Converter Interface (PWM) * Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter Table 14 shows the DC-to-DC Converter Interface pin assignments. Table 14. DC-to-DC Converter Interface Pin Assignments Pin Mnemonic DRIVE[1:0] I/O Pin Description I/O FB[1:0] PWM drive output I PWM feedback input Timers * Internal (RTC) timer * Two internal 16-bit programmable hardware countdown timers General Purpose Input/Output (GPIO) * Three 8-bit and one 3-bit GPIO ports * Supports scanning keyboard matrix Table 15 shows the GPIO pin assignments. Table 16. Hardware Debug Interface Pin Assignments Pin Mnemonic I/O Pin Description TCLK I JTAG clock TDI I JTAG data input TDO O JTAG data output nTRST I JTAG async reset input TMS I JTAG mode select LED Flasher A dedicated LED flasher module can be used to generate a low frequency signal on Port D pin 0 for the purpose of blinking an LED without CPU intervention. The LED flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicator on a portable phone or an appointment reminder on a PDA. Table 17 shows the LED Flasher pin assignments. * * * * Software adjustable flash period and duty cycle Operates from 32 kHz RTC clock Will continue to flash in IDLE and STANDBY states 4 mA drive current Table 17. LED Flasher Pin Assignments Table 15. General Purpose Input/Output Pin Assignments Pin Mnemonic I/O Pin Description Pin Mnemonic PD[0]/LEDFLSH (Note) I/O O Pin Description LED flasher driver PA[7:0] I GPIO port A PB[7:0] I GPIO port B I/O GPIO port D I/O GPIO port D I/O GPIO port D PE[1:0]/BOOTSEL[1:0] (Note) I GPIO port E The internal 128-byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH. PE[2]/CLKSEL I GPIO port E Packaging PD[0]/LEDFLSH (Note) PD[5:1] PD[7:6]/SDQM[1:0] Note: (Note) (Note) Pins are multiplexed. See Table 19 on page 11 for more information. Note: Pins are multiplexed. See Table 19 on page 11 for more information. Internal Boot ROM The EP7312 is available in a 208-pin LQFP package, 256ball PBGA package, or a 204-ball TFBGA package. Hardware Debug Interface * Full JTAG boundary scan and Embedded ICE support Table 16 shows the Hardware Debug Interface pin assignments. 10 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Pin Multiplexing Table 18 shows the pin multiplexing of the DAI, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7312 User's Manual for more information). Table 18. DAI/SSI2/CODEC Pin Multiplexing Pin Mnemonic I/O DAI SSI2 CODEC SSICLK I/O SCLK SSICLK PCMCLK SSITXDA O SDOUT SSITXDA PCMOUT SSIRXDA I SDIN SSIRXDA PCMIN SSITXFR I/O LRCK SSITXFR PCMSYNC SSIRXFR I MCLKIN SSIRXFR p/u BUZ O MCLKOUT DS508PP5 Table 19 shows the pins that have been multiplexed in the EP7312. Table 19. Pin Multiplexing Signal Block Signal Block nMOE Static Memory nSDCAS SDRAM nMWE Static Memory nSDWE SDRAM WRITE Static Memory nSDRAS SDRAM A[27:15] Static Memory DRA[0:12] SDRAM A[14:13] Static Memory DRA[13:14] SDRAM PD[7:6] GPIO SDQM[1:0] SDRAM RUN System Configuration CLKEN System Configuration nMEDCHG Interrupt Controller nBROM Boot ROM select PD[0] GPIO LEDFLSH LED Flasher PE[1:0] GPIO BOOTSEL[1:0] System Configuration PE[2] GPIO CLKSEL System Configuration Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 11 EP7312 High-Performance, Low-Power System on Chip System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated CRYSTAL MOSCIN CRYSTAL RTCIN EP7312 completes a low-power system solution. All necessary interface logic is integrated on-chip. DD[0-3] CL1 CL2 FRM M LCD COL[0-7] KEYBOARD D[0-31] PA[0-7] A[0-27] PB[0-7] nMOE WRITE PD[0-7] SDRAS/ SDCAS x16 SDRAM x16 SDRAM SDCS[0] x16 SDRAM x16 SDRAM SDCS[1] SDQM[0-3] SDQM[0-3] EP7312 PE[0-2] nPOR nPWRFL BATOK nEXTPWR nBATCHG RUN WAKEUP DRIVE[0-1] FB[0-1] nCS[0] nCS[1] DC-TO-DC CONVERTERS x16 FLASH x16 FLASH x16 FLASH x16 FLASH LEDDRV PHDIN IR LED AND PHOTODIODE RXD[[1/2] TXD[1/2] DSR CTS DCD 2x RS-232 TRANSCEIVERS ADCCLK nADCCS ADCOUT ADCIN SMPCLK ADC EXTERNAL MEMORYMAPPED EXPANSION BUFFERS nCS[2] nCS[3] BUFFERS AND LATCHES LEDFLSH DC INPUT BATTERY SSICLK SSITXFR SSITXDA SSIRXDA SSIRXFR CS[n] WORD ADDITIONAL I/O POWER SUPPLY UNIT AND COMPARATORS CODEC/SSI2/ DAI DIGITIZER Figure 1. A Fully-Configured EP7312-Based System Note: 12 A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC Core, PLL, and RTC Supply Voltage 2.9 V DC I/O Supply Voltage (Pad Ring) 3.6 V DC Pad Input Current 10 mA/pin; 100 mA cumulative Storage Temperature, No Power -40C to +125C Recommended Operating Conditions DC core, PLL, and RTC Supply Voltage 2.5 V 0.2 V DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.5 V DC Input / Output Voltage O-I/O supply voltage Operating Temperature Extended -20C to +70C; Commercial 0C to +70C; Industrial -40C to +85C DC Characteristics All characteristics are specified at VDDCORE = 2.5 V, VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0C to +70C for all frequencies of operation. The current consumption figures have test conditions specified per parameter." Symbol Parameter Min Typ Max Unit Conditions VIH CMOS input high voltage 0.65 x VDDIO - VDDIO + 0.3 V VDDIO = 2.5 V VIL CMOS input low voltage VSS - 0.3 - 0.25 x VDDIO V VDDIO = 2.5 V VT+ Schmitt trigger positive going threshold - - 2.1 V VT- Schmitt trigger negative going threshold 0.8 - - V Vhst Schmitt trigger hysteresis 0.1 - 0.4 V VIL to VIH VDD - 0.2 2.5 2.5 - - V V V IOH = 0.1 mA IOH = 4 mA IOH = 12 mA Output drive 2a - - 0.3 0.5 0.5 V V V IOL = -0.1 mA IOL = -4 mA IOL = -12 mA Input leakage current - - 1.0 A VIN = VDD or GND 25 - 100 A VOUT = VDD or GND 8 - 10.0 pF CMOS output high voltagea VOH Output drive 1a Output drive 2a CMOS output low voltagea VOL IIN IOZ CIN DS508PP5 Output drive 1a Bidirectional 3-state leakage currentb c Input capacitance Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 13 EP7312 High-Performance, Low-Power System on Chip Symbol Parameter Min Typ Max Unit COUT Output capacitance 8 - 10.0 pF CI/O Transceiver capacitance 8 - 10.0 pF IDDSTANDBY @ 25 C IDDSTANDBY @ 70 C IDDSTANDBY @ 85 C Standby current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V Standby current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V - 77 41 - - 570 111 A Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD 0.1 V, VIL = GND 0.1 V A Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD 0.1 V, VIL = GND 0.1 V A Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD 0.1 V, VIL = GND 0.1 V mA Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = VDD 0.1 V, VIL = GND 0.1 V Standby current consumption Core, Osc, RTC @2.5 V1 I/O @ 3.3 V IDDidle at 74 MHz Idle current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V IDDIDLE at 90 MHz Idle current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V VDDSTANDBY Standby supply voltage - - - 6 10 1693 163 - - 7 11 - mA Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = VDD 0.1 V, VIL = GND 0.1 V 2.0 - - V Minimum standby voltage for state retention, internal SRAM cache, and RTC operation only a. Refer to the strength column in the pin assignment tables for all package types. b. Assumes buffer has no pull-up or pull-down resistors. c. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven. Note: 14 - Conditions 1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V 2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs). 2) Pull-up current = 50 A typical at VDD = 3.3 V. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Timings Timing Diagram Conventions This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated. C lo c k H ig h H ig h /L o w B u s to to L o w H ig h C h a n g e B u s V a lid U n d e fin e d /In v a lid V a lid B u s to T r is ta te B u s /S ig n a l O m is s io n Figure 2. Legend for Timing Diagrams Timing Conditions Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at VDDIO = 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40C to +85C. Pin loadings is 50 pF. The timing values are referenced to 1/2 VDD. DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 15 EP7312 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter Symbol Min Typ Max Unit SDCLK rising edge to SDCS assert delay time tCSa 0 2 4 ns SDCLK rising edge to SDCS deassert delay time tCSd -3 2 10 ns SDCLK rising edge to SDRAS assert delay time tRAa 1 3 7 ns SDCLK rising edge to SDRAS deassert delay time tRAd -3 1 10 ns SDCLK rising edge to SDRAS invalid delay time tRAnv 2 4 7 ns SDCLK rising edge to SDCAS assert delay time tCAa -2 2 5 ns SDCLK rising edge to SDCAS deassert delay time tCAd -5 0 3 ns SDCLK rising edge to ADDR transition time tADv -3 1 5 ns SDCLK rising edge to ADDR invalid delay time tADx -2 2 5 ns SDCLK rising edge to SDMWE assert delay time tMWa -2 1 5 ns SDCLK rising edge to SDMWE deassert delay time tMWd -4 0 4 ns DATA transition to SDCLK rising edge time tDAs - - 2 ns SDCLK rising edge to DATA transition hold time tDAh - - 1 ns SDCLK rising edge to DATA transition delay time tDAd 0 - 15 ns 16 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip SDRAM Load Mode Register Cycle SDCLK t C Sa t C Sd t R Aa t R Ad t C Aa t C Ad SDCS SDRAS SDCAS t AD v t AD x ADDR DATA SDQM tM W a tM W d SDMW E Figure 3. SDRAM Load Mode Register Cycle Timing Measurement Note: DS508PP5 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM controls and data signals are approximately equal Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 17 EP7312 High-Performance, Low-Power System on Chip SDRAM Burst Read Cycle SDCLK t C Sa SDCS t C Sa t C Sd t C Sd t R Aa SDRAS t R Anv t R Ad t C Aa t C Ad SDCAS t AD v ADDR t AD v ADRAS ADCAS t D As DATA D1 t D Ah t D As t D As D2 t D Ah D3 t D Ah t D As D4 t D Ah SDQM [0 :3 ] SDMW E Figure 4. SDRAM Burst Read Cycle Timing Measurement Note: 18 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM central and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM controls and data signals are approximately equal. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip SDRAM Burst Write Cycle SDCLK t C Sa t C Sa t C Sd SDCS t C Sd t R Aa t R Ad SDRAS t C Aa t C Ad SDCAS t AD v t AD v t D Ad t D Ad t D Ad D2 D1 DATA SDQM ADCAS ADRAS ADDR t D Ad D3 D4 0 tM W a tM W d SDMW E Figure 5. SDRAM Burst Write Cycle Timing Measurement Note: DS508PP5 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM central and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM controls and data signals are approximately equal Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 19 EP7312 High-Performance, Low-Power System on Chip SDRAM Refresh Cycle S D C LK t CSa t CSd t RAa t RAd SDCS SD RA S t CAd SD CA S t CAa S D A TA AD DR SDQM [3:0] SDM WE Figure 6. SDRAM Refresh Cycle Timing Measurement Note: 20 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM central and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM controls and data signals are approximately equal Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes. Parameter Symbol Min Typ Max Unit EXPCLK rising edge to nCS assert delay time tCSd 2 8 20 ns EXPCLK falling edge to nCS deassert hold time tCSh 2 7 20 ns EXPCLK rising edge to A assert delay time tAd 4 9 16 ns EXPCLK falling edge to A deassert hold time tAh 3 10 19 ns EXPCLK rising edge to nMWE assert delay time tMWd 3 6 10 ns EXPCLK rising edge to nMWE deassert hold time tMWh 3 6 10 ns EXPCLK falling edge to nMOE assert delay time tMOEd 3 7 10 ns EXPCLK falling edge to nMOE deassert hold time tMOEh 2 7 10 ns EXPCLK falling edge to HALFWORD deassert delay time tHWd 2 8 20 ns EXPCLK falling edge to WORD assert delay time tWDd 2 8 16 ns EXPCLK rising edge to data valid delay time tDv 8 13 21 ns EXPCLK falling edge to data invalid delay time tDnv 6 15 30 ns Data setup to EXPCLK falling edge time tDs - - 1 ns EXPCLK falling edge to data hold time tDh - - 3 ns EXPCLK rising edge to WRITE assert delay time tWRd 5 11 23 ns EXPREADY setup to EXPCLK falling edge time tEXs - - 0 ns EXPCLK falling edge to EXPREADY hold time tEXh - - 0 ns DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 21 EP7312 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle EXPCLK t C Sd t C Sh nCS t Ad A nM W E t M O Ed t M O Eh nM OE tH W d HALFW ORD tW D d W ORD tD s tD h D t EXs t EXh EXPRDY tW R d W R IT E Figure 7. Static Memory Single Read Cycle Timing Measurement Note: 22 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Address, Halfword, Word, and Write hold state until next cycle. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Static Memory Single Write Cycle EXPCLK t C Sd t C Sh nCS t Ad A tM W d tM W h nM W E nM OE tH W d HALFW ORD tW D d W ORD tD v D t EXs t EXh EXPRDY W R IT E Figure 8. Static Memory Single Write Cycle Timing Measurement Note: DS508PP5 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 3. Address, Data, Halfword, Word, and Write hold state until next cycle. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 23 EP7312 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle EXPCLK t C Sd t C Sh nCS t Ad t Ah t Ah t Ah A nM W E t M O Ed t M O Eh nM OE tH W d HALF W ORD tW D d W ORD tD s tD h tD s tD h tD s tD h tD s tD h D t EXs t EXh EXPRDY tW R d W R IT E Figure 9. Static Memory Burst Read Cycle Timing Measurement Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. 4. Address, Halfword, Word, and Write hold state until next cycle. 24 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Static Memory Burst Write Cycle EXPCLK t C Sd t C Sh nCS t Ah t Ah t Ah t Ad A tM W d tM W d tM W d tM W h nM W E tM W d tM W h tM W h tM W h nM OE tH W d HALF W ORD W ORD tW D d tD v t D nv tD v t D nv tD v t D nv tD v D t EXs t EXh EXPRDY W R IT E Figure 10. Static Memory Burst Write Cycle Timing Measurement Note: DS508PP5 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 4. Address, Data, Halfword, Word, and Write hold state until next cycle. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 25 EP7312 High-Performance, Low-Power System on Chip SSI1 Interface Parameter Symbol Min Max Unit ADCCLK falling edge to nADCCSS deassert delay time tCd 9 10 ms ADCIN data setup to ADCCLK rising edge time tINs - 15 ns ADCIN data hold from ADCCLK rising edge time tINh - 14 ns ADCCLK falling edge to data valid delay time tOvd -7 13 ns ADCCLK falling edge to data invalid delay time tOd -2 3 ns ADC CLK tCd nADC CSS tINs tINh ADCIN tOvd tOd ADC OUT Figure 11. SSI1 Interface Timing Measurement 26 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip SSI2 Interface Parameter Symbol Min Max Unit SSICLK period (slave mode) tclk_per 185 2050 ns SSICLK high time tclk_high 925 1025 ns SSICLK low time tclk_low 925 1025 ns SSICLK rise/fall time tclkrf 3 18 ns SSICLK rising edge to RX and/or TX frame sync high time tFRd - 3 ns SSICLK rising edge to RX and/or TX frame sync low time tFRa - 8 ns tFR_per 960 990 ns SSIRXDA setup to SSICLK falling edge time tRXs 3 7 ns SSIRXDA hold from SSICLK falling edge time tRXh 3 7 ns SSICLK rising edge to SSITXDA data valid delay time tTXd - 2 ns SSITXDA valid time tTXv 960 990 ns SSIRXFR and/or SSITXFR period t clk_per t clk_high t clk_low SSI CLK t clkrf t FR _per t FR d t FR a S S IR X F R / S S IT X F R t R Xh t R Xs SSI RXDA D7 D2 D1 D0 D7 D2 D1 D0 t TXd SSI TXDA t TXv Figure 12. SSI2 Interface Timing Measurement DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 27 EP7312 High-Performance, Low-Power System on Chip LCD Interface Parameter Symbol Min Max Unit CL[2] falling to CL[1] rising delay time tCL1d - 10 25 ns CL[1] falling to CL[2] rising delay time tCL2d 80 3,475 ns CL[1] falling to FRM transition time tFRMd 300 10,425 ns CL[1] falling to M transition time tMd - 10 20 ns CL[2] rising to DD (display data) transition time tDDd - 10 20 ns C L [2 ] t C L2d t C L1d C L [1 ] t FR M d FRM tM d M tD D d D D [3 :0 ] Figure 13. LCD Controller Timing Measurement 28 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip JTAG Interface Parameter Symbol Min Max Units TCK clock period tclk_per 2 - ns TCK clock high time tclk_high 1 - ns TCK clock low time tclk_low 1 - ns JTAG port setup time tJPs - 0 ns JTAG port hold time tJPh - 3 ns JTAG port clock to output tJPco - 10 ns JTAG port high impedance to valid output tJPzx - 12 ns JTAG port valid output to high impedance tJPxz - 19 ns t clk_per t clk_high t clk_low TCK t JPh t JPs TM S TDI t JPzx t JPco t JPxz TDO Figure 14. JTAG Timing Measurement DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 29 EP7312 High-Performance, Low-Power System on Chip Packages 208-Pin LQFP Package Characteristics 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) EP7312 29.60 (1.165) 30.40 (1.197) 208-Pin LQFP 0.50 (0.0197) BSC Pin 1 Indicator Pin 208 Pin 1 0.45 (0.018) 0.75 (0.030) 1.35 (0.053) 1.45 (0.057) 1.00 (0.039) BSC 0.09 (0.004) 0.20 (0.008) 0 MIN 7 MAX 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006) Figure 15. 208-Pin LQFP Package Outline Drawing Note: 30 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 4) For pin locations, please see Figure 16. For pin descriptions see the EP7312 User's Manual. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 1 35 1 34 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 nU R E S ET nM ED C H G /nB R O M nPO R BATO K nE XT P W R n BA T C H G D [7] V S SIO A [7] D [8] A [8] D [9] A [9] D [10] A [10 ] D [11] V S SIO V D D IO A [11 ] D [12] A [12 ] D [13] A [13 ]\D R A [14 ] D [14] A [14 ]/D R A [13 ] D [15] A [15 ] /D R A[12] D [16] A [16 ] /D R A[11] D [17] A [17 ] /D R A[10] n T R ST V S SIO V D D IO D [18] A [18 /D R A[9] D [19] A [19 ] /D R A[8] D [20] A [20 ] /D R A[7] V S SIO D [21] A [21 ] /D R A[6] D [22] A [22 ] /D R A[5] D [23] A [23 ] /D R A[4] D [24] V S SIO V D D IO A [24 ] /D R A[3] H ALF W O R D 208-Pin LQFP Pin Diagram 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 EP7312 208-Pin LQFP (Top View) 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 D [25] A [25]/D R A[2] D [26] A [26]/D R A[1] D [27] A [27]/D R A[0] V SSIO D [28] D [29] D [30] D [31] BUZ C O L[0] C O L[1] T C LK V D D IO C O L[2] C O L[3] C O L[4] C O L[5] C O L[6] C O L[7] F B[0] V SSIO F B[1] S M PC LK ADCOUT A D C C LK D R IV E[0] D R IV E[1] V D D IO V SSIO VDDCORE V SSC O R E nAD C C S A D C IN S SIR XF R S SIR XD A S SITX D A S SITX FR V SSIO S SIC LK P D [0]/LED F LSH P D [1] P D [2] P D [3] TMS V D D IO P D [4] P D [5] P D [6]/SD Q M [0] P D [7]/SD Q M [1] n C S[5 ] V D D IO VS S IO EX P C LK W ORD W R IT E/nSD R AS R UN /CLKEN E XP R D Y TX D [2 ] R X D [2 ] TD I V SS IO P B[7 ] P B[6 ] P B[5 ] P B[4 ] P B[3 ] P B[2 ] P B[1 ] P B[0 ] VD D IO TDO PA [7] PA [6] PA [5] P A[4 ] PA [3] PA [2] PA [1] PA [0] LE D D R V TX D [1 ] V SS IO P H D IN CTS R XD [1] DCD D SR nT E ST [1] nT E ST [0] EIN T[3] nE IN T [2 ] nE IN T [1 ] n E X T F IQ PE [2]/C LK SE L PE [1]B O O TS E L[1] PE [0]B O O TS E L[0] VS S R T C RTCOUT R T C IN VDDRTC N /C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 V D D O SC M O SC IN MOSCOUT VS SO SC W AKE U P nP W R FL A [6] D [6] A [5] D [5] VD D IO V SSIO A [4] D [4] A[3] D [3] A[2] V SSIO D [2] A [1] D [1] A[0] D [0] VS SC O R E VD D C O R E VSS IO V D D IO C L[2] C L[1] FRM M D D [3] D D [2] VS SIO D D [1] D D [0] nS D C S[1] nS D C S[0] S D Q M [3] S D Q M [2] V D D IO VS SIO S D C KE SD C LK nM W E/nSD W E nM O E /nS D C AS VS SIO nC S [0] nC S[1] nC S[2] nC S [3] nC S [4] Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Note: DS508PP5 1. N/C should not be grounded but left as no connects. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 31 EP7312 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Table 20. 208-Pin LQFP Numeric Pin Listing 32 Pin No. Signal Reset State Type Description 1 nCS[5] Low O Chip select 5 2 3 VDDIO Pad Pwr Digital I/O power, 3.3 V VSSIO Pad Gnd 4 EXPCLK 1 I/O ground I Expansion clock input 5 WORD 1 Low O Word access select output 6 WRITE/nSDRAS 1 Low O Transfer direction / SDRAM RAS signal output 7 RUN/CLKEN 1 Low O Run output / clock enable output 8 EXPRDY 1 I Expansion port ready input 9 TXD[2] 1 High O UART 2 transmit data output 10 RXD[2] 11 TDI 12 VSSIO Strength 1 with p/u* I UART 2 receive data input I JTAG data input Pad Gnd I/O ground I/O GPIO port B 13 PB[7] 1 Input 14 PB[6] 1 Input I/O GPIO port B 15 PB[5] 1 Input I/O GPIO port B 16 PB[4] 1 Input I/O GPIO port B 17 PB[3] 1 Input I/O GPIO port B 18 PB[2] 1 Input I/O GPIO port B 19 PB[1] 1 Input I/O GPIO port B 20 PB[0] 1 Input I/O GPIO port B 21 VDDIO Pad Pwr Digital I/O power, 3.3 V O JTAG data out I/O GPIO port A I/O GPIO port A 22 TDO 1 Input 23 PA[7] 1 Input 24 PA[6] 1 Input 25 PA[5] 1 Input I/O GPIO port A 26 PA[4] 1 Input I/O GPIO port A 27 PA[3] 1 Input I/O GPIO port A 28 PA[2] 1 Input I/O GPIO port A 29 PA[1] 1 Input I/O GPIO port A 30 PA[0] 1 Input I/O GPIO port A 31 LEDDRV 1 Low O IR LED drive 32 TXD[1] 1 High O UART 1 transmit data out 33 VSSIO 1 High Pad Gnd I/O ground 34 PHDIN I Photodiode input 35 CTS I UART 1 clear to send input 36 RXD[1] I UART 1 receive data input 37 DCD I UART 1 data carrier detect Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No. DS508PP5 Signal Strength Reset State Type Description 38 DSR I UART 1 data set ready input 39 nTEST[1] With p/u* I Test mode select input 40 nTEST[0] With p/u* I Test mode select input 41 EINT[3] I External interrupt 42 nEINT[2] I External interrupt input 43 nEINT[1] I External interrupt input 44 nEXTFIQ I External fast interrupt input 45 PE[2]/CLKSEL 1 Input I/O GPIO port E / clock input mode select 46 PE[1]/BOOTSEL[1] 1 Input I/O GPIO port E / boot mode select 47 PE[0]/BOOTSEL[0] 1 Input I/O GPIO port E / Boot mode select 48 VSSRTC RTC Gnd Real time clock ground 49 RTCOUT O Real time clock oscillator output 50 RTCIN I Real time clock oscillator input 51 VDDRTC RTC power Real time clock power, 2.5 V 52 N/C 53 PD[7]/SDQM[1] 1 Low I/O GPIO port D / SDRAM byte lane mask 54 PD[6]/SDQM[0] 1 Low I/O GPIO port D / SDRAM byte lane mask 55 PD[5] 1 Low I/O GPIO port D 56 PD[4] 1 Low 57 VDDIO I/O GPIO port D Pad Pwr Digital I/O power, 3.3 V 58 TMS with p/u* I JTAG mode select 59 PD[3] 1 Low I/O GPIO port D 60 PD[2] 1 Low I/O GPIO port D 61 PD[1] 1 Low I/O GPIO port D I/O GPIO port D / LED blinker output I/O DAI/CODEC/SSI2 serial clock 62 PD[0]/LEDFLSH 1 Low 63 SSICLK 1 Input 64 VSSIO Pad Gnd I/O ground 65 SSITXFR 1 Low I/O DAI/CODEC/SSI2 serial clock 66 SSITXDA 1 Low O DAI/CODEC/SSI2 serial data output 67 SSIRXDA I DAI/CODEC/SSI2 serial data input 68 SSIRXFR I/O DAI/CODEC/SSI2 frame sync 69 ADCIN 70 nADCCS 71 Input I SSI1 ADC serial input O SSI1 ADC chip select VSSCORE Core ground Core ground 72 VDDCORE Core Pwr Core power, 2.5 V 73 VSSIO Pad Gnd I/O ground 74 VDDIO Pad Pwr Digital I/O power, 3.3 V 75 DRIVE[1] 2 High / Low I/O PWM drive output 76 DRIVE[0] 2 High / Low I/O PWM drive output 77 ADCCLK 1 Low O SSI1 ADC serial clock 78 ADCOUT 1 Low O SSI1 ADC serial data output 1 High Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 33 EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No. Signal 79 SMPCLK 80 FB[1] 81 82 Type Description Low O SSI1 ADC sample clock I PWM feedback input VSSIO Pad Gnd I/O ground FB[0] I PWM feedback input 1 83 COL[7] 1 High O Keyboard scanner column drive 84 COL[6] 1 High O Keyboard scanner column drive 85 COL[5] 1 High O Keyboard scanner column drive 86 COL[4] 1 High O Keyboard scanner column drive 87 COL[3] 1 High O Keyboard scanner column drive 88 COL[2] 1 High O Keyboard scanner column drive 89 VDDIO Pad Pwr Digital I/O power, 3.3 V 90 TCLK I JTAG clock 91 COL[1] 1 High O Keyboard scanner column drive 92 COL[0] 1 High O Keyboard scanner column drive 93 BUZ 1 Low O Buzzer drive output 94 D[31] 1 Low I/O Data I/O 95 D[30] 1 Low I/O Data I/O 96 D[29] 1 Low I/O Data I/O 97 D[28] 1 Low I/O Data I/O 98 VSSIO Pad Gnd I/O ground System byte address / SDRAM address 99 A[27]/DRA[0] 2 Low O 100 D[27] 1 Low I/O Data I/O System byte address / SDRAM address 101 A[26]/DRA[1] 2 Low O 102 D[26] 1 Low I/O Data I/O 103 A[25]/DRA[2] 2 Low O System byte address / SDRAM address 104 D[25] 1 Low I/O Data I/O 105 HALFWORD 1 Low O Halfword access select output 106 A[24]/DRA[3] 1 Low O System byte address / SDRAM address 107 VDDIO -- Pad Pwr Digital I/O power, 3.3 V 108 VSSIO -- Pad Gnd I/O ground 109 D[24] 1 Low I/O Data I/O 110 A[23]/DRA[4] 1 Low O System byte address / SDRAM address 111 D[23] 1 Low I/O Data I/O System byte address / SDRAM address 112 A[22]/DRA[5] 1 Low O 113 D[22] 1 Low I/O Data I/O O System byte address / SDRAM address 114 34 Reset State Strength A[21]/DRA[6] 1 Low 115 D[21] 1 Low 116 VSSIO 117 A[20]/DRA[7] 1 Low I/O Data I/O Pad Gnd I/O ground O System byte address / SDRAM address Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) DS508PP5 Pin No. Signal 118 D[20] Strength 1 Reset State Type Low I/O Data I/O System byte address / SDRAM address Description 119 A[19]/DRA[8] 1 Low O 120 D[19] 1 Low I/O Data I/O 121 A[18]/DRA[9] 1 Low O System byte address / SDRAM address 122 D[18] 1 Low I/O Data I/O 123 VDDIO Pad Pwr Digital I/O power, 3.3 V 124 VSSIO Pad Gnd I/O ground 125 nTRST I JTAG async reset input 126 A[17]/DRA[10] 1 Low O System byte address / SDRAM address 127 D[17] 1 Low I/O Data I/O 128 A[16]/DRA[11] 1 Low O System byte address / SDRAM address 129 D[16] 1 Low I/O Data I/O System byte address / SDRAM address 130 A[15]/DRA[12] 1 Low O 131 D[15] 1 Low I/O Data I/O System byte address / SDRAM address 132 A[14]/DRA[13] 1 Low O 133 D[14] 1 Low I/O Data I/O 134 A[13]/DRA[14] 1 Low O System byte address / SDRAM address 135 D[13] 1 Low I/O Data I/O 136 A[12] 1 Low O System byte address 137 D[12] 1 Low I/O Data I/O 138 A[11] 1 Low O System byte address 139 VDDIO Pad Pwr Digital I/O power, 3.3 V 140 VSSIO Pad Gnd I/O ground 141 D[11] 1 Low I/O Data I/O 142 A[10] 1 Low O System byte address 143 D[10] 1 Low I/O Data I/O System byte address 144 A[9] 1 Low O 145 D[9] 1 Low I/O Data I/O 146 A[8] 1 Low O System byte address 147 D[8] 1 Low I/O Data I/O 148 A[7] 1 Low O System byte address 149 VSSIO Pad Gnd I/O ground 150 D[7] 151 1 I/O Data I/O nBATCHG I Battery changed sense input 152 nEXTPWR I External power supply sense input 153 BATOK 154 nPOR 155 nMEDCHG/nBROM 156 nURESET 157 VDDOSC Schmitt Schmitt Low I Battery OK input I Power-on reset input I Media change interrupt input / internal ROM boot enable I User reset input Oscillator Power Oscillator power in, 2.5 V 158 MOSCIN I Main oscillator input 159 MOSCOUT O Main oscillator output 160 VSSOSC Oscillator Ground Oscillator Ground Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 35 EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Pin No. Signal 161 WAKEUP 162 nPWRFL 163 A[6] 1 Low 164 D[6] 1 Low I/O Data I/O 165 A[5] 1 Low Out System byte address 166 D[5] 1 Low 167 VDDIO 168 VSSIO Pad Gnd I/O ground 169 A[4] 1 Low O System byte address 170 D[4] 1 Low I/O Data I/O 171 A[3] 2 Low O System byte address 172 D[3] 1 Low I/O Data I/O 173 A[2] 2 Low O System byte address 174 VSSIO Pad Gnd I/O ground 175 D[2] 1 Low I/O Data I/O System byte address Reset State Schmitt Type Description I System wake up input I Power fail sense input O System byte address I/O Data I/O Pad Pwr Digital I/O power, 3.3 V 176 A[1] 2 Low O 177 D[1] 1 Low I/O Data I/O 178 A[0] 2 Low O System byte address 179 D[0] 1 Low I/O Data I/O 180 VSSCORE Core ground Core ground 181 VDDCORE Core Pwr Core power, 2.5 V 182 VSSIO Pad ground I/O ground 183 VDDIO Pad Power Digital I/O power, 3.3 V 184 CL[2] 1 Low O LCD pixel clock out 185 CL[1] 1 Low O LCD line clock O LCD frame synchronization pulse 186 36 Strength FRM 1 Low 187 M 1 Low O LCD AC bias drive 188 DD[3] 1 Low I/O LCD serial display data 189 DD[2] 1 Low I/O LCD serial display data 190 VSSIO 191 DD[1] 1 192 DD[0] 193 194 Pad Gnd I/O ground Low I/O LCD serial display data 1 Low I/O LCD serial display data nSDCS[1] 1 High O SDRAM chip select 1 nSDCS[0] 1 High O SDRAM chip select 0 195 SDQM[3] 2 Low I/O SDRAM byte lane mask 196 SDQM[2] 2 Low I/O SDRAM byte lane mask 197 VDDIO Pad Pwr Digital I/O power, 3.3 V 198 VSSIO Pad Gnd I/O ground 199 SDCKE 2 Low I/O SDRAM clock enable output 200 SDCLK 2 Low I/O SDRAM clock out 201 nMWE/nSDWE 1 High O ROM, expansion write enable/ SDRAM write enable control signal 202 nMOE/nSDCAS 1 High O ROM, expansion OP enable/SDRAM CAS control signal 203 VSSIO Pad Gnd I/O ground 204 nCS[0] 1 High O Chip select 0 205 nCS[1] 1 High O Chip select 1 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) * Pin No. Signal 206 nCS[2] 207 nCS[3] 208 nCS[4] Reset State Type Description 1 High O Chip select 2 1 High O Chip select 3 1 High O Chip select 4 Strength "With p/u" means with internal pull-up of 100 KOhms on the pin. Strength 1 = 4 ma Strength 2 = 12 ma Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 37 EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Package Characteristics TO P V IE W B O TTO M V IE W O 0.08 M C O 0.15 M C A B A 1 CO R N E R 1 2 3 4 5 6 A 1 CO R N E R O 0.25~0.35(204X ) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B B C C D D E E 0.65 A F G F G J K L 12.35 H J 130.05 H K L M M N N P P R R T T U U V V W W Y Y A 0.65 12.35 130.05 0.20 C 0.15(4X ) C 0.10 C 0.530.05 B S ubstrate Thickness : B all Pitch : S E A TIN G P LAN E 0.20~0.30 C B all Diam eter : 1.20 MA X . 0.36 0.65 0.36 M old Thickness : 0.3 0.53 Figure 17. 204-Ball TFBGA Package 38 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Pinout (Top View) 1 2 3 4 12 13 14 15 16 17 18 19 20 A VDDIO EXPCLK nCS[3] nCS[1] GNDCORE D[1] A[2] D[4] A[5] nPWRFL MOSCOUT GNDIO GNDIO GNDIO B WORD VDDIO nCS[5] nCS[2] A[1] D[3] A[4] D[6] WAKEUP MOSCIN GNDIO GNDIO C RUN/ CLKEN EXPRDY VDDIO nCS[4] D[2] A[3] D[5] A[6] GNDOSC VDDOSC GNDIO BATOK nPOR C D PB[7] RXD[2] VDDIO GNDIO nBATCHG A[7] D E PB[4] TXD[2] WRITE/ nSDRAS nMEDCHG/n nEXTPWR BROM D[9] E F PB[3] PB[6] TDI D[7] A[8] D[10] F G PB[1] PB[2] PB[5] D[8] A[9] D[11] G H PA[7] TDO PB[0] A[10] D[12] A[12] H J PA[4] PA[5] PA[6] A[11] D[13] A[13]/ DRA[14] J K PA[1] PA[2] VDDIO D[14] A[14]/ DRA[13] D[15] K L TXD[1] LEDDRV PA[3] VDDIO D[16] A[16]/ DRA[11] L CTS PA[0] A[15]/ DRA[12] A[17]/ DRA[10] nTRST M nTEST[1] PHDIN D[17] D[19] A[18]/ DRA[9] N P EINT[3] nEINT[2] DCD D[18] A[20]/ DRA[7] D[20] P R nEXTFIQ PE2/ nTEST[0] CLKSEL A[19]/ DRA[8] D[22] A[21]/ DRA6 R nEINT[1] D[21] D[23] A[22]/ DRA5 T U GNDRTC RTCOUT RTCIN HALF WORD D[24] A[23]/ DRA4 U V VDDRTC GNDIO GNDIO PD[7]/ SDQM[1] PD[4] PD[2] SSICLK SSIRXDA nADCCS VDDIO W GNDIO GNDIO GNDIO PD[6]/ SDQM[0] TMS PD[1] SSITXFR SSIRXFR GNDCORE DRIVE[1] ADCOUT FB[0] Y GNDIO GNDIO PD[5] PD[3] PD[0]/ LED FLSH SSITXDA DRIVE[0] SMPCLK FB[1] M RXD[1] N T DSR PE[1]/ BOOT SEL[1] GNDIO PE[0]/ BOOT SEL[0] DS508PP5 5 6 8 9 10 nMWE/ SDQM[2] nSDCS[1] nSDWE DD[2] FRM CL[1] nMOE/ SDCKE nSDCS[0] nSDCAS DD[1] M CL[2] D[0] DD[0] DD[3] VDDCORE A[0] nCS[0] SDCLK 7 SDQM[3] ADCIN VDDCORE 11 A nURESET B D[29] A[26]/ DRA[1] VDDIO VDDIO A[24]/ DRA3 V COL[5] COL[2] COL[0] D[30] A[27]/ DRA[0] D[26] VDDIO D[25] W COL[6] COL[3] COL[1] D[31] D[28] D[27] A[25]/ DRA[2] VDDIO Y ADCCLK COL[7] COL[4] TCLK BUZ Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 39 EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing The list is ordered by ball location. Table 21. 204-Ball TFBGA Ball Listing Ball Location Name Strength Reset State Type Description Pad power Digital I/O power, 3.3 V I Expansion clock input A1 VDDIO A2 EXPCLK 1 A3 nCS[3] 1 High O Chip select 3 A4 nCS[1] 1 High O Chip select 1 A5 nMWE/nSDWE 1 High O ROM, expansion write enable/ SDRAM write enable control signal A6 SDQM[2] 2 Low O SDRAM byte lane mask A7 nSDCS[1] 1 High O SDRAM chip select 2 A8 DD[2] 1 Low O LCD serial display data A9 FRM 1 Low O LCD frame synchronization pulse A10 CL[1] 1 Low O LCD line clock A11 VSSCORE A12 D[1] 1 Low I/O Data I/O A13 A[2] 2 Low O System byte address A14 D[4] 1 Low I/O Data I/O A15 A[5] 1 Low O System byte address A16 nPWRFL I Power fail sense input A17 MOSCOUT O Main oscillator out A18 VSSIO Pad ground I/O ground A19 VSSIO Pad ground I/O ground A20 VSSIO Pad ground I/O ground B1 WORD B2 VDDIO B3 nCS[5] 1 Low O Chip select 5 B4 nCS[2] 1 High O Chip select 2 B5 nMOE/nSDCAS 1 High O ROM, expansion OP enable/SDRAM CAS control signal B6 SDCKE 2 Low O SDRAM clock enable output B7 nSDCS[0] 1 High O SDRAM chip select 0 40 Core ground 1 Low Core ground O Word access select output Pad power Digital I/O power, 3.3 V Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength Reset State Type Description B8 DD[1] 1 Low O LCD serial display data B9 M 1 Low O LCD AC bias drive B10 CL[2] 1 Low 0 LCD pixel clock out B11 D[0] 1 Low I/O Data I/O B12 A[1] 2 Low O System byte address B13 D[3] 2 Low I/O Data I/O B14 A[4] 1 Low O System byte address B15 D[6] 1 Low I/O Data I/O B16 WAKEUP B17 MOSCIN B18 VSSIO Pad ground I/O ground B19 VSSIO Pad ground I/O ground B20 nURESET C1 RUN/CLKEN 1 C2 EXPRDY 1 C3 VDDIO C4 nCS[4] 1 High O Chip select 4 C5 nCS[0] 1 High O Chip select 0 C6 SDCLK 2 Low O SDRAM clock out C7 SDQM[3] 2 Low O SDRAM byte lane mask C8 DD[0] 1 Low O LCD serial display data C9 DD[3] 1 Low O LCD serial display data C10 VDDCORE Core power Digital core power, 2.5 V C11 A[0] 2 Low O System byte address C12 D[2] 1 Low I/O Data I/O C13 A[3] 2 Low O System byte address C14 D[5] 1 Low I/O Data I/O C15 A[6] 1 Low O System byte address C16 VSSOSC Oscillator ground PLL ground C17 VDDOSC Oscillator power Oscillator power in, 2.5V C18 VSSIO Pad ground C19 BATOK I DS508PP5 Schmitt Schmitt Low I System wake up input I Main oscillator input I User reset input 0 Run output / clock enable output I Expansion port ready input Pad power Digital I/O power, 3.3 V I/O ground Battery ok input Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 41 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength Reset State Type Description I Power-on reset input I GPIO port B UART 2 receive data input C20 nPOR Schmitt D1 PB[7] 1 D2 RXD[2] I D3 VDDIO Pad power Digital I/O power, 3.3V D18 VSSIO Pad ground I/O ground D19 nBATCHG D20 A[7] 1 Low E1 PB[4] 1 E2 TXD[2] E3 WRITE/nSDRAS E18 Input I Battery changed sense input O System byte address Input I GPIO port B 1 High O UART 2 transmit data output 1 Low O Transfer direction / SDRAM RAS signal output nMEDCHG/nBROM I Media change interrupt input / internal ROM boot enable E19 nEXTPWR I External power supply sense input E20 D[9] 1 Low F1 PB[3] 1 Input F2 PB[6] 1 Input F3 TDI with p/u* F18 D[7] 1 Low I/O Data I/O F19 A[8] 1 Low O System byte address F20 D[10] 1 Low I/O Data I/O G1 PB[1] 1 Input G2 PB[2] 1 Input G3 PB[5] 1 Input G18 D[8] 1 Input G19 A[9] 1 G20 D[11] H1 I/O Data I/O I/O GPIO port B I/O I GPIO port B JTAG data input I/O I/O GPIO port B I/O GPIO port B I/O Data I/O Low O System byte address 1 Low I/O Data I/O PA[7] 1 Input I/O GPIO port A H[2] TDO 1 Input O JTAG data out H[3] PB[0] 1 Input I/O GPIO port B H[18] A[10] 1 Low O System byte address 42 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength Reset State Type Description H19 D[12] 1 Low I/O Data I/O H20 A[12] 1 Low O System byte address J1 PA[4] 1 Input I/O GPIO port A J2 PA[5] 1 Input I/O GPIO port A J3 PA[6] 1 Input I/O GPIO port A J18 A[11] 1 Low O System byte address J19 D[13] 1 Low I/O Data I/O J20 A[13]/DRA[14] 1 Low O System byte address / SDRAM address K1 PA[1] 1 Input K2 PA[2] 1 Input K3 VDDIO K18 D[14] 1 Low I/O Data I/O K19 A[14]/DRA[13] 1 Low O System byte address / SDRAM address K20 D[15] 1 Low I/O Data I/O L1 TXD[1] 1 High O UART 1 transmit data out L2 LEDDRV 1 Low O IR LED drive L3 PA[3] 1 Input I/O GPIO port A L18 VDDIO L19 D[16] 1 Low I/O Data I/O L20 A[16]/DRA[11] 1 Low O System byte address / SDRAM address M1 RXD[1] I UART 1 receive data input M2 CTS I UART 1 clear to send input M3 PA[0] 1 Input I/O M18 A[15]/DRA[12] 1 Low O System byte address / SDRAM address M19 A[17]/DRA[10] 1 Low O System byte address / SDRAM address M20 nTRST I JTAG async reset input N1 DSR I UART 1 data set ready input N2 nTEST[1] I Test mode select input N3 PHDIN I Photodiode input DS508PP5 I/O GPIO port A I/O GPIO port A Pad power Pad power With p/u* Digital I/O power, 3.3V Digital I/O power, 3.3V GPIO port A Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 43 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength Reset State Type Description N18 D[17] 1 Low I/O Data I/O N19 D[19] 1 Low I/O Data I/O N20 A[18]/DRA[9] 1 Low O System byte address / SDRAM address P1 EINT[3] I External interrupt P2 nEINT[2] I External interrupt input P3 DCD I UART 1 data carrier detect P18 D[18] 1 Low I/O Data I/O P19 A[20]/DRA[7] 1 Low O System byte address / SDRAM address P20 D[20] 1 Low I/O Data I/O R1 nEXTFIQ R2 PE[2]/CLKSEL 1 Input R3 PE[1]/BOOTSEL[1] 1 R18 A[19]/DRA[8] R19 I External fast interrupt input I/O GPIO port E / clock input mode select Input I/O GPIO port E / boot mode select 1 Low O System byte address / SDRAM address D[22] 1 Low I/O Data I/O R20 A[21]/DRA[6] 1 Low O System byte address / SDRAM address T1 PE[1]/BOOTSEL[1] 1 Input T2 PE[0]/BOOTSEL[0] 1 Input T3 nEINT[1] T18 D[21] 1 Low I/O Data I/O T19 D[23] 1 Low I/O Data I/O T20 A[22]/DRA[5] 1 Low O System byte address / SDRAM address U1 VSSRTC RTC ground Real time clock ground U2 RTCOUT O Real time clock oscillator output U3 RTCIN I/O Real time clock oscillator input U18 HALFWORD 1 Low O Halfword access select output U19 D[24] 1 Low I/O Data I/O U20 A[23]/DRA[4] 1 Low O System byte address / SDRAM address V1 VDDRTC 44 I/O GPIO port E / boot mode select I/O GPIO port E / boot mode select I External interrupt input RTC power Real time clock power, 2.5V Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength Reset State Type Description V2 VSSIO Pad ground I/O ground V3 VSSIO Pad ground I/O ground V4 PD[7]/SDQM[1] 1 Low I/O GPIO port D / SDRAM byte lane mask V5 PD[4] 1 Low I/O GPIO port D V6 PD[2] 1 Low I/O GPIO port D V7 SSICLK 1 Input I/O DAI/CODEC/SSI2 serial clock V8 SSIRXDA I/O DAI/CODEC/SSI2 serial data input V9 nADCCS O SSI1 ADC chip select V10 VDDIO V11 ADCCLK 1 V12 COL[7] V13 COL[4] V14 TCLK V15 BUZ 1 V16 D[29] V17 A[26]/DRA[1] V18 VDDIO Pad power Digital I/O power, 3.3 V V19 VDDIO Pad power Digital I/O power, 3.3 V V20 A[24]/DRA[3] W1 VSSIO Pad ground I/O ground W2 VSSIO Pad ground I/O ground W3 VSSIO Pad ground I/O ground W4 PD[6]/SDQM[0] W5 TMS with p/u* W6 PD[1] 1 Low I/O GPIO port D W7 SSITXFR 1 Low I/O DAI/CODEC/SSI2 frame sync W8 SSIRXFR 1 Input I/O DAI/CODEC/SSI2 frame sync W9 VSSCORE W10 DRIVE[1] DS508PP5 1 High Pad power Digital I/O power, 3.3V Low O SSI1 ADC serial clock 1 High O Keyboard scanner column drive 1 High O Keyboard scanner column drive I JTAG clock Low O Buzzer drive output 1 Low I/O Data I/O 2 Low O System byte address / SDRAM address ` 1 Low Low O I/O GPIO port D / SDRAM byte lane mask I JTAG mode select Core Ground 2 High / Low System byte address / SDRAM address I/O Core Ground PWM drive output Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 45 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength 1 Reset State Type Low O SSI1 ADC serial data output I PWM feedback input Description W11 ADCOUT W12 FB[0] W13 COL[5] 1 High O Keyboard scanner column drive W14 COL[2] 1 High O Keyboard scanner column drive W15 COL[0] 1 High O Keyboard scanner column drive W16 D[30] 1 Low I/O Data I/O W17 A[27]/DRA[0] 2 Low O System byte address / SDRAM address W18 D[26] 1 Low I/O Data I/O W19 VDDIO W20 D[25] Y1 VSSIO Pad ground I/O ground Y2 VSSIO Pad ground I/O ground Y3 VSSIO Pad ground I/O ground Y4 PD[5] 1 Low I/O GPIO port D Y5 PD[3] 1 Low I/O GPIO port D Y6 PD[0]/LEDFLSH 1 Low I/O GPIO port D / LED blinker output Y7 SSITXDA 1 Low O DAI/CODEC/SSI2 serial data output Y8 ADCIN I SSI1 ADC serial input Y9 VDDCORE Y10 DRIVE[0] 2 Y11 SMPCLK 1 Y12 FB[1] Y13 COL[6] 1 Y14 COL[3] Y15 Pad power 1 Low I/O Digital I/O power, 3.3V Data I/O Core power Digital core power, 2.5V Input I/O PWM drive output Low O SSI1 ADC sample clock I PWM feedback input High O Keyboard scanner column drive 1 High O Keyboard scanner column drive COL[1] 1 High O Keyboard scanner column drive Y16 D[31] 1 Low I/O Data I/O Y17 D[28] 1 Low I/O Data I/O Y18 D[27] 1 Low I/O Data I/O Y19 A[25]/DRA[2] 2 Low O System byte address / SDRAM address 46 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Y20 Name Strength Reset State VDDIO * Type Pad power Description Digital I/O power, 3.3V "With p/u" means with internal pull-up of 100 KOhms on the pin. Strength 1 = 4 ma Strength 2 = 12 ma Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. 256-Ball PBGA Package Characteristics Figure 18. 256-Ball PBGA Package Note: DS508PP5 1) For pin locations see Table 22. 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 47 EP7312 High-Performance, Low-Power System on Chip 0.85 (0.034) 0.05 (.002) 17.00 (0.669) 0.20 (.008) Pin 1 C orner D1 0.40 (0.016) 0.05 (.002) 15.00 (0.590) 0.20 (.008) 30 TYP Pin 1 Indicator 17.00 (0.669) 0.20 (.008) E1 15.00 (0.590) 0.20 (.008) 2 Layer 0.36 (0.014) 0.09 (0.004) TOP VIEW SIDE VIEW D 17.00 (0.669) Pin 1 C orner 1.00 (0.040) 1.00 (0.040) R EF E 16 15 14 13 12 11 10 9 8 7 6 5 1.00 (0.040) R EF 1 A B C D E F G H J K L M N P R T 1.00 (0.040) 0.50 R 3 Places 48 4 3 2 17.00 (0.669) BOTTOM VIEW JEDEC #: MO-151 Ball Diameter: 0.50 mm 0.10 mm 17 17 1.61 mm body Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO A B nCS[5] VDDIO nCS[3] nMOE/ nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C D WRITE/ nSDRAS EXPRDY VSSIO VDDIO nCS[2] nMWE/ nSDWE nSDCS[0] CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] D E RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/ nBROM VDDIO D[9] D[10] E F PB[5] PB[3] VSSIO TXD[2] RUN/ CLKEN VSSIO SDCKE DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO F G PB[1] VDDIO TDO PB[4] PB[6] VSSCore VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] G H PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13]/ DRA[14] VSSIO D[14] D[15] H J PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17]/ DRA[10] A[16]/ DRA[11] A[15]/ DRA[12] A[14]/ DRA[13] nTRST D[16] D[17] J K LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO K L RXD[1] DSR VDDIO nEINT[1] PE[2]/ CLKSEL VSSRTC PD[0]/ LEDFLSH VSSRTC COL[6] D[31] VSSRTC A[22]/ DRA[5] A[21]/ DRA[6] VSSIO A[18]/ DRA[9] A[19]/ DRA[8] L M nTEST[0] nEINT[2] VDDIO PE[0]/ BOOTSEL[0] TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/ DRA[4] VDDIO A[20]/ DRA[7] D[21] M N nEXTFIQ PE[1]/ BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] N P VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO P R RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27]/ DRA[0] A[25]/ DRA[2] VDDIO A[24]\ DRA[3] R T VDDRTC PD[7]/ SDQM[1] PD[6]/ SDQM[0] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/ DRA[1] D[25] VSSIO T DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 49 EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Ball Listing The list is ordered by ball location. Table 22. 256-Ball PBGA Ball Listing 50 Reset State Ball Location Name A1 VDDIO A2 nCS[4] 1 High O Chip select 4 A3 nCS[1] 1 High O Chip select 1 A4 SDCLK 2 Low O SDRAM clock out A5 SDQM[3] 2 Low O SDRAM byte lane mask A6 DD[1] 1 Low O LCD serial display data A7 M 1 Low O A8 VDDIO A9 D[0] 1 Low I/O Data I/O A10 D[2] 1 Low I/O Data I/O A11 A[3] 2 Low O A12 VDDIO A13 A[6] A14 Strength Type Pad power Pad power Pad power 1 Low Description Digital I/O power, 3.3 V LCD AC bias drive Digital I/O power, 3.3 V System byte address Digital I/O power, 3.3V O System byte address MOSCOUT O Main oscillator out A15 VDDOSC Oscillator power A16 VSSIO B1 nCS[5] B2 VDDIO B3 nCS[3] 1 High O Chip select 3 B4 nMOE/nSDCAS 1 High O ROM, expansion OP enable/SDRAM CAS control signal Oscillator power in, 2.5 V Pad ground I/O ground 1 Low O Pad power Pad power Chip select 5 Digital I/O power, 3.3 V B5 VDDIO B6 nSDCS[1] 1 High O Digital I/O power, 3.3 V SDRAM chip select 1 B7 DD[2] 1 Low O LCD serial display data B8 CL[1] 1 Low O LCD line clock B9 VDDCORE B10 D[1] 1 Low I/O Data I/O B11 A[2] 2 Low O System byte address B12 A[4] 1 Low O System byte address B13 A[5] 1 Low O System byte address B14 WAKEUP Schmitt I System wake up input B15 VDDIO Pad power Digital I/O power, 3.3 V B16 nURESET C1 VDDIO C2 EXPCLK C3 VSSIO C4 VDDIO Pad power C5 VSSIO Pad ground I/O ground C6 VSSIO Pad ground I/O ground C7 VSSIO Pad ground I/O ground C8 VDDIO Pad power C9 VSSIO Pad ground I/O ground C10 VSSIO Pad ground I/O ground C11 VSSIO Pad ground I/O ground C12 VDDIO Pad power Core power Digital core power, 2.5V Schmitt 1 I User reset input Pad power Digital I/O power, 3.3V I Expansion clock input Pad ground I/O ground Digital I/O power, 3.3 V Digital I/O power, 3.3 V Digital I/O power, 3.3 V Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 22. 256-Ball PBGA Ball Listing (Continued) DS508PP5 Ball Location Name C13 VSSIO C14 VSSIO C15 nPOR C16 nEXTPWR Strength Reset State Type Description Pad ground I/O ground Pad ground I/O ground Schmitt I I External power supply sense input O Transfer direction / SDRAM RAS signal output I Expansion port ready input D1 WRITE/nSDRAS 1 D2 EXPRDY 1 D3 VSSIO Pad ground I/O ground D4 VDDIO Pad power D5 nCS[2] D6 nMWE/nSDWE D7 D8 D9 VSSRTC 1 Low Power-on reset input High Digital I/O power, 3.3V O Chip select 2 ROM, expansion write enable/ SDRAM write enable control signal 1 High O nSDCS[0] 1 High O SDRAM chip select 2 CL[2] 1 Low O LCD pixel clock out Core ground Real time clock ground D10 D[4] D11 nPWRFL 1 Low I/O I Data I/O Power fail sense input D12 MOSCIN I Main oscillator input D13 VDDIO Pad power D14 VSSIO D15 D[7] 1 Low I/O D16 D[8] 1 Low I/O E1 RXD[2] E2 PB[7] 1 E3 TDI with p/u* E4 WORD 1 E5 VSSIO Digital I/O power, 3.3V Pad ground I/O ground Input Low Data I/O Data I/O I UART 2 receive data input I GPIO port B I JTAG data input O Word access select output Pad ground I/O ground E6 nCS[0] 1 High O Chip select 0 E7 SDQM[2] 2 Low O SDRAM byte lane mask E8 FRM 1 Low O LCD frame synchronization pulse E9 A[0] 2 Low O System byte address E10 D[5] 1 Low I/O Data I/O E11 VSSOSC E12 VSSIO E13 nMEDCHG/nBROM E14 VDDIO E15 D[9] 1 Low I/O Data I/O E16 D[10] 1 Low I/O Data I/O F1 PB[5] 1 Input F2 PB[3] 1 Input F3 VSSIO Oscillator ground PLL ground Pad ground I/O ground I Pad power Media change interrupt input / internal ROM boot enable Digital I/O power, 3.3V I GPIO port B I GPIO port B Pad ground I/O ground F4 TXD[2] 1 High O UART 2 transmit data output F5 RUN/CLKEN 1 Low O Run output / clock enable output F6 VSSIO F7 SDCKE F8 DD[3] 1 Low O LCD serial display data F9 A[1] 2 Low O System byte address Pad ground I/O ground 2 Low O SDRAM clock enable output Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 51 EP7312 High-Performance, Low-Power System on Chip Table 22. 256-Ball PBGA Ball Listing (Continued) Ball Location 52 Name F10 D[6] F11 VSSRTC F12 BATOK F13 nBATCHG F14 VSSIO Strength 1 Reset State Low Type I/O Description Data I/O RTC ground Real time clock ground I Battery OK input I Battery changed sense input Pad ground I/O ground F15 D[11] F16 VDDIO 1 Low I/O G1 PB[1] G2 VDDIO G3 TDO 1 Input G4 PB[4] 1 Input G5 PB[6] 1 Input G6 VSSCore G7 VSSRTC G8 DD[0] 1 Low O LCD serial display data G9 D[3] 1 Low I/O Data I/O G10 VSSRTC G11 A[7] 1 Low O System byte address G12 A[8] 1 Low O System byte address G13 A[9] 1 Low O System byte address G14 VSSIO G15 D[12] 1 Low I/O Data I/O G16 D[13] 1 Low I/O Data I/O I/O GPIO port A I/O GPIO port A Pad power 1 Input I Pad power Data I/O Digital I/O power, 3.3V GPIO port B Digital I/O power, 3.3V O I GPIO port B I GPIO port B JTAG data out Core ground Core ground RTC ground Real time clock ground RTC ground Real time clock ground Pad ground I/O ground H1 PA[7] 1 Input H2 PA[5] 1 Input H3 VSSIO H4 PA[4] 1 Input H5 PA[6] 1 Input H6 PB[0] 1 H7 PB[2] 1 H8 VSSRTC H9 VSSRTC H10 A[10] 1 Low O System byte address H11 A[11] 1 Low O System byte address H12 A[12] 1 Low O System byte address H13 A[13]/DRA[14] 1 Low O System byte address / SDRAM address H14 VSSIO H15 D[14] 1 Low I/O Data I/O H16 D[15] 1 Low I/O Data I/O I/O GPIO port A I/O GPIO port A Pad ground I/O ground I/O GPIO port A I/O GPIO port A Input I/O GPIO port B Input I/O GPIO port B RTC ground Real time clock ground RTC ground Real time clock ground Pad ground I/O ground J1 PA[3] 1 Input J2 PA[1] 1 Input J3 VSSIO J4 PA[2] Pad ground I/O ground 1 Input I/O GPIO port A Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 22. 256-Ball PBGA Ball Listing (Continued) DS508PP5 Reset State Type I/O GPIO port A O UART 1 transmit data out I UART 1 clear to send input Ball Location Name J5 PA[0] 1 Input J6 TXD[1] 1 High J7 CTS J8 VSSRTC RTC ground Real time clock ground J9 VSSRTC RTC ground Real time clock ground J10 A[17]/DRA[10] 1 Low O System byte address / SDRAM address J11 A[16]/DRA[11] 1 Low O System byte address / SDRAM address J12 A[15]/DRA[12] 1 Low O System byte address / SDRAM address J13 A[14]/DRA[13] 1 Low O System byte address / SDRAM address J14 nTRST I JTAG async reset input J15 D[16] 1 Low I/O Data I/O J16 D[17] 1 Low I/O Data I/O K1 LEDDRV 1 Low O IR LED drive K2 PHDIN I Photodiode input K3 VSSIO K4 DCD K5 nTEST[1] K6 EINT[3] K7 VSSRTC K8 ADCIN K9 COL[4] K10 TCLK K11 Strength Description Pad ground I/O ground With p/u* I UART 1 data carrier detect I Test mode select input I External interrupt RTC ground Real time clock ground I SSI1 ADC serial input 1 High O Keyboard scanner column drive D[20] 1 Low I/O Data I/O K12 D[19] 1 Low I/O Data I/O K13 D[18] 1 Low I/O Data I/O I JTAG clock K14 VSSIO Pad ground I/O ground K15 VDDIO Pad power Digital I/O power, 3.3V K16 VDDIO Pad power Digital I/O power, 3.3V L1 RXD[1] I UART 1 receive data input L2 DSR I L3 VDDIO Pad power Digital I/O power, 3.3V L4 nEINT[1] I External interrupt input L5 PE[2]/CLKSEL 1 Input 1 Low I/O UART 1 data set ready input GPIO port E / clock input mode select L6 VSSRTC L7 PD[0]/LEDFLSH RTC ground Real time clock ground L8 VSSRTC L9 COL[6] 1 High O Keyboard scanner column drive L10 D[31] 1 Low I/O Data I/O I/O GPIO port D / LED blinker output Core ground Real time clock ground L11 VSSRTC L12 A[22]/DRA[5] 1 Low RTC ground Real time clock ground L13 A[21]/DRA[6] 1 Low L14 VSSIO L15 A[18]/DRA[9] 1 Low O System byte address / SDRAM address L16 A[19]/DRA[8] 1 Low O System byte address / SDRAM address M1 nTEST[0] With p/u* I Test mode select input M2 nEINT[2] I External interrupt input M3 VDDIO Pad power Digital I/O power, 3.3V O System byte address / SDRAM address O System byte address / SDRAM address Pad ground I/O ground Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 53 EP7312 High-Performance, Low-Power System on Chip Table 22. 256-Ball PBGA Ball Listing (Continued) 54 Reset State Ball Location Name M4 PE[0]/BOOTSEL[0] 1 M5 TMS with p/u* M6 VDDIO M7 SSITXFR 1 Low I/O DAI/CODEC/SSI2 frame sync M8 DRIVE[1] 2 High / Low I/O PWM drive output M9 FB[0] M10 COL[0] 1 High O Keyboard scanner column drive M11 D[27] 1 Low I/O Data I/O 1 Low M12 VSSIO M13 A[23]/DRA[4] Strength Input Type Description I GPIO port E / Boot mode select I JTAG mode select Pad power I Digital I/O power, 3.3V PWM feedback input Pad ground I/O ground O Pad power System byte address / SDRAM address M14 VDDIO M15 A[20]/DRA[7] 1 Low O System byte address / SDRAM address M16 D[21] 1 Low I/O Data I/O N1 nEXTFIQ N2 PE[1]/BOOTSEL[1] I 1 Input I/O Digital I/O power, 3.3V External fast interrupt input GPIO port E / boot mode select N3 VSSIO Pad ground I/O ground N4 VDDIO Pad power Digital I/O power, 3.3V N5 PD[5] 1 Low I/O GPIO port D N6 PD[2] 1 Low I/O GPIO port D N7 SSIRXDA N8 ADCCLK 1 I/O DAI/CODEC/SSI2 serial data input Low O SSI1 ADC serial clock SSI1 ADC sample clock N9 SMPCLK 1 Low O N10 COL[2] 1 High O Keyboard scanner column drive N11 D[29] 1 Low I/O Data I/O N12 D[26] 1 Low I/O Data I/O N13 HALFWORD 1 Low O Halfword access select output N14 VSSIO N15 D[22] 1 Low I/O Data I/O N16 D[23] 1 Low I/O Data I/O Pad ground I/O ground P1 VSSRTC P2 RTCOUT RTC ground Real time clock ground P3 VSSIO Pad ground I/O ground P4 VSSIO Pad ground I/O ground P5 VDDIO Pad power P6 VSSIO Pad ground I/O ground P7 VSSIO Pad ground I/O ground P8 VDDIO Pad power Pad ground I/O ground O Real time clock oscillator output Digital I/O power, 3.3V Digital I/O power, 3.3V P9 VSSIO P10 VDDIO Pad power P11 VSSIO Pad ground I/O ground P12 VSSIO Pad ground I/O ground P13 VDDIO Pad power P14 VSSIO Pad ground I/O ground P15 D[24] P16 VDDIO 1 Low I/O Pad power R1 RTCIN I/O R2 VDDIO Pad power Digital I/O power, 3.3V Digital I/O power Data I/O Digital I/O power, 3.3V Real time clock oscillator input Digital I/O power, 3.3V Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 22. 256-Ball PBGA Ball Listing (Continued) Reset State Type 1 Low I/O GPIO port D 1 Low I/O GPIO port D SSITXDA 1 Low O DAI/CODEC/SSI2 serial data output R6 nADCCS 1 High R7 VDDIO R8 ADCOUT 1 Low O SSI1 ADC serial data output R9 COL[7] 1 High O Keyboard scanner column drive R10 COL[3] 1 High O Keyboard scanner column drive R11 COL[1] 1 High O Keyboard scanner column drive R12 D[30] 1 Low I/O Data I/O R13 A[27]/DRA[0] 2 Low O System byte address / SDRAM address R14 A[25]/DRA[2] 2 Low O System byte address / SDRAM address R15 VDDIO R16 A[24]/DRA[3] T1 VDDRTC T2 PD[7]/SDQM[1] 1 Low I/O GPIO port D / SDRAM byte lane mask T3 PD[6]/SDQM[0] 1 Low I/O GPIO port D / SDRAM byte lane mask T4 PD[3] 1 Low I/O GPIO port D T5 SSICLK 1 Input I/O DAI/CODEC/SSI2 serial clock T6 SSIRXFR 1 Input I/O DAI/CODEC/SSI2 frame sync T7 VDDCORE 2 High / Low I/O 1 High O Ball Location Name R3 PD[4] R4 PD[1] R5 T8 * Strength T9 FB[1] COL[5] T11 VDDIO SSI1 ADC chip select Digital I/O power, 3.3V Low O RTC power Digital I/O power, 3.3V System byte address / SDRAM address Real time clock power, 2.5V Core power Core power, 2.5V DRIVE[0] T10 O Pad power Pad power 1 Description I Pad power PWM drive output PWM feedback input Keyboard scanner column drive Digital I/O power, 3.3V T12 BUZ 1 Low O Buzzer drive output T13 D[28] 1 Low I/O Data I/O T14 A[26]/DRA[1] 2 Low O System byte address / SDRAM address T15 D[25] 1 Low I/O Data I/O T16 VSSIO Pad ground I/O ground "With p/u" means with internal pull-up of 100 KOhms on the pin. Strength 1 = 4 ma Strength 2 = 12 ma Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. JTAG Boundary Scan Signal Ordering Table 23. JTAG Boundary Scan Signal Ordering DS508PP5 LQFP Pin No. TFBGA Ball PBGA Ball Signal Type Position 1 B3 B1 nCS[5] O 1 4 A2 C2 EXPCLK I/O 3 5 B1 E4 WORD O 6 6 E3 D1 WRITE/nSDRAS O 8 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 55 EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) 56 LQFP Pin No. TFBGA Ball PBGA Ball Signal Type Position 7 C1 F5 RUN/CLKEN O 10 8 C2 D2 EXPRDY I 13 9 E2 F4 TXD2 O 14 10 D2 E1 RXD2 I 16 13 F3 E2 PB[7] I/O 17 14 D1 G5 PB[6] I/O 20 15 F2 F1 PB[5] I/O 23 16 E1 G4 PB[4] I/O 26 17 F1 F2 PB[3] I/O 29 18 G2 H7 PB[2] I/O 32 19 G1 G1 PB[1] I/O 35 20 H3 H6 PB[0] I/O 38 23 H1 H1 PA[7] I/O 41 24 J3 H5 PA[6] I/O 44 25 J2 H2 PA[5] I/O 47 26 J1 H4 PA[4] I/O 50 27 L3 J1 PA[3] I/O 53 28 K2 J4 PA[2] I/O 56 29 K1 J2 PA[1] I/O 59 30 M3 J5 PA[0] I/O 62 31 L2 K1 LEDDRV O 65 32 L1 J6 TXD1 O 67 34 N3 K2 PHDIN I 69 35 M2 J7 CTS I 70 36 M1 L1 RXD1 I 71 37 P3 K4 DCD I 72 38 N1 L2 DSR I 73 39 N2 K5 nTEST1 I 74 40 R3 M1 nTEST0 I 75 41 P1 K6 EINT3 I 76 42 P2 M2 nEINT2 I 77 43 T3 L4 nEINT1 I 78 44 R1 N1 nEXTFIQ I 79 45 R2 L5 PE[2]/CLKSEL I/O 80 46 T1 N2 PE[1]/ BOOTSEL[1] I/O 83 47 T2 M4 PE[0]/BOOTSEL0 I/O 86 53 V4 T2 PD[7]/SDQM[1] I/O 89 54 W4 T3 PD[6/SDQM[0]] I/O 92 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) DS508PP5 LQFP Pin No. TFBGA Ball PBGA Ball Signal Type Position 55 Y4 N5 PD[5] I/O 95 56 V5 R3 PD[4] I/O 98 59 Y5 T4 PD[3] I/O 101 60 V6 N6 PD[2] I/O 104 61 W6 R4 PD[1] I/O 107 62 Y6 L7 PD[0]/LEDFLSH O 110 68 W8 T6 SSIRXFR I/O 122 69 Y8 K8 ADCIN I 125 70 V9 R6 nADCCS O 126 75 W10 M8 DRIVE1 I/O 128 76 Y10 T8 DRIVE0 I/O 131 77 V11 N8 ADCCLK O 134 78 W11 R8 ADCOUT O 136 79 Y11 N9 SMPCLK O 138 80 Y12 T9 FB1 I 140 82 Y11 M9 FB0 I 141 83 Y12 R9 COL7 O 142 84 Y13 L9 COL6 O 144 85 W13 T10 COL5 O 146 86 V13 K9 COL4 O 148 87 Y14 R10 COL3 O 150 88 W14 N10 COL2 O 152 91 Y15 R11 COL1 O 154 92 W15 M10 COL0 O 156 93 V15 T12 BUZ O 158 94 Y16 L10 D[31] I/O 160 95 W16 R12 D[30] I/O 163 96 V16 N11 D[29] I/O 166 97 Y17 T13 D[28] I/O 169 99 Y16 R13 A[27]/DRA[0] Out 172 100 Y18 M11 D[27] I/O 174 101 V17 T14 A[26]/DRA[1] O 177 102 W18 N12 D[26] I/O 179 103 Y19 R14 A[25]/DRA[2] O 182 104 Y20 T15 D[25] I/O 184 105 U18 N13 HALFWORD O 187 106 V209 R16 A[24]/DRA[3] O 189 109 U19 P15 D[24] I/O 191 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 57 EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) 58 LQFP Pin No. TFBGA Ball PBGA Ball Signal Type Position 110 U20 M13 A[23]/DRA[4] O 194 111 T19 N16 D[23] I/O 196 112 T20 L12 A[22]/DRA[5] O 199 113 R19 N15 D[22] I/O 201 114 R20 L13 A[21]/DRA[6] O 204 115 T18 M16 D[21] I/O 206 117 P19 M15 A[20]/DRA[7] O 209 118 P20 K11 D[20] I/O 211 119 R18 L16 A[19]/DRA[8] O 214 120 N19 K12 D[19] I/O 216 121 N20 L15 A[18]/DRA[9] O 219 122 P18 K13 D[18] I/O 221 126 M19 J10 A[17]/DRA[10] O 224 127 N18 J16 D[17] I/O 226 128 L20 J11 A[16]/DRA[11] O 229 129 L19 J15 D[16] I/O 231 130 M18 J12 A[15]/DRA[12] O 234 131 K20 H16 D[15] I/O 236 132 K19 J13 A[14]/DRA[13] O 239 133 K18 H15 D[14] I/O 241 134 J20 H13 A[13]/DRA[14] O 244 135 J19 G16 D[13] I/O 246 136 H20 H12 A[12] O 249 137 H19 G15 D[12] I/O 251 138 J18 H11 A[11] O 254 141 G20 F15 D[11] I/O 256 142 H18 H10 A[10] O 259 143 F20 E16 D[10] I/O 261 144 G19 G13 A[9] O 264 145 E20 E15 D[9] I/O 266 146 F19 G12 A[8] O 269 147 G18 D16 D[8] I/O 271 148 D20 G11 A[7] O 274 150 F18 D15 D[7] I/O 276 151 D19 F13 nBATCHG I 279 152 E19 C16 nEXTPWR I 280 153 C19 F12 BATOK I 281 154 C20 C15 nPOR I 282 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) DS508PP5 LQFP Pin No. TFBGA Ball PBGA Ball Signal Type Position 155 E18 E13 nMEDCHG/nBROM I 283 156 B20 B16 nURESET I 284 161 B16 B14 WAKEUP I 285 162 A16 D11 nPWRFL I 286 163 C15 A13 A[6] O 287 164 B15 F10 D[6] I/O 289 165 A15 B13 A[5] O 292 166 C14 E10 D[5] I/O 294 169 B14 B12 A[4] O 297 170 A14 D10 D[4] I/O 299 171 C13 A11 A[3] O 302 172 B13 G9 D[3] I/O 304 173 A13 B11 A[2] O 307 175 C12 A10 D[2] I/O 309 176 B12 F9 A[1] O 312 177 A12 B10 D[1] I/O 314 178 C11 E9 A[0] O 317 179 B11 A9 D[0] I/O 319 184 B10 D8 CL2 O 322 185 A10 B8 CL1 O 324 186 A9 E8 FRM O 326 187 B9 A7 M O 328 188 C9 F8 DD[3] O 330 189 A8 B7 DD[2] O 333 191 B8 A6 DD[1] O 336 192 C8 G8 DD[0] O 339 193 A7 B6 nSDCS[1] O 342 194 B7 D7 nSDCS[0] O 344 195 C7 A5 SDQM[3] I/O 346 196 A6 E7 SDQM[2] I/O 349 199 B6 F7 SDCKE I/O 352 200 C6 A4 SDCLK I/O 355 201 A5 D6 nMWE/nSDWE O 358 202 B5 B4 nMOE/nSDCAS O 360 204 C5 E6 nCS[0] O 362 205 A4 A3 nCS[1] O 364 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 59 EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) LQFP Pin No. TFBGA Ball PBGA Ball Signal Type Position 206 B4 D5 nCS[2] O 366 207 A3 B3 nCS[3] O 368 208 C4 A2 nCS[4] O 370 1) See EP7312 Users' Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. 60 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip CONVENTIONS Table 24. Acronyms and Abbreviations (Continued) Acronym/ Abbreviation This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 24 lists abbreviations and acronyms used in this data sheet. Table 24. Acronyms and Abbreviations Acronym/ Abbreviation Definition TAP test access port TLB translation lookaside buffer UART universal asynchronous receiver Units of Measurement Table 25. Unit of Measurement Definition Symbol Unit of Measure A/D analog-to-digital ADC analog-to-digital converter C degree Celsius CODEC coder / decoder fs sample frequency D/A digital-to-analog Hz hertz (cycle per second) DMA direct-memory access kbps kilobits per second EPB embedded peripheral bus KB kilobyte (1,024 bytes) FCS frame check sequence kHz kilohertz FIFO first in / first out k kilo Ohm FIQ fast interrupt request Mbps megabits (1,048,576 bits) per second GPIO general purpose I/O MB megabyte (1,048,576 bytes) ICT in circuit test MBps megabytes per second IR infrared MHz megahertz (1,000 kilohertz) IRQ standard interrupt request A microampere IrDA Infrared Data Association F microfarad JTAG Joint Test Action Group W microwatt LCD liquid crystal display s microsecond (1,000 nanoseconds) LED light-emitting diode mA milliampere LQFP low profile quad flat pack mW milliwatt LSB least significant bit ms millisecond (1,000 microseconds) MIPS millions of instructions per second ns nanosecond MMU memory management unit V volt MSB most significant bit W watt PBGA plastic ball grid array PCB printed circuit board PDA personal digital assistant PLL phase locked loop p/u pull-up resistor RISC reduced instruction set computer RTC Real-Time Clock SIR slow (9600-115.2 kbps) infrared SRAM static random access memory SSI synchronous serial interface DS508PP5 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 61 EP7312 High-Performance, Low-Power System on Chip General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase "h" appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, `11' designates a binary number). Numbers not indicated by an "h", 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7312 User's Manual. The use of "TBD" indicates values that are "to be determined," "n/a" designates "not available," and "n/c" indicates a pin that is a "no connect." Pin Description Conventions Abbreviations used for signal directions are listed in Table 26. Table 26. Pin Description Conventions Abbreviation Direction I Input O Output I/O Input or Output 62 Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Ordering Information Here is the list of EP7312 parts that are available: -- -- -- -- -- -- EP7312-CV EP7312-CB EP7312-CV-90 EP7312-CR-90 EP7312-IR EP7312-IB-90 -- EP7312-IV -- EP7312-CR -- EP7312-CB-90 -- EP7312-IB -- EP7312-IV-90 -- EP7312-IR-90 Ordering Information Legend Here is the legend for understanding the ordering information on page 1. EP7312 -- CV --XX Processor Speed Package Type: V = Low Profile Quad Flat Pack (208-pin LQFP) B = Plastic Ball Grid Array (17 mm x 17 mm) (256-ball PBGA) R = Reduced Ball Grid Array (13 mm x 13 mm) (204-pin TFBGA) Part Number Product Line: Embedded Processor Note: DS508PP5 Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. Copyright 2001, 2002 Cirrus Logic (All Rights Reserved) 63