SH69P25
PRELIMINARY OTP 4-bit Microcontroller
1V1.0
Features
n SH6610C-based single-chip 4-bit micro-controller
n OTPROM: 4K X 16 bits
n RAM: 160 X 4 bits (data memory)
n Operation voltage: 2.4V - 6.0V (typical 3.0V or 5.0V)
n 22 CMOS bi-directional I/O pins
n Built in pull-up and pull-low resistor for PortA ~ PortF
n 4-level subroutine nesting (including interrupts)
n One 8-bit auto re-load timer/counter
n Warm-up timer for power on reset
n Powerful interrupt sources:
- Internal interrupt (Timer0)
- External interrupts: PortB & PortC (rising/falling edge)
n Oscillator (OTP option)
- X`tal oscillator: 32.768KHz - 4MHz
- Ceramic resonator: 400K - 4MHz
- RC oscillator: 400K - 4MHz
- External clock: 30K - 4MHz
n Instruction cycle time:
- 4/32.768KHz(122us) for 32.768KHz OSC clock
- 4/4MHz (1us) for 4MHz OSC clock
n Two low power operation modes: HALT and STOP
n Built-in watch dog timer (OTP option)
n Built-in power on reset
n Two LPD level(OTP option)
- High level: 4.0V
- Low level: 2.5V
n OTP type &Code protection
General Description
SH69P25 is a 4-bit micro controller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 4K OTPROM, Timer and I/O
Ports.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
PA2
PE3
PE2
PF1
PA3
T0
GND
PB0
PB1
PB2
PB3
PD0
PD1 PD2
PD3
PC0
PC1
PC2
PC3
V
DD
OSCO
OSCI
PA0
PA1
PF0
PE0
PE1
SH69P25
RESET
SH69P25
2
Block Diagram
Pin Description
Pin No. Designation I/O Descriptions
27, 28, 1, 2 PE[0:3] I/O Bit programmable I/O
26, 3 PF[0:1] I/O Bit programmable I/O
24, 25, 4, 5 PA[0:3] I/O Bit programmable I/O
6T0 ITimer Clock/Counter input pin. (Schmitt trigger input)
7RESET IReset input (active low, Schmitt trigger input)
8GND PGround pin
9 - 12 PB[0:3] I/O Bit programmable I/O. Vector Interrupt (Active rising or falling edge by system
register setup)
13- 16 PD[0:3] I/O Bit programmable I/O
17 - 20 PC[0:3] I/O Bit programmable I/O. Vector Interrupt (Active rising or falling edge by system
register setup)
21 VDD PPower supply pin
22 OSCO OOSC output pin. No output for RC mode
23 OSCI IOSC input pin, connected to a crystal, ceramic or external resistor
WDTEN RC
WATCHDOG
TIMER
OSC
PRESCLALER
CTL REG.
OTPROM
4096*16 BITS
DATA RAM
160*4 BITS
CPU
PORTA ( 4-BITS )
PORTB ( 4-BITS )
PORTC ( 4-BITS )
PORTD (4-BITS )
OSCIOSCO
PORTA [0:3]
PORTB [0:3]
PORTC [0:3]
PORTD [0:3]
PORTE ( 4-BITS )
PORTF ( 2-BITS )
PORTE [0:3]
PORTF [0:1]
RESET
RESET
8-BITS TIMER
( Up counter )
TIMER
INTERRUPT
T0
LPDON
LPD
Power
on
SH69P25
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Function Description
1. CPU
The CPU contains the following function blocks: Program
Counter, Arithmetic Logic Unit (ALU), Carry Flag,
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL), and the Stack.
1.1. PC (Program Counter)
The Program Counter is used to address the 4K program
ROM. It consists of 12-bits: the Page Register (PC11), and
the Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5,
PC4, PC3, PC2, PC1, PC0).
The program counter normally increases by one (+1) with
every execution of an instruction except in the following
cases:
(1) When executing a jump instruction (such as JMP, BA0,
BAC),
(2) When executing a subroutine call instruction (CALL),
(3) When an interrupt occurs,
(4) When the chip is in the INITIAL RESET mode.
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
1.2. ALU and CY
ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
Decimal adjustment for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decision (BA0, BA1, BA2, BA3, BAZ, BAC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow which the
arithmetic operation generates. During an interrupt
servicing or call instruction, the carry flag is pushed into the
stack and retrieved back from the stack by the RTNI
instruction. It is unaffected by the RTNW instruction.
1.3. Accumulator
The Accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data
transfer between the accumulator and system register or
data memory can be performed.
1.4. Stack
A group of registers are used to save the contents of CY &
PC (10-0) sequentially with each subroutine call or interrupt.
It is organized into 13 bits X 4 levels. The MSB is saved for
CY. 4 levels are the maximum allowed for subroutine calls
and interrupts.
The contents of the Stack are returned sequentially to the
PC with the return instructions (RTNI/RTNW). The stack is
operated on a first-in, last-out basis. This 4-level nesting
includes both subroutine calls and interrupts requests.
Note that program execution may enter an abnormal state if
the number of calls and interrupt requests exceed 4, and the
bottom of the stack will be shifted out.
2. OTPROM
The SH69P25 can address up to 4096 X 16 bit words of program area from $000 to $FFF.
Service routine as starting vector address.
Address Instruction Remarks
$000H JMP Instruction Jump to RESET service routine
$001H NOP Reserved
$002H JMP Instruction Jump to TIMER0 service routine
$003H NOP Reserved
$004H JMP Instruction Jump to PBC service routine
SH69P25
4
3. RAM
The built-in RAM consists of general-purpose data memory and the system register. Direct addressing in one instruction c
an access both data memory and the system register.
The following is the memory allocation map:
$000 - $01F: System register and I/O.
$020 - $0BF: Data memory (160 X 4 bits, divided into 2 banks. $020 - $07F: bank0, $080 - $0BF: bank1.
The Configuration of the System Register
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks Power On
$00 -IET0 -IEP R/W Interrupt enable flags - 0 - 0
$01 -IRQT0 -IRQP R/W Interrupt request flags - 0 - 0
$02 -TM0.2 TM0.1 TM0.0 R/W Timer0 Mode register (Prescaler) - 000
$03 - - - - - Reserved -
$04 TL0.3 TL0.2 TL0.1 TL0.0 R/W Timer0 load/counter register low digit 0000
$05 TH0.3 TH0.2 TH0.1 TH0.0 R/W Timer0 load/counter register high digit 0000
$06-$07 - - - - - Reserved -
$08 PA.3 PA.2 PA.1 PA.0 R/W PORTA 1111
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB 1111
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC 1111
$0B PD.3 PD.2 PD.1 PD.0 R/W PORTD 1111
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE 1111
$0D - - PF.1 PF.0 R/W PORTF - -11
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch Register -
$0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register -
$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble -
$11 -DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble -
$12 DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble -
$13 - $14 Reserved
$15 PULLEN PH/PL PBCFR -R/W
Bit1:PBC interrupt rising / failing edge set
Bit2:Port pull-hi/low set
Bit3: Port pull-up/low enable control
010 -
$16 PA3OUT PA2OUT PA1OUT PA0OUT R/W Set PORTA as an output port 0000
$17 PB3OUT PB2OUT PB1OUT PB0OUT R/W Set PORTB as an output port 0000
$18 PC3OUT PC2OUT PC1OUT PC0OUT R/W Set PORTC as an output port 0000
$19 PD3OUT PD2OUT PD1OUT PD0OUT R/W Set PORTD as an output port 0000
$1A PE3OUT PE2OUT PE1OUT PE0OUT R/W Set PORTE as an output port 0000
$1B - - PF1OUT PF0OUT R/W Set PORTF as an output port - - 00
$1C - - T0S T0E R/W Bit0: T0 signal edge;
Bit1: T0 signal source - - 00
$1D - - - - - Reserved -
$1E WDT ---WBit3: WDT timer reset (write 1 to reset WDT) -
$1F - - - - - Reserved -
* System Register $00 - $12 (except $07H) refer to "SH6610C User manual".
SH69P25
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4. Low Power Detection (LPD)
The LPD function is used to monitor the supply voltage and applies an internal reset in the micro-controller at the time of
battery replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated using software
control.
- Power supply voltage VDD = 2.4 to 6.0 V
4.1 Functions of the LPD Circuit
The LPD function is selected by OTP option.
The LPD circuit has the following functions:
- It generates an internal reset signal when VDD ≤ VLPD and t tLPD
- It cancels the internal reset signal when VDD > VLPD or VDD ≤ VLPD and t < tLPD
Here, VDD: power supply voltage, VLPD: LPD detect voltage, There are two level selected by OTP option:
Low level: 2.4~2.6V, typical 2.5V
High level: 3.8~4.2V, typical 4.0V
tLPD: 100us~500us, typical 300us
LPD can be enabled or disabled permanently by OTP option.
SH69P25
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5. I/O Ports
The SH69P25 provides 22 I/O pins. When every I/O is used as an input port, the port control register controls ON/OFF of the
output buffer. Sections below show the circuit configuration of I/O ports.
Every I/O pin has a internal pull up / pull low resister, which is controled by PULLEN and PH/PL of $15
Each of these ports contains 4 or 2(PF) bits I/O pins. ON/OFF of the output buffer for port can be controlled by the port control
register. Port I/O mapping address is shown as follows:
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks Power On
$08 PA.3 PA.2 PA.1 PA.0 R/W PORTA 1111
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB 1111
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC 1111
$0B PD.3 PD.2 PD.1 PD.0 R/W PORTD 1111
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE 1111
$0D - - PF.1 PF.0 R/W PORTF - -11
Equivalent Circuit for a Single I/O Pin
DQ
QB
CK
DATA IN
DATA
WRITE
DQ
QBCK
CONTROL
WRITE OR
I/O PIN
RESET
READ
PXXOUT
DATA
SET
RESET
RESET
VDD
VDD
AND
AND
PULL EN AND
PH/PL
PULL EN AND
PH/PL AND
GND
GND
SH69P25
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System Register $16 - $1B
Address Bit3 Bit2 Bit1 Bit0 R/W Remarks Power On
$15 PULLEN PH/PL PBCFR -RW Bit1:PBC interrupt rising / failing edge set
Bit2:Port pull-hi/low set
Bit3: Port pull-up/low enable control 010 -
$16 PA3OUT PA2OUT PA1OUT PA0OUT WSet PORTA as an output port 0000
$17 PB3OUT PB2OUT PB1OUT PB0OUT WSet PORTB as an output port 0000
$18 PC3OUT PC2OUT PC1OUT PC0OUT WSet PORTC as an output port 0000
$19 PD3OUT PD2OUT PD1OUT PD0OUT WSet PORTD as an output port 0000
$1A PE3OUT PE2OUT PE1OUT PE0OUT WSet PORTE as an output port 0000
$1B - - PF1OUT PF0OUT WSet PORTF as an output port - - 00
PAXOUT, PBXOUT, PCXOUT, PDXOUT, PEXOUT (X = 0, 1, 2, 3), PFXOUT (X = 0, 1)
1: Use as an output buffer
0: Use as an input buffer (Power on initial)
PBCFR: 1: Rising Edge interrupt 0: Falling Edge interrupt,
PH/PL: 1: Port Pull up resister ON, 0: Port Pull low resister ON,
PULLEN: 1: Port Pull up /Pull low enable, 0: Port Pull up /Pull low disable
SH69P25
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PORTB & PORTC interrupt
The PORTB and PORTC are used as port interrupt sources. Since PORT I/O is bit programmable I/O, so only the input port
can generate an external interrupt.
When PBCFR set to 0, any one of the PORTB and PORTC input pin transitions from VDD to GND will generate an interrupt
request. And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD.
When PBCFR set to 1, any one of the PORTB and PORTC input pin transitions from GND to VDD will generate an interrupt
request. And further rising edge transition would not be able to make interrupt request until all of the pins return to GND.
Following is the port interrupt function block-diagram.
PBOUT[3]
PB[3]
PBOUT[2]
PB[2]
PBOUT[1]
PB[1]
PBOUT[0]
PB[0]
PCOUT[3]
PC[3]
PCOUT[2]
PC[2]
PCOUT[1]
PC[1]
PCOUT[0]
PC[0]
PORTINT
PBOUT[3]
PB[3]
PBOUT[2]
PB[2]
PBOUT[1]
PB[1]
PBOUT[0]
PB[0]
PCOUT[3]
PC[3]
PCOUT[2]
PC[2]
PCOUT[1]
PC[1]
PCOUT[0]
PC[0]
PORT INTERRUPT
DETECT
PBCFR
SH69P25
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6. T0 & WDT
System Register $1C
Address BIT3 BIT2 BIT1 BIT0 R/W Remark
$1C - - T0S T0E WBit0: T0 signal edge
Bit1: T0 signal source
T0E: T0 signal edge
0: Increment on low-to-high transition T0 pin (Power on initial)
1: Increment on high-to-low transition T0 pin
T0S: T0 signal source.
0: OSC 1/4 (Power on initial).
1: Transition on T0 pin.
T0
EOR
TOE
M
U
X
OSC/4
T0S
TIMER0 (8bits)
Built-in RC
Oscillator
WDT & Warm
Up Counter
TM0 [2:0]
3
3
WDT Enable
WDT Timeout
0
1
(OTP option )
WDT reset
SH69P25
10
System Register $1E
Address Bit3 Bit2 Bit1 Bit0 R/W Remark
$1E WDT - - - WBit3: Watchdog timer reset. (write 1 to reset WDT)
The input clock of the watchdog timer is generated by a built-in RC oscillator so that the WDT will always run even in the STOP
mode. SH69P25 generates a RESET condition when the watchdog times-out. The watchdog can be enabled or disabled
permanently by using the OTP option. To prevent it timing out and generating a device RESET condition, you should write this
bit as “1” before timing-out. The WDT has a time-out period of more than 7ms(typical 18ms) . If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:2048 can be assigned to the WDT under software controll by writing to the
TM0 register.
Pre-scaler divide ratio:
TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio Timer-out Period
1111:1 7ms(min)
1101:2 14ms(min)
1011:4 28ms(min)
1001:8 56ms(min)
0111:32 224ms(min)
0101:128 896ms(min)
0011:512 3,584ms(min)
0001:2048 (Power on initial) 14,336ms(min)
RC OSC Internal
SCALER_1
/8
W D T
PRESCALER TM0
/1
Final WDT
Time out
period
0.875ms
(min)
WDT Time
out Period
7ms(min)
/2 /4 /8 /32 /128 /512
/2048
SH69P25
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7. Timer0
SH69P25 has one 8-bit timer. The time/counter has the following features:
. 8-bit timer/counter
. Readable and writeable
. Automatic reloadable counter
. 8-prescaler scale is available
. Internal and external clock select
. Interrupt on overflow from $FF to $00
. Edge select for external event
Following is a simplified timer block diagram:
PRE-SCALER T0C 8-BIT COUNTER
Fosc/4
T0
T0E T0S
T0M
7.1. Configuration and Operation
Timer0 consists of an 8-bit write-only timer load register
(TL0L, TL0H), and an 8-bit read-only timer counter (TC0L,
TC0H). The counter and load register both have low order
digits and high order digits. Writing data into the timer load
register (TL0L, TL0H) can initialize the timer counter. Load
register programming: Write the low-order digit first and
then the high-order digit. The timer counter is loaded with
the contents of the load register automatically when the
high order digit is written or the counter counts overflow
from $FF to $00.
Timer Load Register: Since the register H controls the
physical READ and WRITE operation, please follow these
rules:
Write Operation:
First write Low nibble,
Then write High nibble to update the counter.
Read Operation:
High nibble first;
Followed by Low nibble.
Load Reg. H
8-bit timer counter
Load Reg. L
Latch Reg. L
SH69P25
12
7.2. Timer0 Interrupt
The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt
enable flag is enabled, then a timer interrupt service routine will proceed. This can also be used to waken the CPU from HALT
mode.
7.3. Timer0 Mode Register
The timer can be programmed in several different prescaler ratios by setting the Timer Mode register (TM0). The 8-bit counter
counts prescaler overflow output pulses. The timer mode registers (TM0) are 3-bit registers used for timer control as shown
in table1. These mode registers select the input pulse sources into the timer.
Table 1. Timer 0 Mode Register ($02)
TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio Ratio N
000 /211 2048 (initial)
001 /29512
010 /27128
011 /2532
100 /238
101 /244
110 /212
111 /201
7.4. External Clock/Event T0 as Timer0 Source
When an external clock/event input is used for the TM0, it is synchronized with the CPU system clock. Therefor the external
source must follow certain constraints. The output from the T0M multiplex is T0C. It is sampled by the system clock in
instruction frame cycle. Therefore it is necessary for the T0C to be high (at least 2 tOSC) and low (at least 2 tOSC). When the
prescaler ratio selects /20, the T0C is the same as the system clock input. Therefore the requirement is as follows
T0H = T0CH = T0 high time
≥
2 tOSC +T∆
T0L = T0CL = T0 low time
≥
2 tOSC + T∆
Note: T∆= 40ns
When another prescaler ratio is selected, the TM0 is scaled by the asynchronous ripple counter and so the prescaler output
is symmetrical.
Then:
T0C high time = T0C low time = 2T0*N
Where T0 = Timer0 input period
N = prescaler value
The requirement is, therefore:
20T*N
≥
2 tOSC +T∆, or T0
≥
NT2+t*4OSC Δ
The limitation is applied for the T0 period time only. The pulse width is not limited by this equation. It is summarized as
follows:
T0 = Timer0 period
≥
NT2t*4OSC ∆+
SH69P25
13
8. System Clock and Oscillator
System clock generator produces the basic clock pulses that provide the system clock to the CPU and any peripherals.
Instruction cycle time
4. 4/32.768KHz (≈122us) for 32.768KHz system clock
(2) 4/4MHz (1us) for 4MHz system clock
8.1 Oscillator
(1) Crystal oscillator: 32.768KHz – 4MHz.
C1, C2 Setting :
Crystal 32.768KHz :
Typical: C1 = 20p C2 = 20p
Crystal 4MHz :
Typical: C1 = 10p C2 = 10p
Crystal
32.768K - 4MHz
C1
C2
OSCI
OSCO
(2) Ceramic resonator: 400KHz – 4MHz.
C1, C2 Setting :
Typical: C1 = 20p C2 = 20p
Ceramic
400K - 4MHz
C1
C2
OSCI
OSCO
(3) RC oscillator: 400KHz – 4MHz.
OSCI
OSCO
R
V
DD
C1 = 1000p
(4) External input clock: 30KHz – 4MHz.
OSCI
OSCO
External clock source
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9. Initial State
Hardware After Power on Reset
Program counter $000
CY Undefined
Data memory Undefined
System register Undefined
AC Undefined
Pseudo index register Undefined
DPL, DPM, DPH Undefined
Table Branch Register Undefined
Interrupt enable flag register 0
Interrupt request flag register 0
Timer mode register 0
Timer counter 0
Timer load register 0
WDT counter 0
WDT prescaler 0
I/O ports Input
SH69P25
15
Instruction Set
All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation.
Arithmetic and Logical Instruction
Accumulator Type
Mnemonic Instruction Code Function Flag Change
ADC X (, B) 00000 0bbb xxx xxxx AC ←Mx + AC + CY CY
ADCM X (, B) 00000 1bbb xxx xxxx AC, Mx ← Mx + AC + CY CY
ADD X (, B) 00001 0bbb xxx xxxx AC ←Mx + AC CY
ADDM X (, B) 00001 1bbb xxx xxxx AC, Mx ← Mx + AC CY
SBC X (, B) 00010 0bbb xxx xxxx AC ← Mx + -AC + CY CY
SBCM X (, B) 00010 1bbb xxx xxxx AC, Mx ← Mx + -AC + CY CY
SUB X (, B) 00011 0bbb xxx xxxx AC ← Mx + -AC + 1 CY
SUBM X (, B) 00011 1bbb xxx xxxx AC, Mx ← Mx + -AC + 1 CY
EOR X (, B) 00100 0bbb xxx xxxx AC ← Mx ⊕ AC
EORM X (, B) 00100 1bbb xxx xxxx AC, Mx ← Mx ⊕ AC
OR X (, B) 00101 0bbb xxx xxxx AC ← Mx | AC
ORM X (, B) 00101 1bbb xxx xxxx AC, Mx ← Mx | AC
AND X (, B) 00110 0bbb xxx xxxx AC ← Mx & AC
ANDM X (, B) 00110 1bbb xxx xxxx AC, Mx ← Mx & AC
SHR 11110 0000 000 0000 0 → AC[3]; AC[0] →CY;
AC shift right one bit CY
Immediate Type
Mnemonic Instruction Code Function Flag Change
ADI X, I 01000 iiii xxx xxxx AC ← Mx + I CY
ADIM X, I 01001 iiii xxx xxxx AC, Mx ← Mx + I CY
SBI X, I 01010 iiii xxx xxxx AC ← Mx + -I +1 CY
SBIM X, I 01011 iiii xxx xxxx AC, Mx ← Mx + -I + 1 CY
EORIM X, I 01100 iiii xxx xxxx AC, Mx ← Mx ⊕ I
ORIM X, I 01101 iiii xxx xxxx AC, Mx ← Mx | I
ANDIM X, I 01110 iiii xxx xxxx AC, Mx ← Mx & I
4. In the assembler ASM66 V1.0, the EORIM mnemonic is EORI. However, EORI has the identical operation to EORIM.
The same is true for the ORIM with respect to ORI, and ANDIM with respect to ANDI.
Decimal Adjustment
Mnemonic Instruction Code Function Flag Change
DAA X 11001 0110 xxx xxxx AC; Mx ← Decimal adjustment for add. CY
DAS X 11001 1010 xxx xxxx AC; Mx ← Decimal adjustment for sub. CY
SH69P25
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Transfer Instructions
Mnemonic Instruction Code Function Flag Change
LDA X (, B) 00111 0bbb xxx xxxx AC ← Mx
STA X (, B) 00111 1bbb xxx xxxx Mx ← AC
LDI X, I 01111 iiii xxx xxxx AC, Mx ← I
Control Instructions
Mnemonic Instruction Code Function Flag Change
BAZ X 10010 xxxx xxx xxxx PC ← X if AC = 0
BNZ X 10000 xxxx xxx xxxx PC ← X if AC ≠ 0
BC X 10011 xxxx xxx xxxx PC ← X if CY = 1
BNC X 10001 xxxx xxx xxxx PC ← X if CY ≠ 1
BA0 X 10100 xxxx xxx xxxx PC ← X if AC(0) = 1
BA1 X 10101 xxxx xxx xxxx PC ← X if AC(1) = 1
BA2 X 10110 xxxx xxx xxxx PC ← X if AC(2) = 1
BA3 X 10111 xxxx xxx xxxx PC ← X if AC(3) = 1
CALL X 11000 xxxx xxx xxxx ST ← CY; PC + 1
PC ← X (Not including p)
RTNW H, L 11010 000h hhh llll PC ←ST; TBR ← hhhh;
AC ← llll
RTNI 11010 1000 000 0000 CY; PC ← ST CY
HALT 11011 0000 000 0000
STOP 11011 1000 000 0000
JMP X 1110p xxxx xxx xxxx PC ← X (Including p)
TJMP 11110 1111 111 1111 PC ← (PC11-PC8) (TBR) (AC)
NOP 11111 1111 111 1111 No Operation
Where,
PC Program counter IImmediate data
AC Accumulator ⊕Logical exclusive OR
-AC Complement of accumulator |Logical OR
CY Carry flag &Logical AND
Mx Data memory bbb RAM bank
pROM page BRAM bank.
Every $7F as one RAM bank.
ST Stack TBR Table Branch Register
SH69P25
17
Absolute Maximum Rating*
DC Supply Voltage . . . . . . . . . . . . . . –0.3V to + 7.0V
Input Voltage . . . . . . . . . . . . . . . –0.3V to VDD + 0.3V
Operating Ambient Temperature . . . –40℃ to + 85℃
Storage Temperature . . . . . . . . . . .-55℃ to + 125℃
*Comments
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device under these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25℃, FOSC = 4MHz, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Condition
Operating Voltage VDD 4.5 5.0 6.0 V
Operating Current IOP 0.6 1.0 mA All output pins unloaded
(Execute NOP instruction)
Stand by Current (HALT) ISB1 0.5 mA All output pins unloaded
Stand by Current (STOP) ISB2 1µAAll output pins unloaded,
LPD off (If LPD on, ISB2X = ISB2 + 2µA)
WDT off (If WDT on, ISB2X = ISB2 + 15µA)
Input Low Voltage VIL1 GND 0.2 X VDD VI/O ports, pins tri-state
Input Low Voltage VIL2 GND 0.15 X VDD VRESET, T0
Input Low Voltage VIL3 GND 0.15 X VDD VOSCI (Driven by external clock)
Input High Voltage VIH1 0.8 X VDD VDD VI/O ports, pins tri-state
Input High Voltage VIH2 0.85 X VDD VDD VRESET , T0
Input High Voltage VIH3 0.85 X VDD VDD VOSCI (Driven by external Clock)
Input Leakage Current IIL1 -1 1µA I/O ports, GND < VI/O < VDD
Input Leakage Current IIL2 -5 µA VRESET = GND + 0.25V
Input Leakage Current IIL3 1 5 µA VRESET = VDD
Input Leakage Current IIL4 -3 1 3 µAT0, GND < Vt0 < VDD
Input Leakage Current IIL5 -3 1 3 µAFor OSCI
Pull-up/ Pull-low
Resistor RP150 KΩPULL-UP/ PULL-LOW resistor
Output High Voltage VOH VDD – 0.7 VI/O ports, IOH = -10mA
Output Low Voltage VOL GND + 0.6 VI/O ports, IOL = 20mA
AC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25℃, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Condition
Oscillator Start Time TOSC1 1sX’tal osc = 32.768KHz
RESET pulse width (low) TRESET 10 µs VDD = 5.0V
WDT Period TWDT 7 18 ms VDD = 5.0V
Frequency Stability (RC) ∆F/F 20 %RC Oscillator: [F(5.0)-F(4.5)]/F(5.0)
SH69P25
18
DC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25℃, FOSC = 4MHz, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Condition
Operating Voltage VDD 2.4 3.0 4.5 V
Operating Current IOP 0.3 0.6 mA All output pins unloaded
(Execute NOP instruction)
Stand by Current (HALT) ISB1 0.2 mA All output pins unloaded
Stand by Current (STOP) ISB2 1µAAll output pins unloaded,
LPD off (If LPD on, ISB2X = ISB2 + 2µA)
WDT off (If WDT on, ISB2X = ISB2 + 5µA)
Input Low Voltage VIL1 GND 0.2 X VDD VI/O ports, pins tri-state
Input Low Voltage VIL2 GND 0.15 X VDD V
RESET
, T0
Input Low Voltage VIL3 GND 0.15 X VDD VOSCI (Driven by external clock)
Input High Voltage VIH1 0.8 X VDD VDD VI/O ports, pins tri-state
Input High Voltage VIH2 0.85 X VDD VDD V
RESET
, T0
Input High Voltage VIH3 0.85 X VDD VDD VOSCI (Driven by external Clock)
Input Leakage Current IIL1 -1 1µAI/O ports, GND < Vi/o < VDD
Input Leakage Current IIL2 -5 µA VRESET = GND + 0.25V
Input Leakage Current IIL3 1 5 µA VRESET = VDD
Input Leakage Current IIL4 -3 1 3 µAT0, GND < Vt0 < VDD
Input Leakage Current IIL5 -3 1 3 µAFor OSCI
Output High Voltage VOH VDD – 0.7 VI/O ports, IOH = -7mA, VDD = 3V
Output Low Voltage VOL GND + 0.4 VI/O ports, IOL = 8mA, VDD = 3V
User Notice:
Max. Current into VDD = 50mA;
Max. Current out of VSS = 150mA
Max. Output current sunk by any I/O port = 25mA;
Max. Output current sourced by any I/O port = 20mA
Max. Output current sunk by all ports (A, B, C, D, E, F) = 50mA;
Max. Output current sourced by all ports (A, B, C, D, E, F) = 40mA
AC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25
℃
, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Condition
Oscillator Start Time TOSC1 1sCrystal Osc = 32.768KHz, VDD = 3.0V
RESET pulse width (low) TRESET 12 µs VDD = 3.0V
WDT Period TWDT 7 18 ms VDD = 3.0V
Frequency Stability (RC) ∆F/F 20 %RC oscillator (1MHz): [F(3.0)-F(2.7)]/F(3.0)
Low Power Detect Electrical Characteristics
(a) VDD = 2.4~6V, GND = 0V, TA = 25°C, FOSC = 4MHz, unless otherwise specified.
Parameter Symbol Min. Typ. Max. Unit Condition
LPD Voltage(Low) VLPD1 2.4 2.5 2.6 VLPD enable
LPD Voltage(High) VLPD2 3.8 4.0 4.2 VLPD enable
Low power detect ignore time tLPD 100 300 500 us LPD enable and VDD<VLPD
SH69P25
19
AC Characteristics
Symbol Parameter Min. Typ. Max. Unit Condition
TCY Instruction Cycle Time 1 122 µs
TIW T0 Input Width (TCY + 40)/N ns N = Prescaler divide ratio
TIWH High Pulse Width 1/2 tIW ns
TIWL LOW Pulse Width 1/2 tIW ns
Timing Waveform
T0 Input Waveform
TiwH TiwL
Tiw
T0
RC OSCO Timing Waveform
T1 T2 T3 T4 T5 T6 T8T7 T1 T3 T5T2 T4 T6
0ns 1000ns
RC - OSC
PORT
OSCO - RC
Built-in RC Oscillator (Only use for Watch Dog)
OSC
WDT
Built-in RC Tosc1 Twdt
RESET
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20
Typical RC oscillator Resistor vs. Frequency: (VDD = 5V, for reference only)
Typical RC Oscillator Resistor vs. Frequency: (VDD = 3V, for reference only)
5V RC Frequency
100.00
1000.00
10000.00
10.00 60.00 110.00 160.00 210.00 260.00 310.00 360.00
R(k om)
Fosc(kHz)
3V RC Frequancy
100.00
1000.00
10000.00
10.00 60.00 110.00 160.00 210.00 260.00 310.00 360.00
R(k om)
Fosc(k Hz)
SH69P25
21
Application Circuit (for reference only)
AP1
(1) Operating voltage: 5.0V
(2) Oscillator: Ceramic resonator 400KHz
(3) T0 input timer clock / counter
(4) PORTA - F: I/O
20P
T0
VDD
GND
OSCI
OSCO
PORTA
~
PORTF I/O
C1
SH69P25
47KΩ
RESET
0.1u
AP2
(1) Operating voltage: 5.0V.
(2) Oscillator: RC 400KHz.
(3) PORTA - E: I/O
SH69P25
T0
VDD
GND
OSCI
OSCO
PORTA
~
PORTF I/O
C1
1000PF
RESET
22KΩ
47KΩ
0.1u
SH69P25
22
AP3
(1) PORTA - C: as scan KEY BOARD (32 keys)
(2) PORTD - F: I/O,
(3) All input pin internal Pull up On
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC3
PC2
PC1
PORTD
~
PORTF
I/O
SH69P25
SH69P25
23
Ap4 (Weight Scale)
(1) Operating voltage: 5.0V
(2) Oscillator: Ceramic resonator 4MHz
(3) Port A0: External interrupt input for ON/OFF switch
(4) Port E2, E3, F1, A2: S4 - S1 analog switch control signals that control Vil is being charged or discharged by both the
reference voltage (Vref) and the amplified voltage (Vo). The charging and discharging times are determined by the values
of C1, R4 and the threshold voltage of the T0 input pin and the ADC resolution can be up to 8 bit
(5) Other Ports: Sink seven-segment LED current directly. 0 - 199 can be displayed in this configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PE2
PE3
PF1
PA2
PA3
T0
RESET
GND
PB0
PB1
PB2
PB3
PD0
PD1
PE1
PE0
PA1
PA0
OSCO
OSCI
PC3
PC2
PC1
PC0
PD3
PD2
PF0
V
DD
4MHz
C
C
XC1
120P - 470P
1
2
V
DD
120P - 470P
VDD
S1
S2
S3
S4
100Ω
S1
S2
S3
S4
ab cde fg a bcde fg ab cdefg
ON/OFF
R1
R2
R2
R3
R3 R4
R5
Vo
Vo = (1 + 2R2/R1) (R4/R3)Vi
Vref
Load
Cell
Vi
Instrumentation Amplifier R6
C1
Vi1
47K
0.1u
SH69P25
24
Bonding Diagram
25
22
27 24 231 285 26
SH69P25
24 367
8
GND1
P
A
3
T
0
P
A
2
P
F
1
P
E
3
P
E
2
P
E
1
P
E
0
P
F
0
P
A
1
P
A
0
OSCO
O
S
C
I
P
D
2
P
D
1
P
D
0
P
B
3
P
B
2
P
B
1
P
B
0
GND2
19 20 211813 14 15 16 179 10 11 12
V
D
D
P
C
3
P
C
2
P
C
1
P
C
0
P
D
3
X
Y
(0,0)
1920.24um
1879.6um
R
E
S
E
T
NOTE:
1. GND1 BONDING TO GROUND PIN
2. GND2 BONDING TO SUBSTRATE
3. SUBSTRATE BONDING TO GROUND PIN
Pad Location unit: µm
Pad No. Designation X Y Pad No. Designation X Y
1PE 2 -23 749.5 16 PD 3 114 -749.5
2PE 3 -153 749.5 17 PC 0 244 -749.5
3PF 1 -283 749.5 18 PC 1 374 -749.5
4PA 2 -413 749.5 19 PC 2 504 -749.5
5PA 3 -543 749.5 20 PC 3 634 -749.5
6T0 -673 749.5 21 VDD 769 -749.5
7RESET -803 749.5 GND2 822 -619.5
8GND1 -818 585 22 OSCO 725 -420
9PB 0 -796 -749.5 23 OSCI 767 749.5
10 PB 1 -666 -749.5 24 PA 0 587 749.5
11 PB 2 -536 -749.5 25 PA 1 467 749.5
12 PB 3 -406 -749.5 26 PF 0 347 749.5
13 PD 0 -276 -749.5 27 PE 0 227 749.5
14 PD 1 -146 -749.5 28 PE 1 107 749.5
15 PD 2 -16 -749.5
SH69P25
25
Ordering Information
Part No. Packages
SH69P25H CHIP FORM
SH69P25K 28L SKINNY
SH69P25M 28L SOP
SH69P25
26
Package Information
SKINNY_28L Outline Dimensions unit: inches/mm
114
15
28
D
E1
Base Plane
B1
e1
S
A2
AL
A1
Mounting Plane
B
C
E
eA
α
Symbol Dimensions in inches Dimensions in mm
A0.175 Max. 4.45 Max.
A10.010 Min. 0.25 Min.
A20.130 ± 0.005 3.30 ± 0.13
B0.018 +0.004 0.46 +0.10
-0.002 -0.05
B10.060 +0.004 1.52 +0.10
-0.002 -0.05
C0.010 +0.004 0.25 +0.10
-0.002 -0.05
D1.388 Typ. (1.400 Max.) 35.26 Typ. (35.56 Max.)
E0.310 ± 0.010 7.87 ± 0.25
E10.288 ± 0.005 7.32 ± 0.13
e10.100 ± 0.010 2.54 ± 0.25
L0.130 ± 0.010 3.30 ± 0.25
α0° ~ 15°0° ~ 15°
eA0.350 ± 0.020 8.89 ± 0.51
S0.055 Max. 1.40 Max.
Notes:
1. The maximum value of dimension D includes the end flash.
2. Dimension E1 does not include the resin fins.
3. Dimension S includes the end flash.
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27
SOP (N.B.) 28L Outline Dimensions unit: inches/mm
1
E
HE
L
LE
c
14
See Detail F
Detail F
b
1528 e1
e1
A1A2
A
s
D
Seating Plane
D
y
e
~
~~
Symbol Dimensions in inches Dimensions in mm
A0.110 Max. 2.79 Max.
A10.004 Min. 0.10 Min.
A20.093 ± 0.005 2.36 ± 0.13
b0.016 +0.004 0.41 +0.10
-0.002 -0.05
c0.010 +0.004 0.25 +0.10
-0.002 -0.05
D0.705 ± 0.020 17.91 ± 0.51
E0.295 ± 0.010 7.49 ± 0.25
e 0.050 ± 0.006 1.27 ± 0.15
e10.376 NOM. 9.40 NOM.
HE0.406 ± 0.012 10.31± 0.31
L0.036 ± 0.008 0.91 ± 0.20
LE0.055 ± 0.008 1.40 ± 0.20
S0.043 Max. 1.09 Max.
y0.004 Max. 0.10 Max.
θ0° ~ 10°0° ~ 10°
Notes:
1.The maximum value of dimension D includes end flash.
2.Dimension E does not include resin fins.
3.Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
SH69P25
28
Product Spec. Change Notice
SH69P25 Specification Revision History
Version Content Date
1.0 Reduce operating current.
Add RC Frequency-Resistance diagram.
Add bonding diagram May.2003
0.1 Original Sep.2002
