19-0891: Rev 1; 8/93 MAAALVI CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function General Description The MAX150/MX7820 is a high speed, microprocessor compatible, 8 bit analog to digital converter which uses a half-flash technique to achieve a conversion time of 1.34 us. The converter has a OV to +5V analog input range and uses a single +5V supply. A built-in track-and-hold function is included, elimi- nating the need for an external track-and-hold for input slew rates up to 100mV/us. The MAX150 also provides an on-chip 2.5 V reference output, making it a complete analog to digital converter. The A/Ds easily interface with microprocessors by appearing as a memory location or I/O port without the need for external interfacing logic. The data out- puts use latched, three-state buffer circuitry to allow direct connection to a microprocessor data bus or system input port. An over-flow output is also provided for cascading devices to achieve higher resolution. The MX7820 is pin compatible with Analog Devices AD7820. The MAX150 is also compatible with the MX7820 but also includes an internal 2.5V reference. Applications Digital Signal Processing High Speed Data Acquisition Telecommunications High Speed Servo Loops Audio Systems Functional Block Diagram Features @ Fast Conversion Time: 1.345 Max. @ Built-in Track-and-Hold Function @ No Adjustment Required @ No External Clock @ Single +5V Supply @ Easy Interface To Microprocessors @ = Internal 2.5V Reference (MAX150 only) Ordering Information PART TEMP. RANGE PACKAGET ERROR MAXI50ACPP = 0C to +70C_~~Plastic DIP. + LSB | MAXI50BCPP 0C. to +70C Plastic DIP +1 LSB [MAX150BC/D 0Cto+70C _ Dice +1 LSB MAX150ACWP 0C to +70C_~ Small Outline = +% LSB MAX150BCWP 0Cto+70C ~ Small Outline = +1 LSB MAX1S0AEPP -40C to +85C Plastic DIP +% LSB MAX150BEPP -40C to +85C Plastic DIP +1 LSB MAX150AEWP -40C to +85C Smali Outline = +%LSB MAX150BEWP. -40C to +85C Smait Outline +1 LSB MAXI50AMJP -55C to +125C = CERDIP +% LSB MAX150BMJP -55C to +125C = CERDIP +1 LSB + Ali devices 20 lead packages y * Consult factory for dice specifications. a0 Ordering information continued on fast page 20 dete 2 ul 8 i Meet] anc, Pin Configuration 4M vn 1 ( I vor KE Tree \ 080-087 Top View TAC STATE OATA GUT >_>) DRIVERS PINS 2-5, ! i 1417 Vacel]_{ Zar Voo 6 FLAS pom mmae TP/REF QUT* (ALSB] 25v OFL REFERENCE MAKIM 087 (MSB) MAX150 MAX150 MX7820 ONLY _ OBB Lennaee R/ADY Le 0B5 [ TIMING AND CONTROL CIRCUITRY 18 REF OUT DB4 | [| ts Mg "ry Je tis Ig Ig Veeck GNO MODE cS AD ONT REF WA/ADY VaeF- REF OUT MAX150 only. PAAXLM! Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. Oc8ZXW/OSIXVWMAX150/MX7820 CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function ABSOLUTE MAXIMUM RATINGS Supply Voltage, Vpp to GND Voltage at any other pins (Pins 1-9, 11-19) Output current (Pin 19} eee ener b eee vette n tenes 30mA Power Dissipation (Any Package) to 75C Derate Above +75C by 20... cece cece cee ee ee eee OV, +10V Operating Temperature Ranges MAX150XCXX, MX7820LN/KN/LCWP/KCWP GND - 0.3V, Vpp +0.3V MX7820BQ/CQ MAX150XEXX 0.0.0 eect eee ... 450mW MAX150XMXX, MX7820TQ/UQ .......--.5- 6mW/C Storage Temperature Range Lead Temperature (Soldering 10 seconds) ...........-- ... OC to +70C eden eee een ene n teen ae -25C to +86C .. 40C to +85C . -55C to +125C Leben eens -65C to +160C +300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect the device reliability. ELECTRICAL CHARACTERISTICS (Vop = +5V, Veer? = +5V, Vaer~ = GND, RD-MODE, Ta = Twin to Tmax, unless otherwise noted) PARAMETER [ SYMBOL | CONDITIONS MIN. TYP. MAX. | UNITS ACCURACY Resolution 8 bits Total Unadjusted Error (Note 1) Max iS0B ROOK IRI 1? LSB No Missing Codes Resolution 8 bits REFERENCE INPUT Reference Resistance i : Xo Tax iss 22 te ko Veer? Input Voltage Range Veer Vop + 0.1 v Vrer Input Voltage Range GND - 0.41 Veer? Vv REFERENCE OUTPUT MAX150 ONLY (Note 2) Output Voltage REF OUT | Ta =+25C 2.47 2.50 2.53 Vv Load Regulation IL =O to 10mA Ta = +25C -6 -10 mV Power Supply Sensitivity Vppo +5% Ta = +25C +1 +3 mV MAX150XC s- Ta = 0C to +70C 40 70 Temperature Drift (Note 3) MAX150XE = Ta = -40C to +85C 40 70 ppm/C MAX150XM = Ta = -55C to +125C 60 100 Output Noise 200 uV/rms Capacitive Load | 0.01 uF ANALOG INPUT 4 Analog Input Voltage Range VINR GND - 04 Vpo + 0.1 ve Analog Input Capacitance Cyvin 45 pF | Analog Input Current lin Vin = OV to +5V " an Trax 8 BA ! Slew Rate, Tracking (Note 4) SR 0.2 01 Wins | LOGIC INPUTS CS, WR, RD; MAX150 2.0 | Input HIGH Voltage VINH MxX7820 2.4 v MODE 3.5 Input LOW Voltage Vin Kone. RD se Vv CS, RD; Ta = +25C 03 I wr; Te S68d 03 | Input High Current lINH Tein to Tmax 3 HA MODE; Ta = +25C 50 150 | Tmin to Twax 200 | Note 1: Total unadjusted error includes offset, full-scale and linearity errors. Note 2: Specified with no external load unless otherwise noted Note 3: Temperature drift is defined as change in output voltage from +25C to Tmin Or Tmax divided by (25 - Twin) OF (Tmax - 25) Note 4: Sample tested at +25C by Quality Assurance to ensure compliance 2 MAXIMCMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function ELECTRICAL CHARACTERISTICS (continued) (Vop = +5V, Vrer* = +5V, Vrer~ = GND, RD-MODE, Ta = Tain to Tmax, unless otherwise noted) PARAMETER | SYMBOL | CONDITIONS | MIN. TYP, MAX. | UNITS | LOGIC INPUTS (continued) mE GA WE Ta = +25C -0.3 | Input Low Current I , RD, WR, MODE A A P INC os Tain to Twax -1 a ! Input Capacitance (Note 5) Cin CS, RD, WR, MODE 5 8 pF | LOGIC OUTPUTS DB0-DB7, OFL, INT Output HIGH Voltage Vou Vop = +4.75V lout = -360nA 4.0 v Vpp = +4.75V lout = -10nA 45 DBO-DB7, OFL, INT, RDY Output LOW Voltage VoL Vpp = +4.75V lour = 1.6mA 0.4 Vv 7 _ Ta = +25C +0.3 Three-state Output Current DBO-DB7, RDY Tain to Tuax +43 LA Output Source Current Isac DBO-DB7, OFL, INT; Vour = 0 ~10 -25 mA Output Sink Current ISINK OBO0-DB7, OFL, INT, ROY; Vout = Voo 15 40 mA Output Capacitance (Note 5) Court DBO-DB7, OFL INT, RDY 5 8 pF POWER SUPPLY Supply Voltage Vop +5V +5% for specified performance 4.75 .25 Vv Re Wp -BR- Ta = +25C 5 10 Supply Current lbp CS =WR=RD=0 Twin to Tyax 15 mA Power Dissipation CS =WR=RD=0 25 mw Power Supply Sensitivity PSS Vpp = +5% +1/16 +1/4 LSB Note 5: Guaranteed by design. Pin Description [PIN | NAME FUNCTION PIN] NAME FUNCTION | 4 Vin Analog input; range = GND < Vin < Vop. 11 Vrer | Lower limit of reference span. Sets the zero | code voltage. Range: GND to Vprer*. 1 2 DBO Three-state data output, bit 0 (LSB). | : 12 Vrere? | Upper limit of reference span. Sets the Full 3 OB1 Three-state data output, bit 1. Scale input voltage. Range: Vaer~ to Vpn. 4 DB2 | Three-state data output, bit 2. 13 cs CHIP-SELECT input. CS must be low for the device to recognize WR or RD inputs 5 DB3 Three-state data output, bit 3. _ 14 DB4 Three-state data output, bit 4. 6 |WR/RDY| WRITE control input/READY status output. See Digital Interface section. 15 DBS Three-state data output, bit 5. | 7 MODE | Mode selection input. This input is 16 DB6 Three-state data output, bit 6. | | internally pulled low with a 50uA current ! source. 17 DB7 Three-state data output, bit 7 (MSB). _ RD Mode: MODE low/open. | WR-RD Mode: MODE high. 18 OFL Overflow Output. If the analog input is greater | __ than Vaer*, OFL will be high at the end of the | 8 RD READ input. RD must be low to access data. ' conversion. It can be used to cascade twoor | See Digital Interface section. more devices to increase resolution. | 9 INT INTERRUPT output. INT going low indicates | 19 TP Test pin for MX7820. Do not connect pin | the completion of a conversion. See Digital | REF OUT) 19 for MX7820. 2.5V Internal reference Interface section. output for MAX150 only. i 10 GND Ground. i 20 Vpo Power supply voltage, +5V. | MAXI/VI 3 OZ8ZXW/O0SIXVWMAX 150/MX7820 CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function TIMING CHARACTERISTICS (Note 1, 2) MAX150, MX7820 (Vop = +5V, Vrert = +5V, Vrer~ = GND, Ta = Tain to Tmax, unless otherwise specified.) [ +, -408C MAX150C/E | MAX150OM | | PARAMETER SYMBOL CONDITIONS A MX7820K/L/B/C | MX78207/U | UNITS : MIN. TYP MAX. | MIN. MAX. MIN. MAX. CStoRD,WR Setup Time | tess 0 0 0 ns [CS to AD Setup Time | tees: For data-access (Note 5) | 20 30 30 ns | CS to AD, WA Hold Time tosh 0 0 ro ns CS to RDY Delay tapy C, = 50pF, R = 3kf2 35 70 90 100 ns Conversion Time (RD Mode) tero 1.2 1.6 2.0 2.5 BS Data Access Time (RD Mode) tern _terp tcrp tera (See Figure 4) tacca (Note 3) +10 +20 +35 ~50 | "8 RD to INT Delay (RD Mode) tintH C, = 50pF 60 125 175 225 ns Data Hold Time tou (Note 4) 40 60 80 100 ns Delay Time Between Conversions 'e $00 600 600 ns Write Pulse Width twa 600 50,000 | 600 50,000 | 600 50,000, ns Conversion Time (WR/RD Mode) tewr-rb 1.34 15 1.53 us Delay between WR and RD Pulses tap 600 700 700 ns Data Access Time 1 (WR/RD Mode) taces tap < tint: 110 160 225 250 ns (See Figure 6) {Note 3) RD to INT Delay tal 100 140 200 225 ns WR to INT Delay tinte 600 =: 1000 1400 1700 ns Data Access Time ten >t (WR/RD Mode) tacce | (Note ys" 60 70 90 110 ns (See Figure 5} : WR to INT Delay t | (Stand-Alone) IHWR, \ C, = 50pF 70 100 130 150 ns Data Access Time After INT tip 10 50 65 | 75 ns Note 1: Sample tested at +25C by Quality Assurance to ensure compliance. Note 2: Ali input control signals are specified with ta = tp = 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V Note 3: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 4: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. Note 5: Guaranteed by design. Not production tested. DBN OBN 3kOD \OOpF Skit 10pF = DGND = = OGND > a. High-Z to Voy a. Vox to High-Z +5V +V 3ki) 3k OBN 0BN T 100pF T" = OGNO = 0GNO b. High-Z to Vo, b. Voz to High-Z Figure 1, Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test ? 4 MAAI/VICMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function Typical Operating Characteristics REFERENCE TEMPERATURE OUTPUT CURRENT DRIFT (MAX150 ONLY) ACCURACY vs. twr vs. TEMPERATURE 2520 20 20 Von = 5V Voo = 5V Vaer = 5 Ty = 425C 16 2.510 = tp = 500ns - a tap = 600ns = Isouace Vout = 24V uu =a = 2 F ER 5 = = 2500 ao 5 2 = faa = = > 8 = 2 Igink Vout = 0.4V 2.490 05 SINK OUT 4 2.480 0 0 -50 0 50 100 150 20 420300s00 500 ooo | 700 -100 _-50 0 50 tou 150 Ta AMBIENT TEMPERATURE (C) twa (ns) Ta AMBIENT TEMPERATURE (C] ACCURACY vs. VREF ACCURACY vs trp ACCURACY vs. tp [Vrer = Vrer(+) - Vrer(-)) 20 20 20 Vo = 5. Vop = 5V Voo = 5 Vrer = 5. Vaer = 5V Ta = 28C Th = 25C Ta = 25C 15 tp = 500ns 15 twr = 600ns 18 Fy twr = 60Ons = ta = 600ns S 3 3 2 s s g = = = = 10 = 1.0 > 10 z z z = = z 05 05 as 0 0 0 200 300400 50060070 300 400 500 800s 700s 0900 0 1 2 3 4 5 tro (ns) tro (ns] Vner (] tinte INTERNAL TIME DELAY vs. CONVERSION TIME (RD MODE) POWER SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE vs. TEMPERATURE (NOT INCLUDING REFERENCE LADDER) 20 25 8 3 = z _ | z 1S = 20 = = = = 6 = 3 = = 10 = 5 > 5 a Von = 475V 3 Vog = 4.75 Vpn = 5.25V = z Vou = 8V 1 Von = 5.0 a 4 E 05 10 3 | Vpo = 5.25V 3 9 05 2 -100 -50 0 50 100 150 100-50 0 50 100 150 -I00-50 Q 50 100 150 Ty AMBIENT TEMPERATURE [C] Ta AMBIENT TEMPERATURE (C] Ta AMBIENT TEMPERATURE (C) MAXI 5 O28ZXW/OSELXVWMAX 150/MX7820 CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function Detailed Description Converter Operation The MAX150/MX7820 uses a half-flash conversion technique (see Functional Block Diagram). Two 4-bit flash A/D converter sections are used to achieve an 8-bit result. Using 15 comparators, the upper 4-bit MS (most significant) flash A/D compares the un- known input voltage to the reference ladder and provides the upper four data bits. An internal DAC uses the MS bits to generate the analog result from the first flash conversion, and generates a residue voltage which is the difference of the unknown input and the DAC voltage. The residue is then compared to the reference ladder using 15 LS (least significant) flash comparators to obtain the - lower four bits of the output. An additional over- range comparator detects if the analog input is greater than the reference voltage. INT GOING LOW INDICATES wi = 500ns 600ns. THAT oon NaS COMPLETE AN ff ee yi DATA CAN BE READ SET-UP TIME REQUIRED BY THE INTERNAL Vin IS SAMPLED COMPARATORS PRIOR TO / AND THE 4 MSB'S OD BROUGHT LOW HERE LATCHES STARTING CONVERSION ARE LATCHED THE 4 LSBS AND ACCESSES OATA ON DB0-087 Vin 1S TRACKED BY INTERNAL COMPARATORS Figure 3. Operating Sequence (WR-RD Mode). Operating Sequence The operating sequence for the WR-RD Mode is shown in Figure 3. The conversion is initiated by a falling edge of WR. The comparator inputs track the analog input voltage for the duration of WR low. A minimum of 600ns is required for the input voltage to be acquired. When WR returns high, the MS fiash result is latched into the output buffers and the LS conversion begins. INT goes low approximately 600ns later, indicating the end of the conversion, and that the lower_4 data bits are latched into the output buffers. RD going low then accesses the data. If an externally controlled conversion time is required, the RD_line can be brought low as soon as 600ns after WR goes high. This will latch the lower 4 data bits and output the conversion result on DBO-DB7. At least 500ns setup time is required from INT going low to the start of another conversion (WR going low). Digital Interface The MAX150/MX7820has two basic interface modes which are set by the status of the MODE input pin. When this pin is low, the converter is in the RD mode, when this pin is high the converter is set up for the WR-RD mode. RD Mode In RD mode, conversion control and data access is controlled by the RD input (see Figure 4). The con- version is initiated by taking RD low. RD is then kept low until output data appears. This mode is useful for microprocessors which can be forced into a WAIT state. The processor can start a conversion, wait, and then read data with a single READ instruction. Pin 6 (WR/RDY) is configured as a status output (RDY) in RD mode. This output can be used to drive the READY or WAIT input of a processor. RDY is an open collector output (with no interna! pull-up device) which goes low after the falling edge of CS and goes high impedance at the end of the conversion. An INT output is also provided which goes low at the end of the conversion and returns high on the rising edge of CS or RD. WR-RD Mode In the WR-RD mode, pin 6 (WR/RDY) is configured as the WRITE input for the converter. With CS low, a conversion is initiated on the falling edge of WR. Several options exist for reading the data from the converter. Using Internal Delay In the first of these options the processor waits for INT_output to go low before reading the data (Figure 5). INT typically goes low 600ns after the rising edge of WR, indicating that the conversion is complete and the result is available in the output latch. With CS low, data outputs DBO-DB7 can be accessed by pul- ling RD_low. INT is then reset by the rising edge of CS or RD. Reading Before Delay An alternative option can be used to externally con- trol the conversion time (see Figure 6). The internally generated 600ns delay varies somewhat with tempera- ture and supply voltage (see Typical Operating Characteristics) and can be_ overridden with RD. To achieve this, the status of INT is ignored and RD is brought low as soon as 600ns after the rising edge of WR. This completes the conversion and enables the output buffers, DBO-DB7, which contain the conver- sion result. INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. MAAXAI/VICMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function Pipelined Operation In addition to the two standard WR-RD mode options, pipe-lined operation can be achieved by tying WR and RD together (see Figure 7). With CS low, WR and RD going low initiates a conversion, and reads the result of the previous conversion at the same time. Stand-Alone Operation The converter can also_be used_in a stand-alone operation (see Figure 8). CS and RD are tied low and a conversion is initiated by pulling WR low. Output data is valid approximately 600ns after the rising edge of WR. & tes | Ro \ LY a tess _>} | tp > ROY j a WITH EXTERNAL PULL-UP ~| tnpy je _| NTH INT | <_ NTL |~< torn J] f ( VALID - 0B0-087 ATA 080-087 wu ,-- _ 1 tacco toa tance? a} {tte ton |~<- Figure 4. RD Mode Timing. Figure 7. WR-RD Mode Pipe-Lined Timing WR = RD. Oc8ZXW/O0OSILXVIN tinwa > ho Ty Th INT w} je tio VALID Figure 5. WR-RD Mode Timing (tap > tinre). Figure 8. WR-RD Mode Stand-Alone Timing CS = RD = 0.MAX 150/MX7820 CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function OUTPUT cone FULL SCALE TRANSITION unt wiinta wnt 1 7 FS _ Vaer(+) - Vaerl-] 1 == i 7 NSB = ae 256 1 1 : 0000011 anoo0010 ese REFI+| oodoo00! / ooocoong Ay ;# 4 -___-_- ++ +> nee _/S 1 2 3 nef l-| Vin. INPUT VOLTAGE FS - 1188 (IN TERMS OF LSB's} Figure 9. Transfer Function. Analog Considerations Reference The MAX150 includes an internal 2.5V reference (REFOUT) which is appropriate for the majority of 8 bit measurement applications. To use the on-chip reference, connect REFOUT, pin 19, to Vrer*, pin 12, and connect Va_er, pin 11, to ground. The 2.5V output is referred to GND, pin 10. Both the MAX150 and the MX7820, which does not have an on-chip reference, can be used with an external reference if desired. Figure 10 shows some possible reference connec- tions. For the MAX150, a 0.01uF bypass capacitor to GND should be used to reduce the high frequency output impedance of the internal reference. Larger capacitors should not be used as this degrades the stability of the reference buffer. The Vaer* and Veer inputs of both converters set the full-scale and zero input voltages of the A/D. In other words, the voltage at Veer defines the input which produces an output code of all zeroes, and the vol- tage at Vrer* defines the input which produces an output code of all ones (see Figure 9). Vint*| _ Vin 10 Vint-} re GND = 20 MAKIM Yoo MX7820 MAKI Al " MX 584 +50 Vree [+] Vaer (-] Figure 10b. External Reference 2.5V Full-Scale. 1 Vin (+) Vin 1 Vin 4-4] GND = MAKIM 20 MAX 150 wv Von MX7820 V2 + Vaer [+] Ol uF Tuk h l 1 Vner (-] Figure 10a. Power Supply as Reference. 1 Van (+1 -J Vin Vin { + GAO ms - 20 MAXIM +5V Yoo MAX150 REFQUT Veer (+) + L DIF A?yF O01 F "1 | | fe Vater (-1 L | Vin(*l Vin MAXI MAX 150 MX7820 Veer (+) Vaer (-] *Current path must still exist from Vini-) to Ground Figure 10c. internal Reference (MAX150 only). Figure 10d. Input Not Referenced to GND. MAKICMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function Bypassing A 47uF electrolytic and O1F ceramic capacitor should be used to bypass the Vpp pin to GND. These capacitors should have the minimum possible lead length. Excess lead length may contribute to conver- sion errors and instability. If the reference inputs (pins 11, 12) are driven by long lines, they should be bypassed to GND with 01 pF capacitors at the Vrer pins. Input Current The MAX150/MX7820 analog input behaves somewhat differently from conventional A/D converters. The sampled data comparators take varying amounts of current from the input depending on the cycle they are in. The equivalent circuit of the converter is_shown in Figure 11. When the conversion starts and WR is low, Vin is connected to the MS and LS comparators. Thus, Viy is connected to thirty-one 1pF capacitors. Fi = 120F Row > _ IgF 10 LS OX IpF e LADDER r : = 15 LSB COMPARATORS Pon a 2% LADDER 16 MSB COMPARATORS Figure 11a. Equivalent Input Circuit. Vn 32pF Cs l2pF 1 Figure 11b. RC Network Model. MAXKIS/VvI During this acquisition phase (WR = Low in the WR-RD Mode) the input capacitors must be charged to the input voltage through the resistance of the internal analog switches (about 2k to 5kQ). In addi- tion, about 12pF of stray capacitance must be charged. The input can be modelled as an equivalent RC network shown in Figure 11. As Rg (source impe- dance) increases, the capacitors take longer to charge. Typical input capacitances of 45pF allow source resis- tances of up to 1kQ to be used without settling problems. For larger resistances, the width of the WR pulse must be increased from 600ns. Since the length of this acquisition time is internally set when in the RD mode, large source resistances (greater than 1k) may cause settling errors. In this case, use the WR-RD mode and greater than 600ns RD time or use a buffer to drive the analog input. input Filtering The transients in the analog input due to the sampled data comparators do not degrade the converter's performance since the A/D does not look at the input when these transients occur. The comparator's outputs track_the input while WR is low, and are latched once WR goes high. Therefore, at least 600ns will be provided to charge the ADCs input capaci- tance. It is not necessary to filter these transients with an external capacitor on the Viy terminal. Inherent Track-and-Hold Due to its sampling behavior, the MAX150/MX7820 has the ability to measure a variety of high speed input signals without the help of an external sample- and-hold. In a conventional SAR type converter, the analog input must remain stable within 1/2 LSB for the duration of the conversion to maintain accuracy. This requires the use of external sample-and-holds whenever the input is a high speed signal. Although the conversion time for the MAX150/MX7820 is 1.34us, the time for which the input must be stable is much less. The MAX150/MX7820 tracks the input while WR is low (in the WR-RD mode) and finishes sampling it approximately 100ns after the rising edge of WR. This aperture delay is caused by the internal logic propa- gation delay. Input signals with slew rates typically below 200mW/us can be converted without error. How- ever, faster signals may cause differential linearity errors due different delays through the MS and LS comparators. Still, the errors caused by fast input signals are far less than the errors caused in a con- ventional SAR type ADC without a sample-and-hold. A ius SAR converter would still not be able to measure a 1kHz, 5V sine wave without the aid of an external sample-and-hold. The MAX150/MX 7820 with no such help, can typically measure 5V, 10kHz waveforms. Of8ZXW/OSEXVINMAX150/MX7820 CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function fi3 +5V 20 Voo cs cs + 7 [6 _ T ON uF T 4TyF MODE WR WR MAKIN = = MAX150. ji -+_(_ }- <j a Mx7820 12 VaeF Vaer [+] Og | VIN Vin 0B0-087 Oy-D; i Veer (-] < a _ 4 GND OFL OFL fe ant \ +O 3 20 Von cs 7 __ 16 > > ka MODE Axim i MAX150 8 MX7820 fi I<} 4 12 Var [+] t VIN 080-087 i Veer I-1 10 GND OFL 18 = Figure 712. 9-Bit Resolution SAMPLE PULSE VinfOV to 5) *tv +18N ahh \6 [3 [18 Vin WR Vrer Voo OF wa +18V 13 cs MAKI SI MAXI 8} a5 | MAX750 1) RESET Mx7224 Vour - ov To +100 tt MX 7820 Ver (-} af l4 ae cs 20 wa Le +5V Von . ; 080-087 080-087 ioe t OF tT MODE I + acno [4 ~ ~ 12 5 +5V Vater [+] OGND Vss Figure 13. Fast Sample-and-Infinite Hold 10 MAXAILSVICMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function CLK VINA Ving I; 6 14 15 |3 vw wR cs sWR Veer 10 GND +150 13] os 18 SS WMAXIM ; Yao _ ] 8}ig = MAX150 RESET ier 1 MX7820 2 Vrer Vout f- L 20 +5 Yoo + 7 DB0-D87 0BO-087 ioac LE uf aTuF MODE I T ano [4 - ~ 12 5 Ver ] Vrer I+) DGNO Vss a4 i + -5 _ Vina X Vine VReF If Vina S Veer Figure 14. 8-Bit Analog Multiplier 10k.2 AD AIS ADDRESS BUS 32k) nl 4, 1 _43 3kHz max) 10k 2 Vin CS -~<+_ in axiun MAX400 MAXIM wale MAEQ EW TeconE 001 uF 16.2k02 MAX150 4 1 AD jk + [Lg cs = 9 av ni 280 un OOluk PY Yate iNT -> - 7 t 1) rerouT WAIT WA/ADY => . 20 3 MAXIM +8V Yoo 0 aD MAX150 . 1 MX 7820 luk Tuk VreFl-] I OY no no -07 DATA BUS 080-087 = = = mone i Sample Rate is 20kHz. = Figure 15, Simple RD-Mode Interface MAXAIWI Figure 16. Telecom A/D Converter W Oc8ZLXW/OSIEXVINMAX 150/MX7820 CMOS High Speed 8 Bit A/D Converter with Reference and Track/Hold Function ___ Ordering Information (continued) [PART TEMP RANGE PACKAGE} ~- ERROR " MX7820LN OCtor70C Plastic DIP +% LSB | MX7820KN orCto+70C _Plastic DIP +1 LSB MX7B20LCWP 0Cto+70C Small Outline =% LSB MX7B820KCWP 0Cto+70C Small Outline +1 LSB MX7820CQ --25C to+85C CERDIP 4% LSB |MX7820BQ -25C to+85C. = CERDIP +1 LSB |Mx7820UQ 56C to +125C ~s CERDIP + LSB MX7820TQ -86C to +125C - CERDIP =1LSB t All devices 20 lead packages Chip Topography 0.125" {3.175mm) 080 Vin Voo TP/REF OUT* 0119" (3.023mm) INT Vaee *MAX150 Only. Package Information 1 itm as tas 0.110 pay jo.762- 2794) 0.250 = 11005 L$ , Le (1060 + 0.005 (1.524 0.127) (3.302 + 0.127) | Ig IS mS S jo:505) MN. D125 ay ae) je (3-175) 0.325 ane 0.018 + 0.003 }i ven 01 0.100 + 0.010 (0.457 + 0.076) e540 0754 8.255 +0658) 20 Lead Plastic DIP (PP) Oya = 125C/W 83c = 60C/W LEAD #1 AAA A i r 0.291-0.299 0.344 -0 364 9.394 - 0.419 (7.390 - 7.959) (8.738 -9.246) (10.008 10.643) \ Et pl fg Bord = 0.019 o] Lg 0.058 ase. (0.356 - 0.482} (1.270) 0.092 - 0.164 {2.337 - 2.642} as, [+ SSE 4 7 ee vc 0.053 MIN. 0.003 - 0.011 =| lees 346) sant 012 (0-076 0.279) ea 250 2.450} (0-220 9-305) 20 Lead Small Outline, Wide (WP) Aya = 90C/W Ajo = 50C/W Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1994 Maxim Integrated Products Printed USA MAXIM. is a registered trademark of Maxim Integrated Products.