 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 6-V VCC Operation (’HC190, 191)
D4.5-V to 5.5-V VCC Operation (’HCT191)
DWide Operating Temperature Range of
−55°C to 125°C
DSynchronous Counting and Asynchronous
Loading
DTwo Outputs for n-Bit Cascading
DLook-Ahead Carry for High-Speed Counting
DBalanced Propagation Delays and
Transition Times
DStandard Outputs Drive Up To 15 LS-TTL
Loads
DSignificant Power Reduction Compared to
LS-TTL Logic ICs
description/ordering information
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and
CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous
parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up
(D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented
synchronously with the low-to-high transition of the clock.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
CD74HC190E CD74HC190E
PDIP − E Tube of 25 CD74HC191E CD74HC191E
PDIP − E
Tube of 25
CD74HCT191E CD74HCT191E
Tube of 40 CD74HC191M
SOIC − M
Reel of 2500 CD74HC191M96 HC191M
SOIC − M Reel of 250 CD74HC191MT
HC191M
−55°C to 125°C
Tube of 40 CD74HCT191M HCT191M
−55°C to 125°CSOP − NS Reel of 2000 CD74HC190NSR HC190M
Tube of 90 CD74HC190PW
TSSOP − PW Reel of 2000 CD74HC190PWR HJ190
TSSOP − PW
Reel of 250 CD74HC190PWT
HJ190
CD54HC190F3A CD54HC190F3A
CDIP − F Tube of 25 CD54HC191F3A CD54HC191F3A
CDIP − F
Tube of 25
CD54HCT191F3A CD54HCT191F3A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
  !" # $%&" !#  '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CD54HC190, 191; CD54HCT191...F PACKAGE
CD74HC190 . . . E, NS, OR PW PACKAGE
CD74HC191, CD74HCT191 ...E OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
QB
QA
CTEN
D/U
QC
QD
GND
VCC
A
CLK
RCO
MAX/MIN
LOAD
C
D
 '*%$"# $')!" " 121343 !)) '!!&"&# !& "&#"&*
%)&## ",&.#& "&*+  !)) ",& '*%$"# '*%$"
'$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes
high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading
(see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO) output, which normally is high, goes
low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO
(see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to
the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
FUNCTION TABLE
INPUTS
FUNCTION
LOAD CTEN D/U CLK
FUNCTION
H L L Count up
H L H Count down
L X X X Asynchronous preset
H H X X No change
D/U or CTEN should be changed only when clock is high.
X = Don’t care
Low-to-high clock transition
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC190 logic diagram
A
D/U
14
4
5
11
CLK
LOAD
32
LOAD
FF0
DATA
CLK
T
Q
Q
LOAD
FF1
DATA
CLK
T
Q
Q
B
15 1
b
c
d
e
f
g
h
i
k
j
l
m
n
o
p
QAQB
CTEN
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC190 logic diagram (continued)
LOAD
FF2
DATA
CLK
T
Q
Q
LOAD
FF3
DATA
CLK
T
Q
Q
7
D
13
9
b
c
d
e
f
g
h
i
k
j
l
m
n
C10
6
o
p
12 MAX/MIN
RCO
QCQD
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC191, ’HCT191 logic diagram
C
LK
D/U
LOAD
LOAD
FF0
DATA
CLK
T
Q
Q
LOAD
FF1
DATA
CLK
T
Q
Q
LOAD
FF2
DATA
CLK
T
Q
Q
A
14
4
5
11
32
B
15 1
b
c
d
e
f
g
h
i
k
j
l
M
N
C
10
6
C
TEN
QAQC
QB
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC191, ’HCT191 logic diagram (continued)
RCO
LOAD
FF3
DATA
CLK
T
Q
Q
13
b
c
d
e
f
g
h
i
k
j
l
m
n
D
9
7
12 MAX/MIN
QD
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC190 and ’HC191/HCT191 flip-flop
Q
CLK
CL
np
Q
T
CLK
CK
CLK
CLK
CLK
CL
CLK
LOAD
LOAD
LOAD
LOAD
p
nn
p
DATA
LOAD
np
p
n
np
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical load, count, and inhibit sequence for ’HC190
The following sequence is illustrated below:
1. Load (preset) to BCD 7
2. Count up to 8, 9 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 9, 8, and 7
Parallel Load
Preset
Input
Data
P0
P1
P2
P3
Clock
Down/Up
Clock Enable
Q0
Q1
Q2
Q3
Terminal Count
Ripple Clock
Load
H
H
789012 2210987
L
L
L
L
H
H
H
H
H
L
L L
L
H
Count Up Inhibit
Count Down
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical load, count, and inhibit sequence for ’HC191 and ’HCT191
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
Data
Inputs
Data
Outputs
LOAD
A
B
C
D
CLK
D/U
CTEN
MAX/MIN
QA
QB
QC
QD
Load
Count Up Inhibit
13 14 15 0 1 2
RCO
Count Down
2210151413
L
H
H
L
H
L
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CE
CP TC
CE
CP TC
CE
CP TC
D/U
Direction
Control
Enable
Clock
D/U D/U
Figure 1. ’HC190 Synchronous n-Stage Counter With Parallel Gated Terminal Count
CE
CP
RC
CE
CP
RC
CE
CP
RC
Direction
Control
Enable
Clock
D/U D/U D/U
Figure 2. ’HC191, ’HCT191 Synchronous n-Stage Counter With Parallel Gated Terminal Count
NOTE: Illegal states in BCD counters corrected in one count
234
5
6
7
89101112
13
14
15
10
Count Up
NOTE: Illegal states in BCD counters corrected in one or two counts
234
5
6
7
89101112
13
14
15
10
Count Down
Figure 3. ’HC190 State Diagram
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output drain current per output, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output source or sink current per output, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): E package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for ’HC190 and ’HC191 (see Note 3)
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 6 2 6 2 6 V
VCC = 2 V 1.5 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 3.15 V
VIH
VCC = 6 V 4.2 4.2 4.2
V
VCC = 2 V 0.5 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 1.35 V
VIL
VCC = 6 V 1.8 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC 0 VCC V
VCC = 2 V 1000 1000 1000
t
t
Input transition (rise and fall) time VCC = 4.5 V 500 500 500 ns
tt
VCC = 6 V 400 400 400
ns
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions for ’HCT191 (see Note 4)
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
VIInput voltage VCC VCC VCC V
VOOutput voltage VCC VCC VCC V
ttInput transition (rise and fall) time 500 500 500 ns
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC190, ’HC191
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.9 5.9 V
VOH
VI = VIH or VIL
IOH = −4 mA 4.5 V 3.98 3.7 3.84
V
IOH = −5.2 mA 6 V 5.48 5.2 5.34
2 V 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.1 0.1 0.1 V
VOL
VI = VIH or VIL
IOL = 4 mA 4.5 V 0.26 0.4 0.33
V
IOL = 5.2 mA 6 V 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±1±1µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci10 10 10 pF
’HCT191
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
VI = VIH or VIL
IOH = −20 µA
4.5 V
4.4 4.4 4.4
V
VOH VI = VIH or VIL IOH = −4 mA 4.5 V 3.98 3.7 3.84 V
VOL
VI = VIH or VIL
IOL = 20 µA
4.5 V
0.1 0.1 0.1
V
VOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.26 0.4 0.33 V
IIVI = VCC to GND 5.5 V ±0.1 ±1±1µA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆ICC†One input at VCC − 2.1 V,
Other inputs at 0 or VCC 4.5 V to 5.5 V 100 360 490 450 µA
Ci10 10 10 pF
†Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
HCT INPUT LOADING TABLE
INPUTS UNIT LOADS
A-D 0.4
CLK 1.5
LOAD 1.5
D/U 1.2
CTEN 1.5
Unit load is nICC limit specified in electrical
characteristics table, (e.g., 360 µA max at 25°C).
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC190, ’HC191 timing requirements over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 4)
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
VCC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 645
f
clock
Clock frequency†4.5 V 30 20 25 MHz
fclock
Clock frequency†
6 V 35 23 29
MHz
2 V 80 120 100
LOAD low 4.5 V 16 24 20
tw
Pulse duration
LOAD low
6 V 14 20 17
ns
twPulse duration 2 V 100 150 125 ns
CLK high or low 4.5 V 20 30 25
CLK high or low
6 V 17 26 21
2 V 60 90 75
Data before LOAD↑4.5 V 12 18 15
Data before LOAD↑
6 V 10 15 13
2 V 60 90 75
t
su
Setup time CTEN before CLK↑4.5 V 12 18 15 ns
tsu
Setup time
CTEN before CLK↑
6 V 10 15 13
ns
2 V 90 135 115
D/U before CLK↑4.5 V 18 27 23
D/U before CLK↑
6 V 15 23 20
2 V 222
Data before LOAD↑4.5 V 222
Data before LOAD
6 V 222
2 V 222
t
h
Hold time CTEN before CLK↑4.5 V 222ns
th
Hold time
CTEN before CLK
6 V 222
ns
2 V 000
D/U before CLK↑4.5 V 000
D/U before CLK
6 V 000
2 V 60 90 75
t
rec
Recovery time LOAD inactive before CLK↑4.5 V 12 18 15 ns
trec
Recovery time
LOAD inactive before CLK↑
6 V 10 15 13
ns
†Applies to noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, CTEN-to-clock setup times, and
CTEN-to-clock hold times determine maximum clock frequency. For example, with these HC devices:
fmax(CLK)+1
CLK-to-MAXńMIN propagation delay )CTEN-to-CLK setup time )CTEN-to-CLK hold time +1
42 )12 )2[18 MHz
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC190, ’HC191
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 4 5
f
max
4.5 V 30 20 25 MHz
fmax
6 V 35 23 29
MHz
2 V 195 295 245
LOAD
Q
C
L
= 50 pF 4.5 V 39 59 49
LOAD Q
CL = 50 pF
6 V 33 50 42
CL = 15 pF 5 V 16
2 V 175 265 220
A, B, C,
Q
C
L
= 50 pF 4.5 V 35 53 44
A, B, C,
or D Q
CL = 50 pF
6 V 30 45 37
or D
CL = 15 pF 5 V 14
2 V 170 255 215
CLK
Q
C
L
= 50 pF 4.5 V 34 51 43
CLK Q
CL = 50 pF
6 V 29 43 37
CL = 15 pF 5 V 14
2 V 125 190 155
CLK
RCO
C
L
= 50 pF 4.5 V 25 38 31
CLK RCO
CL = 50 pF
6 V 21 32 26
tpd
CL = 15 pF 5 V 10
ns
tpd 2 V 210 315 265 ns
CLK
MAX/MIN
C
L
= 50 pF 4.5 V 42 63 53
CLK MAX/MIN
CL = 50 pF
6 V 36 54 45
CL = 15 pF 5 V 18
2 V 150 225 190
D/U
RCO
C
L
= 50 pF 4.5 V 30 45 38
D/U RCO
CL = 50 pF
6 V 26 38 33
CL = 15 pF 5 V 12
2 V 165 250 205
D/U
MAX/MIN
C
L
= 50 pF 4.5 V 33 50 41
D/U MAX/MIN
CL = 50 pF
6 V 28 43 35
CL = 15 pF 5 V 13
2 V 125 190 155
CTEN
RCO
C
L
= 50 pF 4.5 V 25 38 31
CTEN RCO
CL = 50 pF
6 V 21 32 26
CL = 15 pF 5 V 10
2 V 75 110 95
t
t
Any C
L
= 50 pF 4.5 V 15 22 19 ns
tt
Any
CL = 50 pF
6 V 13 19 16
ns
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HCT191
timing requirements over recommended operating free-air temperature range VCC = 4.5 V (unless
otherwise noted) (see Figure 5)
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 30 20 25 MHz
tw
Pulse duration
LOAD low 16 24 20
ns
twPulse duration CLK high or low 20 30 25 ns
Data before LOAD↑12 18 15
t
su
Setup time CTEN before CLK↑12 18 15 ns
tsu
Setup time
D/U before CLK↑18 27 23
ns
Data before LOAD↑222
thHold time CTEN before CLK↑222ns
th
Hold time
D/U before CLK↑000
ns
trec Recovery time LOAD inactive before CLK↑12 18 15 ns
’HCT191
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 4.5 V 30 20 25 MHz
LOAD
Q
CL = 50 pF 4.5 V 40 60 50
LOAD QCL = 15 pF 5 V 17
A, B, C,
Q
CL = 50 pF 4.5 V 38 57 48
A, B, C,
or D QCL = 15 pF 5 V 16
CLK
RCO
CL = 50 pF 4.5 V 35 53 44
CLK RCO CL = 15 pF 5 V 14
CLK
Q
CL = 50 pF 4.5 V 27 41 34
tpd
CLK Q CL = 15 pF 5 V 11
ns
tpd
CLK
MAX/MIN
CL = 50 pF 4.5 V 42 63 53 ns
CLK MAX/MIN CL = 15 pF 5 V 18
D/U
RCO
CL = 50 pF 4.5 V 30 45 38
D/U RCO CL = 15 pF 5 V 12
D/U
MAX/MIN
CL = 50 pF 4.5 V 38 57 48
D/U MAX/MIN CL = 15 pF 5 V 16
CTEN
RCO
CL = 50 pF 4.5 V 27 41 34
CTEN RCO CL = 15 pF 5 V 11
ttAny CL = 50 pF 4.5 V 15 22 19 ns
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TYP UNIT
’HC190 59
Cpd Power dissipation capacitance ’HC191 55 pF
Cpd
Power dissipation capacitance
’HCT191 68
pF
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION − ’HC190, ’HC191
Test
Point
From Output
Under TestCL
(see Note A)
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
Open Closed
S1
Closed Open
S2
Open Closed
Closed Open
Open Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
RL = 1 kΩ
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VC
C
0 V
50% VCC 10%
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
90%
VCC
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC VCC
0 V
LOAD
Input
CLK 50% VCC VCC
trec
0 V
Figure 4. Load Circuit and Voltage Waveforms
 
   
      
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION − ’HCT191
Test
Point
From Output
Under Test
CL
(see Note A)
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
Open Closed
S1
Closed Open
S2
Open Closed
Closed Open
Open Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
RL = 1 kΩ
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VC
C
0 V
50% VCC 10%
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
90%
VCC
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC VCC
0 V
LOAD
Input
CLK 50% VCC VCC
trec
0 V
Figure 5. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8867101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8867101EA
CD54HCT191F3A
5962-8994601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8994601EA
CD54HC190F3A
CD54HC190F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8994601EA
CD54HC190F3A
CD54HC191F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8689101EA
CD54HC191F3A
CD54HCT191F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8867101EA
CD54HCT191F3A
CD74HC190E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC190E
CD74HC190EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC190E
CD74HC190NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC190M
CD74HC190NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC190M
CD74HC190NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC190M
CD74HC190PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC190PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC190PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ190
CD74HC191E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC191E
CD74HC191EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC191E
CD74HC191M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HC191MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC191M
CD74HCT191E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT191E
CD74HCT191EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT191E
CD74HCT191M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT191M
CD74HCT191ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT191M
CD74HCT191MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT191M
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC190, CD54HC191, CD54HCT191, CD74HC190, CD74HC191, CD74HCT191 :
•Catalog: CD74HC190, CD74HC191, CD74HCT191
•Military: CD54HC190, CD54HC191, CD54HCT191
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC190NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC190PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC190PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC191M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC190NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC190PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC190PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HC191M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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