U62H824 Fast 8K x 24 SRAM Features Description ! 196 608 bit static CMOS RAM ! 35 ns Access Time ! Fully static Read and Write The U62H824 is a static RAM manufactured using a CMOS process technology. The device integrates an 8K x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56k Digital Signal Processor Family and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic. The avialability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple devices are used. With either chip enable unasserted, the device will enter standby mode, useful in low-power applications. A single on-chip multiplexer selects A12 or X/Y as the highest order address input depending upon the state of the V/S control input. This feature operations ! Equal address and chip enable access times ! Single bit on-chip address multiplexer ! Active high and active low chip enable inputs ! Output enable controlled three! ! ! ! ! ! ! ! state outputs TTL/CMOS-compatible Low power standby mode Power supply voltage 5 V Operating temperature range 0 to 70 C -40 to 85 C -40 to 125 C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 100 mA Package: PLCC52 A5 A4 A3 2 A2 3 A1 4 A0 NC 5 VCC V/S 6 X/Y 7 Pin Description A12 A10 A11 Pin Configuration allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically repartitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. An application example is at the end of this document for additional information. Multiple power and ground pins have been utilized to minimize effectes induced by output noice. 1 52 51 50 49 48 47 DQ0 8 46 DQ23 Signal Name Signal Description DQ1 9 10 45 44 DQ22 11 43 DQ4 12 13 42 41 A0 - A11 A12, X/Y V/S DQ0 - DQ23 DQ5 14 40 DQ18 DQ6 15 39 DQ17 DQ7 DQ8 16 38 17 18 19 37 36 35 DQ16 DQ15 Address Inputs Multiplexed Address Address Multiplexer Control Data Input / Output Chip Enable Output Enable Write Enable Power Supply Voltage Ground Not Connected November 26, 2002 34 DQ21 VSS DQ20 DQ19 VSS DQ14 E1, E2 G W VCC VSS NC DQ13 For proper operation of the device, all VSS pins must be connected to ground. DQ12 W NC E1 E2 VSS VCC G A6 21 22 23 24 25 26 27 28 29 30 31 32 33 A7 20 DQ11 DQ9 DQ10 A8 VSS A9 DQ2 VSS DQ3 1 U62H824 Block Diagram A0 Row A5 Decoder Memory Cell VCC Array VSS 256 Rows x A10 768 Columns A11 DQ0 Input Data Column I/O Control DQ23 E1 E2 & W G Column Decoder V/S & X/Y A12 & A12i 1 0 Q 2 to 1 MUX A6 A9 (LSB) (MSB) Truth Table Mode E1 E2 G W V/S Supply Current I/O Status Not Selected H * * * * ICC(SB) High - Z Not Selected * L * * * ICC(SB) High - Z Output Disable L H H H * ICC(OP) High - Z Read Using X/Y L H L H H ICC(OP) Data Out Read Using A12 L H L H L ICC(OP) Data Out Write Using X/Y L H * L H ICC(OP) Data In Write Using A12 L H * L L ICC(OP) Data In * H or L 2 November 26, 2002 U62H824 Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.5 VCC + 0.5 b V Output Voltage VO -0.5 VCC + 0.5 b V Power Dissipation PD - 1.75 W Ta 0 -40 -40 70 85 125 C C C Storage Temperature Tstg -65 150 C Output Short-Circuit Current at VCC = 5 V and VO = 0 V c |IOS| 20 mA Power Supply Voltage Operating Temperature a b c d C-Type K-Type A-Type Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Symbol Power Supply Voltage Conditions Min. Max. Unit VCC 4.5 5.5 V Input Low Voltage d VIL -0.3 0.8 V Input High Voltage VIH 2.2 VCC + 0.3 V -2 V at Pulse Width 10 ns November 26, 2002 3 U62H824 Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Symbol ICC(OP) ICC(SB) Conditions VCC VE1 VE2 VG other inputs Iout tcW C/K-Type A-Type = = = = = = = VCC VE1 VE2 all inputs = 5.5 V = V CC - 0.2 V = 0.2 V VCC - 0.2 V or 0.2 V Min. ICC(SB)1 Output High Voltage VOH Output Low Voltage VOL Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ VCC VE1 VE2 all inputs = = = = VCC IOH IOL = 4.5 V = -4.0 mA = 8.0 mA VCC VIH VIL = 5.5 V = 5.5 V = 0 V VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V VCC VOH VOL VG = 5.5 V = 5.5 V = 0 V = VIH 4 Unit 170 180 mA mA 6 8 10 mA mA mA 15 mA 5.5 V 0.8 V 2.2 V 2.2 V VIL or VIH 0 mA 35 ns C-Type K-Type A-Type Supply Current - Standby Mode (TTL level) Max. 5.5 V 2.2 V 0.8 V VIH or VIL 2.4 V 0.4 V 2 A A -2 -4 8 mA 2 -2 mA A A November 26, 2002 U62H824 Symbol 35 Switching Characteristics Read Cycle Alt. IEC Min. Read Cycle Time tRC tcR 35 Address Access Time to Data Valid tAA ta(A) 35 ta(VS) 35 MUX Control to Data Valid Max. Unit ns ns Chip Enable Access Time to Data Valid tACE ta(E) 35 ns G LOW to Data Valid tOE ta(G) 15 ns Output Hold Time from Address Change tOH tv(A) 5 ns tv(VS) 5 ns Output Hold Time from MUX Control Change E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 0 ns G LOW to Output in Low-Z tLZOE ten(G) 0 ns E1 HIGH or E2 LOW to Output in High-Z tHZCE tdis(E) 15 ns G HIGH to Output in High-Z tHZOE tdis(G) 15 ns Switching Characteristics Write Cycle Symbol 35 IEC Min. Write Cycle Time tWC tcW 35 ns Write Pulse Width tWP tw(W) 20 ns Write Pulse Width Setup Time tWP tsu(W) 20 ns Address Setup Time tAS tsu(A) 0 ns tsu(VS) 0 ns tsu(A-WH) 30 ns tsu(VS-WH) 30 ns Adress Valid to End of Write tsu(A-E) 30 ns MUX Control Valid to End of Write tsu(VS-E) 30 ns MUX Control Setup Time Address Valid to End of Write tAW MUX Control Valid to End of Write Max. Unit Alt. Chip Enable Setup Time tCW tsu(E) 20 ns Pulse Width Chip Enable tCW tw(E) 20 ns Data Setup Time tDS tsu(D) 15 ns Data Hold Time tDH th(D) 0 ns Address Hold from End of Write tAH th(A) 0 ns th(VS) 0 ns 5 ns MUX Control from End of Write W HIGH to Output in Low-Z tLZWE ten(W) W LOW to Output in High-Z tHZWE tdis(W) November 26, 2002 5 15 ns U62H824 VCC DQ0 DQ23 X/Y E1 E2 W G V/S ment of all 24 output pins VIL A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Simultaneous measure- VIH relevant test measurement Input level according to the Test Configuration for Functional Check VO Output Load see Figure 1A Unless Otherwise Noted VSS AC Test Loads 5V 480 R L = 50 Output Output Z0 = 50 5 pF 255 VL = 1.5 V Figure 1A Figure 1B Measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) with Output Load from Figure 1B. 6 November 26, 2002 U62H824 Capacitance Input Capacitance Output Capacitance Conditions VCC VI f Ta Symbol = 5.0 V = VSS = 1 MHz = 25 C Min. Max. Unit CI 6 pF C0 8 pF All pins not under test must be connected with ground by capacitors. IC Code Numbers Example U62H824 P K 35 Internal Code Type Access Time 35 = 35 ns Operating Temperature Range C = 0 to 70 C K = -40 to 85 C A = -40 to 125 C Package P = PLCC52 The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. November 26, 2002 7 U62H824 Read Cycle 1: Ai- or V/S-controlled (during Read Cycle: E1 = G = VIL, E2 = W = VIH) tcR Ai DQi Output Address Valid ta(A) Previous Data Valid Output Data Valid tv(A) tcR V/S DQi Output MUX Control Valid ta(VS) Output Data Valid Previous Data Valid tv(VS) Read Cycle 2: E-, G-controlled (during Read Cycle: W = VIH) E1 in the timing diagrams represents both E1 and E2 with E1 asserted Low and E2 asserted High. tcR Ai Address Valid V/S E1 ten(E) tdis(E) ta(G) G DQi MUX Control Valid ta(E) ten(G) tdis(G) High-Z Output Data Output 8 High-Z November 26, 2002 U62H824 Write Cycle1: W-controlled E1 in the timing diagram represents both E1 and E2 with E1 asserted Low and E2 asserted High. tcW Ai Address Valid th(A) tsu(VS-WH) V/S MUX Control Valid tsu(E) tsu(VS) th(VS) E1 tsu(A-WH) W tw(W) tsu(A) th(D) tsu(D) DQi Input Data Valid Input tdis(W) DQi ten(W) High-Z Output G Write Cycle 2: E-controlled E1 in the timing diagram represents both E1 and E2 with E1 asserted Low and E2 asserted High. tcW Ai Address Valid th(A) tsu(A-E) tsu(A) V/S MUX Control Valid E1 tsu(VS-E) tw(E) tsu(VS) th(VS) tsu(W) W tsu(D) DQi Input ten(E) th(D) Input Data Valid tdis(W) DQi High-Z Output G undefined November 26, 2002 L- to H-level H- to L-level 9 U62H824 Application Example DSP SRAM DSP56k U62H824 D[0 ... 23] DQ[0 ... 23] A[0 ... 10] A[0 ... 10] A11 DS PS X/Y A15 A14 DSP P: P: X: Y: 4000 ... 47FF 4800 ... 4FFF 4000 ... 4700 4000 ... 47FF A12 A11 V/S X/Y E1 E2 2k P: 2k X: 2k P: 2k Y: 1FFF 1800 17FF 1000 0FFF 0800 07FF 0000 SRAM 0800 ... 0FFF 1800 ... 1FFF 1000 ... 17FF 0000 ... 07FF No memory overlap with internal P-, X-, Y-memorys. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. 10 November 26, 2002 U62H824 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. November 26, 2002 Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de