A major emphasis in Honeywell’s packaging program is the
use of multichip modules (MCMs). Use of multichip mod-
ules will result in higher density packaging of integrated
circuits (ICs) and components, lower weight and volume
associated with size reduction, higher performance due to
a decrease in interconnect length, and additional improve-
ment with new material systems. Honeywell has had a
leading role in the development and application of space
qualified multichip modules for the last 14 years. In con-
junction with the basic technology, we have also developed
the necessary tools and methodology for the design of
MCMs, Known Good Die (KGD) testing, materials/pro-
cesses for assembly of MCMs, and test capability for MIL
STD and QML screening.
The 5M Memory Module is organized into two separate
64K x 40 memory banks. Each memory bank contains two
32K x 40 blocks, using five SRAMs each. The two banks
of memory are connected to different busses, making
Military & Space Products
5 MEGABIT MEMORY MODULE HX84050
OTHER
• Listed on SMD #5962-96840
• Read/Write Cycle Times
≤ 20 ns (Typical)
≤ 30 ns (-55 to 125°C)
• Asynchronous Operation
• CMOS Compatible I/O
• Single 5 V ± 10% Power Supply
• Low Operating Power
• 200-Lead Quad Flat Pack (2.1 in. x 2.1 in.)
GENERAL DESCRIPTION
RADIATION
• Fabricated with RICMOS™ IV Silicon on Insulator
(SOI) 0.75 µm Process (Leff = 0.6 µm)
• Total Dose Hardness through 1x106 rad (SiO2)
• Neutron Hardness through 1x1014 cm-2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad (Si)/s
• Dose Rate Survivability through 1x1011 rad(Si)/s
• Soft Error Rate of <1x10-10 Upsets/bit-day
in Geosynchronous Orbit
• No Latchup
them logically and physically separate within each bank.
Only one block is enabled and consuming power at any
given time. The die are packaged in a 200-pin 2.1" x 2.1" co-
fired substrate ceramic flat package.
HX84050
2
NCS
A:3-7,12,14-16
CE
NWE
NOE
WE • CS • CE
NWE • CS • CE • OE
Column Decoder
Data Input/Output
Row
Decoder
32,768 x 8
Memory
Array
A:0-2, 8-11, 13
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
8
DQ:0-7
(0 = high Z)
•
•
•
• • •
8
8
9
Figure 2. 32K x 40 Memory Block Functional Diagram
Figure 3. 32K x 8 SRAM Functional Diagram
FUNCTIONAL DIAGRAMS
Figure 1. 2 x 64K x 40 (Top Level Diagram)
I_DATA(39:0)
32Kx8
Die
32Kx8
Die
I_Address(14:0)
I_NOE
I_NWE
I_CE0
I_NCS0
I_CE1
I_NCS1
}
64K x 40 Memory Bank I
32K x 40 Memory Block 0
32K x 40 Memory Block 1
D_DATA(39:0)
32Kx8
Die
32Kx8
Die
D_Address(14:0)
D_NOE
D_NWE
D_CE0
D_NCS0
D_CE1
D_NCS1
}
32K x 40 Memory Block 0
32K x 40 Memory Block 1
64K x 40 Memory Bank D
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CE
NCS
NWE
NOE
U1
32Kx8 Memory
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U2
32Kx8 Memory
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U3
32Kx8 Memory
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U4
32Kx8 Memory
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U5
32Kx8 Memory
ADDRESS (14 : 0)
DATA (39 : 0)
I_CE0
I_NCS0
I_NWE
I_NOE
BANK I, BLOCK 0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CE
NCS
NWE
NOE
CE
NCS
NWE
NOE
CE
NCS
NWE
NOE
CE
NCS
NWE
NOE
HX84050
3
CE NCS NWE NOE MODE DQ
H L H L Read Data Out
H L L X Write Data In
X H XX XX Deselected High Z
L X XX XX Disabled High Z
TRUTH TABLE
Notes:X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
SIGNAL DEFINITIONS
Signal definitions for an individual SRAM within the five chip 32K x 40 memory block are shown below.
A: 0 - 14 Address input pins (A) which select a particular eight bit word within the memory array.
A: 0-3 (Column Select)
A: 4-11 (Row Select)
A: 12-14 (Block Select)
DQ: 0 - 7 Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS Negative chip select, when at a low level, allows normal read or write operation. When at a high level it
defaults the SRAM to a pre-charge condition and holds the data output drivers in a high impedance state.
All input signals except NCS and CE are disabled. The dynamic and DC IDD chip current contribution from
all other input circuits caused by input pins transitioning and/or at VDD or VSS is eliminated. If the NCS signal
is not used it must be connected to VSS.
NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level it allows normal read operation.
NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If the NOE signal is not used
it must be connected to VSS.
CE Chip enable, when at a high level, allows normal operation. When at a low level it forces the array to a pre-
charge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except CE and NCS. The dynamic and DC IDD chip current contribution from all other input circuits caused
by input pins transitioning and/or not at VDD or VSS levels is eliminated. If the CE signal is not used it must
be connected to VDD.
HX84050
4
Total Dose ≥1x106rad(SiO2)
Transient Dose Rate Upset ≥1x109rad(Si)/s
Transient Dose Rate Survivability ≥1x1011 rad(Si)/s
Soft Error Rate <1x10-10 upsets/bit-day
Neutron Fluence ≥1x1014 N/cm2
Parameter Limits (2) Test Conditions
RADIATION HARDNESS RATINGS (1)
Total Ionizing Radiation Dose
The memory module will meet all stated functional and
electrical specifications over the entire operating tempera-
ture range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will re-
main within specifications after rebound at VDD = 5.5 V
and T =125°C extrapolated to ten years of operation. Total
dose hardness is assured by wafer level testing of process
monitor transistors and RAM product using 10 KeV X-ray
and Co60 radiation sources. Transistor gate threshold shift
correlations have been made between 10 KeV X-rays
applied at a dose rate of 1x105 rad(SiO2)/min at T = 25°C
and gamma rays (Cobalt 60 source) to ensure that wafer
level X-ray testing is consistent with standard military
radiation test environments.
Transient Pulse Ionizing Radiation
The memory module is capable of writing, reading, and
retaining stored data during and after exposure to a tran-
sient ionizing radiation pulse, up to the transient dose rate
upset specification, when applied under recommended
operating conditions.
The memory module will meet any functional or electrical
specification after exposure to the transient dose rate
survivability specification, when applied under recom-
mended operating conditions. Note that the current con-
ducted during the pulse by the RAM inputs, outputs, and
power supply may significantly exceed the normal operat-
ing levels. The application design must accommodate
these effects.
Neutron Radiation
The memory module will meet any functional or timing
specification after exposure to the specified neutron flu-
ence under recommended operating or storage conditions.
This assumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
The memory module is immune to Single Event Upsets
(SEU) to the specified Soft Error Rate (SER), under recom-
mended operating conditions. This hardness level is de-
fined by the Adams 90% worst case cosmic ray environ-
ment for geosynchronous orbits.
Latchup
The memory module will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the SIMOX
substrate material provides oxide isolation between adja-
cent PMOS and NMOS transistors and eliminates any
potential SCR latchup structures. Sufficient transistor body
tie connections to the p- and n-channel substrates are made
to ensure no source/drain snapback occurs.
Units
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
Adams 90% worst case
environment, VDD=4.5V
Pulse width ≤50 ns, X-ray,
VDD=6.0 V, TA=25°C
Pulse width ≤1µs
TA=25°C, VDD=5.5V.
X-ray or Co60
1 MeV equivalent energy,
Unbiased, TA=25°C
RADIATION CHARACTERISTICS
HX84050
5
CAPACITANCE (1)
CIN1 Input Capacitance for CE and NCS Inputs 50 pF VIN=VDD or VSS, f=1 MHz
CIN2 Input Capacitance for Address 70 pF VIN=VDD or VSS, f=1 MHz
NOE and NWE Inputs
COUT Output Capacitance 26 pF VIN=VDD or VSS, f=1 MHz
Parameter Max
Min
Symbol Test Conditions
Worst Case Units
(1) This parameter is tested during initial design characterization only.
(2) Worst case operating conditions: TA= -55°C to +125°C, past total dose at 25°C.
ABSOLUTE MAXIMUM RATINGS (1)
VDD Supply Voltage Range (2) -0.5 6.5 V
VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V
VOZ Output Voltage Applied to High Z State (VIN and VOUT) -0.3 VDD+0.3 V
TSTORE Storage Temperature (Zero Bias) -65 150 °C
TSOLDER Soldering Temperature (10 sec) +288 °C
PD Maximum Power Dissipation (3) 5.6 W
IOUT DC or Average Output Current 25 mA
VPROT ESD Input Protection Voltage 2000 V
ΘJC Thermal Resistance (Jct-to-Case) (4) 4.0 °C/W
TJ Junction Temperature 175 °C
Parameter
Symbol Units
MaxMin
Rating
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) All voltages are referenced to VSS (VSS = ground) unless otherwise specified.
(3) Maximum power dissipation with 20 chips utilized at 50 percent (each bank is maximally utilized, alternating between blocks).
(4) Assumes a uniform temperature on the bottom surface of the package, and a uniform power distribution over the top surface of the die and all
die at equal power level.
RECOMMENDED OPERATING CONDITIONS
Symbol MaxTyp
Description
Parameter Min Units
VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V
TAC Case Operating Temperature -55 25 125 °C
VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V
HX84050
6
TAVAVR Address Read Cycle Time 20 30 ns
TAVQV Address Access Time 17 26 ns
TAVQX Address Change to Output Invalid Time 3 ns
TSLQV Chip Select Access Time 30 ns
TSLQX Chip Select Output Enable Time 5 ns
TSHQZ Chip Select Output Disable Time 16 ns
TEHQV Chip Enable Access Time 30 ns
TEHQX Chip Enable Output Enable Time 5 ns
TELQZ Chip Enable Output Disable Time 16 ns
TGLQV Output Enable Access Time 13 ns
TGLQX Output Enable Output Enable Time 0 ns
TGHQZ Output Enable Output Disable Time 16 ns
READ CYCLE AC TIMING CHARACTERISTICS (1)
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels
shown in the Tester AC Timing Characteristics table, capacitive output loading CL>50 pF, or equivalent capacitive output loading CL=5 pF for
TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C.
Worst Case (3)
HIGH
IMPEDANCE
NCS
NOE
DATA VALID
CE
TAVAVR
TAVQV TAXQX
TSLQV
TSLQX TSHQZ
TEHQX
TEHQV
TGLQX
TGLQV TGHQZ
TELQZ
ADDRESS
(NWE = high)
DATA OUT
Symbol Parameter Typical -55 to 125°C Units
(2) Min Max
(1)
HX84050
7
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Symbol Parameter Typical -55 to 125°C Units
(2) Min Max
Worst Case (3)
TAVAVW Write Cycle Time 20 30 ns
TWLWH Write Enable Write Pulse Width 12 20 ns
TSLWH Chip Select to End of Write Time 25 ns
TDVWH Data Valid to End of Write Time 20 ns
TAVWH Address Valid to End of Write Time 25 ns
TWHDX Data Hold Time after End of Write Time 1 ns
TAVWL Address Valid Setup to Start of Write Time 5 ns
TWHAX Address Valid Hold after End of Write Time 0 ns
TWLQZ Write Enable to Output Disable Time 16 ns
TWHQX Write Disable to Output Enable Time 5 ns
TWHWL Write Disable to Write Enable Pulse Width 6 ns
TEHWH Chip Enable to End of Write Time 25 ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels
shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
ADDRESS
HIGH
IMPEDANCE
DATA OUT
NWE
DATA IN
DATA VALID
T
AVAVW
NCS
CE
T
AVWH
T
WLWH
T
AVWL
T
WLQZ
T
DVWH
T
WHQX
T
WHDX
T
SLWH
T
EHWH
T
WHAX
T
WHWL
(1)
HX84050
8
DC ELECTRICAL CHARACTERISTICS
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) Tested at die level test, not in MCM.
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1CCItnerruCylppuSgnitarepO052525Am
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2CCI)detceleseD(tnerruCylppuS203Am
zHM02=f,V5.5=EWN=EC=EON=SCN=DDV
3CCI)ybdnatS(tnerruCylppuS203Am
zHM0.0=f,V5.5=EC=SCN=DDV
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zHM02=f,V0=EC=SCN,V5.5=DDV
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zHM0.0=f,V0=EC=SCN,V5.5=DDV
6CCItnerruCnoitneteRataD01Am
V5.2=EWN=EC=EON=SCN=DDV
LIIwoL,tnerruCtupnI05-05+Aµ
V0=LIV=SCN,V5.5=EWN=EC=EON=DDV
HIIhgiH,tnerruCtupnI05-05+Aµ
V0=EWN=EON=SCN,V5.5=HIV=EC=DDV
LZOIwoL,tnerruCegakaeLtuptuO05-05+Aµ
V0=HOV=SCNV5.5=EWN=EC=EON=DDV
HZOIhgiH,tnerruCegakaeLtuptuO05-05+Aµ
0=EWN=SCN,V5.5=HOV=EC=EON=DDV
LIV)SOMC(egnaRegatloVtupnIleveLwoL3.0-Vx3.0
DD
V
)3(V5.4=DDV
HIV)SOMC(egnaRegatloVtupnIleveLhgiHVx7.0
DD
V
DD
3.0+V
)3(V5.5=DDV
LOVegataloVwoLtuptuO4.0V
Am01=LOI,0=EON=SCN,V5.4=EWN=EC=DDV
HOVegatloVhgiHtuptuO2.4V
Am5-=HOI,0=EON=SCN,V5.4=EWN=EC=DDV
DUT
output Valid low
output
Vref1
CL>50 pF*
249
Tester Equivalent Load Circuit
2.9 V Valid high
output
Vref2
-
+
-
+
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
HX84050
9
Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write
enable (NWE) must be high. The output drivers can be
controlled independently by the NOE signal. Consecutive
read cycles can be executed with NCS held continuously
low, and with CE held continuously high, and toggling the
addresses.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between ad-
dress edge transitions is permissible; however, data outputs
will become valid TAVQV time following the latest occurring
address edge transition. The minimum address activated
read cycle time is TAVAV. When the RAM is operated at the
minimum address activated read cycle time, the data out-
puts will remain valid on the RAM I/O until TAXQX time
following the next sequential address transition.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS, however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can occur
later than the specified setup times to CE; however, the
valid data access time will be delayed. Any address edge
transition which occurs during the time when CE is high will
initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TELQZ time following a disabling CE edge transition.
DYNAMIC ELECTRICAL CHARACTERISTICS
Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. NCS
differs from CE in that it does not disable the input buffers;
however, both CE and NCS fully disable the RAM decode
logic for power savings. Only the NWE controlled mode is
shown in the table and diagram on the previous page for
simplicity; however, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.
To write data into the RAM, NWE and NCS must be held low
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tive write operations, write pulses must be separated by the
minimum specified TWHWL/TSHSL/TELEH time. Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
HX84050
10
TESTER AC TIMING CHARACTERISTICS
QUALITY AND RADIATION HARDNESS
ASSURANCE
Honeywell maintains a high level of product integrity through
process control, utilizing statistical process control, a com-
plete “Total Quality Assurance System,” a computer data
base process performance tracking system, and a radia-
tion hardness assurance strategy.
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiating
test structures as well as SRAM product, and then monitor-
ing key parameters which are sensitive to ionizing radia-
tion. Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and con-
tinuing through product qualification and screening.
SCREENING LEVELS
Honeywell offers several levels of device screening to meet
your system needs. “Engineering Devices” are available
with varying degrees of limited performance and screening
for breadboarding and/or evaluation testing. Hi-Rel Level B
and S devices undergo additional screening per the require-
ments of MIL-STD-883. As a QML supplier, Honeywell also
offers QML Class Q and V devices per MIL-PRF-38535 and
are available per the applicable Standard Microcircuits
Drawing (SMD). QML devices offer ease of procurement by
eliminating the need to create detailed specifications and
offer benefits of improved quality and cost savings through
standardization.
RELIABILITY
Honeywell understands the stringent reliability requirements
that space and defense systems require and has extensive
experience in reliability testing on programs of this nature.
This experience is derived from comprehensive testing of
VLSI processes. Reliability attributes of the RICMOS
™
pro-
cess were characterized by testing specially designed irradi-
ated and non-irradiated test structures from which specific
failure mechanisms were evaluated. These specific mecha-
nisms included, but were not limited to, hot carriers, elec-
tromigration and time dependent dielectric breakdown. This
data was then used to make changes to the design models
and process to ensure more reliable products.
In addition, the reliability of the RICMOS™ process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is qualified
by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
Input
Levels*
Output
Sense
Levels
CMOS I/O Configuration
* Input rise and fall times <1 ns/V
VDD-0.5 V
0.5 V VDD/2
VDD/2
0.4 V High Z
3.4 V
2.4 V
High Z
High Z = 2.9V
VDD-0.4V
HX84050
11
PACKAGING
The memory MCM is offered in a custom 200-lead ceramic
quad flat pack. The package is constructed of multilayer
ceramic (Al
2
O
3
) and features internal power and ground
planes.
Ceramic chip capacitors (20) are mounted inside the pack-
age to maximize supply noise decoupling and avoid ground
bounce. These capacitors effectively attach to the internal
package power and ground planes. This design minimizes
resistance and inductance of the bond wire and package,
both of which are critical in a transient radiation environment.
200-LEAD QUAD FLAT PACK PIN LIST
Pin Si gnal Name Pi n Type Pin Si gnal Name Pin Type Pin Signal Name Pin Type Pin Signal Name Pin Type Pin Signal Name Pin Type
1 VSS Pwr/Gnd 41 D_DATA(08) Tri–State 81 D_DATA(22) Tri–State 121 D_DATA(38) Tri–State 161 I_DATA(27) Tri–State
2 I_ADRS(04) Input 42 D_DATA(09) Tri–State 82 VSS Pwr/Gnd 122 D_DATA(39) Tri–State 162 VDD Pwr/Gnd
3 I_ADRS(03) Input 43 D_ADRS(00) Input 83 VDD Pwr/Gnd 123 D_NCS0 Input 163 VSS Pwr/Gnd
4 I_ADRS(02) Input 44 VSS Pwr/Gnd 84 D_DATA(23) Tri–State 124 VDD Pwr/Gnd 164 I_DATA(26) Tri–State
5 I_ADRS(01) Input 45 VDD Pwr/Gnd 85 D_DATA(24) Tri–State 125 VSS Pwr/Gnd 165 I_DATA(25) Tri–State
6 VDD Pwr/Gnd 46 D_ADRS(01) Input 86 D_DATA(25) Tri–State 126 VSS Pwr/Gnd 166 I_DATA(24) Tri–State
7 VSS Pwr/Gnd 47 D_ADRS(02) Input 87 D_DATA(26) Tri–State 127 VDD Pwr/Gnd 167 I_DATA(23) Tri–State
8 I_ADRS(00) Input 48 D_ADRS(03) Input 88 VSS Pwr/Gnd 128 D_NCS0 Input 168 VDD Pwr/Gnd
9 I_DATA(09) Tri–State 49 D_ADRS(04) Input 89 VDD Pwr/Gnd 129 I_DATA(39) Tri–State 169 VSS Pwr/Gnd
10 I_DATA(08) Tri–State 50 VSS Pwr/Gnd 90 D_DATA(27) Tri–State 130 I_DATA(38) Tri–State 170 I_DATA(22) Tri–State
11 I_DATA(07) Tri–State 51 VSS Pwr/Gnd 91 D_DATA(28) Tri–State 131 I_DATA(37) Tri–State 171 I_DATA(21) Tri–State
12 VDD Pwr/Gnd 52 VDD Pwr/Gnd 92 D_DATA(29) Tri–State 132 VSS Pwr/Gnd 172 I_DATA(20) Tri–State
13 VSS Pwr/Gnd 53 D_ADRS(05) Input 93 D_ADRS(09) Input 133 VDD Pwr/Gnd 173 I_NOE Input
14 I_DATA(06) Tri–State 54 D_ADRS(06) Input 94 VSS Pwr/Gnd 134 I_DATA(36) Tri–State 174 VDD Pwr/Gnd
15 I_DATA(05) Tri–State 55 D_ADRS(07) Input 95 VDD Pwr/Gnd 135 I_DATA(35) Tri–State 175 VSS Pwr/Gnd
16 I_DATA(04) Tri–State 56 VDD Pwr/Gnd 96 D_ADRS(10) Input 136 I_DATA(34) Tri–State 176 VSS Pwr/Gnd
17 I_DATA(03) Tri–State 57 VSS Pwr/Gnd 97 D_ADRS(11) Input 137 I_DATA(33) Tri–State 177 VDD Pwr/Gnd
18 VDD Pwr/Gnd 58 D_ADRS(08) Input 98 D_ADRS(12) Input 138 VSS Pwr/Gnd 178 I_NWE Input
19 VSS Pwr/Gnd 59 D_DATA(10) Tri–State 99 VDD Pwr/Gnd 139 VDD Pwr/Gnd 179 I_DATA(19) Tri–State
20 I_DATA(02) Tri–State 60 D_DATA(11) Tri–State 100 VSS Pwr/Gnd 140 I_DATA(32) Tri–State 180 I_DATA(18) Tri–State
21 I_DATA(01) Tri–State 61 D_DATA(12) Tri–State 101 VSS Pwr/Gnd 141 I_DATA(31) Tri–State 181 I_DATA(17) Tri–State
22 I_DATA(00) Tri–State 62 VDD Pwr/Gnd 102 VDD Pwr/Gnd 142 I_DATA(30) Tri–State 182 VSS Pwr/Gnd
23 I_NCS1 Input 63 VSS Pwr/Gnd 103 D_CE0 Input 143 I_ADRS(14) Input 183 VDD Pwr/Gnd
24 VDD Pwr/Gnd 64 D_DATA(13) Tri–State 104 D_CE1 Input 144 VSS Pwr/Gnd 184 I_DATA(16) Tri–State
25 VSS Pwr/Gnd 65 D_DATA(14) Tri–State 105 D_ADRS(13) Input 145 VDD Pwr/Gnd 185 I_DATA(15) Tri–State
26 VSS Pwr/Gnd 66 D_DATA(15) Tri–State 106 VDD Pwr/Gnd 146 I_ADRS(13) Input 186 I_DATA(14) Tri–State
27 VDD Pwr/Gnd 67 D_DATA(16) Tri–State 107 VSS Pwr/Gnd 147 I_CE1 Input 187 I_DATA(13) Tri–State
28 D_NCS1 Input 68 VDD Pwr/Gnd 108 D_ADRS(14) Input 148 I_CE0 Input 188 VSS Pwr/Gnd
29 D_DATA(00) Tri–State 69 VSS Pwr/Gnd 109 D_DATA(30) Tri–State 149 VDD Pwr/Gnd 189 VDD Pwr/Gnd
30 D_DATA(01) Tri–State 70 D_DATA(17) Tri–State 110 D_DATA(31) Tri–State 150 VSS Pwr/Gnd 190 I_DATA(12) Tri–State
31 D_DATA(02) Tri–State 71 D_DATA(18) Tri–State 111 D_DATA(32) Tri–State 151 VSS Pwr/Gnd 191 I_DATA(11) Tri–State
32 VSS Pwr/Gnd 72 D_DATA(19) Tri–State 112 VDD Pwr/Gnd 152 VDD Pwr/Gnd 192 I_DATA(10) Tri–State
33 VDD Pwr/Gnd 73 D_NWE Input 113 VSS Pwr/Gnd 153 I_ADRS(12) Input 193 I_ADRS(08) Input
34 D_DATA(03) Tri–State 74 VDD Pwr/Gnd 114 D_DATA(33) Tri–State 154 I_ADRS(11) Input 194 VSS Pwr/Gnd
35 D_DATA(04) Tri–State 75 VSS Pwr/Gnd 115 D_DATA(34) Tri–State 155 I_ADRS(10) Input 195 VDD Pwr/Gnd
36 D_DATA(05) Tri–State 76 VSS Pwr/Gnd 116 D_DATA(35) Tri–State 156 VDD Pwr/Gnd 196 I_ADRS(07) Input
37 D_DATA(06) Tri–State 77 VDD Pwr/Gnd 117 D_DATA(36) Tri–State 157 VSS Pwr/Gnd 197 I_ADRS(06) Input
38 VSS Pwr/Gnd 78 D_NOE Input 118 VDD Pwr/Gnd 158 I_ADRS(09) Input 198 I_ADRS(05) Input
39 VDD Pwr/Gnd 79 D_DATA(20) Tri–State 119 VSS Pwr/Gnd 159 I_DATA(29) Tri–State 199 VDD Pwr/Gnd
40 D_DATA(07) Tri–State 80 D_DATA(21) Tri–State 120 D_DATA(37) Tri–State 160 I_DATA(28) Tri–State 200 VSS Pwr/Gnd
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Helping You Control Your World
900172, Rev B
2/97
H
ORDERING INFORMATION (1)
SOURCE
H=HONEYWELL
(1) Orders may be faxed to 612-954-2051. For technical assistance, contact our Customer Service Department at 612-954-2888.
(2) Engineering device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
Contact Factory with other needs.
To learn more about Honeywell Solid State Electronics Center,
visit our web site at http://www.ssec.honeywell.com
200-LEAD QUAD FLAT PACK
R
TOTAL DOSE
HARDNESS
R=1x105 rad(SiO2)
F=3x105 rad(SiO2)
H=1x106rad(SiO2)
N=No Level Guaranteed
PART NUMBER
84050
X
PROCESS
X=SOI
A1
a
KOVAR
LID
CERAMIC
BODY
C
LEAD
ALLOY 42
CERAMIC
TIE BAR
Ac
• • •
• • •
• • •
1
• • •
A
A1
a
b
C
c
D
E
e
F
f
0.203 max
0.149±.015
0.035±.005
0.010 +.002 - 0.001
0.006 +.002 -0.001
0.008 REF
2.100±.021
2.100±.021
0.035
3.500±.035
0.200±.005
Dimensions in inches
F
Ef
b
(width)
e
(pitch)
D
• • •
• • •
• • •
1
• • •
S
SCREEN LEVEL
V=QML Class V
Q=QML Class Q
S=Class S
B=Class B
E=Engr Device (2)
HX84050
