ORCATM Series 3C and 3T FPGA Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line OR3C80 OR3T20 OR3T30 OR3T55 Ordering Part Number OR3C805PS208-DB OR3C804PS208-DB OR3C804PS208I-DB OR3C804BA352-DB OR3T206T144-DB OR3T207S208-DB OR3T206S208-DB OR3T206S208I-DB OR3T207BA256-DB OR3T206BA256-DB OR3T307S208-DB OR3T306S208-DB OR3T306S208I-DB OR3T307S240-DB OR3T306S240-DB OR3T306S240I-DB OR3T307BA256-DB OR3T306BA256-DB OR3T306BA256I-DB OR3T557S208-DB OR3T556S208-DB OR3T556S208I-DB OR3T557PS240-DB OR3T556PS240-DB OR3T556PS240I-DB Product Status Reference PCN Discontinued PCN#02-06 Discontinued PCN#09-10 Active / Orderable Discontinued PCN#12A-09 Active / Orderable Active / Orderable Discontinued PCN#06-07 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com Product Line OR3T55 (Cont'd) OR3T80 OR3T125 Ordering Part Number OR3T557BA256-DB OR3T556BA256-DB OR3T556BA256I-DB OR3T557BA352-DB OR3T556BA352-DB OR3T556BA352I-DB OR3T807S208-DB OR3T806S208-DB OR3T806S208I-DB OR3T807PS240-DB OR3T806PS240-DB OR3T806PS240I-DB OR3T807BA352-DB OR3T806BA352-DB OR3T806BA352I-DB OR3T807BC432-DB OR3T806BC432-DB OR3T806BC432I-DB OR3T1257PS208-DB OR3T1256PS208-DB OR3T1256PS208I-DB OR3T1257PS240-DB OR3T1256PS240-DB OR3T1256PS240I-DB OR3T1257BA352-DB OR3T1256BA352-DB OR3T1256BA352I-DB OR3T1257BC432-DB OR3T1256BC432-DB OR3T1256BC432I-DB Product Status Reference PCN Active / Orderable Discontinued PCN#09-10 Discontinued PCN#09-10 Discontinued PCN#06-07 Discontinued PCN#09-10 PCN#06-07 Discontinued PCN#09-10 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: http://www.latticesemi.com Data Sheet November 2006 SE L D E IS C C T O D N E TI VI N C U E ED S ORCA(R) Series 3C and 3T Field-Programmable Gate Arrays Features High-performance, cost-effective, 0.35 m (OR3C) and 0.3 m (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 m). Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See ORCA Series 3L FPGA documentation.) Up to 186,000 usable gates. Up to 342 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Pin selectable I/O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance on OR3Txxx devices. Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU. Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs. Fast-carry logic and routing to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU for up to 40% speed improvement. Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL*like AND-OR with optional INVERT in each programma- ble logic cell (PLC), with over 50% speed improvement typical. Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay. TTL or CMOS input levels programmable per pin for the OR3Cxx (5.0 V) devices. Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source. Built-in boundary scan (IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins. Enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any I/O. Up to four ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. StopCLK feature to glitchlessly stop/start ExpressCLKs independently by user command. Programmable I/O (PIO) has: -- Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time. -- Capability to (de)multiplex I/O signals. -- Fast access to SLIC for decodes and PAL-like functions. -- Output FF and two-signal function generator to reduce CLK to output propagation delay. -- Fast open-drain dive capability -- Capability to register 3-state enable signal. Baseline FPGA family used in Series 3+ FPSCs (field programmable system chips) which combine FPGA logic and standard cell logic on one device. * PAL is a trademark of Advanced Micro Devices, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table 1. ORCA Series 3 (3C and 3T) FPGAs Device System Gates LUTs Registers Max User RAM Max User I/Os Array Size Process Technology OR3T20 36K 1152 1872 18K 192 12 x 12 0.3 m/4 LM OR3T30 48K 1568 2436 25K 221 14 x 14 0.3 m/4 LM OR3T55 80K 2592 3780 42K 288 18 x 18 0.3 m/4 LM OR3C/3T80 116K 3872 5412 62K 342 22 x 22 0.3 m/4 LM OR3T125 186K 6272 8400 100K 342 28 x 28 0.3 m/4 LM The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table of Contents Contents Page Page PCM Detailed Programming .................................... 78 PCM Applications .................................................... 81 PCM Cautions ......................................................... 82 FPGA States of Operation........................................ 83 Initialization .............................................................. 83 Configuration ........................................................... 84 Start-Up ................................................................... 85 Reconfiguration ....................................................... 86 Partial Reconfiguration ............................................ 86 Other Configuration Options .................................... 86 Using ispLEVER to Generate Configuration RAM Data ....................................... 87 Configuration Data Frame ....................................... 87 Bit Stream Error Checking ....................................... 89 FPGA Configuration Modes...................................... 90 Master Parallel Mode ............................................... 90 Master Serial Mode ................................................. 91 Asynchronous Peripheral Mode .............................. 92 Microprocessor Interface (MPI) Mode ..................... 92 Slave Serial Mode ................................................... 95 Slave Parallel Mode ................................................. 95 Daisy-Chaining ........................................................ 96 Daisy-Chaining with Boundary Scan ....................... 97 Absolute Maximum Ratings...................................... 98 Recommended Operating Conditions ..................... 98 Electrical Characteristics .......................................... 99 Timing Characteristic Description .......................... 101 Description ............................................................. 101 PFU Timing ........................................................... 102 PLC Timing ............................................................ 109 SLIC Timing ........................................................... 109 PIO Timing ............................................................. 110 Special Function Blocks Timing ............................. 113 Clock Timing .......................................................... 121 Configuration Timing ............................................. 131 Readback Timing ................................................... 140 Input/Output Buffer Measurement Conditions ........ 141 Output Buffer Characteristics ................................. 142 OR3Cxx ................................................................. 142 OR3Txxx ................................................................ 143 Estimating Power Dissipation ................................. 144 OR3Cxx ................................................................. 144 OR3Txxx................................................................. 145 Pin Information ....................................................... 147 Pin Descriptions...................................................... 147 Package Compatibility ........................................... 151 Compatibility with OR2C/TxxA Series .................... 152 Package Thermal Characteristics........................... 188 FPGA Maximum Junction Temperature ................ 190 Package Coplanarity .............................................. 191 Package Parasitics ................................................. 191 Package Outline Diagrams..................................... 192 Lattice Semiconductor SE L D E IS C C T O D N E TI VI N C U E ED S Features ......................................................................1 System-Level Features................................................4 Description...................................................................5 FPGA Overview ..........................................................5 PLC Logic ...................................................................5 Description (continued)................................................6 PIC Logic ....................................................................6 System Features ........................................................6 Routing .......................................................................6 Configuration ..............................................................6 Description (continued)................................................7 ispLEVER Development System ................................7 Architecture .................................................................7 Programmable Logic Cells ..........................................9 Programmable Function Unit ......................................9 Look-Up Table Operating Modes .............................11 Supplemental Logic and Interconnect Cell (SLIC).....19 PLC Latches/Flip-Flops ............................................23 PLC Routing Resources ...........................................25 PLC Architectural Description ...................................32 rogrammable Input/Output Cells................................34 5 V Tolerant I/O ........................................................35 PCI Compliant I/O .....................................................35 Inputs ........................................................................36 Outputs .....................................................................39 PIC Routing Resources ............................................42 PIC Architectural Description ....................................43 High-Level Routing Resources..................................45 Interquad Routing .....................................................45 Programmable Corner Cell Routing .........................46 PIC Interquad (MID) Routing ....................................47 Clock Distribution Network ........................................48 PFU Clock Sources ..................................................48 Clock Distribution in the PLC Array ..........................49 Clock Sources to the PLC Array ...............................50 Clocks in the PICs ....................................................50 ExpressCLK Inputs ...................................................51 Selecting Clock Input Pins ........................................51 Special Function Blocks ............................................52 Single Function Blocks .............................................52 Boundary Scan .........................................................55 Microprocessor Interface (MPI) .................................62 PowerPC System .....................................................63 i960 System ..............................................................64 MPI Interface to FPGA .............................................65 MPI Setup and Control .............................................66 Programmable Clock Manager (PCM) ......................70 PCM Registers .........................................................71 Delay-Locked Loop (DLL) Mode ...............................73 Phase-Locked Loop (PLL) Mode ..............................74 PCM/FPGA Internal Interface ...................................77 PCM Operation .........................................................77 2 Contents Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table of Contents Contents Page Contents Page SE L D E IS C C T O D N E TI VI N C U E ED S Terms and Definitions .............................................192 144-Pin TQFP .........................................................193 208-Pin SQFP ........................................................194 208-Pin SQFP2 ......................................................195 240-Pin SQFP .........................................................196 240-Pin SQFP2 .......................................................197 256-Pin PBGA ........................................................198 352-Pin PBGA ........................................................199 432-Pin EBGA ........................................................200 Ordering Information................................................201 Lattice Semiconductor 3 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs System-Level Features phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create complex functions, such as digital phase-locked loops (DPLL), frequency counters, and frequency synthesizers or clock doublers. Two PCMs are provided per device. System-level features reduce glue logic requirements and make a system on a chip possible. These features in the ORCA Series 3 include: Full PCI local bus compliance. True, internal, 3-state, bidirectional buses with simple control provided by the SLIC. 32 x 4 RAM per PFU, configurable as single- or dualport at >176 MHz. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. SE L D E IS C C T O D N E TI VI N C U E ED S Dual-use microprocessor interface (MPI) can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA. Glueless interface to i960 * and PowerPC processors with user-configurable address space provided. Parallel readback of configuration data capability with the built-in microprocessor interface. Programmable clock manager (PCM) adjusts clock * i960 is a registered trademark of Intel Corporation. PowerPC is a registered trademark of International Business Machines Corporation. Table 2. ORCA Series 3 System Performance Parameter 16-bit Loadable Up/Down Counter 16-bit Accumulator 8 x 8 Parallel Multiplier: Multiplier Mode, Unpipelined1 ROM Mode, Unpipelined2 Multiplier Mode, Pipelined3 32 x 16 RAM (synchronous): Single-port, 3-state Bus4 Dual-port5 128 x 8 RAM (synchronous): Single-port, 3-state Bus4 Dual-port5 8-bit Address Decode (internal): Using Softwired LUTs Using SLICs6 32-bit Address Decode (internal): Using Softwired LUTs Using SLICs7 36-bit Parity Check (internal) # PFUs -4 Speed -6 -5 -7 Unit 2 2 78 78 102 102 131 131 168 168 MHz MHz 11.5 8 15 19 51 76 25 66 104 30 80 127 38 102 166 MHz MHz MHz 4 4 97 127 127 166 151 203 192 253 MHz MHz 8 8 88 88 116 116 139 139 176 176 MHz MHz 0.25 0 4.87 2.35 3.66 1.82 2.58 1.23 2.03 0.99 ns ns 2 0 2 16.06 6.91 16.06 12.07 5.41 12.07 9.01 4.21 9.01 7.03 3.37 7.03 ns ns ns 1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers). 4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus. 5. Implemented using 32 x 4 dual-port RAM mode. 6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC. 7. Implemented in five partially occupied SLICs. 4 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Description PLC Logic FPGA Overview Each PFU within a PLC contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. SE L D E IS C C T O D N E TI VI N C U E ED S The ORCA Series 3 FPGAs are a new generation of SRAM-based FPGAs built on the successful OR2C/ TxxA FPGA Series, with enhancements and innovations geared toward today's high-speed designs and tomorrow's systems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA 2C/2T devices, Series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. The ORCA Series 3 FPGAs consist of three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the system-level functions include the new microprocessor interface (MPI) and the programmable clock manager (PCM). Lattice Semiconductor The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPGA, reducing required routing and allowing for realworld system performance. 5 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Description (continued) PIC Logic Routing SE L D E IS C C T O D N E TI VI N C U E ED S Series 3 PIC addresses the demand for ever-increasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fastcapture latch that is clocked by an ExpressCLK. This latch is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two input signals are available to the PLC array from each PIO, and the ORCA 2C/2T capability to use any input pin as a clock or other global input is maintained. innovative programmable clock manager. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed systems. On the output side of each PIO, two outputs from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is very similar to the ORCA 2C/2T Series buffer with a new, fast, open-drain option for ease of use on system buses. System Features The abundant routing resources of the ORCA Series 3 FPGAs are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast ExpressCLK pins. ExpressCLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the new StopCLK feature. The improved PIC routing resources are now similar to the patented intra-PLC routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins. Configuration The FPGA's functionality is determined by internal configuration RAM. The FPGA's internal initialization/ configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes. The configuration data resides externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin count method for configuring FPGAs. A new, easy method for configuring the devices is through the microprocessor interface. Series 3 also provides system-level functionality by means of its dual-use microprocessor interface and its 6 Lattice Semiconductor Data Sheet November 2006 Description (continued) ispLEVER Development System The OR3T55 array in Figure 1 has PLCs arranged in an array of 18 rows and 18 columns. The location of a PLC is indicated by its row and column so that a PLC in the second row and the third column is R2C3. PICs are located on all four sides of the FPGA between the PLCs and the device edge. PICs are indicated using PT and PB to designate PICs on the top and bottom sides of the array, respectively, and PL and PR to designate PICs along the left and right sides of the array, respectively. The position of a PIC on an edge of the array is indicated by a number, counting from left to right for PT and PB and top to bottom for PL and PR PICs. SE L D E IS C C T O D N E TI VI N C U E ED S The ispLEVER Development System is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture and then place and route it using ispLEVER's timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis. ORCA Series 3C and 3T FPGAs The ispLEVER Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow: at design entry and at the bit stream generation stage. Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPGA. A static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation. Timing and simulation output files from ispLEVER are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGA's internal configuration RAM. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end tools, ispLEVER produces configuration data that implements the various logic and routing options discussed in this data sheet. Architecture The ORCA Series 3 FPGA comprises three basic elements: PLCs, PICs, and system-level functions. Figure 1 shows an array of programmable logic cells (PLCs) surrounded by programmable input/output cells (PICs). Also shown are the interquad routing blocks (hIQ, vIQ) present in Series 3. System-level functions (located in the corners of the array) and the routing resources and configuration RAM are not shown in Figure 1. Lattice Semiconductor Each PIC contains routing resources and four programmable I/Os (PIOs). Each PIO contains the necessary I/O buffers to interface to bond pads. PIOs in Series 3 FPGAs also contain input and output FFs, fast opendrain capability on output buffers, special output logic functions, and signal multiplexing/demultiplexing capabilities. PLCs comprise a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), and routing resources. The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential logic. Combinatorial logic is done in look-up tables (LUTs) located in the PFU. The PFU can be used in different modes to meet different logic requirements. The LUT's twin-quad architecture provides a configurable medium-/large-grain architecture that can be used to implement from one to eight independent combinatorial logic functions or a large number of complex logic functions using multiple LUTs. The flexibility of the LUT to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per PFU while increasing system speed. The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can realize any 4- or 5-input logic function and many multilevel logic functions using ORCA's softwired LUT (SWL) connections. In ripple mode, the high-speed carry logic is used for arithmetic functions, comparator functions, or enhanced data path functions. In memory mode, the LUTs can be used as a 32 x 4 synchronous read/write or read-only memory, in either single- or dual-port mode. 7 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Architecture (continued) PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 TMID PT10 PT11 PT12 PT13 PT14 PT15 PT16 PT17 R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17 PT18 R1C18 PL2 R2C9 PL3 R3C1 R3C2 R3C3 R3C4 R3C5 R3C6 R3C7 R3C8 PL4 R4C1 R4C2 R4C3 R4C4 R4C5 R4C6 R4C7 PL5 R5C1 R5C2 R5C3 R5C4 R5C5 R5C6 PL6 R6C1 R6C2 R6C3 R6C4 R6C5 PL7 R7C1 R7C2 R7C3 R7C4 PL8 R8C1 R8C2 R8C3 R9C1 R9C2 R9C3 R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17 R2C18 R3C9 R3C10 R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17 R3C18 R4C8 R4C9 R4C10 R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17 R4C18 R5C7 R5C8 R5C9 R5C10 R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17 R5C18 R6C6 R6C7 R6C8 R6C9 R6C10 R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17 R6C18 R7C5 R7C6 R7C7 R7C8 R7C9 R7C10 R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17 R7C18 R8C4 R8C5 R8C6 R8C7 R8C8 R8C9 R8C10 R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17 R8C18 R9C4 R9C5 R9C6 R9C7 R9C8 R9C9 R9C10 R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17 R9C18 PR9 R2C8 PR8 R2C7 PR7 R2C6 PR6 R2C5 PR5 R2C4 PR4 R2C3 PR3 R2C2 PR2 R2C1 PL9 SE L D E IS C C T O D N E TI VI N C U E ED S PT1 PR1 PL1 VI vIQ LMID PL10 R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9 R10C10 R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18 RMID PL11 R11C1 R11C2 R11C3 R11C4 R11C5 R11C6 R11C7 R11C8 R11C9 R11C10 R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18 PR11 PL12 R12C1 R12C2 R12C3 R12C4 R12C5 R12C6 R12C7 R12C8 R12C9 R12C10 R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18 PR12 PL13 R13C1 R13C2 R13C3 R13C4 R13C5 R13C6 R13C7 R13C8 R13C9 R13C10 R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18 PR13 PL14 R14C1 R14C2 R14C3 R14C4 R14C5 R14C6 R14C7 R14C8 R14C9 R14C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18 PR14 PL15 R15C1 R15C2 R15C3 R15C4 R15C5 R15C6 R15C7 R15C8 R15C9 R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18 PR15 PL16 R16C1 R16C2 R16C3 R16C4 R16C5 R16C6 R16C7 R16C8 R16C9 R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18 PR16 PL17 R17C1 R17C2 R17C3 R17C4 R17C5 R17C6 R17C7 R17C8 R17C9 R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18 PR17 PL18 R18C1 R18C2 R18C3 R18C4 R18C5 R18C6 R18C7 R18C8 R18C9 R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18 PR18 PR10 hIQ PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 BMID PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 5-4489(F) Figure 1. OR3T55 Array 8 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 SE L D E IS C C T O D N E TI VI N C U E ED S The programmable logic cell (PLC) consists of a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), and routing resources. All PLCs in the array are functionally identical with only minor differences in routing connectivity for improved routability. The PFU, which contains eight 4-input LUTs, eight latches/FFs, and one FF for logic implementation, is discussed in the next section, followed by discussions of the SLIC and PLC routing resources. Programmable Function Unit The PFUs are used for logic. Each PFU has 50 external inputs and 18 outputs and can operate in several modes. The functionality of the inputs and outputs depends on the operating mode. The PFU uses 36 data input lines for the LUTs, eight data input lines for the latches/FFs, five control inputs (ASWE, CLK, CE, LSR, SEL), and a carry input (CIN) for fast arithmetic functions and general-purpose data input for the ninth FF. There are eight combinatorial data outputs (one from each LUT), eight latched/registered outputs (one from each latch/FF), a carry-out (COUT), and a registered carry-out (REGCOUT) that comes from the ninth FF. The carry-out signals are used principally for fast arithmetic functions. Figure 2 and Figure 3 show high-level and detailed views of the ports in the PFU, respectively. The eight sets of LUT inputs are labeled as K0 through K7 with each of the four inputs to each LUT having a suffix of _x, where x is a number from 0 to 3. There are four F5 inputs labeled A through D. These inputs are used for a fifth LUT input for 5-input LUTs or as a selector for multiplexing two 4-input LUTs. The eight direct data inputs to the latches/FFs are labeled as DIN[7:0]. Registered LUT outputs are shown as Q[7:0], and combinatorial LUT outputs are labeled as F[7:0]. The PFU implements combinatorial logic in the LUTs and sequential logic in the latches/FFs. The LUTs are static random access memory (SRAM) and can be used for read/write or read-only memory. Each latch/FF can accept data from its associated LUT. Alternatively, the latches/FFs can accept direct data from DIN[7:0], eliminating the LUT delay if no combinatorial function is needed. Additionally, the CIN input can be used as a direct data source for the ninth FF. The LUT outputs can bypass the latches/FFs, which reduces the delay out of the PFU. It is possible to use the LUTs and latches/FFs more or less independently, allowing, for instance, a comparator function in the LUTs simultaneously with a shift register in the FFs. Lattice Semiconductor K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 F5C DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 PROGRAMMABLE FUNCTION UNIT (PFU) COUT REGCOUT CIN F7 F6 F5 F4 F3 F2 F1 F0 F5B K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 K0_0 K0_1 K0_2 K0_3 F5A LSR CLK CE SEL ASWE 5-5752(F) 5-5752(F) Figure 2. PFU Ports The PFU can be configured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (RAM/ROM) mode. In addition, ripple mode has four submodes and RAM mode can be used in either a single- or dual-port memory fashion. These submodes of operation are discussed in the following sections. 9 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) F7 F5D 0 K7_0 DIN7 K7 A B K7_1 K7_2 0 Q7 F6 SE L D E IS C C T O D N E TI VI N C U E ED S C D REG7 D0 D1 DSEL CE CK S/R K7_3 K6_0 K6_1 K6_2 K6 A B C K6_3 D F5MODE67 K5 A B C D K4 A B C D K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 DIN6 0 1 0 REG6 D0 D1 DSEL CE CK S/R F5 DIN5 0 Q5 F4 DIN4 0 F5MODE45 0 REG5 D0 D1 DSEL CE CK S/R 1 0 F5C Q6 CLK REG4 D0 D1 DSEL CE CK S/R Q4 0 SEL 0 CIN COUT 0 CE 1 1 FF8 1 D CE CK S/R ASWE REGCOUT 1 0 LSR 0 0 0 F3 F5B 0 K3_0 DIN3 K3 A B C D K3_1 K3_2 K3_3 K2_0 K2 A B C K2_1 K2_2 K2_3 D K1_0 K1_1 K1_2 K1_3 K1 A B C D K0_0 K0_1 K0_2 K0_3 K0 A B C D 0 DIN2 0 1 0 REG2 D0 D1 DSEL CE CK S/R F5MODE23 REG1 D0 D1 DSEL CE CK S/R 1 0 F2 Q2 Q1 F0 DIN0 F5MODE01 Q3 F1 DIN1 0 F5A 0 REG3 D0 D1 DSEL CE CK S/R 0 REG0 D0 D1 DSEL CE CK S/R Q0 5-5743(F) Note: All multiplexers without select inputs are configuration selector multiplexers. Figure 3. Simplified PFU Diagram 10 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Look-Up Table Operating Modes SE L D E IS C C T O D N E TI VI N C U E ED S The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode, the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT memory. Table 3 lists the basic operating modes of the LUT. Figure 4--Figure 10 show block diagrams of the LUT operating modes. The accompanying descriptions demonstrate each mode's use for generating logic. Table 3. Look-Up Table Operating Modes Mode Function Logic 4- and 5-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to ninth FF or as pass through to COUT. Half Logic/ Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN Half Rip- and ninth FF for logic or ripple functions. ple Ripple All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. Memory All LUTs and latches/FFs used to create a 32 x 4 synchronous dual-port RAM. Can be used as singleport or as ROM. PFU Control Inputs Each PFU has five routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that affects all latches and FFs in the device. The five control inputs are CLK, LSR, CE, ASWE, and SEL, and their functionality for each logic mode of the PFU (discussed subsequently) is shown in Table 4. The clock signal to the PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal itself. ASWE stands for add/subtract/write enable, which are its functions, along with being an optional clock enable, and SEL is used to dynamically select between direct PFU input and LUT output data as the input to the latches/FFs. All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple modes of the PFU, the LSR, CE, and ASWE (as a clock enable) inputs can be disabled individually for each nibble (latch/FF[3:0], latch/FF[7:4]) and for the ninth FF. Lattice Semiconductor 11 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Table 4. Control Input Functionality Mode LSR CLK to all latches/ LSR to all latches/ FFs FFs, enabled per nibble and for ninth FF Half Logic/ CLK to all latches/ LSR to all latches/FF, Half Ripple FFs enabled per nibble and for ninth FF Ripple CLK to all latches/ LSR to all latches/ FFs FFs, enabled per nibble and for ninth FF Memory CLK to RAM Port enable 2 (RAM) Memory Optional for sync. Not used (ROM) outputs CE ASWE SEL CE to all latches/FFs, selectable per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF Port enable 1 CE to all latches/FFs, selectable per nibble and for ninth FF Ripple logic control input Write enable Select between LUT input and direct input for eight latches/FFs Select between LUT input and direct input for eight latches/FFs Select between LUT input and direct input for eight latches/FFs Not used Not used Not used Not used SE L D E IS C C T O D N E TI VI N C U E ED S Logic CLK Ripple logic control input Logic Mode The PFU diagram of Figure 3 represents the logic mode of operation. In logic mode, the eight LUTs are used individually or in flexible groups to implement user logic functions. The latches/FFs may be used in conjunction with the LUTs or separately with the direct PFU data inputs. There are three basic submodes of LUT operation in PFU logic mode: F4 mode, F5 mode, and softwired LUT (SWL) mode. Combinations of these submodes are possible in each PFU. F4 mode, shown simplified in Figure 4, illustrates the uses of the basic 4-input LUTs in the PFU. The output of an F4 LUT can be passed out of the PFU, captured at the LUTs associated latch/FF, or multiplexed with the adjacent F4 LUT output using one of the F5[A:D] inputs to the PFU. Only adjacent LUT pairs (K0 and K1, K2 and K3, K4 and K5, K6 and K7) can be multiplexed, and the output always goes to the even-numbered output of the pair. The F5 submode of the LUT operation, shown simplified in Figure 4, indicates the use of 5-input LUTs to implement logic. 5-input LUTs are created from two 4-input LUTs and a multiplexer. The F5 LUT is the same as the multiplexing of two F4 LUTs described previously with the constraint that the inputs to the F4 LUTs be the same. The F5[A:D] input is then used as the fifth LUT input. The equations for the two F4 LUTs will differ by the assumed value for the F5[A:D] input, one F4 LUT assuming that the F5[A:D] input is zero, and the other assuming it is a one. The selection of the appropriate F4 LUT output in the F5 MUX by the F5[A:D] signal creates a 5-input LUT. Any combination of F4 and F5 LUTs is allowed per PFU using the eight 16-bit LUTs. Examples are eight F4 LUTs, four F5 LUTs, and a combination of four F4 plus two F5 LUTs. F5D K7 F7 K7 F6 K6 K5 K6 F6 F5 F6 K5/K4 F4 K3/K2 F2 K1/K0 F0 K5 F4 K4 K7/K6 F4 K4 F5C F5B K3 F3 K3 F2 K2 F2 K2 K1 F1 F5 MODE K1 F0 K0 K0 F0 F5A F4 MODE MULTIPLEXED F4 MODE 5-5970(F) Figure 4. Simplified F4 and F5 Logic Modes 12 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) SE L D E IS C C T O D N E TI VI N C U E ED S Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic functions up to three LUT-levels deep. Figure 3 shows multiplexers between the KZ[3:0] inputs to the PFU and the LUTs. These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs. In this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single PFU at greatly enhanced speeds. Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an F4 or F5 LUT. It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equation need only be generated once and PLC routing resources will not be required to use it in the larger equation. F4 F4 F4 F4 F5 F5 F4 F4 F4 F4 F5 F5 FOUR 7-INPUT FUNCTIONS IN ONE PFU F5 F5 TWO 9-INPUT FUNCTIONS IN ONE PFU F4 F4 F5 F5 ONE 17-INPUT FUNCTION IN ONE PFU ONE 21-INPUT FUNCTION IN ONE PFU F4 3 5-5753(F) F4 F4 F4 F4 F4 F5 F5 F4 F4 F4 F4 TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU 5-5754(F) KEY: F4 4-INPUT LUT F5 5-INPUT LUT Figure 5. Softwired LUT Topology Examples Lattice Semiconductor 13 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) with half-logic ripple connections shown as dashed lines. Half-Logic Mode The result output and ripple output are calculated by using generate/propagate circuitry. In ripple mode, the two operands are input into KZ[1] and KZ[0] of each LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see Figure 6). The ripple output from LUT K7/K3 can be routed on dedicated carry circuitry into any of four adjacent PLCs, and it can be placed on the PFU COUT/ FCOUT outputs. This allows the PLCs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. SE L D E IS C C T O D N E TI VI N C U E ED S Series 3 FPGAs are based upon a twin-quad architecture in the PFUs. The byte-wide nature (eight LUTs, eight latches/FFs) may just as easily be viewed as two nibbles (two sets of four LUTs, four latches/FFs). The two nibbles of the PFU are organized so that any nibble-wide feature (excluding some softwired LUT topologies) can be swapped with any other nibble-wide feature in another PFU. This provides for very flexible use of logic and for extremely flexible routing. The halflogic mode of the PFU takes advantage of the twinquad architecture and allows half of a PFU, K[7:4] and associated latches/FFs, to be used in logic mode while the other half of the PFU, K[3:0] and associated latches/ FFs, is used in ripple mode. In half-logic mode, the ninth FF may be used as a general-purpose FF or as a register in the ripple mode carry chain. Result outputs and the carry-out may optionally be registered within the PFU. The capability to register the ripple results, including the carry output, provides for improved counter performance and simplified pipelining in arithmetic functions. Ripple Mode The PFU LUTs can be combined to do byte-wide ripple functions with high-speed carry logic. Each LUT has a dedicated carry-out net to route the carry to/from any adjacent LUT. Using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one PFU. Similarly, each PFU has carry-in (CIN, FCIN) and carry-out (COUT, FCOUT) ports for fast-carry routing between adjacent PFUs. The ripple mode is generally used in operations on two data buses. A single PFU can support an 8-bit ripple function. Data buses of 4 bits and less can use the nibble-wide ripple chain that is available in half-logic mode. This nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. For example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one PFU in ripple mode (8 bits) and one PFU in half-logic mode (4 bits), freeing half of a PFU for general logic mode functions. Each LUT has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. A single bit is rippled from the previous LUT and is used as input into the current LUT. For LUT K0, the ripple input is from the PFU CIN or FCIN port. The CIN/FCIN data can come from either the fast-carry routing (FCIN) or the PFU input (CIN), or it can be tied to logic 1 or logic 0. In the following discussions, the notations LUT K7/K3 and F[7:0]/F[3:0] are used to denote the LUT that provides the carry-out and the data outputs for full PFU ripple operation (K7, F[7:0]) and half-logic ripple operation (K3, F[3:0]), respectively. The ripple mode diagram in Figure 6 shows full PFU ripple operation, 14 C D Q REGCOUT FCOUT COUT C F7 K7[1] K7[0] K7 D K6[1] K6[0] K6 D K5[1] K5[0] K5 D K4[1] K4[0] K4 D K3[1] K3[0] K3 D K2[1] K2[0] K2 D K1[1] K1[0] K1 D K0[1] K0[0] K0 D Q Q7 F6 Q Q6 F5 Q Q5 F4 Q Q4 Q Q3 Q Q2 F3 F2 F1 Q Q1 F0 Q Q0 CIN/FCIN 5-5755(F) Figure 6. Ripple Mode Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) C D Q The third LUT output creates the result bit for each LUT output connected to F[7:0]/F[3:0]. If an adder/subtractor is needed, the control signal to select addition or subtraction is input on ASWE, with a logic 0 indicating subtraction and a logic 1 indicating addition. The result bit is created in one-half of the LUT from a single bit from each input bus KZ[1:0], along with the ripple input bit. The second submode is the counter submode (see Figure 7). The present count, which may be initialized via the PFU DIN inputs to the latches/FFs, is supplied to input KZ[0], and then output F[7:0]/F[3:0] will either be incremented by one for an up counter or decremented by one for a down counter. If an up/down counter is needed, the control signal to select the direction (up or down) is input on ASWE with a logic 1 indicating an up counter and a logic 0 indicating a down counter. Generally, the latches/FFs in the same PFU are used to hold the present count value. Lattice Semiconductor REGCOUT FCOUT COUT C K7[0] SE L D E IS C C T O D N E TI VI N C U E ED S The ripple mode can be used in one of four submodes. The first of these is adder-subtractor submode. In this submode, each LUT generates three separate outputs. One of the three outputs selects whether the carry-in is to be propagated to the carry-out of the current LUT or if the carry-out needs to be generated. If the carry-out needs to be generated, this is provided by the second LUT output. The result of this selection is placed on the carry-out signal, which is connected to the next LUT carry-in or the COUT/FCOUT signal, if it is the last LUT (K7/K3). Both of these outputs can be any equation created from KZ[1] and KZ[0], but in this case, they have been set to the propagate and generate functions. K7 D K6 D K5 D K4 D K3 D K2 D Q K1 D Q K0 D Q K6[0] Q K5[0] Q K4[0] Q K3[0] Q K2[0] K1[0] K0[0] Q CIN/FCIN F7 Q7 F6 Q6 F5 Q5 F4 Q4 F3 Q3 F2 Q2 F1 Q1 F0 Q0 5-5756(F) Figure 7. Counter Submode 15 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) C ASWE D Q COUT C K7[1] 0 1 0 REGCOUT F7 D Q + Q7 SE L D E IS C C T O D N E TI VI N C U E ED S In the third submode, multiplier submode, a single PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode) multiply and sum with a partial product (see Figure 8). The multiplier bit is input at ASWE, and the multiplicand bits are input at KZ[1], where K7[1] is the most significant bit (MSB). KZ[0] contains the partial product (or other input to be summed) from a previous stage. If ASWE is logical 1, the multiplicand is added to the partial product. If ASWE is logical 0, 0 is added to the partial product, which is the same as passing the partial product. CIN/FCIN can bring the carry-in from the less significant PFUs if the multiplicand is wider than 8 bits, and COUT/FCOUT holds any carry-out from the multiplication, which may then be used as part of the product or routed to another PFU in multiplier mode for multiplicand width expansion. Ripple mode's fourth submode features equality comparators. The functions that are explicitly available are A > B, A B, and A < B, where the value for A is input on KZ[0], and the value for B is input on KZ[1]. A value of 1 on the carry-out signals valid argument. For example, a carry-out equal to 1 in AB submode indicates that the value on KZ[0] is greater than or equal to the value on KZ[1]. Conversely, the functions A < B, A + B, and A > B are available using the same functions but with a 0 output expected. For example, A > B with a 0 output indicates A < B. Table 5 shows each function and the output expected. K7[0] K7 K6[1] 0 1 0 F6 K6[0] Q6 K6 K5[1] 0 1 0 F5 D Q + K5[0] Q5 K5 K4[1] 0 1 0 F4 D Q + K4[0] Q4 K4 K3[1] 0 1 0 F3 D Q + K3[0] Q3 K3 K2[1] 0 1 0 F2 D Q + K2[0] Q2 K2 K1[1] 0 1 0 F1 D Q + K1[0] Q1 K1 K0[1] 0 K0[0] D Q + 1 0 F0 D Q + Q0 K0 5-5757(F) Key: C = configuration data. Figure 8. Multiplier Submode If larger than 8 bits, the carry-out signal can be cascaded using fast-carry logic to the carry-in of any adjacent PFU. The use of this submode could be shown using Figure 6, except that the CIN/FCIN input for the least significant PFU is controlled via configuration. Table 5. Ripple Mode Equality Comparator Functions and Outputs Equality Function ispLEVER Submode True, if Carry-Out Is: A>B A>B 1 A<B A<B 1 B AB 1 A<B A>B 0 A>B A<B 0 A=B AB 0 A 16 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Memory Mode SE L D E IS C C T O D N E TI VI N C U E ED S The Series 3 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory (RAM). A block diagram of a PFU in memory mode is shown in Figure 9. This RAM can also be configured to work as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be used as a read-only memory (ROM). F5[A:D] CIN(WA4) D Q DIN7(WA3) D Q DIN5(WA2) D Q DIN3(WA1) D Q DIN1(WA0) D Q DIN6(WD3) READ ADDRESS[4:0] 4 KZ[3:0] D Q DIN4(WD2) D Q DIN2(WD1) D Q DIN0(WD0) D Q ASWE(WREN) CE(WPE1) D Q EN S/R 5 WRITE ADDRESS[4:0] F6 F4 F2 F0 READ DATA[3:0] 4 D Q Q6 D Q Q4 D Q Q2 D Q Q0 4 WRITE DATA[3:0] WRITE ENABLE RAM CLOCK LSR(WPE2) CLK 5-5969(F) Figure 9. Memory Mode The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in Figure 9. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable signal is input at ASWE, and two write port enables are input on CE and LSR. The PFU CLK signal is used to synchronously write the data. The polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if they are not to be used. Lattice Semiconductor 17 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) SE L D E IS C C T O D N E TI VI N C U E ED S Data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the RAM until the next clock edge one-half cycle later. The read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. If the read and write address lines are tied together (maintaining MSB to MSB, etc.), then the dual-port RAM operates as a synchronous single-port RAM. If the write enable is disabled, and an initial memory contents is provided at configuration time, the memory acts as a ROM (the write data and write address ports and write port enables are not used). 8-bit data path. Depth expansion is applied to achieve 128 words deep using the 32-word deep PFU memories. In addition to the PFU in each PLC, the SLIC (described in the next section) in each PLC is used for read address decodes and 3-state drivers. The 128 x 8 RAM shown could be made to operate as a single-port RAM by tying (bit-for-bit) the read and write addresses. Wider memories can be created by operating two or more memory mode PFUs in parallel, all with the same address and control signals, but each with a different nibble of data. To increase memory word depth above 32, two or more PLCs can be used. Figure 10 shows a 128 x 8 dual-port RAM that is implemented in eight PLCs. This figure demonstrates data path width expansion by placing two memories in parallel to achieve an Figure 10 also shows a new optional capability to provide a read enable for RAMs/ROMs in Series 3 using the SLIC cell. The read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired. 8 WD[7:0] 4 4 PLC WA 5 5 WA PFU WD[7:4] RA 5 5 WA RA WD[3:0] 5 5 WA WPE0 WPE0 WPE0 WPE0 WPE1 WPE1 WPE1 WPE1 WE WE WE WE RD[7:4] 4 RA 5 RD[3:0] SLIC SLIC SLIC 4 RD[7:4] RD[3:0] PLC PFU WD[3:0] RA 4 PLC PFU WD[7:4] 5 4 PLC PFU RD[7:0] To achieve depth expansion, one or two of the write address bits (generally the MSBs) are routed to the write port enables as in Figure 10. For 2 bits, the bits select which 32-word bank of RAM of the four available from a decode of two WPE inputs is to be written. Similarly, 2 bits of the read address are decoded in the SLIC and are used to control the 3-state buffers through which the read data passes. The write data bus is common, with separate nibbles for width expansion, across all PLCs, and the read data bus is common (again, with separate nibbles) to all PLCs at the output of the 3-state buffers. 4 SLIC 4 8 WE WA[6:0] RA[6:0] 7 7 CLK RE 5-5749(F) Figure 10. Memory Mode Expansion Example--128 x 8 RAM 18 Lattice Semiconductor Data Sheet November 2006 Programmable Logic Cells (continued) Supplemental Logic and Interconnect Cell (SLIC) The SLIC may also be used to generate PAL-like ANDOR with optional INVERT (AOI) functions or a decoder of up to 10 bits. Each group of buffers can feed into an AND gate (4-input AND for the nibble groups and 2input AND for the other two buffers). These AND gates then feed into a 3-input gate that can be configured as either an AND gate or an OR gate. The output of the 3input gate is invertible and is output at the DEC output of the SLIC. Figure 16 shows the SLIC in full decoder mode. SE L D E IS C C T O D N E TI VI N C U E ED S Each PLC contains a supplemental logic and interconnect cell (SLIC) embedded within the PLC routing, outside of the PFU. As its name indicates, the SLIC performs both logic and interconnect (routing) functions. Its main features are 3-statable, bidirectional buffers, and a PAL-like decoder capability. Figure 11 shows a diagram of a SLIC with all of its features shown. All modes of the SLIC are not available at one time. ORCA Series 3C and 3T FPGAs Each SLIC contains ten bidirectional (BIDI) buffers, each buffer capable of driving left and/or right out of the SLIC. These BIDI buffers are twin-quad in nature and are segregated into two groups of four (nibbles) and a third group of two for control. Each of these groups of BIDIs can drive from the left (BLI[9:0]) to the right (BRO[9:0]), the right (BRI[9:0]) to the left (BLO[9:0]), or from the central input (I[9:0]) to the left and/or right. This central input comes directly from the PFU outputs (O[9:0]). Each of the BIDIs in the nibble-wide groups also has a 3-state buffer capability, but not the third group. There is one 3-state control (TRI) for each SLIC, with the capability to invert or disable the 3-state control for each group of four BIDIs. Separate 3-state control for each nibble-wide group is achievable by using the SLIC's decoder (DEC) output, driven by the group of two BIDIs, to control the 3-state of one BIDI nibble while using the TRI signal to control the 3-state of the other BIDI nibble. Figure 12 and Figure 13 show the SLIC in buffer mode with available 3-state control from the TRI and DEC signals. If the entire SLIC is acting in a buffer capacity, the DEC output may be used to generate a constant logic 1 (VHI) or logic 0 (VLO) signal for general use. Lattice Semiconductor The functionality of the SLIC is parsed by the two nibble-wide groups and the 2-bit buffer group. Each of these groups may operate independently as BIDI buffers (with or without 3-state capability for the nibblewide groups) or as a PAL/decoder. As discussed in the memory mode section, if the SLIC is placed into one of the modes where it contains both buffers and a decode or AOI function (e.g., BUF_BUF_DEC mode), the DEC output can be gated with the 3-state input signal. This allows up to a 6-input decode (e.g., BUF_DEC_DEC mode) plus the 3-state input to control the enable/disable of up to four buffers per SLIC. Figure 12--Figure 16 show several configurations of the SLIC, while Table 6 shows all of the possible modes. Table 6. SLIC Modes Mode # Mode BUF [3:0] BUF [7:4] BUF [9:8] 1 BUFFER Buffer Buffer Buffer 2 BUF_BUF_DEC Buffer Buffer Decoder 3 BUF_DEC_BUF Buffer Decoder Buffer 4 BUF_DEC_DEC Buffer Decoder Decoder 5 DEC_BUF_BUF Decoder Buffer Buffer 6 DEC_BUF_DEC Decoder Buffer Decoder 7 DEC_DEC_BUF Decoder Decoder 8 DECODER Buffer Decoder Decoder Decoder 19 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) BRI9 I9 BLI9 BRI9 I9 BLI9 BL09 BL09 BR09 BR09 BRI8 I8 BLI8 BRI8 I8 BLI8 BL08 BR08 SE L D E IS C C T O D N E TI VI N C U E ED S BL08 BR08 BRI7 I7 BLI7 BRI7 I7 BLI7 BL07 BR07 BRI6 I6 BLI6 BL06 BRI6 I6 BLI6 BR06 BRI5 I5 BLI5 BL07 BR07 BL06 BR06 BL05 BR05 DEC BRI4 I4 BLI4 BL04 BR04 BRI5 I5 BLI5 BL05 BR05 BRI4 I4 BLI4 TRI BL04 BR04 0/1 0/1 TRI DEC HIGH Z WHEN LOW 0/1 1 0/1 0/1 BRI3 I3 BLI3 BRI2 I2 BLI2 BRI1 I1 BLI1 BRI0 I0 BLI0 DEC 0 HIGH Z WHEN LOW THIS CAN BE USED TO GENERATE A VHI OR VLO BL03 BR03 0/1 BL02 BRI3 I3 BLI3 BR02 BL03 BR03 BL01 BRI2 I2 BLI2 BR01 BL02 BR02 BL00 BR00 5-5744(F) BRI1 I1 BLI1 BL01 BR01 Figure 11. SLIC All Modes Diagram BRI0 I0 BLI0 BL00 BR00 5-5745(F) Figure 12. Buffer Mode 20 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) BRI9 I9 BLI9 BRI9 BLI9 BL08 SE L D E IS C C T O D N E TI VI N C U E ED S BRI8 I8 BLI8 BL09 BR09 BRI8 BR08 BLI8 BRI7 BRI7 I7 BLI7 BL07 BLI7 BR07 BRI6 BRI6 I6 BLI6 BL06 BLI6 BR06 BRI5 BRI5 I5 BLI5 BL05 BLI5 BR05 BRI4 BRI4 I4 BLI4 BL04 BLI4 BR04 1 DEC HIGH Z WHEN LOW TRI TRI DEC 1 1 1 HIGH Z WHEN LOW HIGH Z WHEN LOW 1 1 BRI3 I3 BLI3 BRI2 I2 BLI2 BRI1 I1 BLI1 BRI0 I0 BLI0 BRI3 I3 BLI3 BL03 BR03 BRI2 I2 BLI2 BL02 BR02 BL01 BRI1 I1 BLI1 BR01 BL00 BR00 5-5746(F) Figure 13. Buffer-Buffer-Decoder Mode Lattice Semiconductor BRI0 I0 BLI0 BL03 BR03 BL02 BR02 BL01 BR01 BL00 BR00 5-5747(F) Figure 14. Buffer-Decoder-Buffer Mode 21 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) BRI9 BLI9 BLI9 BRI8 BRI8 BLI8 BLI8 BRI7 BRI7 BLI7 BLI7 SE L D E IS C C T O D N E TI VI N C U E ED S BRI9 BRI6 BRI6 BLI6 BLI6 BRI5 BRI5 BLI5 BLI5 BRI4 BRI4 BLI4 BLI4 DEC DEC TRI 1 HIGH Z WHEN LOW 1 BRI3 I3 BLI3 BRI2 I2 BLI2 BRI1 I1 BLI1 BRI0 I0 BLI0 BL03 BRI3 BR03 BLI3 BL02 BR02 BRI2 BL01 BLI2 BR01 BRI1 BLI1 BL00 BR00 BRI0 5-5750(F) BLI0 5-5748(F) Figure 15. Buffer-Decoder-Decoder Mode Figure 16. Decoder Mode 22 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) PLC Latches/Flip-Flops The set/reset operation of the latch/FF is controlled by two parameters: reset mode and set/reset value. When the global set/reset (GSRN) and local set/reset (LSR) signals are not asserted, the latch/FF operates normally. The reset mode is used to select a synchronous or asynchronous LSR operation. If synchronous, LSR has the option to be enabled only if clock enable (CE or ASWE) is active or for LSR to have priority over the clock enable input, thereby setting/resetting the FF independent of the state of the clock enable. The clock enable is supported on FFs, not latches. It is implemented by using a 2-input multiplexer on the FF input, with one input being the previous state of the FF and the other input being the new data applied to the FF. The select of this 2-input multiplexer is clock enable (CE or ASWE), which selects either the new data or the previous state. When the clock enable is inactive, the FF output does not change when the clock edge arrives. SE L D E IS C C T O D N E TI VI N C U E ED S The eight general-purpose latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration options apply to all eight latches/FFs in the PFU and some apply to the latches/FFs on a nibble-wide basis where the ninth FF is considered independently. For other options, each latch/FF is independently programmable. In addition, the ninth FF can be used for a variety of functions. The eight latches/FFs in a PFU share the clock (CLK) and options for clock enable (CE), local set/reset (LSR), and front-end data select (SEL) inputs. When CE is disabled, each latch/FF retains its previous value when clocked. The clock enable, LSR, and SEL inputs can be inverted to be active-low. Table 7 summarizes these latch/FF options. The latches/FFs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered flip-flops (the ninth register can only be FF). All latches/FFs in a given PFU share the same clock, and the clock to these latches/FFs can be inverted. The input into each latch/FF is from either the corresponding LUT output (F[7:0]) or the direct data input (DIN[7:0]). The latch/FF input can also be tied to logic 1 or to logic 0, which is the default. Table 7. Configuration RAM Controlled Latch/ Flip-Flop Operation Function Options Common to All Latches/FFs in PFU LSR Operation Asynchronous or synchronous Clock Polarity Noninverted or inverted Front-end Select* Direct (DIN[7:0]) or from LUT (F[7:0]) LSR Priority Either LSR or CE has priority Latch/FF Mode Latch or flip-flop Enable GSRN GSRN enabled or has no effect on PFU latches/FFs Set Individually in Each Latch/FF in PFU Set/Reset Mode Set or reset By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8]) Clock Enable CE or ASWE or none LSR Control LSR or none * Not available for FF[8]. Lattice Semiconductor 23 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs The latches/FFs can be configured in three basic modes: The GSRN signal is only asynchronous, and it sets/ resets all latches/FFs in the FPGA based upon the set/ reset configuration bit for each latch/FF. The set/reset value determines whether GSRN and LSR are set or reset inputs. The set/reset value is independent for each latch/FF. A new option is available to disable the GSRN function per PFU after initial device configuration. 1. Local synchronous set/reset: the input into the PFU's LSR port is used to synchronously set or reset each latch/FF. 2. Local asynchronous set/reset: the input into LSR asynchronously sets or resets each latch/FF. 3. Latch/FF with front-end select, LSR either synchronous or asynchronous: the data select signal selects the input into the latches/FFs between the LUT output and direct data in. For all three modes, each latch/FF can be independently programmed as either set or reset. Figure 17 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. SE L D E IS C C T O D N E TI VI N C U E ED S Programmable Logic Cells (continued) The latch/FF can be configured to have a data frontend select. Two data inputs are possible in the frontend select mode, with the SEL signal used to select which data input is used. The data input into each latch/FF is from the output of its associated LUT, F[7:0], or direct from DIN[7:0], bypassing the LUT. In the frontend data select mode, both signals are available to the latches/FFs. If either or both of these inputs is unused or is unavailable, the latch/FF data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). SEL CE/ASWE CE/ASWE F DIN LOGIC 1 LOGIC 0 The ninth PFU FF, which is generally associated with registering the carry-out signal in ripple mode functions, can be used as a general-purpose FF. It is only an FF and is not capable of being configured as a latch. Because the ninth FF is not associated with an LUT, there is no front-end data select. The data input to the ninth FF is limited to the CIN input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. CE D Q s_set F DIN LOGIC 1 LOGIC 0 D CE Q F DIN LOGIC 1 LOGIC 0 CE/ASWE D DIN CE Q LSR s_reset CLK GSRN LSR CLK GSRN LSR CLK SET RESET SET RESET SET RESET GSRN CD CD CD Key: C = configuration data. Figure 17. Latch/FF Set/Reset Configurations 24 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) PLC Routing Resources INDEPENDENT CIP B Generally, the ispLEVER Development System is used to automatically route interconnections. Interactive routing with the ispLEVER design editor (EPIC) is also available for design optimization. To use EPIC for interactive layout, an understanding of the routing resources is needed and is provided in this section. CD = SE L D E IS C C T O D N E TI VI N C U E ED S A A B MULTIPLEXED CIP The routing resources consist of switching circuitry and metal interconnect segments. Generally, the metal lines which carry the signals are designated as routing segments. The switching circuitry connects the routing segments, providing one or more of three basic functions: signal switching, amplification, and isolation. A net running from a PFU or PIC output (source) to a PLC or PIC input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (CIPs). The following sections discuss PLC, PIC, and interquad routing resources. This section discusses the PLC switching circuitry, intra-PLC routing, inter-PLC routing, and clock distribution. Configurable Interconnect Points The process of connecting routing segments uses three basic types of switching circuits: two types of configurable interconnect points (CIPs) and bidirectional buffers (BIDIs). The basic element in CIPs is one or more pass transistors, each controlled by a configuration RAM bit. The two types of CIPs are the mutually exclusive (or multiplexed) CIP and the independent CIP. A mutually exclusive set of CIPs contains two or more CIPs, only one of which can be on at a time. An independent CIP has no such restrictions and can be on independent of the state of other CIPs. Figure 18 shows an example of both types of CIPs. Lattice Semiconductor CD O 2 A B C A B O C Key: C = configuration data. 5-5973(C) Figure 18. Configurable Interconnect Point 3-Statable Bidirectional Buffers Bidirectional buffers, previously described in the SLIC section of the programmable logic cell discussion, provide isolation as well as amplification for signals routed a long distance. Bidirectional buffers are also used to route signals diagonally in the PLC (described later in the subsection entitled Intra-PLC Routing), and BIDIs can be used to indirectly route signals through the switching routing (xSW) segments. Any number from zero to ten BIDIs can be used in a given PLC. 25 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) General Routing Structure SE L D E IS C C T O D N E TI VI N C U E ED S Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths and connectivity to logic and other routing resources. The varying lengths of routing segments provides a hierarchy of routing capability from chip-length routes to routes within a PLC. The hierarchical nature of the routing provides the ispLEVER development tools with the necessary resources to route a design completely and to optimize the routing for system speed while reducing the overall power required by the device. Within each group of ten routing segments there is an equivalency of connectivity between pairs of segments. These pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. The equivalency in connectivity ensures that signals on either segment in a pair have the same capability to get to a given destination. This, in turn, allows for signal distribution from a source to varying destinations without using special routing. It also provides for routing flexibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group of signals and allows easy connectivity from either of the twin quads in a source PFU to either of the twin quads in any destination PFU. BL[9:0] vxH[9:0] VCK LCK FC vx1R[9:0] SUL[9:0] vx1L[9:0] vx5[9:0] vxL[9:0] BL[9:0] Having ten segments in a group is significant in that it provides for routing a byte of data and two control signals or parity. Due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control signal. Figure 19 is an overview of the routing for a single PLC. hxH[9:0] hx1U[9:0] hCK FC FC SLL[9:0] SLL[9:0] FINS PFU 5 2 SLR[9:0] SLIC OUTPUT SWITCHING SUR[9:0] LCK hx1B[9:0] 2 hx5[9:0] 5 hxL[9:0] BR[9:0] BR[9:0] SUL[9:0] SUL[9:0] FC BL[9:0] KEY: CONFIGURABLE SIGNAL LINE BREAKS LINE-BY-LINE 2 2 OF 5 5 5-5766(F) Figure 19. Single PLC View of Inter-PLC Route Segments 26 Lattice Semiconductor Data Sheet November 2006 Programmable Logic Cells (continued) Intra-PLC Routing ally labeled for the upper-left, upper-right, lower-left, and lower-right sections of the PFUs, respectively. The xSW routing segments connect to the PFU inputs and outputs as well as the BIDI routing segments, to be described later. They also connect to both the horizontal and vertical x1 and x5 routing segments (inter-PLC routing resources, described later) in their specific corner. xSW segments can be used for fast connections between adjacent PLCs or PICs without requiring the use of inter-PLC routing resources. This capability not only increases signal speed on adjacent PLC routing, but also reduces routing congestion on the principal inter-PLC routing resources. The SLL and SUR segments combine to provide connectivity to the PLCs to the left and right of the current PLC; the SLR and SUL segments combine to provide connectivity to the PLCs above and below the current PLC. SE L D E IS C C T O D N E TI VI N C U E ED S The function of the intra-PLC routing resources is to connect the PFU's input and output ports to the routing resources used for entry to and exit from the PLC. This routing provides PFU feedback, corner turning, or switching from one type of routing resource to another. ORCA Series 3C and 3T FPGAs Flexible Input Structure (FINS) The flexible input switching structure (FINS) in each PLC of the ORCA Series 3 provides for the flexibility of a crossbar switch from the routing resources to the PFU inputs while taking advantage of the routability of shared inputs. Connectivity between the PLC routing resources and the PFU inputs is provided in two stages. The primary FINS switch has 50 inputs that connect the PLC routing to the 35 inputs on the secondary switch. The outputs of the second switch connect to the 50 PFU inputs. The switches are implemented to provide connectivity for bused signals and individual connections. PFU Output Switching The PFU outputs are switched onto PLC routing resources via the PFU output multiplexer (OMUX). The PFU output switching segments from the output multiplexer provide ten connections to the PLC routing out of 18 possible PFU outputs (F[7:0], Q[7:0], DOUT, REGCOUT). These output switching segments connect segment for segment to the SUR, SUL, SLR, and SLL switching segments described below (e.g., O4 connects only to SUR4, not SUR5). The output switching segments also feed directly into the SLIC on a segment-by-segment basis. This connectivity is also described below. Switching Routing Segments (xSW) There are four sets of switching routing segments in each PLC. Each set consists of ten switching elements: SUL[9:0], SUR[9:0], SLL[9:0], and SLR[9:0], tradition- Lattice Semiconductor Fast routes on switching segments to diagonally adjacent PLCs/PICs are possible using the BIDI routing segments (discussed below) and the SLL and SLR switching segments. The BR BIDI routing segments combine with the SUL switching segments of the PLC below and to the right of the current PLC to connect to that PLC. The BL BIDI routing segments combine with the SLL switching segments of the PLC above and to the right of the current PLC to connect to that PLC. These fast diagonal connections provide a great amount of flexibility in routing congested areas of logic and in shifting data on a per-PLC basis such as performing implicit multiplications/divisions in routing between functional logic elements. Switching routing segments are also the chief means by which signals are transferred between the inter-PLC routing resources and the PFU. Each set of switching segments has connectivity to the x1 routing segments, and there is varying connectivity to the x5, xH, and xL inter-PLC routing segments. Detailed information on switching segment/inter-PLC routing connectivity is provided later in this section in the Inter-PLC Routing Resources subsection. 27 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) BIDI Routing and SLIC Connectivity Control Signal and Fast-Carry Routing PFU control signal and the fast-carry routing are performed using the FINS structure and several dedicated routing paths. The fast-carry (FC) routing resources consist of a dedicated bidirectional segment between each orthogonal pair of PLCs. This means that a fastcarry can go to or come from each PLC to the right or left, above or below the subject PLC. The FINS structure is used to control the switching of these fast-carry paths between the fast-carry input (FCIN) and fastcarry output (FCOUT) ports of the PFU. SE L D E IS C C T O D N E TI VI N C U E ED S The SLIC is connected to the rest of the PLC by the bidirectional (BIDI) routing segments and the PFU output switching segments coming from the PFU output multiplexer. The BIDI routing segments (xBID) are labeled as BL for BIDI-left and BR for BIDI-right. Each set of BR and BL xBID segments is composed of ten bidirectional lines (note that these lines are diagramed as ten input lines to the SLIC and ten output lines from the SLIC that can be used in a mutually exclusive fashion). Because the SLIC is connected directly to the outputs of the PFU, it provides great flexibility in routing via the xBID segments. The PFU routing segments, O[9:0], only connect to their respective line in the SLL, SUL, SUR, and SLR switching segment groups. That is, O9 only connects to SLL9, SUL9, SUR9, and SLR9. The BIDI lines provide the capability to connect to the other member of the routing set. That means, for example, that O9 can be routed to BR8 or BL8. This connectivity can be used as a means to distribute or gather signals on intra-PLC routing without disturbing inter-PLC resources. As described in the Switching Routing Segments subsection, the BIDI routing segments are also used for routes to a diagonally adjacent PFU. Data Sheet November 2006 In addition to the intra-PLC connections, the xBID and output switching segments also have connectivity to the x1, x5, and xL inter-PLC routing resources, providing an alternate routing path rather than using PLC xSW segments. These connections also provide a path to the 3-state buffers in the SLIC without encumbering the xSW segments. In this manner, buffering or 3-state control can be added to inter-PLC routing without disturbing local functionality within a PFU. 28 The PFU control inputs (CE, SEL, LSR, ASWE) and CIN can be reached via the FINS by two special routing segments, E1 and E2. The E1 routing segment provides connectivity between all of the xBID routing segments and the FINS. It is unidirectional from the BIDI routing to the FINS. E1 also provides connectivity to the PFU clock input via FINS for a local clock signal. The E2 segment connects the SLIC DEC output to the FINS and to a group of CIPS that provide bidirectional connectivity with all of the BIDI routing segments. This allows the DEC signal to be used in the PFU and/or routed on the BIDI segments. It also allows signals to be routed to the PFU on the xBID segments if the SLIC DEC output is not used. There is also a dedicated routing segment from the FINS to the SLIC TRI input used for BIDI buffer 3-state control. Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Inter-PLC Routing Resources SE L D E IS C C T O D N E TI VI N C U E ED S The inter-PLC routing is used to route signals between PLCs. The routing segments occur in groups of ten, and differ in the numbers of PLCs spanned. The x1 routing segments span one PLC, the x5 routing segments span five PLCs, the xH routing segments span one-half the width (height) of the PLC array, and the xL routing segments span the width (height) of the PLC array. All types of routing segments run in both horizontal and vertical directions. x1 Routing Segments. There are a total of 40 x1 routing segments per PLC: 20 vertical and 20 horizontal. Each of these are subdivided into two, 10-bit wide buses: hx1T[9:0], hx1B[9:0], vx1L[9:0], and vx1R[9:0]. An x1 segment is one PLC long. If a signal net is longer than one PLC, an x1 segment can be lengthened to n times its length by turning on n - 1 CIPs. A signal is routed onto an x1 route segment via the switching routing segments or BIDI routing segments which also allows the x1 route segment to be connected to other inter-PLC segments of different lengths. Corner turning between x1 segments is provided through direct connections, xSW segments, and xBID segments. Table 8 shows the groups of inter-PLC routing segments in each PLC. In the table, there are two rows/columns for x1 lines. They are differentiated by a T for top, B for bottom, L for left, and R for right. In the ispLEVER design editor representation, the horizontal x1 routing segments are located above and below the PFU. The two groups of vertical segments are located on the left side of the PFU. The xL and x5 routing segments only run below and to the left of the PFU, while the xH segments only run above and to the right of the PFU. The indexes specify individual routing segments within a group. For example, the vx5[2] segment runs vertically to the left of the PFU, spans five PLCs, and is the third line in the 10-bit wide group. PLCs are arranged like tiles on the ORCA device. Breaks in routing occur at the middle of the tile (e.g., x1 lines break in the middle of each PLC) and run across tiles until the next break. Table 8. Inter-PLC Routing Resources Horizontal Routing Segments Vertical Routing Segments Distance Spanned hx1U[9:0] hx1B[9:0] hx5[9:0] hx5[9:0] hxL[9:0] hxH[9:0] hCLK vx1R[9:0] vx1L[9:0] vx5[9:0] vx5[9:0] vxL[9:0] vxH[9:0] vCLK One PLC One PLC Five PLCs Five PLCs PLC Array 1/2 PLC Array PLC Array x5 Routing Segments. There are two sets of ten x5 routing segments per PLC. One set (vx5[9:0]) runs vertically, and the other (hx5[9:0]) runs horizontally. Each x5 segment traverses five PLCs before it is broken by a CIP. Two x5 segments in each group break in each PLC. The two that break are in an equivalent pair; for example, x5[0] and x5[4]. The x5 segments that break shift by one at the next PLC. For example, if hx5[0] and hx5[4] are broken at the current PLC, hx5[1] and hx5[5] will be broken at the PLC to the right of the current PLC. There are direct connections to the BIDI routing segments in the PLC at which the x5 segments break, on both sides of the break. Signal corner turning is enabled by CIPs in each PLC that allow the broken x5 segments to directly connect to the broken x5 segments that run in the orthogonal direction. x5 corner turning can also be accomplished via the xSW and xBID segments in a PLC. In addition, the x5 segments are connected to the FINS and PFU outputs on a bitby-bit basis by the xSW segments. x5 segments can be connected for signal runs in multiples of five PLCs, or they can be combined with x1 and xH routing segments for runs of varying distances. Figure 20 provides a global view of inter-PLC routing resources across multiple PLCs. Lattice Semiconductor 29 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs vCLK vxH[9:0] vx1[9:0] vx1[9:0] vx5[9:0] vxL[9:0] vCLK vxH[9:0] vx1[9:0] vx1[9:0] vx5[9:0] vxL[9:0] vCLK vxH[9:0] vx1[9:0] vx1[9:0] vx5[9:0] vx1L[9:0] Programmable Logic Cells (continued) SE L D E IS C C T O D N E TI VI N C U E ED S hxH[9:0] hx1[9:0] hCLK 10 10 10 PFU 2 PFU 2 SLIC PFU 2 SLIC SLIC hx1[9:0] 2 2 10 2 10 10 hx5[9:0] hxL[9:0] hxH[9:0] hx1[9:0] hCLK 10 10 PFU 2 10 PFU 2 SLIC PFU 2 SLIC SLIC hx1[9:0] 2 2 10 2 10 10 hx5[9:0] hxL[9:0] hxH[9:0] hx1[9:0] hCLK 10 10 PFU 2 SLIC 10 PFU 2 SLIC PFU 2 SLIC hx1[9:0] 2 2 10 2 10 10 hx5[9:0] hxL[9:0] KEY: CONFIGURABLE SIGNAL-LINE BREAKS: LINE-BY-LINE 2 2 OF 10 10 PLC BOUNDARY 5-5767(F) Figure 20. Multiple PLC View of Inter-PLC Routing 30 Lattice Semiconductor Data Sheet November 2006 Programmable Logic Cells (continued) The clock routing segments are designed to be a clock spine. In each PLC, there is a fast connection available from the clock segment to a long-line driver (described earlier). With this connection, one of the clock routing segments in each PLC can be used to drive one of the ten xL routing segments perpendicular to it, which, in turn, creates a clock spine tree. This feature is discussed in detail in the Clock Distribution Network section. SE L D E IS C C T O D N E TI VI N C U E ED S xL Routing Lines. The xL routing lines run vertically and horizontally the height and width of the array, respectively. There are a total of 20 xL routing lines per PLC: ten horizontal (hxL[9:0]) and ten vertical (vxL[9:0]). Each of the xL lines connects to the PIC routing at either end. The xL lines are intended primarily for global signals that must travel long distances and require minimum delay and/or skew, such as clocks or 3-state buses. ORCA Series 3C and 3T FPGAs Each xL line (also called a long line) drives a buffer in each PLC that can drive onto the horizontal and vertical local clock routing segments (lCLK) in the PLC. Also, two out of each group of ten xL segments in each PLC can be driven by a buffer attached to a clock spine (described later) allowing local distribution of global clock signals. More general-purpose connections to the long lines can be made through the xBID segments in a PLC. Each long line is connected to an xBID segment on a bit-by-bit basis. These BIDI connections allow corner turning from horizontal to vertical long lines, and connection between long lines and x1 or x5 segments. xH Routing Segments. Ten by-half (xH) routing segments run horizontally (hxH[9:0]) and ten xH routing segments run vertically (vxH[9:0]) in each row and column in the array. These routing segments travel a distance of one-half the PLC array before being broken in the middle of the array in the interquad area (discussed later). They also connect at the periphery of the FPGA to the PICs, like the xL lines. xH routing segments connect to the PLCs only by switching segments. They are intended for fast signal interconnect. Clock (and Global CE and LSR) Routing Segments. For a very fast and low-skew clock (or other global signal tree), clock routing segments run the entire height and width of the PLC array. There are two clock routing segments per PLC: one horizontal (hCLK) and one vertical (vCLK). The source for these clock routing segments can be any of the I/O buffers in the PIC, the Series 3 ExpressCLK inputs, user logic, or the programmable clock manager (PCM). The horizontal clock routing segments (hCLK) are alternately driven by the left and right PICs. The vertical clock routing segments (vCLK) are alternately driven by the top and bottom PICs. Lattice Semiconductor Special connectivity is provided in each PLC to connect the clock enable signals (CE and ASWE) and the LSR signal to the clock network for fast global control signal distribution. CE and ASWE have a special connection to the horizontal clock spine, and LSR has a special connection to the vertical clock spine. This allows both signals to be routed globally within the same PLC, if desired; however, this will consume some of the resources available for clock signal routing. If using these spines, the clock enable signal must come from the right or left edge of the device, and the LSR signal must come from the top or bottom of the device due to their horizontal and vertical connectivity, respectively, to the clock network. Minimizing Routing Delay The CIP is an active element used to connect two routing segments. As an active element, it adds significantly to the resistance and capacitance of a routing network (net), thus increasing the net's delay. The advantage of the x1 segment over an x5 segment is routing flexibility. A net from one PLC to the next is easily routed by using x1 routing segments. As more CIPs are added to a net, the delay increases. To increase speed, routes that are greater than two PLCs away are routed on the x5 routing segments because a CIP is located only in every fifth PLC. A net that spans eight PLCs requires seven x1 routing segments and six CIPs. Using x5 routing segments, the same net uses two routing segments and one CIP. 31 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) PLC Architectural Description J. These are the ten switched output routing segments from the PFU. They connect to the PLC switching segments and are input to the SLIC. K. These lines deliver the auxiliary signals clock enable (CE), local set/reset (LSR), front-end select (SEL), add/subtract/write enable (ASWE), as well as the carry signals (CIN and FCIN) to the latches/FFs. L. This is the local clock buffer. Any of the horizontal and vertical xL lines can drive the clock input of the PLC latches/FFs. The clock routing segments (vCLK and hCLK) and multiplexers/drivers are used to connect to the xL routing segments for low-skew, lowdelay global signals. M. These routing segments are used to route the fastcarry signal to/from the neighboring four PLCs. The carry-out (COUT) and registered carry-out (REGCOUT) can also be routed out of the PFU. N. This is the E2 control routing segment. It runs from the SLIC DEC output to the FINS and also provides connectivity to all xBID segments. O. The xH routing segments run one-half the length (width) of the array before being broken by a CIP. P. These CIPs connect the xH segments to the xSW segments. Q. The xBID segments are used to connect the SLIC to the xSW segments, x1 segments, x5 segments, and xL lines, as well as providing for diagonal PLC to PLC connections. R. These CIPs provide connections from the xBID segments to the E1/E2 routing segments that feed PFU control inputs CE, LSR, CIN, ASWE, SEL, and the clock input. Alternatively, these CIPs connect the BIDI lines to the decoder (DEC) output of the SLIC, for routing the DEC signal. S. These are clock spines (vCLK and hCLK) with the multiplexers and drivers to connect to the xL routing segments. T. These CIPs connect xBID segments to switching segments in diagonally and orthogonally adjacent PFUs. U. These CIPs connect xSW segments to the PFU output segments. V. These CIPS connect xSW segments in orthogonally adjacent PFUs. W.This is the SLIC 3-state control routing segment from the FINS to the SLIC 3-state control. X. This is the E1 control routing segment. It provides a PFU input path from all xBID segments. Y. These CIPs are used to select which xBID segments are connected to the E1/E2 signal as described in (R). SE L D E IS C C T O D N E TI VI N C U E ED S Figure 21 is an architectural drawing of the PLC (as seen in ispLEVER) that reflects the PFU, the routing segments, and the CIPs. A discussion of each of the letters in the drawing follows. Data Sheet November 2006 A. These are switching routing segments (xSW) that give the router flexibility. In general switching theory, the more levels of indirection there are in the routing, the more routable the network is. The xSW segments can also connect to the xSW lines in adjacent PLCs. B. These CIPs connect the x1 routing. These are located in the middle of the PLC to allow the block to connect to either the left end of the horizontal x1 segment from the right or the right end of the horizontal x1 segment from the left, or both. By symmetry, the same principle is used in the vertical direction. C. This set of CIPs is used to connect the x1 and x5 nets to the xSW segments or to other x1 and x5 nets. The CIPs on the major diagonal allow data to be transmitted on a bit-by-bit basis from x1 nets to the xSW segments and between the x1 and x5 nets. D. This structure is the supplemental logic and interconnect cell, or SLIC. It contains 3-statable bidirectional buffers and logic for building decoders and AND-OR-INVERT type structures. E. These are the primary and secondary elements of the flexible input structure or FINS. FINS is a switch matrix that provides high connectivity while retaining routing capability. FINS also includes feedback paths for softwired LUT implementation. F. This is the PFU output switch matrix. It is a complex switch network which, like the FINS at the input, provides high connectivity and maintains routability. G. This set of CIPs allows an xBID segment to transfer a signal to/from xSW segments on each side. The BIDIs can access the PFU through the xSW segments. These CIPs allow data to be routed through the BIDIs for amplification or 3-state control and continue to another PLC. They also provide an alternative routing resource to improve routability. H. These CIPs are used to transfer data from/to the xBID segments to/from the x1 and xL routing segments. These CIPs have been optimized to allow the BIDI buffers to drive the loads usually seen when using each type of routing segment. I. Clock input to PFU. 32 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) P A M O H B C C SE L D E IS C C T O D N E TI VI N C U E ED S C S Q M E O A G M E C A B A C Q C A SECONDARY FINS C A PRIMARY FINS A A PFU B D H H N K W SLIC U U U J OUTPUT F SWITCHING P R R L X Y V C A C C C H B T C H G L Q Q H Q Q T M A S 5-5758(F) Figure 21. PLC Architecture Lattice Semiconductor 33 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells PICs in the Series 3 FPGAs have significant local routing resources, similar to routing in the PLCs. This new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. The flexibility provided by the routing also provides for increased signal speed due to a greater variety of signal paths possible. SE L D E IS C C T O D N E TI VI N C U E ED S The programmable input/output cells (PICs) are located along the perimeter of the device. The PIC's name is represented by a two-letter designation to indicate on which side of the device it is located followed by a number to indicate in which row or column it is located. The first letter, P, designates that the cell is a PIC and not a PLC. The second letter indicates the side of the array where the PIC is located. The four sides are left (L), right (R), top (T), and bottom (B). The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at the end of the PIC name. As an example, PL10A indicates a pad located on the left side of the array in the tenth row. Included in the PIC routing is a fast path from the input pins to the SLICs in each of the three adjacent PLCs (one orthogonal and two diagonal). This feature allows for input signals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA. Also new to the Series 3 PIOs are latches and FFs and options for using fast, dedicated clocks called ExpressCLKs. These features will all be discussed in subsequent sections. Each PIC interfaces to four bond pads and contains the necessary routing resources to provide an interface between I/O pads and the PLCs. Each PIC is composed of four programmable I/Os (PIOs) and significant routing resources. Each PIO contains input buffers, output buffers, routing resources, latches/FFs, and logic and can be configured as an input, output, or bidirectional I/O. A diagram of a single PIO (one of four in a PIC) is shown in Figure 22. Table 9 provides an overview of the programmable functions in an I/O cell. PIO LOGIC AND NAND OR NOR XOR XNOR PULL-MODE OUT1 FROM ROUTING UP DOWN NONE OUT1OUTREG OUT2OUTREG OUT1OUT2 0 PAD OUT2 0 ECLK SCLK D Q CK SP LSR CE 0 RESET SET D0 Q CK 1 LSR 1 TS CE_OVER_LSR LSR_OVER_CE ASYNC LSR LEVEL MODE BUFFER MODE FAST SLEW SINK TTL CMOS CLKIN PD ECLK SCLK NORMAL INVERTED 1 INREGMODE LATCHFF LATCH FF D Q CK D0 D1 Q IN1 CK SP SD LSR TO ROUTING PMUX RESET SET IN2 ENABLE_GSR DISABLE_GSR 5-5805(F).c Figure 22. OR3C/Txxx Programmable Input/Output (PIO) Image from ispLEVER 34 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) The I/O on the OR3Txxx Series devices allow interconnection to both 3.3 V and 5 V devices (selectable on a per-pin basis). Table 9. PIO Options Input Option Clock Sense TTL, OR3Cxx only CMOS, OR3Cxx or OR3Txxx 3.3 V PCI Compliant, OR3Txxx 5 V PCI Compliant, OR3Txxx Fast, Delayed Pull-up, Pull-down, None Latch, FF, Fast Zero Hold FF, None (direct input) Inverted, Noninverted Input Selection Input 1, Input 2, Clock Input The OR3Txxx devices will drive the pin to the 3.3 V levels when the output buffer is enabled. If the other device being driven by the OR3Txxx device has TTLcompatible inputs, then the device will not dissipate much input buffer power. This is because the OR3Txxx output is being driven to a higher level than the TTL level required. If the other device has a CMOS-compatible input, the amount of input buffer power will also be small. Both of these power values are dependent upon the input buffer characteristics of the other device when driven at the OR3Txxx output buffer voltage levels. SE L D E IS C C T O D N E TI VI N C U E ED S Input Level 5 V Tolerant I/O Input Speed Float Value Register Mode Output Output Drive Current Output Function Output Speed Output Source Output Sense 3-State Sense FF Clocking Clock Sense Logic Options Option 12 mA/6 mA or 6 mA/3 mA Normal, Fast Open Drain Fast, Slewlim, Sinklim FF Direct-out, General Routing Active-high, Active-low Active-high, Active-low (3-state) ExpressCLK, System Clock Inverted, Noninverted See Table 10. I/O Controls Clock Enable Set/Reset Level Set/Reset Type Set/Reset Priority GSR Control Option Active-high, Active-low, Always Enabled Active-high, Active-low, No Local Reset Synchronous, Asynchronous CE over LSR, LSR over CE Enable GSR, Disable GSR Lattice Semiconductor The OR3Txxx device has internal programmable pullups on the I/O buffers. These pull-up voltages are always referenced to VDD and are always sufficient to pull the input buffer of the OR3Txxx device to a high state. The pin on the OR3Txxx device will be at a level 1.0 V below VDD (minimum of 2.0 V with a minimum VDD of 3.0 V). This voltage is sufficient to pull the external pin up to a 3.3 V CMOS high input level (1.8 V, min) or a TTL high input level (2.0 V, min) in a 5 V tolerant system. Therefore, in a 5 V tolerant system using 5 V CMOS parts, care must be taken to evaluate the use of these pull-ups to pull the pin of the OR3Txxx device to a typical 5 V CMOS high input level (2.2 V, min). PCI Compliant I/O The I/O on the OR3Txxx Series devices allows compliance with PCI Local Bus (Rev. 2.2) 5 V and 3.3 V signaling environments. The signaling environment used for each input buffer can be selected on a per-pin basis. The selection provides the appropriate I/O clamping diodes for PCI compliance. Choosing an IBT input buffer will provide PCI compliance in OR3Txxx devices. OR3Cxx devices have PCI Local Bus compliant I/Os for 5 V signaling. 35 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Inputs Warning: During configuration, all OR3Txxx inputs have internal pull-ups enabled. If these inputs are driven to 5 V, they will draw substantial current ( 5 mA). This is due to the fact that the inputs are pulled up to 3 V. Floating inputs increase power consumption, produce oscillations, and increase system noise. The OR3Cxx inputs have a typical hysteresis of approximately 280 mV (200 mV for the OR3Txxx) to reduce sensitivity to input noise. The PIC contains input circuitry which provides protection against latch-up and electrostatic discharge. SE L D E IS C C T O D N E TI VI N C U E ED S As outlined earlier in Table 9, there are six major options on the PIO inputs that can be selected in the ispLEVER tools. For OR3Cxx devices, the inputs and bidirectional buffers can be configured as either TTL or CMOS compatible. OR3Txxx devices support CMOS levels only for input or bidirectional buffers, have 5 V tolerant I/Os as previously explained, but can optionally be selected on a pin-by-pin basis to be PCI bus 3.3 V signaling compliant (PCI bus 5 V signaling compliance occurs in 5 V tolerant operation). The default buffer upon powerup for the unused sites is 5 V tolerant/5 V PCI compliant. Consult the ORCA macro library, Series 3 I/O cells, for the appropriate buffers. Inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. Input signals in a PIO can be passed to PIC routing on any of three paths, two general signal paths into PIC routing, and/or a fast route into the clock routing system. Data Sheet November 2006 There is also a programmable delay available on the input. When enabled, this delay affects the IN1 and IN2 signals of each PIO, but not the clock input. The delay allows any signal to have a guaranteed zero hold time when input. This feature is discussed subsequently. The other features of the PIO inputs relate to the new latch/FF structure in the input path. As shown in Figure 23, the input is optionally passed to a register or latch/register pair. These structures can operate in the modes listed in Table 9. In latch mode, the input signal is fed to a latch that is clocked by a system clock signal. The clock may be inverted or noninverted from its sense in the PIC routing. There is also a local set/reset signal to the latch from the PIC routing. The senses of these signals are also programmable as well as the capability to enable or disable the global set/reset signal and select the set/reset priority. The same control signals may also be used to control the input latch/FF when it is configured as a FF instead of a latch, with the addition of another control signal used as a clock enable. Inputs should have transition times of less than 500 ns and should not be left floating. If any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. 36 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Zero-Hold Input SE L D E IS C C T O D N E TI VI N C U E ED S There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system clock. To guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. The fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data from a dedicated latch that is clocked by the ExpressCLK from the PIC. The ExpressCLK is a clock from a dedicated input pin designed for fast, low-skew operation at the I/Os and is described more fully in the Clock Distribution Network and PIC Interquad (MID) Routing sections that follow. The combination of ExpressCLK latch and system clock FF guarantees a zero-hold capture of input data in the PIO FF, while at the same time reducing input setup time. Figure 23 shows a schematic of the fast-capture latch/FF and a sample timing diagram. FF LATCH INPUT DATA O EXPRESSCLK I D Q D CLK CE DATA OUT TO PIC ROUTING Q S/R CD = 1 O SYSTEM CLK I CLOCK ENABLE LOCAL SET/RESET EXPRESSCLK SYSTEM CLK INPUT DATA QLATCH QFF A B C A D B A E C B D C E D 5-5974(F) Note: CE and LSR signals not shown. Figure 23. Fast-Capture Latch and Timing Lattice Semiconductor 37 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Input Demultiplexing SE L D E IS C C T O D N E TI VI N C U E ED S The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1. The address and data are then both available at the rising edge of the system clock. These signals may be registered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC decoder to perform an address decode to enable which registers are to receive the input data. Although the timing shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the signals found in PIO inputs IN1 and IN2 can be interchanged. OTHER ADDRESS LINES PLC PIO D PAD SCLK Q DEC IN1 SLIC IN2 D CE Q SCLK PIO INPUT DATA1 PIO LATCH OUTPUT ADDR1 PLC FF OUTPUT DATA0 ADDR2 DATA2 ADDR2 DATA1 ADDR3 DATA3 ADDR3 ADDR4 DATA4 ADDR4 DATA2 DATA3 ADDR5 ADDR5 DATA4 5-5798(F) Figure 24. PIO Input Demultiplexing 38 Lattice Semiconductor Data Sheet November 2006 Programmable Input/Output Cells (continued) Outputs An FF has been added to the output path of the PIO. The register has a local set/reset and clock enable. The LSR has the option to be synchronous or asynchronous and have priority set as clock enable over LSR or LSR over clock enable. Clocking to the output FF can come from either the system clock or the ExpressCLK associated with the PIC. The input to the FF can come from either OUT1 or OUT2, or it can be tied to VDD or GND. Additionally, the input to the FF can be inverted. SE L D E IS C C T O D N E TI VI N C U E ED S The PIC's output drivers have programmable drive capability and slew rates. Three propagation delays (fast, slewlim, sinklim) are available on output drivers. The sinklim mode has the longest propagation delay and is used to minimize system noise and minimize power consumption. The fast and slewlim modes allow critical timing to be met. ORCA Series 3C and 3T FPGAs The drive current is 12 mA sink/6 mA source for the slewlim and fast output speed selections and 6 mA sink/3 mA source for the sinklim output. Two adjacent outputs can be interconnected to increase the output sink/source current to 24 mA/12 mA. All outputs that are not speed critical should be configured as sinklim to minimize power and noise. The number of outputs that switch simultaneously in the same direction should be limited to minimize ground bounce. To minimize ground bounce problems, locate heavily loaded output buffers near the ground pads. Ground bounce is generally a function of the driving circuits, traces on the printed-circuit board, and loads and is best determined with a circuit simulation. At powerup, the output drivers are in slewlim mode, and the input buffers are configured as TTL-level compatible (CMOS for OR3Txxx) with a pull-up. If an output is not to be driven in the selected configuration mode, it is 3-stated. The output buffer signal can be inverted, and the 3-state control signal can be made active-high, activelow, or always enabled. In addition, this 3-state signal can be registered or nonregistered. Additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the output buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. Because there is no explicit route required to create the open-drain output, its response is very fast. Like the input side of the PIO, there are two output connections from PIC routing to the output side of the PIO, OUT1, and OUT2. These connections provide for flexible routing and can be used in data manipulation in the PIO as described in subsequent paragraphs. Lattice Semiconductor Output Multiplexing The Series 3 PIO output FF can be combined with the new PIO logic block to perform output data multiplexing with no PLC resources required. The PIO logic block has three multiplexing modes: OUT1OUTREG, OUT2OUTREG, and OUT1OUT2. OUT1OUTREG and OUT2OUTREG are equivalent except that either OUT1 or OUT2 is MUXed with the FF, where the FF data is output on the clock phase after the active edge. The simplest multiplexing mode is OUT1OUT2. In this mode, the signal at OUT1 is output to the pad while the clock is low, and the signal on OUT2 is output to the pad when the clock is high. Figure 25 shows a simple schematic of a PIO in OUT1OUT2 mode and a general timing diagram for multiplexing an address and data signal. Often an address will be used to generate or read a data sample from memory with the goal of multiplexing the data onto a single line. In this case, the address often precedes the data by one clock cycle. OUT1OUTREG and OUT2OUTREG modes of the PIO logic can be used to address this situation. Because OUT1OUTREG mode is equivalent to OUT2OUTREG, only OUT2OUTREG mode is described here. Figure 26 shows a simple PIO schematic in OUT2OUTREG mode and general timing for multiplexing data with a leading address. The address signal on OUT1 is registered in the PIO FF. This delays the address so that it aligns with the data signal. The PIO logic block then sends the OUTREG signal (address) to the pad when the clock is high and the OUT2 signal (data) to the pad when the clock is low, resulting in an aligned, multiplexed signal. 39 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) PIC ADDRESS FROM ROUTING OUT1 SE L D E IS C C T O D N E TI VI N C U E ED S PLC OUT2 DATA FROM ROUTING PIO LOGIC PAD CLK CLK OUT1 ADDR1 ADDR2 OUT2 DATA1 PIC OUTPUT ADDR1 ADDR3 DATA2 DATA1 ADDR4 DATA3 ADDR2 DATA2 ADDR5 DATA4 ADDR3 DATA3 DATA5 ADDR4 DATA4 NOTE: PIO LOGIC MODE, OUT1OUT2 5-5799(F) Figure 25. Output Multiplexing (OUT1OUT2 Mode) PLC ADDRESS FROM ROUTING PIC OUT1 D Q CLK DATA FROM ROUTING P/O LOGIC OUT2 PAD CLK ADDR ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 DATA DATA1 DATA2 DATA3 DATA4 REG ADDRESS ADDR1 ADDR2 ADDR3 ADDR4 PAD ADDR1 DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 NOTE: PIO LOGIC MODE, OUT1OUT2 5-5797(F) Figure 26. Output Multiplexing (OUT2OUTREG Mode) 40 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells PIO Register Control Signals (continued) As discussed in the Inputs and Outputs subsections, the PIO latches/FFs have various clock, clock enable (CE), local set/reset (LSR), and global set/reset (GSRN) controls. Table 11 provides a summary of these control signals and their effect on the PIO latches/FFs. Note that all control signals are optionally invertible. PIO Logic Function Generator SE L D E IS C C T O D N E TI VI N C U E ED S The PIO logic block can also generate logic functions based on the signals on the OUT2 and CLK ports of the PIO. The functions are AND, NAND, OR, NOR, XOR, and XNOR. Table 10 is provided as a summary of the PIO logic options. Table 10. PIO Logic Options Control Signal Option Description OUT1OUTREG Data at OUT1 output when clock low, data at FF out when clock high. Data at OUT2 output when clock low, data at FF out when clock high. Data at OUT1 output when clock low, data at OUT2 when clock high. Output logical AND of signals on OUT2 and clock. Output logical NAND of signals on OUT2 and clock. Output logical OR of signals on OUT2 and clock. Output logical NOR of signals on OUT2 and clock. Output logical XOR of signals on OUT2 and clock. Output logical XNOR of signals on OUT2 and clock. OUT2OUTREG OUT1OUT2 AND NAND OR NOR XOR XNOR Lattice Semiconductor Table 11. PIO Register Control Signals Effect/Functionality Clocks input fast-capture latch; optionally clocks output FF, or 3-state FF. System Clock Clocks input latch/FF; optionally (SCLK) clocks output FF, or 3-state FF. Clock Enable Optionally enables/disables input (CE) FF (not available for input latch mode); optionally enables/disables output FF; separate CE inversion capability for input and output. Local Set/Reset Option to disable; affects input (LSR) latch/FF, output FF, and 3-state FF if enabled. Global Set/Reset Option to enable or disable per (GSRN) PIO after initial configuration. Set/Reset Mode The input latch/FF, output FF, and 3-state FF are individually set or reset by both the LSR and GSRN inputs. ExpressCLK 41 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) PIC Routing Resources switching segments of the PIC to the right (below). This means of connectivity between PICs using staggered connections of groups of switching segments allows a given PIC to route signals to both adjacent PICs and all adjacent PLCs efficiently. This provides single signal routing flexibility and routing of multiple buses on groups of I/Os without tying up global routing resources. SE L D E IS C C T O D N E TI VI N C U E ED S The PIC routing borrows many of the concepts and constructs from the PLC routing. It is designed to be able to gather an 8-bit bidirectional bus from any eight consecutive I/O pads and route them to either or both of the two adjacent PLCs. The eight I/O bits do not need to start at a PIC boundary; that is, they may start at one of the middle two PIOs in a PIC and span three PICs. Data Sheet November 2006 Substantial routing has been added to the PIC to offload PLC routing from being used to move signals around the PLC array perimeter. This saves PLC routing for logic purposes and provides greater flexibility for locking design pinouts prior to final placement and routing of the device, or allowing a change in the pinout late in the design cycle. The PIC routing has also been increased substantially to allow routing to the complex PIO cells that now allow multiple inputs and outputs per device pin, along with new sequential control signals, such as clock enable, LSR, and clock. PICs are grouped in pairs for purposes of discussing PIC routing. On the sides of a device, the PICs in a pair are referred to as top and bottom. On the top or bottom of a device, the PICs in a pair are referred to as left or right. For example, on the top edge of the device, the leftmost PIC, PT1, is the left PIC of a pair, and PIC PT2 is the right PIC of that pair. The next PIC to the right, PT3, is the left PIC of the next pair, and so on. The need for PIC pairs stems from the routing of switching segments and PLC half- and long-line drivers. As described below, the connectivity for these types of routing is grouped across pairs of PICs to provide complete and fast routing of I/O signals between a given PIC and the three adjacent PLCs: one orthogonal and two diagonal. PIC routing segments use the same terminology as PLC routing segments, but are prefixed with a p to distinguish them as belonging to the PICs. PIC Switching Segments. Each PIC has two groups of switching segments (pSW), each group having eight lines with connectivity to the PIOs in groups of four. One set of switching segments connects to the PIC to the left (above), and the other set connects to the 42 px1 Routing Segments. There are five px1 routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides, each broken by a CIP in each PIC. The px1 segments have connectivity to the pSW segments and to the x1 routing segments of the two adjacent PLCs. px2 Routing Segments. There are five px2 routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides. To provide greater routing flexibility, the CIPs that break the px2 segments every two PICs are staggered across the two PICs in a pair. One PIC of the pair has break CIPs on the evennumbered px2 segments, and the other has them on the odd-numbered px2 segments. The px2 segments have connectivity to the pSW segments and to the x1 routing segments of the two adjacent PLCs. px5 Routing Segments. There are ten px5 routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides. Two of the ten segments are broken in each PIC so that each segment is broken every five PICs. All ten px5 segments break at the corners of the chip, allowing independent px5 routing on each edge of the chip. The px5 routing segments connect to the pSW segments and the x5 and xH routing segments of the two adjacent PLCs. pxH Routing Segments. Each PIC contains eight pxH routing segments that run parallel to the edge of the chip on which the PIC resides. The pxH segments have connectivity with the xL, xH, and one set of xBID routing segments in the immediately adjacent PLC. pxL Routing Segments. There are ten pxL routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides. Each of the xL lines makes a connection to an xL line from the adjacent PLC. PIC long lines (xL) can be used for global signal distribution just as PLC xL lines can. Lattice Semiconductor Data Sheet November 2006 Programmable Input/Output Cells (continued) PIC Architectural Description P. BIDI routing segments from the adjacent PLC routing. Q. These are the IN2 routing segments. There is one IN2 line from each PIO, and all eight IN2 lines from each PIC pair are present in both PICs of a pair. R. These CIPs connect the IN1 and IN2 routing segments from the PIOs to the PIC switching segments. SE L D E IS C C T O D N E TI VI N C U E ED S The PIC architecture as seen in ispLEVER is shown in Figure 27. The figure is the left PIC of a PIC pair on the top edge of a Series 3 array. Both PICs in a pair are similar, with the differences mainly lying in the connections between the PIC switching segments (pSW), the IN2 connections across PIC boundaries, and the system clock spine driver residing in only one PIC of a pair. ORCA Series 3C and 3T FPGAs A. This is a programmable input/output (PIO). There are four PIOs per PIC. The PIOs contain the PIC logic and I/O buffers. S. These CIPs break the PIC switching segments at the interface between a PIC pair. T. These CIPs connect adjacent PLC routing resources to the PIC switching segments. U. These CIPs connect inter-PIC routing with the PIC switching segments. B. This is the PIC output switching block. It connects the PIC switching segments and local clock lines to the PIO output and control signals. V. These CIPs break the px1, px2, and px5 routing at the middle of a PIC. The px2 and px5 CIP placement varies depending on the PLC. C. This is the system clock spine switching block and buffer. There is only one system clock spine per pair of PICs. Its inputs can come from the PIC switching segments or any of the eight PIO inputs in a PIC pair. W. These mutually exclusive buffers can drive one long line signal onto a PIC local clock routing segment. D. PIC switching segments (pSW). These routing segments are used to interconnect routing resources within the PIC and to a lesser degree, between PICs. E. px1 routing segments. The PIC x1 routing segments traverse one PIC and break at a CIP in the middle of each PIC. F. px2 routing segments. The PICs have routing that traverses two PICs between breaks. The breaks are staggered among the five px2 segments. X. These mutually exclusive buffers can select a source from one of the local system clock routes to drive the PIO 3-state control signal. Y. These are the four local system clock routing segments. Two come from connections within the PIC, one from the other PIC in the pair, and one from the adjacent PLC. Z. These mutually exclusive buffers allow a signal on the PIC switching segments to be routed to a system clock spine or to a PIO system clock. AA. ExpressCLK routing line. AB. System clock spine. G. px5 routing segments. Each of the ten PIC x5 routing segments traverses five PICs in between breaks at a CIP. Two px5 segments break in each PIC. AC. These various groups of CIPs connect routing resources from the adjacent PLC to the inter-PIC routing resources. H. pxH routing segments. The eight PIC xH routing segments traverse half of the array and break at CIPs in the interquad routing region that is in the middle of the array. AD. These buffers provide connectivity between the PLC xL (xH) lines and the PIC xL (xH) lines or connectivity between one of the IN2 routing segments and the PIC and/or PLC xL (xH) routing segments. I. (Not used intentionally for clarity.) J. pxL routing segments. The PIC long lines run the entire length of the side of the array. K. x5 routing segments from the adjacent PLC routing. L. xL routing segments from the adjacent PLC routing. M. x1 routing segments from the adjacent PLC routing. N. Switching segments from the adjacent PLC routing. AE. These mutually exclusive buffers and CIPs provide connectivity to the PLC xL and xH lines from one of the IN2 input segments. AF. These buffers allow the IN2 signals to drive onto the BIDI routing of the adjacent PLC, or the BIDI routing of the adjacent PLC, and the PIC switching segments and/or PIC half lines may be connected. O. xH routing segments from the adjacent PLC routing. Lattice Semiconductor 43 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs P O AB AD Q D D D D E F G H AD K W AC T J L A K AE M R A N T U B V Y Z U J X AC M A R Q R A W C AA H AC AE SE L D E IS C C T O D N E TI VI N C U E ED S T AF S Programmable Input/Output Cells (continued) 5-5823(F) Figure 27. PIC Architecture 44 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs High-Level Routing Resources The high-level routing resources in the ORCA Series 3 devices are interquad routing, corner cell routing, and PIC interquad routing. These resources and their related structures are discussed in the following subsections. SE L D E IS C C T O D N E TI VI N C U E ED S Interquad Routing In the ORCA Series 3 devices, the PLC array is split into four equal quadrants. In between these quadrants, routing has been added to route signals between the quadrants and distribute clocks. In addition to general routing, there are four specialized clock routing spines. The general routing is discussed below, followed by the special clock routing. One of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and control signals. There are two types of interquad blocks: vertical and horizontal. Vertical interquad blocks (vIQ) run between quadrants on the left and right, while horizontal interquad blocks (hIQ) run between top and bottom quadrants. Interquad lines begin and end in the MID cells that are discussed later. Since hIQ and vIQ blocks have the same logic, only the hIQ block is described below. The interquad routing connects to x5 and xH segments. It does not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether PLC-PLC connections cross quadrants or not. Figure 28 presents a (not to scale) view of interquad routing. TMID vIQ8[4:0] vIQ6[4:0] vIQ4[4:0] vIQ2[4:0] vIQ0[4:0] FAST CLOCK T 5 5 5 5 5 FAST CLOCK L hIQ9[4:0] hIQ7[4:0] hIQ5[4:0] hIQ3[4:0] hIQ1[4:0] hIQ8[4:0] hIQ6[4:0] hIQ4[4:0] hIQ2[4:0] hIQ0[4:0] FAST CLOCK R 5 5 5 5 5 RMID FAST CLOCK B vIQ9[4:0] vIQ7[4:0] vIQ5[4:0] vIQ3[4:0] vIQ1[4:0] LMID 5 5 5 5 5 5 5 5 5 5 BMID 5-4538(F) Figure 28. Interquad Routing Lattice Semiconductor 45 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs High-Level Routing Resources (continued) Programmable Corner Cell Routing Programmable Routing The programmable corner cell (PCC) contains the circuitry to connect the routing of the two PICs in each corner of the device. The PIC px1 and px2 segments and eight PIC switching segments are directly connected together from one PIC to another. The px5 lines are all broken with CIPs and the PIC pxL and pxH segments are connected from one block to another through programmable buffers. SE L D E IS C C T O D N E TI VI N C U E ED S Figure 29 shows the connections from the interquad routing to the inter-PLC routing for a block of the horizontal interquad. The vertical interquad has similar connections. The connections shown in Figure 29 are made with PLCs located above and below the routing shown in the figure. The interquad routing segments, prefixed IH for interquad horizontal, are in ten groups of five lines. Any one line from each group can be routed to one of the xH segments from the top of the device (left for vertical interquad), one of the xH segments from the bottom of the device (right for vertical interquad), and one of the x5 segments crossing the interquad. device. Fast clocks and other clock resources are discussed in the Clock Distribution Network section. Figure 28 shows four fast middle clock (fast clock) signals with the suffixes T (top), B (bottom), R (right), and L (left), respectively. Figure 29 also shows the fast clock R and fast clock L lines; these are dedicated interquad clock spines. They originate in the CLKCNTRL special function blocks in the middle of each edge of the device, with the name referencing the edge of origin. For example, fast clock R originates in the CLKCNTRL block on the right edge of a device. Fast clock spines traverse the entire PLC array but do not connect to the PICs on the edge of the device opposite to the source. Each fast clock line connects to two of the xL lines in each PLC that run orthogonally to the fast clock. These connections allow the fast clock lines to generate a clock tree that can reach any PLC in the Corner Cell Special Functions In addition to routing functions, special-purpose functions are located in each FPGA corner. The upper-left PCC contains connections to the boundary-scan logic and microprocessor interface. The upper-right PCC contains connections to the readback logic, connectivity to the global 3-state signal (TS_ALL), and a programmable clock manager. The lower-left PCC contains connections to the internal oscillator and a programmable clock manager. The lower-right PCC contains connections to the start-up and global reset logic. These functions are all more completely described in the Special Function Blocks section of this data sheet. IH0[4:0] IH1[4:0] IH2[4:0] IH3[4:0] IH4[4:0] FAST CLOCK R FAST CLOCK L IH5[4:0] IH6[4:0] IH7[4:0] IH8[4:0] IH9[4:0] BL[9:0] vxL[9:0] vx5[9:0] vx1[9:0] SUL[9:0] vx1[9:0] FAST CARRY vck vxH[9:0] BL[9:0] 5-5821(F) Figure 29. hIQ Block Detail 46 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs High-Level Routing Resources (continued) PIC Interquad (MID) Routing SE L D E IS C C T O D N E TI VI N C U E ED S There is also connectivity between the PICs in each quadrant, as well as a clock control (CLKCNTRL) module (discussed in the Special Function Blocks section) between the PIC routing and the interquad routing. These blocks are called LMID (left), TMID (top), RMID (right), and BMID (bottom). The TMID routing is shown in Figure 30. As with the hIQ and vIQ blocks, the only connectivity to the PIC routing is to the global pxH and px5 segments. The pxH segments from the one quadrant can be connected through a CIP to its counterpart in the opposite quadrant, providing a path that spans the array of PICs. Since a passive CIP is used to connect the two pxH segments, a 3-state signal can be routed on the two pxH segments in the opposite quadrants, and then connected through this CIP. As with the hIQ and vIQ blocks, CIPs and buffers allow nibble-wide connections between the interquad segments, the xH segments, and the x5 segments. SHUTOFF EXPRESSCLK LEFT EXPRESSCLK RIGHT PIC LOCAL CLOCKS FROM RIGHT PIC LOCAL CLOCKS FROM LEFT pxL[9:0] pxH[7:0] px5[9:0] px2[4:0] px1[4:0] pSW[7:4] pSW[3:0] pSW[7:4] pSW[3:0] in2[A:D] FROM LEFT in[A:D] FROM RIGHT 1v0xL[2] 1v0xL[0] Iv1xL[3] Iv1xL[1] Iv2xL[0] Iv2xL[2] Iv3xL[1] Iv3xL[3] Iv4xL[3] Iv4xL1] Iv5xL[2] Iv5xL[0] FAST CLOCK Iv6xL[3] Iv6xL[1] Iv7xL[2] Iv7xL[0] 1v8xL[3] 1v9xL[4] CORNER ExpressCLK 5-5822(F) Figure 30. Top (TMID) Routing Lattice Semiconductor 47 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Clock Distribution Network SE L D E IS C C T O D N E TI VI N C U E ED S The Series 3 FPGAs provide three types of highspeed, low-skew clock distributions: system clock, fast middle clock (fast clock), and ExpressCLK. Because of the great variety of sources and distribution for clock signals in the ORCA Series 3, the clock mechanisms will be described here from the inside out. The clock connections to the PFU will be described, followed by clock distribution to the PLC array, clock sources to the PLC array, and finally ending with clock sources and distribution in the PICs. The ExpressCLK inputs are new, dedicated clock inputs in Series 3 FPGAs. They are mentioned in several of the clock network descriptions and are described fully later in this section. is generated from the PLC to the left or right of the current PLC, and one is generated from the PLC above or below the current PLC. The selection decision as to where these signals come from, above/below and left/ right, is based on the position of the PLC in the array and has to do with the alternating nature of the source of the system clock spines (discussed later). The last of the five clock sources is also generated within the PLC. The E1 control signal, described in the PLC Routing Resources section, can drive the PFU clock. The E1 signal can come from any xBID routing resource in the PLC. The selection and switching of clock signals in a PLC is performed in the FINS. Figure 31 shows the PFU clock sources for a set of four adjacent PLCs. PFU Clock Sources Within a PLC there are five sources for the clock signal of the latches/FFs in the PFU. Two of the signals are generated off of the long lines (xL) within the PLC: one from the set of vertical long lines and one from the set of horizontal long lines. For each of these signals, any one of the ten long lines of each set, vertical or horizontal, can generate the clock signal. Two of the five PFU clock sources come from neighboring PLCs. One clock vxL[9:0] Global Control Signals The four clock signals in each PLC that are generated from the long lines (xL) in the current PLC or an adjacent PLC can also be used to drive the PFU clock enable (CE), local set/reset (LSR) and add/subtract/ write enable (ASWE) signals. The clock signals generated from vertical long lines can drive CE and ASWE, and the clocks generated from horizontal long lines can drive LSR. This allows for low-skew global distribution of two of these three control signals with the clock routing while still allowing a global clock route to occur. vxL[9:0] PLC PLC PFU PFU E1 E1 hxL[9:0] PLC PLC PFU E1 PFU E1 hxL[9:0] 5-6054(F) Figure 31. PFU Clock Sources 48 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Clock Distribution Network (continued) Clock Distribution in the PLC Array System Clock (SCLK) SE L D E IS C C T O D N E TI VI N C U E ED S The clock distribution network, or clock spine network, within the PLC array is designed to minimize clock skew while maximizing clock flexibility. Clock flexibility is expressed in two ways: the ease with which a single clock is routed to the entire array, and the capability to provide multiple clocks to the PLC array. The clock spine structure previously described provides for complete distribution of a clock from any I/O pin to the entire PLC array by means of a single clock spine and long lines (xL). This distribution system also provides a means to have many different clocks routed to many different and dispersed locations in the PLC array. Each spine can carry a different clock signal, so for the OR3T55 (which has an 18 x 18 array of PLCs, implying nine clock spines per side), 36 input clock signals can be supported using the system clock network. There is one horizontal and one vertical clock spine passing through each PLC. The horizontal clock spine is sourced from the PIC in the same row on either the left- or right-hand side of the array, with the source side (left or right) alternating for each row. The vertical clock spines are similarly sourced from the PICs alternating from the top or bottom of a column. Each clock spine is capable of driving one of the ten xL routing segments that run orthogonal to it within each PLC. Full connectivity to all PFUs is maintained due to the connectivity from the xL lines to the PFU clock signals described in the previous section; however, only an xL line in every other row (column) needs to be driven to allow the given clock signal to be distributed to every PFU. Figure 32 is a high-level diagram of the Series 3 system clock spine network with sample xL line connections for a 4 x 4 array of PLCs. Fast Clock Fast clocks are high-speed, low-skew clock spines that originate from the CLKCNTRL special function blocks (described later). There are four fast clock spines--one originating on the middle of each edge of the array. The spines run in the interquad region of the PLC array from their source side of the device to the last row or column on the opposite side of the device. The fast clocks connect to two long lines, xL[8] and xL[9], that run orthogonal to the spine direction in each PLC. These long lines can then be connected to the PFU clock input in the same manner as the general system clocks, and, like the system clock connections, xL lines are only needed in every other row (column) to distribute a clock to every PFU. The limited number of longline connections and the low skew of the CLKCNTRL source combine to make the fast clocks a very robust, low-skew clock source. UNUSED SCLK SPINE VERTICAL SCLK SPINE UNUSED SCLK SPINE UNUSED SCLK SPINE (xL) HORIZONTAL SCLK SPINE (xL) UNUSED SCLK SPINE UNUSED SCLK SPINE (xL) UNUSED SCLK SPINE (xL) UNUSED SCLK SPINE (xL) UNUSED SCLK SPINE 5-5801(F).a Figure 32. ORCA Series 3 System Clock Distribution Overview Lattice Semiconductor 49 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Clock Distribution Network (continued) Clocks in the PICs Clock Sources to the PLC Array Because the Series 3 FPGAs have latches and FFs in the I/Os, it is necessary to have clock signal distribution to the PIOs as well as in the PLC array. The system clock, the fast clock, and the ExpressCLK are available for PIO clocking. SE L D E IS C C T O D N E TI VI N C U E ED S The source of a clock that is globally available to the PLC array can be from any user I/O pad, any of the ExpressCLK pads, or an internally generated source. System Clock PIC System Clock As described in the Programmable Input/Output Cells section, PICs are grouped in adjacent pairs. Any one of the eight pads in a PIC pair can drive a clock spine in a row or column. For PIC pairs on the top of the chip, the column associated with the left PIC has the clock spine, for pairs on the bottom, the right PIC column has the spine. The top PIC of the pair sources the spine from the left side of the array, and the bottom PIC of the pair sources the spine from the right side of the array. Clock delay and skew are minimized by having a single clock buffer per pair of PICs. The clock spine for each pair can also be driven by one of the four PIC switching segments (pSW) in each PIC of the pair. This allows a signal generated in the PLC array to be routed onto the global clock spine network. The system clock output of the programmable clock manager (PCM) may also be routed to the global system clock spines via the pSW segments. Figure 33 shows the clock spine multiplexing structure for a pair of PICs on the top of the array. There are five local system clock lines in each PIC. Much like the sources for a clock in the PFU, two of the local PIC clocks are generated within the PIC from long lines. One is generated from the set of ten PIC long lines (pxL) that runs parallel to the PICs on a side, and the other is generated from the set of ten long lines (xL) from the PLC array that terminate in the PIC. Another local PIC system clock route comes from the set of ten xL lines in the adjacent PLC that is parallel to the side of the array on which the PIC resides. The fourth local PIC system clock route comes from the set of ten long lines (xL) from the PLC array that terminate in the adjacent PIC that is not part of the same PIC pair. Much like the E1 signals in the PLCs that are used to distribute a local clock to the PFU source, the fifth local clock line in each PIC comes from local pSW signals. This clock signal for each PIC is shown in Figure 33. One of these five local PIC system clocks is selected for the system clock signal in the PIO. It is used as the PIO system clock for both input and output clocking as selected within the PIO. All PIOs in a PIC share the same system clock. Fast Clock PAD A PAD B PAD C PAD D pSW[4] pSW[5] pSW[6] pSW[7] The fast clock spines are sourced to the PLC array from each side of the device by the ExpressCLK pads via the CLKCNTRL function block (described in the Special Function Blocks section). The ExpressCLK and fast clock source from the pads is shown in Figure 34 and will be described further in the ExpressCLK Inputs subsection. PIC ExpressCLK The ExpressCLK signal used at the PIC latches/FFs comes from the CLKCNTRL function block that resides in the middle of the side on which the PIC resides. A single signal comes from the CLKCNTRL and is driven by separate buffers onto two ExpressCLK long wires. One of these ExpressCLK signals goes to the PICs on the right of (above) the CLKCNTRL block, and the other ExpressCLK signal goes to the PICs on the left of (below) the CLKCNTRL block on that side. PAD A PAD B PAD C PAD D pSW[4] pSW[5] pSW[6] pSW[7] TO LOCAL CLOCKS TO LOCAL CLOCKS SPINE TPICL TPICR 5-5800(F) Figure 33. PIC System Clock Spine Generation 50 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Clock Distribution Network (continued) ExpressCLK Inputs SE L D E IS C C T O D N E TI VI N C U E ED S There are four dedicated ExpressCLK pads on each Series 3 device: one in the middle of each side. Two other user I/O pads can also be used as corner ExpressCLK inputs, one on the lower-left corner, and one on the upper-right corner. The corner ExpressCLK pads feed the ExpressCLK to the two sides of the array that are adjacent to that corner, always driving the same signal in both directions. The ExpressCLK route from the middle pad and from the corner pad associated with that side are multiplexed and can be glitchlessly stopped/started under user control using the StopCLK feature of the CLKCNTRL function block (described under Special Function Blocks) on that side. The ExpressCLK output of the programmable clock manager (PCM) is programmably connected to the corner ExpressCLK routes. PCM blocks are found in the same corners as the corner ExpressCLK signals and are described in the Special Function Blocks section. The ExpressCLK structure is shown in Figure 34 (PCM blocks are not shown). pin is completely arbitrary, but using a pin that is near the center of an edge of the device will provide the lowest skew system clock network. The pin-to-pin timing numbers in the Timing Characteristics section assume that the clock pin is in one of the PICs at the center of any side of the device next to an ExpressCLK pad. For actual timing characteristics for a given clock pin, use the timing analyzer results from ispLEVER. CLKCNTRL BLOCK EXPRESSCLK PADS FAST CLOCKS EXPRESSCLKS TO PIOs 5-5802(F) Note: All multiplexers are set during configuration. Figure 34. ExpressCLK and Fast Clock Distribution Selecting Clock Input Pins Any user I/O pin on an ORCA FPGA can be used as a fast, low-skew system clock input. Since the four dedicated ExpressCLK inputs can only be used to distribute global signals into the FPGA, these pins should be selected first as clock pins. Within the interquad region of the device, these clocks sourced by the ExpressCLK inputs are called fast clocks. Choosing the next clock Lattice Semiconductor To select subsequent clock pins, certain rules should be followed. As discussed in the Programmable Input/ Output Cells section, PICs are grouped into adjacent pairs. Each of these pairs contains eight I/Os, but only one of the eight I/Os in a PIC pair can be routed directly onto a system clock spine. Therefore, to achieve top performance, the next clock input chosen should not be one of the pins from a PIC pair previously used for a clock input. If it is necessary to have a second input in the same PIC pair route onto global system clock routing, the input can be routed to a free clock spine using the PIC switching segment (pSW) connections to the clock spine network at some small sacrifice in speed. Alternatively, if global distribution of the secondary clock is not required, the signal can be routed on long lines (xL) and input to the PFU clock input without using a clock spine. Another rule for choosing clock pins has to do with the alternating nature of clock spine connections to the xL and pxL routing segments. Starting at the left side of the device, the first vertical clock spine from the top connects to hxL[0] (horizontal xL[0]), and the first vertical clock spine from the bottom connects to hxL[5] in all PLC rows. The next vertical clock spine from the top connects to hxL[1], and the next one from the bottom connects to hxL[6]. This progression continues across the device, and after a spine connects to hxL[9], the next spine connects to hxL[0] again. Similar connections are made from horizontal clock spines to vxL (vertical xL) lines from the top to the bottom of the device. Because the ORCA Series 3 clock routing only requires the use of an xL line in every other row or column, even two inputs chosen 20 PLCs apart on the same xL line will not conflict, but it is always better to avoid these choices, if possible. The fast clock spines in the interquad routing region also connect to xL[8] and xL[9] for each set of xL lines, so it is better to avoid user I/Os that connect to xL[8] or xL[9] when a fast clock is used that might share one of these connections. Another reason to use the fast clock spines is that since they use only the xL[9:8] lines, they will not conflict with internal data buses which typically use xL[7:0]. For more details on clock selection, refer to application notes on clock distribution in ORCA Series 3 devices. 51 ORCA Series 3C and 3T FPGAs Special Function Blocks Readback can be performed via the Series 3 microprocessor interface (MPI) or by using dedicated FPGA readback controls. If the MPI is enabled, readback via the dedicated FPGA readback logic is disabled. Readback using the MPI is discussed in the Microprocessor Interface (MPI) section. The pins used for dedicated readback are readback data (RD_DATA), read configuration (RD_CFG), and configuration clock (CCLK). A readback operation is initiated by a high-to-low transition on RD_CFG. The RD_CFG input must remain low during the readback operation. The readback operation can be restarted at frame 0 by driving the RD_CFG pin high, applying at least two rising edges of CCLK, and then driving RD_CFG low again. One bit of data is shifted out on RD_DATA at the rising edge of CCLK. The first start bit of the readback frame is transmitted out several cycles after the first rising edge of CCLK after RD_CFG is input low (see the Readback Timing Characteristics table in the Timing Characteristics section). To be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. SE L D E IS C C T O D N E TI VI N C U E ED S Special function blocks in the Series 3 provide extra capabilities beyond general FPGA operation. These blocks reside in the corners and MIDs (middle interquad areas) of the FPGA array. Data Sheet November 2006 Single Function Blocks Most of the special function blocks perform a specific dedicated function. These functions are data/configuration readback control, global 3-state control (TS_ALL), internal oscillator generation, global set/reset (GSRN), and start-up logic. Readback Logic The readback logic is located in the upper right corner of the FPGA and can be enabled via a bit stream option or by instantiation of a library readback component. Readback is used to read back the configuration data and, optionally, the state of the PFU outputs. A readback operation can be done while the FPGA is in normal system operation. The readback operation cannot be daisy-chained. To use readback, the user selects options in the bit stream generator in the ispLEVER Development System. Table 12 provides readback options selected in the bit stream generator tool. The table provides the number of times that the configuration data can be read back. This is intended primarily to give the user control over the security of the FPGA's configuration program. The user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (U). Table 12. Readback Options Option 52 Function 0 Prohibit Readback 1 Allow One Readback Only U Allow Unrestricted Number of Readbacks Readback can be initiated at an address other than frame 0 via the new microprocessor interface (MPI) control registers (see the Microprocessor Interface (MPI) section for more information). In all cases, readback is performed at sequential addresses from the start address. It should be noted that the RD_DATA output pin is also used as the dedicated boundary-scan output pin, TDO. If this pin is being used as TDO, the RD_DATA output from readback can be routed internally to any other pin desired. The RD_CFG input pin is also used to control the global 3-state (TS_ALL) function. Before and during configuration, the TS_ALL signal is always driven by the RD_CFG input and readback is disabled. After configuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. If used as the RD_CFG input for readback, the internal TS_ALL input can be routed internally to be driven by any input pin. Lattice Semiconductor Data Sheet November 2006 Special Function Blocks (continued) The following occur when TS_ALL is activated: 1. All of the user I/O output buffers are 3-stated, the user I/O input buffers are pulled up (with the pulldown disabled), and the input buffers are configured with TTL input thresholds (OR3Cxx only). 2. The TDO/RD_DATA output buffer is 3-stated. SE L D E IS C C T O D N E TI VI N C U E ED S The readback frame contains the configuration data and the state of the internal logic. During readback, the value of all registered PFU and PIC outputs can be captured. The following options are allowed when doing a capture of the PFU outputs. ORCA Series 3C and 3T FPGAs 1. Do not capture data (the data written to the RAMs, usually 0, will be read back). 3. The RD_CFG, RESET, and PRGM input buffers remain active with a pull-up. 2. Capture data upon entering readback. 4. The DONE output buffer is 3-stated, and the input buffer is pulled up. 3. Capture data based upon a configurable signal internal to the FPGA. If this signal is tied to logic 0, capture RAMs are written continuously. Internal Oscillator 4. Capture data on either options 2 or 3 above. The readback frame has an identical format to that of the configuration data frame, which is discussed later in the Configuration Data Format section. If LUT memory is not used as RAM and there is no data capture, the readback data (not just the format) will be identical to the configuration data for the same frame. This eases a bitwise comparison between the configuration and readback data. The configuration header, including the length count field, is not part of the readback frame. The readback frame contains bits in locations not used in the configuration. These locations need to be masked out when comparing the configuration and readback frames. The development system optionally provides a readback bit stream to compare to readback data from the FPGA. Also note that if any of the LUTs are used as RAM and new data is written to them, these bits will not have the same values as the original configuration data frame either. Global 3-State Control (TS_ALL) To increase the testability of the ORCA Series FPGAs, the global 3-state function (TS_ALL) disables the device. The TS_ALL signal is driven from either an external pin or an internal signal. Before and during configuration, the TS_ALL signal is driven by the input pad RD_CFG. After configuration, the TS_ALL signal can be disabled, driven from the RD_CFG input pad, or driven by a general routing signal in the upper right corner. Before configuration, TS_ALL is active-low; after configuration, the sense of TS_ALL can be inverted. Lattice Semiconductor The internal oscillator resides in the lower left corner of the FPGA array. It has output clock frequencies of 1.25 MHz and 10 MHz. The internal oscillator is the source of the internal CCLK used for configuration. It may also be used after configuration as a generalpurpose clock signal. Global Set/Reset (GSRN) The GSRN logic resides in the lower right corner of the FPGA. GSRN is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ FFs on the device. GSRN is automatically asserted at powerup and during configuration of the device. The timing of the release of GSRN at the end of configuration can be programmed in the start-up logic described below. Following configuration, GSRN may be connected to the RESET pin via dedicated routing, or it may be connected to any signal via normal routing. Within each PFU and PIO, individual FFs and latches can be programmed to either be set or reset when GSRN is asserted. A new option in Series 3 allows individual PFUs and PIOs to turn off the GSRN signal to its latches/FFs after configuration. The RESET input pad has a special relationship to GSRN. During configuration, the RESET input pad always initiates a configuration abort, as described in the FPGA States of Operation section. After configuration, the global set/reset signal (GSRN) can either be disabled (the default), directly connected to the RESET input pad, or sourced by a lower-right corner signal. If the RESET input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. 53 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) Start-Up Logic SE L D E IS C C T O D N E TI VI N C U E ED S The start-up logic block is located in the lower right corner of the FPGA. This block can be configured to coordinate the relative timing of the release of GSRN, the activation of all user I/Os, and the assertion of the DONE signal at the end of configuration. If a start-up clock is used to time these events, the start-up clock can come from CCLK, or it can be routed into the startup block using lower right corner routing resources. These signals are described in the Start-Up subsection of the FPGA States of Operation section. The source clock for the CLKCNTRL block comes either from the ExpressCLK pad at the middle of the side of the FPGA or from the corner ExpressCLK route that comes from the corner ExpressCLK pad (at the lower left or upper right of the device, whichever is closer). The programmable clock manager ExpressCLK output can also be sourced to this corner routing for distribution at the two closest CLKCNTRL blocks. Clock Control (CLKCNTRL) and StopCLK There is one CLKCNTRL block in the MID section of the interquad routing on each side of the FPGA. This block is used to selectively distribute the fast clock to the PLC array and the left (top) and right (bottom) ExpressCLKs (ECKL and ECKR) to the side of the array on which the CLKCNTRL block resides. Each CLKCNTRL block also features an invertible StopCLK shutoff input that is available from local routing. This feature may be used to glitchlessly stop and start the clock at the three outputs of each CLKCNTRL block and has the option of doing so on either the rising or falling edge of the clock. When the clock is halted based on its rising edge, it stops and stays at VDD. When it is stopped based on its falling edge, it stops and stays at GND. If the StopCLK shutoff signal meets the CLKCNTRL setup and hold times, the clock is stopped on the second clock cycle after the shutoff signal. A diagram of the bottom CLKCNTRL block and StopCLK timing is shown in Figure 35. CORNER EXPRESSCLK CLOCK SHUTOFF EXPRESSCLK LEFT EXPRESSCLK RIGHT FAST CLOCK OFF_SET OFF_SET OFF_HLD OFF_HLD CLOCK SHUTOFF CLKCNTRL OUTPUT CLOCKS 5-5981(F) Notes: CLKCNTRL output clocks are ExpressCLK left and right and fast clock. Clock shutoff shown active-high acting on clock falling edge. Figure 35. Top CLKCNTRL Function Block 54 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) s TMS TDI TCK TDO Boundary Scan net b U2 The increasing complexity of integrated circuits (ICs) and IC packages has increased the difficulty of testing printed-circuit boards (PCBs). To address this testing problem, the IEEE standard 1149.1/D1 (IEEE Standard Test Access Port and Boundary-Scan Architecture) is implemented in the ORCA series of FPGAs. It allows users to efficiently test the interconnection between integrated circuits on a PCB as well as test the integrated circuit itself. The IEEE 1149.1/D1 standard is a well-defined protocol that ensures interoperability among boundary-scan (BSCAN) equipped devices from different vendors. TMS TDI TCK TDO net a U2 SE L D E IS C C T O D N E TI VI N C U E ED S net c TMS TDI TCK TDO Figure 37 provides a system interface for components used in the boundary-scan testing of PCBs. The three major components shown are the test host, boundaryscan support circuit, and the devices under test (DUTs). The DUTs shown here are ORCA Series FPGAs with dedicated boundary-scan circuitry. The test host is normally one of the following: automatic test equipment (ATE), a workstation, a PC, or a microprocessor. Lattice Semiconductor TMS TDI TCK TDO U3 U4 SEE ENLARGED VIEW BELOW The IEEE 1149.1/D1 standard defines a test access port (TAP) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of integrated circuits in a system. The ORCA Series FPGA provides four interface pins: test data in (TDI), test mode select (TMS), test clock (TCK), and test data out (TDO). The PRGM pin used to reconfigure the device also resets the boundary-scan logic. The user test host serially loads test commands and test data into the FPGA through these pins to drive outputs and examine inputs. In the configuration shown in Figure 36, where boundary scan is used to test ICs, test data is transmitted serially into TDI of the first BSCAN device (U1), through TDO/TDI connections between BSCAN devices (U2 and U3), and out TDO of the last BSCAN device (U4). In this configuration, the TMS and TCK signals are routed to all boundary-scan ICs in parallel so that all boundary-scan components operate in the same state. In other configurations, multiple scan paths are used instead of a single ring. When multiple scan paths are used, each ring is independently controlled by its own TMS and TCK signals. TDI TMS TCK TDO TDO TCK TMS TDI PT[ij] TAPC BSC BDC DCC SCAN IN BYPASS REGISTER INSTRUCTION REGISTER p_in p_ts p_out SCAN OUT BSC DCC SCAN IN p_ts p_in PLC ARRAY p_out BDC PL[ij] SCAN OUT p_out BSC BDC PR[ij] DCC p_in p_ts SCAN IN SCAN OUT p_out p_ts SCAN OUT p_in BSC DCC BDC SCAN IN PB[ij] 5-5972(F) Key: BSC = boundary-scan cell, BDC = bidirectional data cell, and DCC = data control cell. Figure 36. Printed-Circuit Board with BoundaryScan Circuitry 55 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) D[7:0] D[7:0] TDO TDI TDO ORCA SERIES FPGA TDO ORCA SERIES FPGA SE L D E IS C C T O D N E TI VI N C U E ED S BOUNDARYSCAN MASTER TDI MICROPROCESSOR INTR CE RA R/W DAV INT SP TMS0 TCK (BSM) TMS (DUT) TCK TMS (DUT) TCK TDI TDI TDO ORCA SERIES FPGA TMS (DUT) TCK 5-6765(F) Figure 37. Boundary-Scan Interface The boundary-scan support circuit shown in Figure 37 is the 497AA Boundary-Scan Master (BSM). The BSM off-loads tasks from the test host to increase test throughput. To interface between the test host and the DUTs, the BSM has a general microprocessor interface and provides parallel-to-serial/serial-to-parallel conversion, as well as three 8K data buffers. The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. The PCbased boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. Table 13. Boundary-Scan Instructions Code 000 001 010 011 100 101 110 111 Instruction EXTEST PLC Scan Ring 1 (PSR1)/USERCODE RAM Write (RAM_W) IDCODE SAMPLE/PRELOAD PLC Scan Ring 2 (PSR2) RAM Read (RAM_R) BYPASS Boundary-Scan Instructions The ORCA Series boundary-scan circuitry is used for three mandatory IEEE 1149.1/D1 tests (EXTEST, SAMPLE/PRELOAD, BYPASS), the optional IEEE 1149.1/D1 IDCODE instruction, and five ORCA-defined instructions. The 3-bit wide instruction register supports the nine instructions listed in Table 13, where the use of PSR1 or USERCODE is selectable by a bit stream option. 56 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) SE L D E IS C C T O D N E TI VI N C U E ED S The external test (EXTEST) instruction allows the interconnections between ICs in a system to be tested for opens and stuck-at faults. If an EXTEST instruction is performed for the system shown in Figure 36, the connections between U1 and U2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether the same value is seen at the other device. This is determined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the BSR until each one aligns to the appropriate pin. Then, based upon the value of the 3-state signal, either the I/O pad is driven to the value given in the BSR, or the BSR is updated with the input value from the I/O pad, which allows it to be shifted out TDO. operation or written during test operation. The data for all of the I/Os is captured simultaneously into the BSR, allowing them to be shifted-out TDO to the test host. Since each I/O buffer in the PICs is bidirectional, two pieces of data are captured for each I/O pad: the value at the I/O pad and the value of the 3-state control signal. For preload operation, data is written from the BSR to all of the I/Os simultaneously. The SAMPLE/PRELOAD instruction is useful for system debugging and fault diagnosis by allowing the data at the FPGA's I/Os to be observed during normal There are five ORCA-defined instructions. The PLC scan rings 1 and 2 (PSR1, PSR2) allow user-defined internal scan paths using the PLC latches/FFs. The RAM_Write Enable (RAM_W) instruction allows the user to serially configure the FPGA through TDI. The RAM_Read Enable (RAM_R) allows the user to read back RAM contents on TDO after configuration. The IDCODE instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at TDO. The IDCODE format is shown in Table 14. Table 14. Boundary-Scan ID Code Device Version (4 bits) OR3T20 Part* (10 bits) Family (6 bits) Manufacturer (11 bits) LSB (1 bit) 0000 0011000000 110000 00000011101 1 OR3T30 0000 0111000000 110000 00000011101 1 OR3T55 0000 0100100000 110000 00000011101 1 OR3C/T80 0000 0110100000 110000 00000011101 1 OR3T125 0000 0011100000 110000 00000011101 1 * PLC array size of FPGA, reverse bit order. Note: Table assumes version 0. Lattice Semiconductor 57 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) the BSR (which requires a two FF delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. ORCA Boundary-Scan Circuitry The boundary-scan logic is enabled before and during configuration. After configuration, a configuration option determines whether or not boundary-scan logic is used. SE L D E IS C C T O D N E TI VI N C U E ED S The ORCA Series boundary-scan circuitry includes a test access port controller (TAPC), instruction register (IR), boundary-scan register (BSR), and bypass register. It also includes circuitry to support the four predefined instructions. The 32-bit boundary-scan identification register contains the manufacturer's ID number, unique part number, and version (as described earlier). The identification register is the default source for data on TDO after RESET if the TAP controller selects the shiftdata-register (SHIFT-DR) instruction. If boundary scan is not used, TMS, TDI, and TCK become user I/Os, and TDO is 3-stated or used in the readback operation. Figure 38 shows a functional diagram of the boundaryscan circuitry that is implemented in the ORCA Series. The input pins' (TMS, TCK, and TDI) locations vary depending on the part, and the output pin is the dedicated TDO/RD_DATA output pad. Test data in (TDI) is the serial input data. Test mode select (TMS) controls the boundary-scan test access port controller (TAPC). Test clock (TCK) is the test clock on the board. An optional USERCODE is available if the boundaryscan PSR1 instruction is not used. The selection between PSR1 and USERCODE is a configuration option and can be performed in ispLEVER. The USERCODE is an 11-bit value that the user can set during device configuration and can be written to and read from the FPGA via the boundary-scan logic. The USERCODE value replaces the manufacturer field of the boundary-scan ID code when the USERCODE instruction is issued, allowing users to have configured devices identified in a user-defined manner. The manufacturer ID field remains available when the IDCODE instruction is issued. The BSR is a series connection of boundary-scan cells (BSCs) around the periphery of the IC. Each I/O pad on the FPGA, except for CCLK, DONE, and the boundaryscan pins (TCK, TDI, TMS, and TDO), is included in the BSR. The first BSC in the BSR (connected to TDI) is located in the first PIC I/O pad on the left of the top side of the FPGA (PTA PIC). The BSR proceeds clockwise around the top, right, bottom, and left sides of the array. The last BSC in the BSR (connected to TDO) is located on the top of the left side of the array (PL1D). The bypass instruction uses a single FF, which resynchronizes test data that is not part of the current scan operation. In a bypass instruction, test data received on TDI is shifted out of the bypass register to TDO. Since I/O BUFFERS DATA REGISTERS BOUNDARY-SCAN REGISTER IDCODE REGISTER PSR1 REGISTER (PLCs) PSR2 REGISTER (PLCs) VDD TDI DATA MUX CONFIGURATION REGISTER (RAM_R, RAM_W) BYPASS REGISTER INSTRUCTION DECODER VDD RESET CLOCK DR SHIFT-DR UPDATE-DR TMS INSTRUCTION REGISTER SELECT ENABLE TAP CONTROLLER VDD TDO RESET CLOCK IR SHIFT-IR UPDATE-IR VDD TCK M U X PUR PRGM 5-5768(F) 58 Figure 38. ORCA Series Boundary-Scan Circuitry Functional Diagram Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) ORCA Series TAP Controller (TAPC) SE L D E IS C C T O D N E TI VI N C U E ED S The ORCA Series TAP controller (TAPC) is a 1149.1/ D1 compatible test access port controller. The 16 JTAG state assignments from the IEEE 1149.1/D1 specification are used. The TAPC is controlled by TCK and TMS. The TAPC states are used for loading the IR to allow three basic functions in testing: providing test stimuli (Update-DR), test execution (Run-Test/Idle), and obtaining test responses (Capture-DR). The TAPC allows the test host to shift in and out both instructions and test data/results. The inputs and outputs of the TAPC are provided in the table below. The outputs are primarily the control signals to the instruction register and the data register. The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. Table 15. TAP Controller Input/Outputs The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This sequences the TAPC through states in order to perform the desired function on the instruction register or a data register. Figure 39 provides a diagram of the state transitions for the TAPC. The next state is determined by the TMS input value. 1 TEST-LOGICRESET 0 RUN-TEST/ IDLE 0 Symbol TMS TCK PUR PRGM TRESET Select Enable Capture-DR Capture-IR Shift-DR Shift-IR Update-DR Update-IR I/O I I I I O O O O O O O O O Function Test Mode Select Test Clock Powerup Reset BSCAN Reset Test Logic Reset Select IR (High); Select-DR (Low) Test Data Out Enable Capture/Parallel Load-DR Capture/Parallel Load-IR Shift Data Register Shift Instruction Register Update/Parallel Load-DR Update/Parallel Load-IR 1 1 SELECTDR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR SHIFT-IR 1 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 1 0 1 SELECTIR-SCAN 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 5-5370(F) Figure 39. TAP Controller State Transition Diagram Lattice Semiconductor 59 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) Boundary-Scan Cells The TAPC signals (capture, update, shiftn, treset, and TCK) and the MODE signal control the operation of the BSC. The bidirectional data cell is also controlled by the high out/low in (HOLI) signal generated by the direction control cell. When HOLI is low, the bidirectional data cell receives input buffer data into the BSC. When HOLI is high, the BSC is loaded with functional data from the PLC. SE L D E IS C C T O D N E TI VI N C U E ED S Figure 40 is a diagram of the boundary-scan cell (BSC) in the ORCA series PICs. There are four BSCs in each PIC: one for each pad, except as noted above. The BSCs are connected serially to form the BSR. The BSC controls the functionality of the in, out, and 3-state signals for each pad. direction control cell is used to access the 3-state value. Both cells consist of a flip-flop used to shift scan data which feeds a flip-flop to control the I/O buffer. The bidirectional data cell is connected serially to the direction control cell to form a boundary-scan shift register. The BSC allows the I/O to function in either the normal or test mode. Normal mode is defined as when an output buffer receives input from the PLC array and provides output at the pad or when an input buffer provides input from the pad to the PLC array. In the test mode, the BSC executes a boundary-scan operation, such as shifting in scan data from an upstream BSC in the BSR, providing test stimuli to the pad, capturing test data at the pad, etc. The primary functions of the BSC are shifting scan data serially in the BSR and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. The BSC consists of two circuits: the bidirectional data cell is used to access the input and output data, and the The MODE signal is generated from the decode of the instruction register. When the MODE signal is high (EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE), functional data from the FPGA's internal logic is propagated to the output buffer. The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the ispLEVER CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information. SCAN IN I/O BUFFER PAD_IN p_in PAD_OUT BIDIRECTIONAL DATA CELL 0 0 0 D 1 Q D Q 1 PAD_TS 1 p_out HOLI 0 0 p_ts D Q D Q 1 1 DIRECTION CONTROL CELL SHIFTN/CAPTURE TCK SCAN OUT UPDATE/TCK MODE 5-2844(F Figure 40. Boundary-Scan Cell 60 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) Boundary-Scan Timing SE L D E IS C C T O D N E TI VI N C U E ED S To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum frequency allowed for TCK is 10 MHz. RUN-TEST/IDLE UPDATE-IR EXIT1-IR SHIFT-IR EXIT2-IR PAUSE-IR EXIT1-IR SHIFT-IR CAPTURE-IR SELECT-IR-SCAN SELECT-DR-SCAN RUN-TEST/IDLE TEST-LOGIC-RESET Figure 41 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is clocked into the DUT on the rising edge. TCK TMS TDI 5-5971(F) Figure 41. Instruction Register Scan Timing Diagram Lattice Semiconductor 61 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) The control portion of the microprocessor interface is available following powerup of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet configured. The mode pin (M[2:0]) settings can be found in the FPGA Configuration Modes section of this data sheet, and the setup and use of the MPI for configuration is discussed in the MPI Setup and Control subsection. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ORCA macro library, or by setting the MP_USER bit of the MPI configuration control register prior to the start of configuration (MPI registers are discussed later). SE L D E IS C C T O D N E TI VI N C U E ED S The Series 3 FPGAs have a dedicated synchronous microprocessor interface function block (see Figure 42). The MPI is programmable to operate with PowerPC MPC800 series microprocessors and Intel* i960* J core processors; see Table 16 and Table 17, respectively, for compatible processors. The MPI implements an 8-bit interface to the host processor (PowerPC or i960) that can be used for configuration and readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA function. In addition to dedicated-function registers, the microprocessor interface allows for the control of up to 16 user registers (RAM or flip-flops) in the FPGA logic. A synchronous/asynchronous handshake procedure is used to control transactions with user logic in the FPGA array. There is also capability for the FPGA logic to interrupt the host processor either by a hard interrupt or by having the host processor poll the microprocessor interface. * Intel and i960 are registered trademarks of Intel Corporation. D[7:0]IN D[7:0]OUT TO FPGA ROUTING ORCAORCA 3C/Txxx MPI DONE RD_DATA INIT D6 D6IN D6OUT D5IN D5OUT D4IN D4OUT D3IN D3OUT D2IN D2OUT D1IN D1OUT D0IN D0OUT D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 RD CS0 CS1 CCLK M3 M2 M1 M0 MPI_IRQ MPI_ACK MPI_CLK MPI_STRB MPI_ALE MPI_RW MPI_B1 STATUS REGISTER SCRATCHPAD REGISTER READBACK DATA REGISTER READBACK ADDR REGISTER POWERPC ONLY D7IN D7OUT CONTROL REGISTERS RESET RD_CFG PRGM GSR IRQ DECODE/CONTROL D7 PART ID REGISTERS USER_START USER_END WR_CTRL A[3:0] TO GSR BLOCK TO FPGA ROUTING RDYRCV CLK i960 LOGIC ADS ALE W/R RD/WR BT TS POWERPC LOGIC CLKOUT TA DEVICE PAD I/O BUFFER 5-5806(F) Figure 42. MPI Block Diagram 62 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) PowerPC System SE L D E IS C C T O D N E TI VI N C U E ED S In Figure 43, the ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The PowerPC interface uses separate address and data buses and has several control lines. The ORCA chip select lines, CS0 and CS1, are each connected to an address line coming from the PowerPC. In this manner, the FPGA is capable of a transaction with the PowerPC whenever the address line connected to CS0 is low, the address line for CS1 is high, and there is a valid address on PowerPC address lines A[27:31]. Other forms of selection are possible by using the FPGA chip selects in a different way. For example, PowerPC address bits A[0:26] could be decoded to select CS0 and CS1, or if the FPGA is the only peripheral to the PowerPC, CS0 and CS1 could be tied low and high, respectively, to cause them to always be selected. If the MPI is not used for FPGA configuration, decoding logic can be implemented internal or external to the FPGA. If logic internal to the FPGA is used, the chip selects must be routed out on an output pin and then connected externally to CS0 and/or CS1. If the MPI is to be used for configuration, any decode logic used must be implemented external to the FPGA since the FPGA logic has not been configured yet. (read high, write low) signals are set up at the FPGA pins by the PowerPC. The PowerPC then asserts its transfer start signal (TS) low. Data is available to the MPI during a write at the rising clock edge after the clock cycle during which TS is low. The transfer is acknowledged to the PowerPC by the low asser tion of the TA signal. The MPI PowerPC interface does not support burst transfers, so the burst inhibit signal, BI, is also asserted low during the transfer acknowledge . The same process applies to a read from the MPI except that the read data is expected at the FPGA data pins by the PowerPC at the rising edge of the clock when TA is low. The MPI only drives TA low for one clock cycle. D[7:0] A[27:31] CLKOUT RD/WR TA POWERPC BI IRQx TS A26 A25 8 DOUT CCLK D[7:0] A[4:0] MPI_CLK MPI_RW ORCA MPI_ACK SERIES 3 MPI_BI FPGA MPI_IRQ MPI_STRB DONE CS0 INIT CS1 HDC LDC TO DAISYCHAINED DEVICES 5-5761(F) Note: FPGA shown as a memory-mapped peripheral using CS0 and CS1. Other decoding schemes are possible using CS0 and/or CS1. Figure 43. PowerPC/MPI Interrupt requests can be sent to the PowerPC asynchronously to the read/write process. Interrupt requests are sourced by the user-logic in the FPGA. The MPI will assert the request to the PowerPC as a direct interrupt signal and/or a pollable bit in the MPI status register (discussed in the MPI Setup and Control section). The MPI will continue to assert the interrupt request until the user-logic deasserts its interrupt request signal. Table 16. PowerPC/MPI Configuration PowerPC Signal ORCA Pin Name MPI D[0:7] D[7:0] I/O A[27:31] A[4:0] I 5-bit MPI address bus TS RD/MPI_STRB I Transfer start signal -- CS0 I Active-low MPI select -- CS1 I Active-high MPI select CLKOUT A7/MPI_CLK I PowerPC interface clock RD/WR A8/MPI_RW I Read (high)/write (low) signal TA A9/MPI_ACK O Active-low transfer acknowledge signal BI A10/MPI_BI O Active-low burst transfer inhibit signal Any of IRQ[7:0] A11/MPI_IRQ O Active-low interrupt request signal Function I/O 8-bit data bus The basic flow of a transaction on the PowerPC/MPI interface is given below. Pin descriptions are shown in Table 16 and timing is shown in the Timing Characteristics section of this data sheet. For both read and write transactions, the address, chip select, and read/write Lattice Semiconductor 63 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) i960 System SE L D E IS C C T O D N E TI VI N C U E ED S Figure 44 shows a schematic for connecting the ORCA MPI to supported i960 processors. In the figure, the FPGA is shown as the only peripheral, with the FPGA chip select lines, CS0 and CS1, tied low and high, respectively. The i960 address and data are multiplexed onto the same bus. This precludes memory mapping of the FPGA in the i960 memory space of a multiperipheral system without some form of address latching to capture and hold the address signals to drive the CS0 and/or CS1 signals. Multiple address signals could also be decoded and latched to drive the CS0 and/or CS1 signals. If the MPI is not used for FPGA configuration, decoding/latching logic can be implemented internal or external to the FPGA. If logic internal to the FPGA is used, the chip selects must be routed out an output pin and then connected externally to CS0 and/or CS1. If the MPI is to be used for configuration, any decode/latch logic used must be implemented external to the FPGA since the FPGA logic has not been configured yet. set up at the FPGA pins by the i960 at the next rising edge of the clock. At this same rising clock edge, the i960 asserts its address/data strobe (ADS) low. Data is available to the MPI during a write at the rising clock edge of the following clock cycle. The transfer is acknowledged to the i960 by the low assertion of the ready/recover (RDYRCV) signal. The same process applies to a read from the MPI except that the read data is expected at the FPGA data pins by the i960 at the rising edge of the clock when RDYRCV is low. The MPI only drives RDYRCV low for one clock cycle. Interrupts can be sent to the i960 asynchronously to the read/write process. Interrupt requests are sourced by the user-logic in the FPGA. The MPI will assert the request to the i960 as a direct interrupt signal and/or a pollable bit in the MPI status register (discussed in the MPI Setup and Control section). The MPI will continue to assert the interrupt request until the user-logic deasserts its interrupt request signal. Table 17. i960/MPI Configuration i960 Signal ORCA Pin MPI Name I/O AD[7:0] D[7:0] I/O Multiplexed 5-bit address/ 8-bit data bus. The address appears on D[4:0]. ALE RDY/RCLK/ MPI_ALE I Address latch enable used to capture address from AD[4:0] on falling edge of clock. ADS RD/ MPI_STRB I Address/data strobe to indicate start of transaction. -- CS0 I Active-low MPI select. -- CS1 I Active-high MPI select. System Clock A7/ MPI_CLK I i960 system clock. This clock is sourced by the system and not the i960. W/R A8/MPI_RW I Write (high)/read (low) signal. RDYRCV A9/ MPI_ACK O Active-low ready/recover signal indicating acknowledgment of the transaction. Any of XINT[7:0] A11/ MPI_IRQ O Active-low interrupt request signal. BE0 A0/ MPI_BE0 I Byte-enable 0 used as address bit 0 in i960 8-bit mode. BE1 A1/ MPI_BE1 I Byte-enable 1 used as address bit 1 in i960 8-bit mode. i960 SYSTEM CLOCK AD[7:0] 8 CLKIN W/R RDYRCV XINTx ALE i960 ADS BE0 BE1 VDD D[7:0] DOUT CCLK MPI_CLK MPI_RW MPI_ACK MPI_IRQ ORCA MPI_ALE SERIES 3 MPI_STRB FPGA MPI_BE0 MPI_BE1 DONE INIT CS1 HDC CS0 LDC TO DAISYCHAINED DEVICES 5-5762(F) Note: FPGA shown as only system peripheral with fixed-chip select signals. For multiperipheral systems, address decoding and/or latching can be used to implement chip selects. Figure 44. i960/MPI The basic flow of a transaction on the i960/MPI interface is given below. Pin descriptions are shown in Table 17, and timing is shown in the ORCA Timing Characteristics section of this data sheet. For both read and write transactions, the address latch enable (ALE) is set up by the i960 at the FPGA to the falling edge of the clock. The address, byte enables, chip selects, and read/write (read low, write high) signals are normally 64 Function Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) MPI Interface to FPGA The MPI will insert wait-states in the host processor bus cycles, holding the host processor until the userlogic completes its task and returns a UEND signal, upon which the MPI generates an acknowledge signal. If the host processor is reading from the FPGA, the user logic must have the read data available on the D[7:0] pins of the FPGA when the UEND signal is asserted. If the user logic is fast or if the MPI user address is being decoded for use as a control signal, the MPI transaction time can be minimized by routing the USTART signal directly to the UEND input of the MPI. The timing section of this data sheet contains a parameter table with delay, setup, and hold timing requirements to operate the user-logic either synchronously or asynchronously with the MPI host interface clock. SE L D E IS C C T O D N E TI VI N C U E ED S The MPI interfaces to the user-programmable FPGA logic using a 4-bit address, read/write control signal, interrupt request signal, and user start and user end handshake signals. Timing numbers are provided so that the user-logic data transfers can be performed synchronously with the host processor (PowerPC or i960) interface clock or asynchronously. Table 18 shows the internal interface signals between the MPI and the FPGA user-programmable logic. All of the signals are connected to the MPI in the upper-left corner of the device except for the D[7:0] and CLK signals that come directly from the I/O pin. data written by the host processor from the D[7:0] pins once the USTART signal is asserted. The user logic ends a transaction by asserting an active-high user end (UEND) signal to the MPI. The 4-bit addressing from the MPI to the PLCs allows for up to 16 locations to be addressed by the host processor. The user address space of the MPI does not address any hard register. Rather, the user is free to construct registers from FFs, latches, or RAM that can be selected by the addressing. Alternately, the decoded address signals may be used as control signals for other functions such as state machines or timers. The transaction sequence between the MPI and the user-logic is as follows. When the host processor initiates a transaction as discussed in the preceding sections, the MPI outputs the 4-bit user address (UA[3:0]) and the read/write control signal (URDWR, which is read-high, write-low regardless of host processor), and then asserts the user start signal, USTART. During a write from the host processor, the user logic can accept The user-logic may also assert an active-low interrupt request (UIRQ) to the MPI, which, in turn, asserts an interrupt to the host processor. Assertion of an interrupt request is asynchronous to the host processor clock and any read or write transaction occurring in the MPI. The user-logic is responsible for providing any required interrupt vectors for the host processor, and the user-logic must deassert the interrupt request once serviced. If the interrupt request is not deasserted in the user logic, it will continue to be asserted to the host processor via the MPI_IRQ pin. Table 18. MPI Internal Interface Signals Signal MPI I/O Function UA[3:0] O User Logic Address. Addresses up to 16 unique user registers or use as control signals. URDWRN O User Logic Read/Write Control Signal. High indicates a read from user logic by the host processor, low indicates a write to user-logic by the host processor. USTART O Active-High User Start Signal. Indicates the start of an MPI transaction between the host processor and the user logic. UEND I Active-High User End Signal. Indicates that the user-logic is finished with the current MPI transaction. UIRQ I Active-Low Interrupt. Sends request from the user-logic to the host processor. D[7:0] FPGA I/O User Data. Eight data bits come directly from the FPGA pins--not through the MPI. MPI_CLK FPGA I MPI Clock. The MPI clock is sourced by the host processor and comes directly from the FPGA pin--not through the MPI. Lattice Semiconductor 65 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) MPI Setup and Control SE L D E IS C C T O D N E TI VI N C U E ED S The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The address map for these registers and the user-logic address space are shown in Table 19, followed by descriptions of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the least significant bit is bit 0. Table 19. MPI Setup and Control Registers Address (Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B--0F 10--1F Register Control Register 1. Control Register 2. Scratchpad Register. Status Register. Configuration/Readback Data Register. Readback Address Register 1 (bits [7:0]). Readback Address Register 2 (bits [15:8]). Device ID Register 1 (bits [7:0]). Device ID Register 2 (bits [15:8]). Device ID Register 3 (bits [23:16]). Device ID Register 4 (bits [31:24]). Reserved. User-definable Address Space. Control Register 1 The MPI control register 1 is a read/write register. The host processor writes a control byte to configure the MPI. It is readable by the host processor to verify the status of control bits previously written. Table 20. MPI Setup and Control Registers Descriptions Bit # Description Bit 0 GSR Input. Setting this bit to a 1 invokes a global set/reset on the FPGA. The host processor must return this bit to a 0 to remove the GSR signal. GSR does not affect the registers at MPI addresses 0 through F hexadecimal or any configuration registers. Default state = 0. Reserved. Reserved. Reserved. Reserved. RD_CFG Input. Changing this bit to a 0 after configuration will initiate readback. The host processor must return this bit to a 1 to remove the RD_CFG signal. Since this bit works exactly like the RD_CFG input pin, please see the FPGA pin descriptions for more information on this signal. Default state = 1. Reserved. PRGM Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundaryscan circuitry. The host processor must return this bit to a 1 to remove the PRGM signal. Since this bit works exactly like the PRGM input pin (except that it does not reset the MPI), please see the FPGA pin descriptions for more information on this signal. Default state = 1. Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 66 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) Scratchpad Register The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any userdefined function. SE L D E IS C C T O D N E TI VI N C U E ED S Control Register 2 The MPI control register 2 is a read/write register. The host processor writes a control byte to configure the MPI. It is readable by the host processor to verify the status of control bits it had previously written. Table 21. MPI Control Register 2 Bit # Bit Name Description Bit 0 EN_IRQ_CFG Enable IRQ for Configuration Data Request in Daisy-Chain Configuration Mode. Setting this bit to a 1 prior to configuration enables the IRQ signal to go active when new data is requested for configuration writes or is available for configuration reads to/from the configuration data register. A 0 clears the IRQ enable. This bit is only valid for daisy-chain configuration. Default = 0. Bit 1 EN_IRQ_ERR Enable IRQ for Bit Stream Error. Setting this bit to a 1 prior to configuration enables the IRQ signal to go active on the occurrence of a bit stream error during configuration. A 0 clears the IRQ enable. This bit only has effect while in configuration mode. Default = 0. Bit 2 EN_IRQ_USR Enable IRQ from the User FPGA Space. Setting this bit to a 1 allows user-defined circuitry in the FPGA to generate an interrupt to the host processor by sourcing a logic low on the UIRQ signal in the user logic. Default = 0. Bit 3 MP_DAISY MPI Daisy-Chain Output Enable. Setting this bit to a 1 enables daisy-chain output of the configuration data. See the Configuration section of this data sheet for daisychain configuration details. Default = 0. Bit 4 MP_HOLD_BUS Enable Bus Holding During Daisy-Chain Configuration Mode. Setting this bit to a 1 will cause the MPI to wait until the FPGA configuration logic has serialized a byte of configuration data before acknowledging the transaction. The data is only serialized if the MP_DAISY (bit 3 above) control bit is set to 1. If MP_HOLD_BUS is set to 0, the MPI will immediately acknowledge a configuration data byte transfer. Immediate acknowledgment allows the host processor to perform other tasks during FPGA configuration by polling the MPI status register (or by interrupt) and only write configuration data when the FPGA is ready. Default = 0. Bit 5 MP_USER MPI User Mode Enable. Setting this bit to a 1 will enable the MPI for user mode operation. MP_USER must be set prior to the FPGA DONE signal going high during configuration. The MPI may also be enabled for user operation via the configuration bit stream. Default = 0. Bit 6 Reserved -- Bit 7 Reserved -- Lattice Semiconductor 67 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) Status Register The microprocessor interface status register is a read-only register, providing information to the host processor. SE L D E IS C C T O D N E TI VI N C U E ED S Table 22. Status Register Bit # Description Bit 0 Bit 1 Reserved. Data Ready. Set by the MPI, a 1 on this bit during configuration alerts the host processor that the FPGA is ready for another byte of configuration data. During byte-wide readback, the MPI sets this bit to a 1 to tell the host processor that a byte of configuration data is available for reading. This bit is cleared by a host processor access (read or write) to the configuration data register. IRQ Pending. The MPI sets this bit to 1 to indicate to the host processor that the FPGA has a pending interrupt request. This bit may be used for the host processor to poll for interrupts if the MPI_IRQ pin output of the FPGA has been masked at the host processor. This bit is set to 0 when the status register is read. Interrupt requests from the FPGA user space must be cleared in FPGA user logic in addition to reading this bit. Bit Stream Error Flags. Bits 3 and 4 are set by the MPI to indicate any error during FPGA configuration. See bit 2 of control register 2 for the capability to alert the host processor of an error via the IRQ signal during configuration. In the truth table below, bit 3 is the LSB (bit on right). These bits are cleared to 0 when PRGM goes active: 00 = No error 01 = ID error 10 = Checksum error 11 = Stop-bit/alignment error Reserved. INIT. This bit reflects the binary value of the FPGA INIT pin. DONE. This bit reflects the binary value of the FPGA DONE pin. Bit 2 Bits [4:3] Bit 5 Bit 6 Bit 7 Configuration Data Register The MPI configuration data register is a writable register in configuration mode and a readable register in readback mode. For FPGA configuration, this is where the configuration data bytes are sequentially written by the host processor. Similarly, for readback mode, the MPI provides the readback data bytes in this register for the host processor. Readback Address Register 1 The MPI readback address register 1 is a writable register used to accept the least significant address byte (bits [7:0]) of the configuration data location to be read back. Readback Address Register 2 The MPI readback address register 2 is a writable register used to accept the most significant address byte (bits [15:8]) of the configuration data location to be read back. 68 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) Device ID Registers SE L D E IS C C T O D N E TI VI N C U E ED S The MPI device ID is broken into four registers holding 1 byte each. The device ID that is available through the MPI is the same as the boundary-scan ID code, except that the device ID in the MPI has a reverse bit order. There is no means to overwrite any of the device ID as can be done with the boundary-scan ID, but the MPI scratchpad register can be used as a personalization register. The format for the entire device ID is shown below followed by family and device values and the partitioning of the device ID into the four device ID registers. Table 23. Device ID Code Version Part* Family Manufacturer 4 bits 10 bits 6 bits 11 bits Example: (First version of OR3C80) 0000 0110100000 110000 00000011101 1 MSB 1 bit * PLC array size of FPGA. Table 24 shows the family and device values for all parts covered by this data sheet. Table 24. Series 3 Family and Device ID Values Part Name Family ID (Hex) Device ID (Hex) 03 03 03 03 03 0C 0E 12 16 1C OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 Table 25 describes the device IDs for all parts covered by this data sheet as they are partitioned into the four registers found in the MPI. Table 25. ORCA Series 3 Device ID Descriptions Device ID Register 1 Bit 0 Bits [7:1] Logic 1. This bit is always a one. 0011101, the 7 least significant bits of the manufacturer ID. Device ID Register 2 Bits [3:0] Bits [7:4] 0000, the 4 most significant bits of the manufacturer ID. The 4 least significant bits of the 10-bit part number. Device ID Register 3 Bits [5:0] Bits [7:6] The 6 most significant bits of the 10-bit part number. The 2 least significant bits of the device family code. Device ID Register 4 Bits [3:0] Bits [7:4] Lattice Semiconductor The 4 most significant bits of the device family code. The 4-bit device version code. 69 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) ner ExpressCLK that feeds the CLKCNTRL blocks on the two sides adjacent to the PCM, and one to the system clock spine network through general routing. Figure 45 shows a high-level block diagram of the PCM. The ORCA programmable clock manager (PCM) is a special function block that is used to modify or condition clock signals for optimum system performance. Some of the functions that can be performed with the PCM are clock skew reduction (both internal and board level), duty-cycle adjustment, clock delay reduction, clock phase adjustment, and clock frequency multiplication/division. Due to the different capabilities required by customer application, each PCM contains both a PLL (phase-locked loop) and a DLL (delayedlocked loop) mode. By using PLC logic resources in conjunction with the PCM, many other functions, such as frequency synthesis, are possible. SE L D E IS C C T O D N E TI VI N C U E ED S Functionality of the PCM is programmed during operation through a read/write interface internal to the FPGA array or via the configuration bit stream. The internal FPGA interface comprises write enable and read enable signals, a 3-bit address bus, an 8-bit input (to the PCM) data bus, and an 8-bit output data bus. There is also a PCM output signal, LOCK, that indicates a stable output clock state. These signals are used to program a series of registers to configure the PCM functional core for the desired functionality. There are two PCMs on each Series 3 device, one in the lower left corner and one in the upper right corner. Each can drive two different, but interrelated clock networks inside the FPGA. Each PCM can take a clock input from the ExpressCLK pad in its corner or from general routing resources. There are also two input sources that provide feedback to the PCM from the PLC array. One of these is a dedicated corner ExpressCLK feedback, and the other is from general routing. Each PCM sources two clock outputs, one to the cor- Operation of the PCM is divided into two modes, delaylocked loop (DLL) and phase-locked loop (PLL). Some operations can be performed by either mode and some are specific to a particular mode. These will be described in each individual mode section. In general, DLL mode is preferable to PLL mode for the same function because it is less sensitive to input clock noise. In the discussions that follow, the duty cycle is the percent of the clock period during which the output clock is high. USER CONTROL SIGNALS PCM-FPGA INTERFACE CORNER EXPRESSCLK IN PCM CORE FUNCTIONS GENERAL CLOCKIN (FROM GENERAL ROUTING) FEEDBACK ExpressCLK EXPRESSCLK OUT SYSTEM CLOCK OUT (TO GENERAL ROUTING) FEEDBACK CLOCK FROM ROUTING 5-5828(F) Figure 45. PCM Block Diagram 70 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM Registers SE L D E IS C C T O D N E TI VI N C U E ED S The PCM contains eight user-programmable registers used for configuring the PCM's functionality. Table 26 shows the mapping of the registers and their functions. See Figure 46 for more information on the location of PCM elements that are discussed in the table. The PCM registers are referenced in the discussions that follow. Detailed explanations of all register bits are supplied following the functional description of the PCM. Table 26. PCM Registers Address Function 0 Divider 0 Programming. Programmable divider, DIV0, value and DIV0 reset bit. DIV0 can divide the input clock to the PCM or can be bypassed. Divider 1 Programming. Programmable divider, DIV1, value and DIV1 reset bit. DIV1 can divide the feedback clock input to the PCM or can be bypassed. Valid only in PLL mode. Divider 2 Programming. Programmable divider, DIV2, value and DIV2 reset bit. DIV2 can divide the output of the tapped delay line or can be bypassed and is only valid for the ExpressCLK output. DLL 2x Duty-Cycle Programming. DLL mode clock doubler (2x) duty-cycle selection. DLL 1x Duty-Cycle Programming. Depending on the settings in other registers, this register is for: a. PLL mode phase/delay selection; b. DLL mode 1x duty cycle selection; and c. DLL mode programmable delay. Mode Programming. DLL/PLL mode selection, DLL 1x/2x clock selection, phase detector feedback selection. Clock Source Status/Output Clock Selection Programming. Input clock selection, feedback clock selection, ExpressCLK output source selection, system clock output source selection. PCM Control Programming. PCM power, reset, and configuration control. 1 2 3 4 5 6 7 Lattice Semiconductor 71 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM CHARGE PUMP AND LOW-PASS FILTER SE L D E IS C C T O D N E TI VI N C U E ED S INPUT CLOCK EXPRESSCLK PAD FROM ROUTING 0 1 S0 2 PROGRAMMABLE DIVIDER DIV0 3 REGISTER 7 REGISTER 6 0 S4 1 PHASE DETECTOR PROGRAMMABLE DELAY LINES (32 TAPS) 1 S2 0 FEEDBACK CLOCK 0 1 S3 2 PROGRAMMABLE DIVIDER DIV1 1...7 1...7 1...7 1...7 S5 S6 S7 S8 REGISTER 5 REGISTER 3 REGISTER 2 3 REGISTER 1 REGISTER 0 0 1 S4 2 0 1 S4 2 REGISTER 4 PROGRAMMABLE DIVIDER DIV2 3 EXPRESSCLK FEEDBACK FROM ROUTING EXPRESSCLK OUTPUT 3 COMBINATORIAL LOGIC FPGA-PCM INTERFACE SYSTEM CLOCK OUTPUT DATA_IN[7:0] ADDR_IN[2:0] DATA_OUT[7:0] WE RE LOCK 0 0 1 S10 2 3 5-5829(F) Figure 46. PCM Functional Block Diagram 72 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) 1x Clock Duty-Cycle Adjustment (continued) A duty-cycle adjusted replica of the input clock can be constructed in DLL mode. The duty cycle can be adjusted in 1/32 (3.125%) increments of the input clock period. DLL 1x clock mode is selected by setting bit 4 of register five to a 1, and output clock source selection is selected by setting register six, bits [5:4] to 01 for ExpressCLK output, and/or bits [7:6] to 01 for system clock output. The duty-cycle percentage value is entered in register four. See register four programming details for more information. Duty cycle values are also shown in the third column of Table 27. Delay-Locked Loop (DLL) Mode SE L D E IS C C T O D N E TI VI N C U E ED S DLL mode is used for implementing a delayed clock (phase adjustment), clock doubling, and duty cycle adjustment. All DLL functions stem from a delay line with 32 taps. The delayed input clock is pulled from various taps and processed to implement the desired result. There is no feedback clock in DLL mode, providing a very stable output and a fast lock time for the output clock. DLL mode is selected by setting bit 0 in PCM register five to a 0. The settings for the various submodes of DLL mode are described in the following paragraphs. Divider DIV0 may be used with any of the DLL modes to divide the input clock by an integer factor of 1 to 8 prior to implementation of the DLL process. Delayed Clock A delayed version of the input clock can be constructed in DLL mode. The output clock can be delayed by increments of 1/32 of the input clock period. Express CLK and system CLK outputs in delay modes are selected by setting register six, bits [5:4] to 10 or 11 for ExpressCLK output, and/or bits [7:6] to 10 for system clock output. The delay value is entered in register four. See register four programming details for more information. Delay values are also shown in the second column of Table 27. Note that when register six, bits [5:4] are set to 11, the ExpressCLK output is divided by an integer factor from 1 to 8 while the system clock cannot be divided. The ExpressCLK divider is provided so that the I/O clocking provided by the ExpressCLK can operate slower than the internal system clock. This allows for very fast internal processing while maintaining slower interface speeds off-chip for improved noise and power performance or to interoperate with slower devices in the system. The divisor of the ExpressCLK frequency is selected in register two. See the register two programming details for more information. Lattice Semiconductor Table 27. DLL Mode Delay/1x Duty Cycle Programming Values Register 4 [7:0] 76543210 Delay (CLK_IN/32) Duty Cycle (% of CLK_IN) 00XXX000 00XXX001 00XXX010 00XXX011 00XXX100 00XXX101 00XXX110 00XXX111 01XXX000 01XXX001 01XXX010 01XXX011 01XXX100 01XXX101 01XXX110 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3.125 6.250 9.375 12.500 15.625 18.750 21.875 25.000 28.125 31.250 34.375 37.500 40.625 43.750 46.875 50.000 53.125 56.250 59.375 62.500 65.625 68.750 71.875 75.000 78.125 81.250 84.375 87.500 90.625 93.750 96.875 73 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) Clock Delay Minimization (continued) PLL mode can be used to minimize the effects of the input buffer and input routing delay on the clock signal. PLL mode causes a feedback clock signal to align in phase with the input clock (refer back to the block diagram in Figure 45) so that the delay between them is effectively eliminated. 2x Clock Duty-Cycle Adjustment SE L D E IS C C T O D N E TI VI N C U E ED S A doubled-frequency, duty-cycle adjusted version of the input clock can be constructed in DLL mode. The first clock cycle of the 2x clock output occurs when the input clock is high, and the second cycle occurs when the input clock is low. The duty cycle can be adjusted in 1/32 (6.25%) increments of the input clock period. Additionally, each of the two doubled-clock cycles that occurs in a single input clock cycle may be adjusted to have different duty cycles. DLL 2x clock mode is selected by setting bit 4 of register five to a 1, and by setting register six, bits [5:4] to 01 for ExpressCLK output, and/or bits [7:6] to 01 for system clock output. The duty-cycle percentage value is entered in register three. See register three programming details for more information. Duty-cycle values where both cycles of the doubled clock have the same duty cycle are also shown in Table 28. Table 28. DLL Mode Delay/2x Duty Cycle Programming Values Register 3 [7:0] 76543210 00000000 00001001 00010010 00011011 00100100 00101101 00110110 00111111 11000000 11001001 11010010 11011011 11100100 11101101 11110110 Duty Cycle (%) 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 62.50 68.75 75.00 81.25 87.50 93.75 There is a dedicated feedback path from an adjacent middle CLKCNTRL block to the PCM. Using the corner ExpressCLK pad as the input to the PCM and using this dedicated feedback path, the clock from the ExpressCLK output of the PCM, as viewed at the CLKCNTRL block, will be phase-aligned with the ExpressCLK input to the PCM. These relationships are diagrammed in Figure 47. A feedback clock can also be input to the PCM from general routing. This allows for compensating for delay between the PCM input and a point in the general routing. The use of this routed-feedback path is not generally recommended. Because compensation is based on the programmable routing, the amount of clock delay compensation can vary between FPGA lots and fabrication processes, and will vary each time that the feedback line is routed using different resources. Contact Lattice for application notes regarding the use of routed-feedback delay compensation. DELAY COMPENSATION EQUALS DELAY CORNER EXPRESSCLK INPUT CLKCNTRL EXPRESSCLK OUTPUT WITHOUT USING PCM DELAY IS COMPENSATED CLKCNTRL EXPRESSCLK OUTPUT USING PCM 5-5980(F) Figure 47. ExpressCLK Delay Minimization Using the PCM Phase-Locked Loop (PLL) Mode The PLL mode of the PCM is used for clock multiplication (1/8x to 64x) and clock delay minimization functions. PLL functions make use of the PCM dividers and use feedback signals, often from the FPGA array. The use of feedback is discussed with each PLL submode. PLL mode is selected by setting bit 0 of register five to 1. 74 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Clock Multiplication SE L D E IS C C T O D N E TI VI N C U E ED S An output clock that is a multiple (not necessarily an integer multiple) of the input clock can be generated in PLL mode. The multiplication ratio is programmed in the division registers DIV0, DIV1, and DIV2. Note that DIV2 applies only to the ExpressCLK output of the PCM and any reference to DIV2 is implicitly 1 for the system clock output of the PCM. The clock multiplication formulas when using ExpressCLK feedback are: The multiplied output is selected by setting register six, bits [5:4] to 10 or 11 for ExpressCLK output and/or bits [7:6] to 10 for system clock output. Note that when register six, bits [5:4] are set to 11, the ExpressCLK output is divided by DIV2, while the system clock cannot be divided. The ExpressCLK divider is provided so that the I/O clocking provided by the ExpressCLK can operate slower than the internal system clock. This allows for very fast internal processing while maintaining slower interface speeds off-chip for improved noise and power performance or to interoperate with slower devices in the system. FExpressCLK_OUT = FINPUT_CLOCK * DIV1 DIV0 FSYSTEM_CLOCK_OUT = FExpressCLK_OUT * DIV2 Where the values of DIV0, DIV1, and DIV2 range from 1 to 8. The ExpressCLK multiplication range of output clock frequencies is, therefore, from 1/8x up to 8x, with the system clock range up to 8x the ExpressCLK frequency or 64x the input clock frequency. If system clock feedback is used, the formulas are: FSYSTEM_CLOCK_OUT = FINPUT_CLOCK * DIV1 DIV0 FExpressCLK_OUT = FSYSTEM_CLOCK/DIV2 It is also necessary to configure the internal PCM oscillator for operation in the proper frequency range. Table 29 and Table 30 show the settings required for register four for a given frequency range for Series 3C and 3T devices. In addition, the acquisition time is shown for each frequency range. This is the time that is required for the PCM to acquire LOCK. The PCM oscillator frequency range is chosen based on the desired output frequency at the system clock output. If using the ExpressCLK output, the equivalent system clock frequency can be selected by multiplying the expected ExpressCLK output frequency by the value for DIV2. Choose the nominal frequency from the table that is closest to the desired frequency, and use that value to program register four. Minor adjustments to match the exact input frequency are then performed automatically by the PCM. The divider values, DIV0, DIV1, and DIV2 are programmed in registers zero, one, and two, respectively. Lattice Semiconductor 75 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Table 29. PCM Oscillator Frequency Range 3Txxx Table 30. PCM Oscillator Frequency Range 3Cxx System Clock Output Frequency T Register 4 Min (MHz) Max Acquisition 76543210 (MHz) NOM (MHz) (s) 00XXX010 00XXX011 00XXX100 00XXX101 00XXX110 00XXX111 01XXX000 01XXX001 01XXX010 01XXX011 01XXX100 01XXX101 01XXX110 01XXX111 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX 00XXX010 10.50 00XXX011 10.00 00XXX100 9.50 00XXX101 9.10 00XXX110 8.60 00XXX111 8.10 01XXX000 7.80 01XXX001 7.60 01XXX010 7.30 01XXX011 7.10 01XXX100 6.80 01XXX101 6.50 01XXX110 6.30 01XXX111 6.00 10000XXX 5.90 10001XXX 5.90 10010XXX 5.80 10011XXX 5.80 10100XXX 5.70 10101XXX 5.60 10110XXX 5.60 10111XXX 5.50 11000XXX 5.40 11001XXX 5.40 11010XXX 5.30 11011XXX 5.30 11100XXX 5.20 11101XXX 5.10 11110XXX 5.10 11111XXX 5.00 SE L D E IS C C T O D N E TI VI N C U E ED S System Clock Output Frequency T Register 4 Min (MHz) Max Acquisition 76543210 (MHz) NOM (MHz) (s) 17.00 16.10 15.17 14.25 13.33 12.40 12.20 12.10 11.90 11.70 11.10 10.50 10.00 9.40 9.20 9.00 8.80 8.60 8.40 8.10 7.90 7.70 7.60 7.45 7.30 7.20 6.60 6.00 5.50 5.00 58.50 52.50 49.00 45.00 41.50 38.00 36.75 35.00 33.00 31.30 30.00 29.15 28.10 27.00 26.25 25.65 25.00 24.45 23.70 22.90 22.20 21.50 20.80 20.10 19.45 18.85 18.30 17.70 17.10 16.50 100.00 89.00 82.80 76.50 70.30 64.00 61.30 58.00 54.30 51.00 49.40 47.80 46.20 44.60 43.30 42.30 41.30 40.30 39.00 37.70 36.50 35.20 34.00 32.80 31.60 30.50 30.00 29.40 28.60 28.00 36.00 37.00 38.00 39.00 40.00 41.00 43.75 46.50 49.25 52.00 54.75 57.50 60.25 63.00 65.40 67.80 70.10 72.50 74.90 77.30 79.60 82.00 84.30 86.50 88.80 91.00 93.30 95.50 97.80 100.00 Note: Use of settings in the first three rows is not recommended. X means don't care. 76 73.00 68.00 63.00 58.50 53.80 49.00 47.70 46.30 45.00 43.60 42.10 40.75 39.40 38.00 37.40 36.70 36.00 35.40 35.00 34.10 33.50 32.80 32.10 31.50 30.70 30.10 29.50 28.80 28.20 27.50 135.00 126.00 117.00 108.00 99.00 90.00 87.50 85.00 82.50 80.00 77.50 75.00 72.50 70.00 68.80 67.50 66.30 65.00 63.80 62.50 61.30 60.00 58.80 57.50 56.30 55.00 53.80 52.50 51.30 50.00 36.00 37.00 38.00 39.00 40.00 41.00 43.80 46.50 49.30 52.00 55.00 57.50 60.30 63.00 65.40 67.80 70.10 72.50 74.90 77.30 79.60 82.00 84.30 86.50 88.80 91.00 93.30 95.50 97.80 100.00 Note: Use of settings in the first three rows is not recommended. X means don't care. Lattice Semiconductor Data Sheet November 2006 Programmable Clock Manager (PCM) (continued) PCM/FPGA Internal Interface PCM Operation Several features are available for the control of the PCM's overall operation. The PCM may be programmably enabled/disabled via bit 0 of register 7. When disabled, the analog power supply of the PCM is turned off, conserving power and eliminating the possibility of inducing noise into the system power buses. Individual bits (register 7, bits [2:1]) are provided to reset the DLL and PLL functions of the PCM. These resets affect only the logic generating the DLL or PLL function; they do not reset the divider values (DIV0, DIV1, DIV2) or registers [7:0]. The global set/reset (GSRN) is also programmably controlled via register 7, bit 7. If register 7, bit 7 is set to 1, GSRN will have no effect on the PCM logic, allowing the clock to operate during a global set/reset. This function allows the FPGA to be reset without affecting a clock that is sent off-chip and used elsewhere in the system. Bit 6 of register 7 affects the functionality of the PCM during configuration. If set to 1, this bit enables the PCM to operate during configuration, after the PCM has been configured. The PCM functionality is programmed via the bit stream. If register 7, bit 6 is 0, the PCM cannot function and its power supply is disabled until after the configuration DONE signal goes high. SE L D E IS C C T O D N E TI VI N C U E ED S Writing and reading the PCM registers is done through a simple asynchronous interface that connects with the FPGA routing resources. Reads from the PCM by the FPGA logic are accomplished by setting up the 3-bit address, A[2:0], and then applying an active-high read enable (RE) pulse. The read data will be available as long as RE is held high. The address may be changed while RE is high, to read other addresses. When RE goes low, the data output bus is 3-stated. ORCA Series 3C and 3T FPGAs Writes to the PCM by the FPGA logic are performed by applying the write data to the data input bus of the PCM, applying the 3-bit address to write to, and asserting the write enable (WE) signal high. Data will be written by the high-going transition of the WE pulse. The read enable (RE) and write enable (WE) signals may not be active at the same time. For detailed timing information and specifications, see the Timing Characteristics section of this data sheet. The LOCK signal output from the PCM to the FPGA routing indicates a stable output clock signal from the PCM. The LOCK signal is high when the PCM output clock parameters fall within the programmed values and the PCM specifications for jitter. Due to phase corrections that occur internal to the PCM, the LOCK signal might occasionally pulse low when the output clock is out of specification for only one or two clock cycles (high jitter due to temperature, voltage fluctuation, etc.) To accommodate these pulses, it is suggested that the user integrate the LOCK signal over a period suitable to their application to achieve the desired usage of the LOCK signal. When the PCM is powered up via register 7, bit 0, there is a wake-up time associated with its operation. Following the wake-up time, the PCM will begin to fully function, and, following an acquisition time during which the output clock may be unstable, the PCM will be in steady-state operation. There is also a shutdown time associated with powering off the PCM. The output clock will be unstable during this period. Waveforms and timing parameters can be found in the Timing Characteristics section of this data sheet. The LOCK signal will also pulse high and low during the acquisition time as the output clock stabilizes. True LOCK is only achieved when the LOCK signal is a solid high. Again, it is suggested that the user integrate the LOCK signal over a time period suitable to the subject application. Lattice Semiconductor 77 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM Detailed Programming SE L D E IS C C T O D N E TI VI N C U E ED S Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to Figure 46 for more information on the location of the PCM elements that are discussed. In the following discussion, the duty cycle is in the percentage of the clock period where the clock is high. Table 31. PCM Control Registers Bit # Function Register 0 Divider 0 Programming Bits [3:0] 4-Bit Divider, DIV0, Value. This value enables the input clock to immediately be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV0 is bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). Bits [6:4] Reserved. Bit 7 DIV 0 Reset Bit. DIV0 may not be reset by GSRN depending on the value of register 7, bit 7. This bit may be set to 1 to reset DIV0 to its default value. Bit 0 must be set to 0 (the default) to remove the reset. Register 1 Divider 1 Programming Bits [3:0] 4-Bit Divider, DIV1, Value. This value enables the feedback clock to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV1 is bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). Bits [6:4] Reserved. Bit 7 DIV1 Reset Bit. DIV1 may not be reset by GSRN, depending on the value of register 7, bit 7. This bit may be set to 1 to reset DIV1 to its default value. Bit 0 must be set to 0 (the default) to remove the reset. Register 2 Divider 2 Programming Bits [3:0] 4-Bit Divider, DIV2, Value. This value enables the tapped delay line output clock driven onto ExpressCLK to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV2 is bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). Bits [6:4] Reserved. Bit 7 DIV2 Reset Bit. DIV2 may not be reset by GSRN, depending on the value of register 7, bit 7. This bit may be set to 1 to reset DIV2 to its default value. Bit 7 must be set to 0 (the default) to remove the reset. Register 3 DLL 2x Duty-Cycle Programming Bits [2:0] Duty-cycle selection for the doubled clock period associated with the input clock high. The duty cycle is (value of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 6. Bits [5:3] Duty-cycle selection for the doubled clock period associated with the input clock low. The duty cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 7. Bit 6 Master duty-cycle control for the first clock period of the doubled clock: 0 = less than or equal to 50%, 1 = greater than 50%. Bit 7 Master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal to 50%, 1 = greater than 50%. Example: Both clock periods having a 62.5% duty cycle, bits [7:0] are 11 001 001. 78 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Table 31. PCM Control Registers (continued) Bit # Function SE L D E IS C C T O D N E TI VI N C U E ED S Register 4 DLL 1x Duty-Cycle Programming Bits [2:0] Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or Equal to 50%. The dutycycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1) * 3.125%. See the description for bits [7:6]. Bits [5:3] Duty-Cycle/Delay Selection for Duty Cycle/Delays Greater Than 50%. The duty-cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. See the description for bits [7:6]. Bits [7:6] Master Duty Cycle Control: 00: duty cycle 3.125% to 25% 01: duty cycle 28.125% to 50% 10: duty cycle 53.125% to 75% 11: duty cycle 78.125% to 96.875% Example: A 40.625% duty cycle, bits [7:0] are 01 XXX 100, where X is a don't care because the duty cycle is not greater than 50%. Example: The PCM output clock should be delayed 96.875% (31/32) of the input clock period. Bits [7:0] are 11110XXX, which is 78.125% from bits [7:6] and 18.75% from bits [5:3]. Bits [2:0] are don't care (X) because the delay is greater than 50%. Register 5 Mode Programming Bit 0 DLL/PLL Mode Selection Bit. 0 = DLL, 1 = PLL. Default is DLL mode. Bit 1 Reserved. Bit 2 PLL Phase Detector Feedback Input Selection Bit. 0 = feedback signal from routing/ ExpressCLK, 1 = feedback from programmable delay line output. Default is 0. Has no effect in DLL mode. Bit 3 Reserved. Bit 4 1x/2x Clock Selection Bit for DLL Mode. 0 = 1x clock output, 1 = 2x clock output. Default is 1x clock output. Has no effect in PLL mode. Bits [7:5] Reserved. Lattice Semiconductor 79 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Table 31. PCM Control Registers (continued) Bit # Function ExpressCLK Output Source Selector. Default is 00. 00: PCM input clock, bypass path through PCM 01: DLL output 10: tapped delay line output 11: divided (DIV2) delay line output Bits [7:6] System Clock Output Source Selector. Default is 00. 00: PCM input clock, bypass path through PCM 01: DLL output 10: tapped delay line output 11: reserved Register 7 PCM Control Programming Bit 0 PCM Analog Power Supply Switch. 1 = power supply on, 0 = power supply off. Bit 1 PCM Reset. A value of 1 resets all PCM logic for PLL and DLL modes. Bit 2 DLL Reset. A value of 1 resets the clock generation logic for DLL mode. No dividers or user registers are affected. Bits [5:3] Reserved. Bit 6 PCM Configuration Operation Enable Bit. 0 = normal configuration operation. During configuration (DONE = 0), the PCM analog power supply will be off, the PCM output data bus is 3-stated, and the LOCK signal is asserted to logic 0. The PCM will power up when DONE = 1. SE L D E IS C C T O D N E TI VI N C U E ED S Bits [5:4] Bit 7 80 1 = PCM operation during configuration. The PCM may be powered up (see bit 0) and begin operation, or continue operation. The setup of the PCM can be performed via the configuration bit stream. PCM GSRN Enable Bit. 0 = normal GSRN operation. 1 = GSRN has no effect on PCM logic, so clock processing will not be interrupted by a chip reset. Default is 0. Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM Applications In some systems, it is desirable to operate logic from several clocks that operate at different phases. This technique is often used in microprocessor-based systems to transfer and process data synchronously between functional areas, but without incurring excessive delays. Figure 48B shows an input clock and an output clock operating 180 out of phase. It also shows a version of the input clock that was shifted approximately 180 using logic gates to create an inverter. Note that the inverted clock is really shifted more than 180 due to the propagation delay of the inverter. The PCM output clock does not suffer from this delay. Additionally, the 180 shifted PCM output could be shifted by some smaller amount to effect an early 180 shifted clock that also accounts for loading effects. SE L D E IS C C T O D N E TI VI N C U E ED S The applications discussed below are only a small sampling of the possible uses for the PCM. Check the Lattice website for additional application notes. clock setup time and some margin, is the amount less than one full clock cycle that the output clock is delayed from the input clock. Clock Phase Adjustment The PCM may be used to adjust the phase of the input clock. The result is an output clock which has its active edge either preceding or following the active edge of the input clock. Clock phase adjustment is accomplished in DLL mode by delaying the clock. This is discussed in the Delay-Locked Loop (DLL) Mode section. Examples of using the delayed clock as an early or late phase-adjusted clock are outlined in the following paragraphs. An output clock that precedes the input clock can be used to compensate for clock delay that is largely due to excessive loading. The preceding output clock is really not early relative to the input clock, but is delayed almost a full cycle. This is shown in Figure 48A. The amount of delay that is being compensated for, plus In terms of degrees of phase shift, the phase of a clock is adjustable in DLL mode with resolution relative to the delay increment (see Table 27): Phase Adjustment = (Delay)* 11.25, Delay < 16 Phase Adjustment = ((Delay)* 11.25) - 360, Delay > 16 CLOCK DELAY AND SETUP BEING COMPENSATED DLL DELAY INPUT CLOCK OUTPUT CLOCK A. Generating an Early Clock UNINTENDED PHASE SHIFT DUE TO INVERTER DELAY DLL DELAY INPUT CLOCK PCM OUTPUT CLOCK INVERTED INPUT CLOCK B. Multiphase Clock Generation Using the DLL 5-5979(F) Figure 48. Clock Phase Adjustment Using the PCM Lattice Semiconductor 81 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) High-Speed Internal Processing with Slow I/Os Resultant signals from the PCM must meet the FPGA timing specifications. It is possible to specify pulses by using duty-cycle adjustments that are too narrow to function in the FPGA. For instance, if a 40 MHz clock is doubled to 80 MHz and a 6.25% duty cycle is selected, the result will be a 780 ps pulse that repeats every 12.5 ns. This pulse falls outside of the clock pulse width specification and is not valid. SE L D E IS C C T O D N E TI VI N C U E ED S The PCM PLL mode provides two outputs, one sent to the global system clock routing of the FPGA and the other to the ExpressCLK(s) that serve the FPGA I/Os. The ExpressCLK output of the PCM has a divide capability (DIV2) that the system clock output does not. This feature allows an input clock to be multiplied up to a higher frequency for high-speed internal processing, and also allows the ExpressCLK output to be divided down to a lower frequency to accommodate off-FPGA data transfers. For example, a 10 MHz input clock may be multiplied (see Clock Multiplication in the PhaseLocked Loop (PLL) Mode subsection) to 25 MHz (DIV0 = 4, DIV1 = 5, DIV2 = 2) and output to the FPGA ExpressCLK. This allows the I/Os of the circuit to run at 25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run at DIV2 times the ExpressCLK rate, which is 2 times 25 MHz, or 50 MHz. This setup allows for internal processing to occur at twice the rate of on/off device I/O transfers. Data Sheet November 2006 PCM Cautions Cautions do apply when using the PCM. There are a number of configurations that are possible in the PCM that are theoretically valid, but may not produce viable results. This section describes some of those situations, and should leave the user with an understanding of the types of pitfalls that must be avoided when modifying clock signals. 82 Using divider DIV2, it is possible to specify a clock multiplication factor of 64 between the input clock and the output system clock. As mentioned above, the resultant frequency must meet all FPGA timing specifications. The input clock must also meet the minimum specifications. An input clock rate that is below the PCM clock minimum cannot be used even if the multiplied output is within the allowable range. The use of the PCM to tweak a clock signal to eliminate a particular problem, such as a single setup time violation, is discouraged. A small shift in delay, duty cycle, or phase to correct a single-point problem is in essence an asynchronous patch to a synchronous system, making the system less stable. This type of local problem, as opposed to a global clock control issue like devicewide clock delay, can usually be eliminated through more robust design practices. If this type of change is made, the designer must be aware that depending on the extent of the change made, the design may fail to operate correctly in a different speed grade or voltage grade (e.g., 3C vs. 3T), or even in a different production lot of the same device. Divider DIV2 is available in DLL mode for the ExpressCLK output, but its use is not recommended with dutycycle adjusted clocks. Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Initialization Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration, and start-up. Figure 49 outlines these three FPGA states. Upon powerup, the device goes through an initialization process. First, an internal power-on-reset circuit is triggered when power is applied. When VDD reaches the voltage at which portions of the FPGA begin to operate (2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the OR3Txxx), the I/Os are configured based on the configuration mode, as determined by the mode select inputs M[2:0]. A time-out delay is initiated when VDD reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to 3.0 V (OR3Txxx) to allow the power supply voltage to stabilize. The INIT and DONE outputs are low. At powerup, if VDD does not rise from 2.0 V to VDD in less than 25 ms, the user should delay configuration by inputting a low into INIT, PRGM, or RESET until VDD is greater than the recommended minimum operating voltage (4.75 V for OR3Cxx commercial devices and 3.0 V for OR3Txxx devices). SE L D E IS C C T O D N E TI VI N C U E ED S FPGA States of Operation POWERUP - POWER-ON TIME DELAY INITIALIZATION - CLEAR CONFIGURATION MEMORY - INIT LOW, HDC HIGH, LDC LOW YES BIT ERROR NO RESET, INIT, OR PRGM LOW YES NO CONFIGURATION - M[3:0] MODE IS SELECTED - CONFIGURATION DATA FRAME WRITTEN - INIT HIGH, HDC HIGH, LDC LOW - DOUT ACTIVE RESET OR PRGM LOW START-UP - ACTIVE I/O - RELEASE INTERNAL RESET - DONE GOES HIGH PRGM LOW OPERATION 5-4529(F) Figure 49. FPGA States of Operation At the end of initialization, the default configuration option is that the configuration RAM is written to a low state. This prevents shorts prior to configuration. As a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration RAM first. The active-low, open-drain initialization signal INIT is released and must be pulled high by an external resistor when initialization is complete. To synchronize the configuration of multiple FPGAs, one or more INIT pins should be wire-ANDed. If INIT is held low by one or more FPGAs or an external device, the FPGA remains in the initialization state. INIT can be used to signal that the FPGAs are not yet initialized. After INIT goes high for two internal clock cycles, the mode lines (M[3:0]) are sampled, and the FPGA enters the configuration state. The high during configuration (HDC), low during configuration (LDC), and DONE signals are active outputs in the FPGA's initialization and configuration states. HDC, LDC, and DONE can be used to provide control of external logic signals such as reset, bus enable, or PROM enable during configuration. For parallel master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. Lattice Semiconductor 83 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs not used during the configuration process are 3-stated with internal pull-ups. If configuration has begun, an assertion of RESET or PRGM initiates an abort, returning the FPGA to the initialization state. The PRGM and RESET pins must be pulled back high before the FPGA will enter the configuration state. During the start-up and operating states, only the assertion of PRGM causes a reconfiguration. Warning: During configuration, all OR3Txxx inputs have internal pull-ups enabled. If these inputs are driven to 5V, they will draw substantial current ( 5 ma). This is due to the fact that the inputs are pulled up to 3V. SE L D E IS C C T O D N E TI VI N C U E ED S FPGA States of Operation (continued) In the master configuration modes, the FPGA is the source of configuration clock (CCLK). In this mode, the initialization state is extended to ensure that, in daisychain operation, all daisy-chained slave devices are ready. Independent of differences in clock rates, master mode devices remain in the initialization state an additional six internal clock cycles after INIT goes high. When configuration is initiated, a counter in the FPGA is set to 0 and begins to count configuration clock cycles applied to the FPGA. As each configuration data frame is supplied to the FPGA, it is internally assembled into data words. Each data word is loaded into the internal configuration memory. The configuration loading process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. All OR3Cxx I/Os operate as TTL inputs during configuration (OR3Txxx I/Os are CMOS-only). All I/Os that are During configuration, the PIC and PLC latches/FFs are held set/reset and the internal BIDI buffers are 3stated. The combinatorial logic begins to function as the FPGA is configured. Figure 50 shows the general waveform of the initialization, configuration, and startup states. Configuration The ORCA Series FPGA functionality is determined by the state of internal configuration RAM. This configuration RAM can be loaded in a number of different modes. In these configuration modes, the FPGA can act as a master or a slave of other devices in the system. The decision as to which configuration mode to use is a system design issue. Configuration is discussed in detail, including the configuration data format and the configuration modes used to load the configuration data in the FPGA, following a description of the start-up state. VDD RESET PRGM INIT M[3:0] CCLK HDC LDC DONE USER I/O INTERNAL RESET (gsrn) INITIALIZATION CONFIGURATION START-UP OPERATION 5-4482(F) Figure 50. Initialization/Configuration/Start-Up Waveforms 84 Lattice Semiconductor Data Sheet November 2006 FPGA States of Operation (continued) Start-Up DONE is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired ANDing. The open-drain DONE signals from multiple FPGAs can be tied together (ANDed) with a pull-up (internal or external) and used as an active-high ready signal, an active-low PROM enable, or a reset to other portions of the system. When used in SYNC mode, these ANDed DONE pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. This signal will not rise until all FPGAs release their DONE pins, allowing the signal to be pulled high. SE L D E IS C C T O D N E TI VI N C U E ED S After configuration, the FPGA enters the start-up phase. This phase is the transition between the configuration and operational states and begins when the number of CCLKs received after INIT goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. The system design issue in the startup phase is to ensure the user I/Os become active without inadvertently activating devices in the system or causing bus contention. A second system design concern is the timing of the release of global set/reset of the PLC latches/FFs. ORCA Series 3C and 3T FPGAs There are configuration options that control the relative timing of three events: DONE going high, release of the set/reset of internal FFs, and user I/Os becoming active. Figure 51 shows the start-up timing for ORCA FPGAs. The system designer determines the relative timing of the I/Os becoming active, DONE going high, and the release of the set/reset of internal FFs. In the ORCA Series FPGA, the three events can occur in any arbitrary sequence. This means that they can occur before or after each other, or they can occur simultaneously. There are four main start-up modes: CCLK_NOSYNC, CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC. The only difference between the modes starting with CCLK and those starting with UCLK is that for the UCLK modes, a user clock must be supplied to the start-up logic. The timing of start-up events is then based upon this user clock, rather than CCLK. The difference between the SYNC and NOSYNC modes is that for SYNC mode, the timing of two of the start-up events, release of the set/reset of internal FFs, and the I/Os becoming active is triggered by the rise of the external DONE pin followed by a variable number of rising clock edges (either CCLK or UCLK). For the NOSYNC mode, the timing of these two events is based only on either CCLK or UCLK. Lattice Semiconductor The default for ORCA is the CCLK_SYNC synchronized start-up mode where DONE is released on the first CCLK rising edge, C1 (see Figure 51). Since this is a synchronized start-up mode, the open-drain DONE signal can be held low externally to stop the occurrence of the other two start-up events. Once the DONE pin has been released and pulled up to a high level, the other two start-up events can be programmed individually to either happen immediately or after up to four rising edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4). The default is for both events to happen immediately after DONE is released and pulled high. A commonly used design technique is to release DONE one or more clock cycles before allowing the I/O to become active. This allows other configuration devices, such as PROMs, to be disconnected using the DONE signal so that there is no bus contention when the I/Os become active. In addition to controlling the FPGA during start-up, other start-up techniques that avoid contention include using isolation devices between the FPGA and other circuits in the system, reassigning I/O locations, and maintaining I/Os as 3stated outputs until contentions are resolved. Each of these start-up options can be selected during bit stream generation in ispLEVER, using Advanced Options. For more information, please see the ispLEVER documentation. 85 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA States of Operation (continued) Reconfiguration To reconfigure the FPGA when the device is operating in the system, a low pulse is input into PRGM. The configuration data in the FPGA is cleared, and the I/Os not used for configuration are 3-stated. The FPGA then samples the mode select inputs and begins reconfiguration. When reconfiguration is complete, DONE is released, allowing it to be pulled high. SE L D E IS C C T O D N E TI VI N C U E ED S CCLK_NOSYNC F DONE C1 C2 C3 C4 C1 C2 C3 C4 Partial Reconfiguration C1 C2 C3 C4 All ORCA device families have been designed to allow a partial reconfiguration of the FPGA at any time. This is done by setting a bit stream option in the previous configuration sequence that tells the FPGA to not reset all of the configuration RAM during a reconfiguration. Then only the configuration frames that are to be modified need to be rewritten, thereby reducing the configuration time. I/O GSRN ACTIVE CCLK_SYNC DONE IN DONE I/O F C1, C2, C3, OR C4 GSRN ACTIVE UCLK Di Di + 1 Di + 2 Di + 3 Di + 4 Di Di + 1 Di + 2 Di + 3 Di + 4 Other bit stream options are also available that allow one portion of the FPGA to remain in operation while a partial reconfiguration is being done. If this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the FPGA and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded. UCLK_NOSYNC F DONE I/O C1 GSRN ACTIVE U1 U2 U3 U4 U1 U2 U3 U4 U1 U2 U3 U4 Other Configuration Options There are many other configuration options available to the user that can be set during bit stream generation in ispLEVER. These include options to enable boundary scan and/or the microprocessor interface (MPI) and/or the programmable clock manager (PCM), readback options, and options to control and use the internal oscillator after configuration. UCLK_SYNC DONE IN DONE I/O GSRN ACTIVE C1 F U1, U2, U3, OR U4 Di Di + 1 Di + 2 Di + 3 Di Di + 1 Di + 2 Di + 3 Di + 4 UCLK PERIOD SYNCHRONIZATION UNCERTAINTY Note: F = finished, no more CLKs required. 5-2761(F) Other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, disable the 3-state of I/Os during configuration, and disable the reset of internal RAMs during configuration to allow for partial configurations (see above). For more information on how to set these and other configuration options, please see the ispLEVER documentation. Figure 51. Start-Up Waveforms 86 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Configuration Data Frame The ispLEVER Development System interfaces with front-end design entry tools and provides tools to produce a fully configured FPGA. This section discusses using the ispLEVER Development System to generate configuration RAM data and then provides the details of the configuration frame format. Configuration data can be presented to the FPGA in two frame formats: autoincrement and explicit. A detailed description of the frame formats is shown in Figure 52, Figure 53, and Table 32. The two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. In both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count field representing the total number of configuration clocks needed to complete the loading of the FPGAs. SE L D E IS C C T O D N E TI VI N C U E ED S Configuration Data Format The ORCA OR3Cxx and OR3Txxx Series FPGAs are bit stream compatible. Using ispLEVER to Generate Configuration RAM Data The configuration data bit stream defines the I/O functionality, logic, and interconnections within the FPGA. The bit stream is generated by the development system. The bit stream created by the bit stream generation tool is a series of 1s and 0s used to write the FPGA configuration RAM. It can be loaded into the FPGA using one of the configuration modes discussed later. In the bit stream generator, the designer selects options that affect the FPGA's functionality. Using the output of the bit stream generator, circuit_name.bit, the development system's download tool can load the configuration data into the ORCA series FPGA evaluation board from a PC or workstation. Alternatively, a user can program a PROM (such as a Serial ROM or a standard EPROM) and load the FPGA from the PROM. The development system's PROM programming tool produces a file in .mks or .exo format. Following the header frame is a mandatory ID frame. (Note that the ID frame was optional in the ORCA 2C and 2C/TxxA Series.) The ID frame contains data used to determine if the bit stream is being loaded to the correct type of ORCA FPGA (i.e., a bit stream generated for an OR3T55 is being sent to an OR3T55). Error checking is always enabled for Series 3 devices, through the use of an 8-bit checksum. One bit in the ID frame also selects between the autoincrement and explicit address modes for this load of the configuration data. A configuration data frame follows the ID frame. A data frame starts with a 01-start bit pair and ends with enough 1-stop bits to reach a byte boundary. If using autoincrement configuration mode, subsequent data frames can follow. If using explicit mode, one or more address frames must follow each data frame, telling the FPGA at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). Following all data and address frames is the postamble. The format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones. Lattice Semiconductor 87 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Configuration Data Format (continued) CONFIGURATION DATA CONFIGURATION DATA 0 0 1 0 0 1 ID FRAME CONFIGURATION DATA FRAME 1 0 0 CONFIGURATION DATA FRAME 2 POSTAMBLE SE L D E IS C C T O D N E TI VI N C U E ED S PREAMBLE LENGTH COUNT 0 1 CONFIGURATION HEADER 5-5759(F) Figure 52. Serial Configuration Data Format--Autoincrement Mode CONFIGURATION DATA 0 0 1 0 PREAMBLE LENGTH COUNT 0 1 ID FRAME CONFIGURATION DATA 0 0 CONFIGURATION DATA FRAME 1 0 1 ADDRESS FRAME 1 0 0 CONFIGURATION DATA FRAME 2 ADDRESS FRAME 2 0 0 POSTAMBLE CONFIGURATION HEADER 5-5760(F) Figure 53. Serial Configuration Data Format--Explicit Mode Table 32. Configuration Frame Format and Contents Header ID Frame Configuration Data Frame (repeated for each data frame) Configuration Address Frame Postamble 11110010 24-bit Length Count 11111111 0101 1111 1111 1111 Configuration Mode Reserved [41:0] ID Checksum 11111111 01 Data Bits Alignment Bits = 0 Checksum 11111111 00 14 Address Bits Checksum 11111111 00 11111111 111111 1111111111111111 Preamble Configuration frame length. Trailing header--8 bits. ID frame header. 00 = autoincrement, 01 = explicit. Reserved bits set to 0. 20-bit part ID. 8-bit checksum. Eight stop bits (high) to separate frames. Data frame header. Number of data bits depends upon device. String of 0 bits added to bit stream to make frame header, plus data bits reach a byte boundary. 8-bit checksum. Eight stop bits (high) to separate frames. Address frame header. 14-bit address of location to start data storage. 8-bit checksum. Eight stop bits (high) to separate frames. Postamble header. Dummy address. 16 stop bits.* * In MPI configuration mode, the number of stop bits = 32. Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode. 88 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Configuration Data Format (continued) The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in Table 33. Table 33. Configuration Frame Size OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 # of Frames 856 984 1240 1496 1880 Data Bits/Frame 202 232 292 352 442 Configuration Data (# of frames x # of data bits/frame) 172,912 228,288 362,080 526,592 830,960 Maximum Total # Bits/Frame (align bits, 01 frame start, 8-bit checksum, 8 stop bits) 224 256 312 376 464 Maximum Configuration Data (# bits/frame x # of frames) 191,744 251,904 386,880 562,496 872,320 Maximum PROM Size (bits) (add configuration header and postamble) 191,912 252,072 387,048 562,664 872,488 SE L D E IS C C T O D N E TI VI N C U E ED S Devices Bit Stream Error Checking There are three different types of bit stream error checking performed in the ORCA Series 3 FPGAs: ID frame, frame alignment, and CRC checking. The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are flagged as an ID error. This frame is automatically created by the bit stream generation program in ispLEVER. Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to 1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment error. Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on evaluation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and data frames. When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will remain in this state until either the RESET or PRGM pins are asserted. If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the MPI registers by the FPGA configuration logic. The PGRM bit of the MPI control register can also be used to reset out of the error condition and restart configuration. Lattice Semiconductor 89 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Master Parallel Mode There are eight methods for configuring the FPGA. Seven of the configuration modes are selected on the M0, M1, and M2 inputs. The eighth configuration mode is accessed through the boundary-scan interface. A fourth input, M3, is used to select the frequency of the internal oscillator, which is the source for CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz frequency is selected when the M3 input is unconnected or driven to a high state. The master parallel configuration mode is generally used to interface to industry-standard, byte-wide memory, such as the 2764 and larger EPROMs. Figure 54 provides the connections for master parallel mode. The FPGA outputs an 18-bit address on A[17:0] to memory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serialized starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. SE L D E IS C C T O D N E TI VI N C U E ED S FPGA Configuration Modes There are three basic FPGA configuration modes: master, slave, and peripheral. The configuration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the control signals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK input. In the three peripheral modes, the FPGA acts as a microprocessor peripheral. Table 34 lists the functions of the configuration mode pins. Note that two configuration modes previously available on the OR2Cxx and OR2C/TxxA devices (master parallel down and synchronous peripheral) have been removed for Series 3 devices. DOUT A[17:0] A[17:0] D[7:0] D[7:0] EPROM OE DONE CCLK TO DAISYCHAINED DEVICES ORCA SERIES FPGA CE Table 34. Configuration Modes PROGRAM M2 M1 M0 CCLK 0 0 0 0 0 1 0 1 0 Output Input Output 0 1 1 Output 1 1 1 1 0 0 1 1 0 1 0 1 Output Output Input Configuration Mode Master Serial Slave Parallel Microprocessor: Motorola* PowerPC Microprocessor: Intel i960 Master Parallel Async Peripheral Reserved Slave Serial * Motorola is a registered trademark of Motorola, Inc. 90 Data Serial Parallel Parallel Parallel Parallel Parallel Serial VDD VDD OR GND PRGM M2 M1 M0 HDC LDC RCLK Figure 54. Master Parallel Configuration Schematic In master parallel mode, the starting memory address is 00000 Hex, and the FPGA increments the address for each byte loaded. One master mode FPGA can interface to the memory and provide configuration data on DOUT to additional FPGAs in a daisy-chain. The configuration data on DOUT is provided synchronously with the falling edge of CCLK. The frequency of the CCLK output is eight times that of RCLK. Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) configuration, the high on the FPGA's DONE disables the serial ROM. Master Serial Mode Serial ROMs can also be cascaded to support the configuration of multiple FPGAs or to load a single FPGA when configuration data requirements exceed the capacity of a single serial ROM. After the last bit from the first serial ROM is read, the serial ROM outputs CEO low and 3-states the DATA output. The next serial ROM recognizes the low on CE input and outputs configuration data on the DATA output. After configuration is complete, the FPGA's DONE output into CE disables the serial ROMs. SE L D E IS C C T O D N E TI VI N C U E ED S In the master serial mode, the FPGA loads the configuration data from an external serial ROM. The configuration data is either loaded automatically at start-up or on a PRGM command to reconfigure. The ATT1700A Series Serial PROMs can be used to configure the FPGA in the master serial mode. This provides a simple 4-pin interface in a compact package. Configuration in the master serial mode can be done at powerup and/or upon a configure command. The system or the FPGA must activate the serial ROM's RESET/OE and CE inputs. At powerup, the FPGA and serial ROM each contain internal power-on reset circuitry that allows the FPGA to be configured without the system providing an external signal. The power-on reset circuitry causes the serial ROM's internal address pointer to be reset. After powerup, the FPGA automatically enters its initialization phase. The serial ROM/FPGA interface used depends on such factors as the availability of a system reset pulse, availability of an intelligent host to generate a configure command, whether a single serial ROM is used or multiple serial ROMs are cascaded, whether the serial ROM contains a single or multiple configuration programs, etc. Because of differing system requirements and capabilities, a single FPGA/serial ROM interface is generally not appropriate for all applications. Data is read in the FPGA sequentially from the serial ROM. The DATA output from the serial ROM is connected directly into the DIN input of the FPGA. The CCLK output from the FPGA is connected to the CLK input of the serial ROM. During the configuration process, CCLK clocks one data bit on each rising edge. Since the data and clock are direct connects, the FPGA/serial ROM design task is to use the system or FPGA to enable the RESET/OE and CE of the serial ROM(s). There are several methods for enabling the serial ROM's RESET/OE and CE inputs. The serial ROM's RESET/OE is programmable to function with RESET active-high and OE active-low or RESET activelow and OE active-high. In Figure 55, serial ROMs are cascaded to configure multiple daisy-chained FPGAs. The host generates a 500 ns low pulse into the FPGA's PRGM input. The FPGA's INIT input is connected to the serial ROMs' RESET/OE input, which has been programmed to function with RESET active-low and OE active-high. The FPGA DONE is routed to the CE pin. The low on DONE enables the serial ROMs. At the completion of Lattice Semiconductor This FPGA/serial ROM interface is not used in applications in which a serial ROM stores multiple configuration programs. In these applications, the next configuration program to be loaded is stored at the ROM location that follows the last address for the previous configuration program. The reason the interface in Figure 55 will not work in this application is that the low output on the INIT signal would reset the serial ROM address pointer, causing the first configuration to be reloaded. In some applications, there can be contention on the FPGA's DIN pin. During configuration, DIN receives configuration data, and after configuration, it is a user I/O. If there is contention, an early DONE at start-up (selected in ispLEVER) may correct the problem. An alternative is to use LDC to drive the serial ROM's CE pin. In order to reduce noise, it is generally better to run the master serial configuration at 1.25 MHz (M3 pin tied high), rather than 10 MHz, if possible. DATA DOUT DIN CLK TO DAISYCHAINED DEVICES CCLK ATT1700A CE RESET/OE DONE INIT ORCA SERIES FPGA CEO DATA CLK PRGM ATT1700A CE RESET/OE CEO TO MORE SERIAL ROMs AS NEEDED M2 M1 M0 PROGRAM 5-4456.1(F) Figure 55. Master Serial Configuration Schematic 91 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) DOUT Asynchronous Peripheral Mode PRGM D[7:0] RDY/BUSY INIT DONE 8 MICROPROCESSOR CCLK SE L D E IS C C T O D N E TI VI N C U E ED S Figure 56 shows the connections needed for the asynchronous peripheral mode. In this mode, the FPGA system interface is similar to that of a microprocessorperipheral interface. The microprocessor generates the control signals to write an 8-bit byte into the FPGA. The FPGA control inputs include active-low CS0 and activehigh CS1 chip selects and WR and RD inputs. The chip selects can be cycled or maintained at a static level during the configuration cycle. Each byte of data is written into the FPGA's D[7:0] input pins. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. TO DAISYCHAINED DEVICES The FPGA provides an RDY/BUSY status output to indicate that another byte can be loaded. A low on RDY/ BUSY indicates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. The shortest time RDY/BUSY is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. The longest time for RDY/BUSY to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration RAM. The RDY/BUSY status is also available on the D7 pin by enabling the chip selects, setting WR high, and applying RD low, where the RD input provides an output enable for the D7 pin when RD is low. The D[6:0] pins are not enabled to drive when RD is low and, therefore, only act as input pins in asynchronous peripheral mode. Optionally, the user can ignore the RDY/BUSY status and simply wait until the maximum time it would take for the RDY/BUSY line to go high, indicating the FPGA is ready for more data, before writing the next data byte. 92 ADDRESS DECODE LOGIC CS0 CS1 BUS CONTROLLER RD WR VDD M2 M1 M0 ORCA SERIES FPGA HDC LDC Figure 56. Asynchronous Peripheral Configuration Microprocessor Interface (MPI) Mode The built-in MPI in Series 3 FPGAs is designed for use in configuring the FPGA. Figure 57 and Figure 58 show the glueless interface for FPGA configuration and readback from the PowerPC and i960 processors, respectively. When enabled by the mode pins, the MPI handles all configuration/readback control and handshaking with the host processor. For single FPGA configuration, the host sets the configuration control register PRGM bit to zero then back to a one and, after reading that the INIT signal is high in the MPI status register, transfers data 8 bits at a time to the FPGA's D[7:0] input pins. If configuring multiple FPGAs through daisy-chain operation is desired, the MP_DAISY bit must be set in the configuration control register of the MPI. Because of the latency involved in a daisy-chain configuration, the MP_HOLD_BUS bit may be set to zero rather than one for daisy-chain operation. This allows the MPI to acknowledge the data transfer before the configuration information has been serialized and transferred on the FPGA daisy-chain. The early acknowledgment frees the host processor to perform other system tasks. Configuring with the MP_HOLD_BUS bit at zero requires that the host microprocessor poll the RDY/BUSY bit of the MPI status register and/or use the MPI interrupt capability to confirm the readiness of the MPI for more configuration data. Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) SE L D E IS C C T O D N E TI VI N C U E ED S There are two options for using the host interrupt request in configuration mode. The configuration control register offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the FPGA is ready for more configuration data. The MPI status register may be used in conjunction with, or in place of, the interrupt request options. The status register contains a 2-bit field to indicate the bit stream error status. As previously mentioned, there is also a bit to indicate the MPI's readiness to receive another byte of configuration data. A flow chart of the MPI configuration process is shown in Figure 59. The MPI status and configuration register bit maps can be found in the Special Function Blocks section and MPI configuration timing information is available in the Timing Characteristics section of this data sheet. Configuration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user mode by setting the MP_USER bit to 1 in the configuration control register prior to the start of configuration or through a configuration option. To perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the RD_CFG bit to 0 in the configuration control register. Readback data is returned 8 bits at a time to the readback data register and is valid when the DATA_RDY bit of the status register is 1. There is no error checking during readback. A flow chart of the MPI readback operation is shown in Figure 60. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI readback. D[7:0] A[27:31] CLKOUT RD/WR TA POWERPC BI IRQx TS A26 A25 8 DOUT CCLK D[7:0] A[4:0] MPI_CLK MPI_RW ORCA MPI_ACK SERIES 3 MPI_BI FPGA MPI_IRQ MPI_STRB DONE CS0 INIT CS1 HDC LDC POWER ON WITH VALID M[3:0] TO DAISYCHAINED DEVICES WRITE CONFIGURATION CONTROL REGISTER BITS READ STATUS REGISTER INIT = 1? NO YES 5-5761(F) READ STATUS REGISTER Note: FPGA shown as a memory-mapped peripheral using CS0 and CS1. Other decoding schemes are possible using CS0 and/or CS1. Figure 57. PowerPC/MPI Configuration Schematic DONE YES DONE = 1? NO i960 SYSTEM CLOCK AD[7:0] 8 CLKIN W/R RDYRCV XINTx ALE i960 ADS BE0 BE1 VDD D[7:0] DOUT CCLK MPI_CLK MPI_RW MPI_ACK MPI_IRQ ORCA MPI_ALE SERIES 3 MPI_STRB FPGA MPI_BE0 MPI_BE1 DONE INIT CS1 HDC CS0 LDC TO DAISYCHAINED DEVICES ERROR YES BIT STREAM ERROR? NO DATA_RDY = 1? NO YES WRITE DATA TO CONFIGURATION DATA REG 5-5762(F) 5-5763(F) Note: FPGA shown as only system peripheral with fixed chip select signals. For multiperipheral systems, address decoding and/or latching can be used to implement chip selects. Figure 59. Configuration Through MPI Figure 58. i960/MPI Configuration Schematic Lattice Semiconductor 93 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) ENABLE MICROPROCESSOR INTERFACE IN USER MODE SE L D E IS C C T O D N E TI VI N C U E ED S SET READBACK ADDRESS WRITE RD_CFG TO 0 IN CONTROL REGISTER 1 READ STATUS REGISTER NO DATA_RDY = 1? YES READ DATA REGISTER ERROR NO DATA = 0xFF? YES READ DATA REGISTER ERROR NO DATA = 0xFF? YES READ DATA REGISTER ERROR NO START OF FRAME FOUND? YES READ UNTIL END OF FRAME STOP WRITE RD_CFG TO 1 IN CONTROL REGISTER 1 YES FINISHED READBACK? NO 5-5764(F) Figure 60. Readback Through MPI 94 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) Slave Parallel Mode Slave Serial Mode The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. SE L D E IS C C T O D N E TI VI N C U E ED S The slave serial mode is primarily used when multiple FPGAs are configured in a daisy-chain (see the DaisyChaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in the slave serial mode can be used as the lead device in a daisy-chain. Figure 61 shows the connections for the slave serial configuration mode. The configuration data is provided into the FPGA's DIN input synchronous with the configuration clock CCLK input. After the FPGA has loaded its configuration data, it retransmits the incoming configuration data on DOUT. CCLK is routed into all slave serial mode devices in parallel. Multiple slave FPGAs can be loaded with identical configurations simultaneously. This is done by loading the configuration data into the DIN inputs in parallel. DOUT INIT MICROPROCESSOR OR DOWNLOAD CABLE PRGM DONE TO DAISYCHAINED DEVICES ORCA SERIES FPGA Figure 62 is a schematic of the connections for the slave parallel configuration mode. WR and CS0 are active-low chip select signals, and CS1 is an activehigh chip select signal. These chip selects allow the user to configure multiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can then be used to select the FPGA(s) to be configured with a given bit stream. The chip selects must be active for each valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. 8 CCLK DIN D[7:0] DONE INIT MICROPROCESSOR OR SYSTEM VDD M2 M1 M0 HDC LDC CCLK PRGM ORCA SERIES FPGA VDD CS1 CS0 5-4485(F) WR Figure 61. Slave Serial Configuration Schematic M2 HDC M1 LDC M0 5-4487(F) Figure 62. Slave Parallel Configuration Schematic Lattice Semiconductor 95 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) The loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the number of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT. Daisy-Chaining Multiple FPGAs can be configured by using a daisychain of the FPGAs. Daisy-chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave parallel mode. (Daisy-chaining is available with the boundary-scan ram_w instruction discussed later.) SE L D E IS C C T O D N E TI VI N C U E ED S The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the negative edge of CCLK. Figure 63 shows the connections for loading multiple FPGAs in a daisychain configuration. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on positive CCLK and out on negative CCLK edges. The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the configuration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead device and to all of the daisy-chained devices. An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its configuration data frames. CCLK A[17:0] EPROM D[7:0] D[7:0] OE CE DONE CCLK DIN ORCA SERIES FPGA MASTER DIN DOUT ORCA SERIES FPGA SLAVE #1 VDD VDD OR GND M2 M1 M0 INIT HDC LDC RCLK VDD PRGM M2 M1 M0 DOUT ORCA SERIES FPGA SLAVE #2 DONE PRGM PROGRAM CCLK DOUT A[17:0] VDD DONE INIT VDD HDC LDC RCLK PRGM M2 M1 M0 INIT HDC LDC RCLK VDD 5-4488(F Figure 63. Daisy-Chain Configuration Schematic As seen in Figure 63, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be required, depending upon the start-up sequence desired. 96 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) Daisy-Chaining with Boundary Scan SE L D E IS C C T O D N E TI VI N C U E ED S Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chaining operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on the positive TCK and out on the negative TCK edges. An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device had received its configuration read into TDI of downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK. Figure 63 shows the connections for loading multiple FPGAs in a JTAG daisy-chain configuration. Lattice Semiconductor 97 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. SE L D E IS C C T O D N E TI VI N C U E ED S The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. Table 35. Absolute Maximum Ratings Parameter Symbol Min Max Unit Storage Temperature Tstg -65 150 C Supply Voltage with Respect to Ground VDD -0.5 7.0 V Input Signal with Respect to Ground -- -0.5 VDD + 0.3 V Signal Applied to High-impedance Output -- -0.5 VDD + 0.3 V Maximum Package Body Temperature -- -- 220 C Recommended Operating Conditions Table 36. Recommended Operating Conditions OR3Cxx Mode Commercial Industrial OR3Txxx Temperature Range (Ambient) Supply Voltage (VDD) Temperature Range (Ambient) Supply Voltage (VDD) 0 C to 70 C 5 V 5% 0 C to 70 C 3.0 V to 3.6 V -40 C to +85 C 5 V 10% -40 C to +85 C 3.0 V to 3.6 V Note: The maximum recommended junction temperature (TJ) during operation is 125 C. 98 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Electrical Characteristics Table 37. Electrical Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol OR3Cxx OR3Txxx SE L D E IS C C T O D N E TI VI N C U E ED S Parameter Input Voltage: High Low VIH VIL Input Voltage: High Low VIH VIL Input Voltage: High Low VIH VIL Output Voltage: High Low VOH VOL Test Conditions Min Input configured as CMOS (includes OR3Txxx) Max Min 50% VDD VDD + 0.5 50% VDD GND - 0.5 20% VDD GND - 0.5 Unit Max VDD + 0.5 30% VDD V V OR3Txxx 5 V Tolerant -- -- -- -- 50% VDD GND - 0.5 5.8 V 30% VDD V V 2.0 -0.5 VDD + 0.3 0.8 -- -- -- -- V V VDD = min, IOH = 6 mA or 3 mA VDD = min, IOL = 12 mA or 6 mA 2.4 -- -- 0.4 2.4 -- -- 0.4 V V IL VDD = max, VIN = VSS or VDD -10 10 -10 10 A Standby Current: OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 IDDSB OR3Cxx (TA = 25 C, VDD = 5.0 V) OR3Txxx (TA = 25 C, VDD = 3.3 V) internal oscillator running, no output loads, inputs VDD or GND (after configuration) -- -- -- -- -- -- -- 4.06 4.56 -- -- -- -- -- -- 4.70 4.90 5.30 5.80 6.70 mA mA mA mA mA Standby Current: OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 IDDSB OR3Cxx (TA = 25 C, VDD = 5.0 V) OR3Txxx (TA = 25 C, VDD = 3.3 V) internal oscillator stopped, no output loads, inputs VDD or GND (after configuration) -- -- -- -- -- -- -- 3.05 3.42 -- -- -- -- -- -- 3.52 3.68 3.98 4.35 5.02 mA mA mA mA mA Powerup Current: OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 Ipp -- -- 3.2 5.4 -- -- -- -- -- -- 1.2 1.6 2.7 4.0 6.5 -- -- -- -- -- mA mA mA mA mA Data Retention Voltage VDR TA = 25 C 2.3 -- 2.3 -- V Input Capacitance CIN OR3Cxx (TA = 25 C, VDD = 5.0 V) OR3Txxx (TA = 25 C, VDD = 3.3 V) Test frequency = 1 MHz -- 9 -- 8 pF -- 9 -- 8 pF Input Leakage Current Output Capacitance Lattice Semiconductor COUT Input configured as TTL (not valid for OR3Txxx) Power supply current @ approximately 1 V, within a recommended power supply ramp rate of 1 ms--200 ms OR3Cxx (TA = 25 C, VDD = 5.0 V) OR3Txxx (TA = 25 C, VDD = 3.3 V) Test frequency = 1 MHz 99 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Electrical Characteristics (continued) Table 37. Electrical Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. OR3Cxx OR3Txxx SE L D E IS C C T O D N E TI VI N C U E ED S Parameter Symbol Test Conditions Min Max Min Max Unit DONE Pull-up Resistor* RDONE -- 100 -- 100 -- k M[3:0] Pull-up Resistors* RM -- 100 -- 100 -- k I/O Pad Static Pull-up Current* IPU OR3Cxx (VDD = 5.25 V, VIN = VSS, TA = 0 C) OR3Txxx (VDD = 3.6 V, VIN = VSS, TA = 0 C) 14.4 50.9 14.4 50.9 A I/O Pad Static Pull-down Current IPD OR3Cxx (VDD = 5.25 V, VIN = VSS, TA = 0 C) OR3Txxx (VDD = 3.6 V, VIN = VSS, TA = 0 C) 26 103 26 103 A I/O Pad Pull-up Resistor* RPU VDD = all, VIN = VSS, TA = 0 C 100 -- 100 -- k I/O Pad Pull-down Resistor RPD VDD = all, VIN = VDD, TA = 0 C 50 -- 50 -- k * On the OR3Txxx devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD. Note: For 3T devices driven to 5 V. 100 Lattice Semiconductor Data Sheet November 2006 Timing Characteristics Description mercial and industrial devices. Table 40 provides the same information for the OR3Txxx devices (both commercial and industrial). The delay values in this data sheet and reported by ispLEVER are shown as 1.00 in the tables. The method for determining the maximum junction temperature is defined in the Package Thermal Characteristics section. Taken cumulatively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach 3 to 1. SE L D E IS C C T O D N E TI VI N C U E ED S To define speed grades, the ORCA Series part number designation (see Ordering Information) uses a singledigit number to designate a speed grade. This number is not related to any single ac parameter. Higher numbers indicate a faster set of timing parameters. The actual speed sorting is based on testing the delay in a path consisting of an input buffer, combinatorial delay through all PLCs in a row, and an output buffer. Other tests are then done to verify other delay parameters, such as routing delays, setup times to FFs, etc. ORCA Series 3C and 3T FPGAs The most accurate timing characteristics are reported by the timing analyzer in the ispLEVER Development System. A timing report provided by the development system after layout divides path delays into logic and routing delays. The timing analyzer can also provide logic delays prior to layout. While this allows routing budget estimates, there is wide variance in routing delays associated with different layouts. The logic timing parameters noted in the Electrical Characteristics section of this data sheet are the same as those in the design tools. In the PFU timing given in Table 41--Table 48, symbol names are generally a concatenation of the PFU operating mode (as defined in Table 3) and the parameter type. The setup, hold, and propagation delay parameters, defined below, are designated in the symbol name by the SET, HLD, and DEL characters, respectively. The values given for the parameters are the same as those used during production testing and speed binning of the devices. The junction temperature and supply voltage used to characterize the devices are listed in the delay tables. Actual delays at nominal temperature and voltage for best-case processes can be much better than the values given. It should be noted that the junction temperature used in the tables is generally 85 C. The junction temperature for the FPGA depends on the power dissipated by the device, the package thermal characteristics (JA), and the ambient temperature, as calculated in the following equation and as discussed further in the Package Thermal Characteristics section: TJmax = TAmax + (P * JA) C Note: The user must determine this junction temperature to see if the delays from ispLEVER should be derated based on the following derating tables. Table 38 and Table 39 provide approximate power supply and junction temperature derating for OR3Cxx comLattice Semiconductor Table 38. Derating for Commercial Devices (OR3Cxx) TJ (C) 0 25 85 100 125 Power Supply Voltage 4.75 V 0.81 0.85 1.00 1.05 1.12 5.0 V 0.79 0.83 0.97 1.02 1.09 5.25 V 0.77 0.81 0.95 1.00 1.07 Table 39. Derating for Industrial Devices (OR3Cxx) TJ (C) --40 0 25 85 100 125 Power Supply Voltage 4.5 V 0.71 0.80 0.84 1.00 1.05 1.12 4.75 V 0.70 0.78 0.82 0.97 1.01 1.09 5.0 V 0.68 0.76 0.80 0.94 0.99 1.06 5.25 V 0.66 0.74 0.78 0.93 0.97 1.04 5.5 V 0.65 0.73 0.77 0.91 0.95 1.02 Table 40. Derating for Commercial/Industrial Devices (OR3Txxx) TJ (C) --40 0 25 85 100 125 Power Supply Voltage 3.0 V 0.73 0.82 0.87 1.00 1.04 1.10 3.3 V 0.66 0.73 0.78 0.90 0.94 1.00 3.6 V 0.61 0.68 0.72 0.83 0.87 0.92 Note: The derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. Since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. The approximate derating values vs. temperature are 0.26% per C for logic delay and 0.45% per C for routing delay. The approximate derating values vs. voltage are 0.13% per mV for both logic and routing delays at 25 C. 101 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Propagation Delay--The time between the specified reference points. The delays provided are the worst case of the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. SE L D E IS C C T O D N E TI VI N C U E ED S In addition to supply voltage, process variation, and operating temperature, circuit and process improvements of the ORCA Series FPGAs over time will result in significant improvement of the actual performance over those listed for a speed grade. Even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed grades higher than that designated on a product brand. Design practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing. The waveform test points are given in the Input/Output Buffer Measurement Conditions section of this data sheet. The timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and the values they reflect are described below. The routing delays are a function of fan-out and the capacitance associated with the CIPs and metal interconnect in the path. The number of logic elements that can be driven (fan-out) by PFUs is unlimited, although the delay to reach a valid logic level can exceed timing requirements. It is difficult to make accurate routing delay estimates prior to design compilation based on fan-out. This is because the CAE software may delete redundant logic inserted by the designer to reduce fanout, and/or it may also automatically reduce fan-out by net splitting. Setup Time--The interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. Hold Time--The interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-State Enable--The time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state. PFU Timing Table 41. Combinatorial PFU Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Combinatorial Delays (TJ = +85 C, VDD = min): Four-input Variables (Kz[3:0] to F[z])* Five-input Variables (F5[A:D] to F[0, 2, 4, 6]) Two-level LUT Delay (Kz[3:0] to F w/feedbk)* Two-level LUT Delay (F5[A:D] to F w/feedbk) Three-level LUT Delay (Kz[3:0] to F w/feedbk)* Three-level LUT Delay (F5[A:D] to F w/feedbk) CIN to COUT Delay (logic mode) Symbol F4_DEL F5_DEL SWL2_DEL SWL2F5_DEL SWL3_DEL SWL3F5_DEL CO_DEL -4 -6 -5 Unit -7 Min Max Min Max Min Max Min Max -- -- -- -- -- -- -- 1.80 1.57 3.66 3.51 5.15 5.08 2.65 -- -- -- -- -- -- -- 1.32 1.23 2.58 2.48 3.63 3.54 1.79 -- -- -- -- -- -- -- 1.05 0.99 2.03 1.94 2.82 2.75 1.43 -- -- -- -- -- -- -- 2.34 2.11 4.87 4.69 6.93 6.89 3.47 ns ns ns ns ns ns ns * Four-input variables' (KZ[3:0]) path delays are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes. 102 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) FDBK-DEL SE L D E IS C C T O D N E TI VI N C U E ED S PFU KZ[3:0] F4_DEL LUT 8 F[7:0] KZ[3:0], F5[A:D] F5-DEL LUT 4 F[6, 4, 2, 0] F4_DEL/ F5_DEL LUT KZ[3:0] F[7:0] F4_DEL/ LUT SWL2_DEL F4_DEL/ F5_DEL LUT F[7:0] OMUX_DEL F4_DEL/ F5_DEL LUT KZ[3:0] O[9:0] F4_DEL/ LUT SWL3_DEL F4_DEL/ F5_DEL LUT F5[A:D] F[7:0] F4_DEL/ F5_DEL LUT SWL2F5_DEL F4_DEL/ F5_DEL LUT F[7:0] F4_DEL/ F5_DEL LUT F5[A:D] F4_DEL/ F5_DEL LUT SWL3F5_DEL Note: See Table 46 for an explanation of FDBK_DEL and OMUX_DEL. 5-5751(F) Figure 64. Combinatorial PFU Timing Lattice Semiconductor 103 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 42. Sequential PFU Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter Symbol -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max Input Requirements Clock Low Time CLKL_MPW 3.36 -- 2.07 -- 0.94 -- 0.72 -- ns Clock High Time CLKH_MPW 1.61 -- 1.06 -- 0.54 -- 0.45 -- ns Global S/R Pulse Width (GSRN) GSR_MPW 3.36 -- 2.07 -- 0.94 -- 0.72 -- ns Local S/R Pulse Width LSR_MPW 3.36 -- 2.07 -- 0.94 -- 0.72 -- ns F4_SET F5_SET DIN_SET CINDIR_SET CE1_SET CE2_SET LSR_SET SEL_SET SWL2_SET SWL2F5_SET SWL3_SET SWL3F5_SET 1.99 1.79 0.47 1.25 2.86 1.68 1.86 1.37 3.98 4.06 6.49 6.39 -- -- -- -- -- -- -- -- -- -- -- -- 1.47 1.33 0.32 0.99 2.15 1.30 1.36 1.00 2.99 2.97 4.81 4.73 -- -- -- -- -- -- -- -- -- -- -- -- 1.08 1.03 0.18 0.71 1.80 0.95 0.86 0.92 2.13 2.29 3.42 3.34 -- -- -- -- -- -- -- -- -- -- -- -- 0.85 0.81 0.16 0.58 1.37 0.77 0.68 0.70 1.63 1.68 2.64 2.57 -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns DIN_HLD CINDIR_HLD 0.00 0.00 -- -- 0.00 0.00 -- -- 0.00 0.00 -- -- 0.00 0.00 -- -- ns ns CE1_HLD CE2_HLD LSR_HLD SEL_HLD -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns LSR_DEL -- 7.02 -- 5.29 -- 3.64 -- 2.90 ns GSR_DEL REG_DEL -- -- 5.21 2.38 -- -- 3.90 1.75 -- -- 2.55 1.26 -- -- 2.00 0.97 ns ns LTCH_DEL LTCHD_DEL -- -- 2.51 2.73 -- -- 1.88 2.10 -- -- 1.21 1.38 -- -- 0.96 1.12 ns ns Combinatorial Setup Times (TJ = +85 C, VDD = min): Four-input Variables to Clock (Kz[3:0] to CLK)* Five-input Variables to Clock (F5[A:D] to CLK) Data In to Clock (DIN[7:0] to CLK) Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK) Clock Enable to Clock (CE to CLK) Clock Enable to Clock (ASWE to CLK) Local Set/Reset to Clock (SYNC) (LSR to CLK) Data Select to Clock (SEL to CLK) Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)* Two-level LUT to Clock (F5[A:D] to CLK w/feedbk) Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)* Three-level LUT to Clock (F5[A:D] to CLK w/feedbk) Combinatorial Hold Times (TJ = all, VDD = all): Data In (DIN[7:0] from CLK) Carry-in from Clock, DIRECT to REGCOUT (CIN from CLK) Clock Enable (CE from CLK) Clock Enable from Clock (ASWE from CLK) Local Set/Reset from Clock (sync) (LSR from CLK) Data Select from Clock (SEL from CLK) All Others Output Characteristics Sequential Delays (TJ = +85 C, VDD = min): Local S/R (async) to PFU Out (LSR to Q[7:0], REGCOUT) Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT) Clock to PFU Out--Register (CLK to Q[7:0], REGCOUT) Clock to PFU Out--Latch (CLK to Q[7:0]) Transparent Latch (DIN[7:0] to Q[7:0]) * Four-input variables' (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes. Note: The table shows worst-case delays. ispLEVER reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. 104 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 43. Ripple Mode PFU Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter (TJ = +85 C, VDD = min) Symbol -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max Full Ripple Setup Times (byte wide): Operands to Clock (Kz[1:0] to CLK) Bitwise Operands to Clock (Kz[1:0] to CLK at F[z]) Fast Carry-in to Clock (FCIN to CLK) Carry-in to Clock (CIN to CLK) Add/Subtract to Clock (ASWE to CLK) Operands to Clock (Kz[1:0] to CLK at REGCOUT) Fast Carry-in to Clock (FCIN to CLK at REGCOUT) Carry-in to Clock (CIN to CLK at REGCOUT) Add/Subtract to Clock (ASWE to CLK at REGCOUT) RIP_SET FRIP_SET FCIN_SET CIN_SET AS_SET RIPRC_SET FCINRC_SET CINRC_SET ASRC_SET 3.50 1.99 2.55 3.80 8.82 2.09 2.29 3.09 8.14 -- -- -- -- -- -- -- -- -- 2.50 1.47 1.87 2.79 6.18 1.61 1.76 2.36 5.73 -- -- -- -- -- -- -- -- -- 1.96 1.08 1.34 1.97 4.68 1.19 1.28 1.73 4.54 -- -- -- -- -- -- -- -- -- 1.48 0.85 1.04 1.56 3.50 0.93 1.02 1.35 3.39 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns Full Ripple Hold Times (TJ = all, VDD = all): Fast Carry-in from Clock (FCIN from CLK at REGCOUT) All Others FCINRC_HLD 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns GENERIC_HLD 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns Half Ripple Setup Times (nibble wide): Operands to Clock (Kz[1:0] to CLK) Bitwise Operands to Clock (Kz[1:0] to CLK at F[z]) Fast Carry-in to Clock (FCIN to CLK) Carry-in to Clock (CIN to CLK) Add/Subtract to Clock (ASWE to CLK) Operands to Clock (Kz[1:0] to CLK at REGCOUT) Fast Carry-in to Clock (FCIN to CLK at REGCOUT) Carry-in to Clock (CIN to CLK at REGCOUT) Add/Subtract to Clock (ASWE to CLK at REGCOUT) HRIP_SET HFRIP_SET HFCIN_SET HCIN_SET HAS_SET HRIPRC_SET HFCINRC_SET HCINRC_SET HASRC_SET 3.91 1.99 2.55 3.80 8.82 3.03 2.29 3.09 8.14 -- -- -- -- -- -- -- -- -- 2.81 1.47 1.87 2.79 6.18 2.31 1.76 2.36 5.73 -- -- -- -- -- -- -- -- -- 2.21 1.08 1.34 1.97 4.68 1.68 1.28 1.73 4.54 -- -- -- -- -- -- -- -- -- 1.66 0.85 1.04 1.56 3.50 1.32 1.02 1.35 3.39 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns HFCINRC_HLD 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns GENERIC_HLD 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns Half Ripple Hold Times (TJ = all, VDD = all): Fast Carry-in from Clock (HFCIN from CLK at REGCOUT) All Others Note: The table shows worst-case delay for the ripple chain. ispLEVER reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. Lattice Semiconductor 105 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 43. Ripple Mode PFU Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter (TJ = +85 C, VDD = min) Symbol -4 Min Max Full Ripple Delays (byte wide): RIPCO_DEL Operands to Carry-out (Kz[1:0] to COUT) RIPFCO_DEL Operands to Carry-out (Kz[1:0] to FCOUT) RIP_DEL Operands to PFU Out (Kz[1:0] to F[7:0]) FRIP_DEL Bitwise Operands to PFU Out (Kz[1:0] to F[z]) FCINCO_DEL Fast Carry-in to Carry-out (FCIN to COUT) Fast Carry-in to Fast Carry-out (FCIN to FCOUT) FCINFCO_DEL CINCO_DEL Carry-in to Carry-out (CIN to COUT) CINFCO_DEL Carry-in to Fast Carry-out (CIN to FCOUT) FCIN_DEL Fast Carry-in PFU Out (FCIN to F[7:0]) CIN_DEL Carry-in PFU Out (CIN to F[7:0]) ASCO_DEL Add/Subtract to Carry-out (ASWE to COUT) ASFCO_DEL Add/Subtract to Carry-out (ASWE to FCOUT) AS_DEL Add/Subtract to PFU Out (ASWE to F[7:0]) -- -- -- -- -- -- -- -- -- -- -- -- -- 5.32 5.30 7.37 2.34 2.59 2.57 3.47 3.46 6.03 6.91 8.28 8.11 10.66 Half Ripple Delays (nibble wide): Operands to Carry-out (Kz[1:0] to COUT) Operands to Fast Carry-out (Kz[1:0] to FCOUT) Operands to PFU Out (Kz[1:0] to F[3:0]) Bitwise Operands to PFU Out (Kz[1:0] to F[z]) Fast Carry-in to Carry-out (FCIN to COUT) Fast Carry-in to Fast Carry-out (FCIN to FCOUT) Carry-in to Carry-out (CIN to COUT) Carry-in to Carry-out (CIN to FCOUT) Fast Carry-in PFU Out (FCIN to F[3:0]) Carry-in PFU Out (CIN to F[3:0]) Add/Subtract to Carry-out (ASWE to COUT) Add/Subtract to Carry-out (ASWE to FCOUT) Add/Subtract to PFU Out (ASWE to F[3:0]) -- -- -- -- -- -- -- -- -- -- -- -- -- 5.32 5.30 5.50 2.34 2.59 2.57 3.47 3.46 3.76 4.65 8.28 8.11 9.12 HRIPCO_DEL HRIPFCO_DEL HRIP_DEL HFRIP_DEL HFCINCO_DEL HFCINFCO_DEL HCINCO_DEL HCINFCO_DEL HFCIN_DEL HCIN_DEL HASCO_DEL HASFCO_DEL HAS_DEL -5 -6 Unit -7 Min Max Min Max Min Max -- -- -- -- -- -- -- -- -- -- -- -- -- 4.11 4.10 5.60 1.80 1.99 1.98 2.65 2.64 4.55 5.21 5.89 5.78 7.55 -- -- -- -- -- -- -- -- -- -- -- -- -- 2.98 2.98 4.18 1.32 1.43 1.41 1.79 1.78 3.21 3.53 4.58 4.48 5.85 -- -- -- -- -- -- -- -- -- -- -- -- -- 2.32 2.32 3.10 1.05 1.14 1.13 1.43 1.43 2.51 3.05 3.45 3.38 4.38 ns ns ns ns ns ns ns ns ns ns ns ns ns -- -- -- -- -- -- -- -- -- -- -- -- -- 4.11 4.10 4.07 1.80 1.99 1.98 2.65 2.64 2.84 3.50 5.89 5.78 6.49 -- -- -- -- -- -- -- -- -- -- -- -- -- 2.98 2.98 3.20 1.32 1.43 1.41 1.79 1.78 2.01 2.33 4.58 4.48 4.86 -- -- -- -- -- -- -- -- -- -- -- -- -- 2.32 2.32 2.40 1.05 1.14 1.13 1.43 1.43 1.58 2.12 3.45 3.38 3.69 ns ns ns ns ns ns ns ns ns ns ns ns ns Note: The table shows worst-case delay for the ripple chain. ispLEVER reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. 106 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 44. Synchronous Memory Write Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter Symbol Write Operation for RAM Mode: Maximum Frequency Clock Low Time Clock High Time Clock to Data Valid (CLK to F[6, 4, 2, 0])* Write Operation Setup Time: Address to Clock (CIN to CLK) Address to Clock (DIN[7, 5, 3, 1] to CLK) Data to Clock (DIN[6, 4, 2, 0] to CLK) Write Enable (WREN) to Clock (ASWE to CLK) Write-port Enable 0 (WPE0) to Clock (CE to CLK) Write-port Enable 1 (WPE1) to Clock (LSR to CLK) Write Operation Hold Time: Address from Clock (CIN from CLK) Address from Clock (DIN[7, 5, 3, 1] from CLK) Data from Clock (DIN[6, 4, 2, 0] from CLK) Write Enable (WREN) from Clock (ASWE from CLK) Write-port Enable 0 (WPE0) from Clock (CE from CLK) Write-port Enable 1 (WPE1) from Clock (LSR from CLK) -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max SMCLK_FRQ SMCLKL_MPW SMCLKH_MPW MEM_DEL -- 2.34 3.79 -- 151.00 -- -- 10.00 -- 1.80 2.77 -- 197.00 -- -- 7.14 -- 1.32 2.13 -- 254.00 -- -- 5.00 -- 1.05 1.62 -- WA4_SET WA_SET WD_SET WE_SET WPE0_SET 1.25 0.72 0.02 0.18 2.25 -- -- -- -- -- 0.99 0.52 0.06 0.16 1.69 -- -- -- -- -- 0.71 0.35 0.00 0.14 1.16 -- -- -- -- -- 0.58 0.28 0.00 0.12 0.84 -- -- -- -- -- ns ns ns ns ns WPE1_SET 2.79 -- 2.13 -- 1.58 -- 1.31 -- ns WA4_HLD WA_HLD WD_HLD WE_HLD 0.00 0.00 0.59 0.03 -- -- -- -- 0.00 0.00 0.42 0.00 -- -- -- -- 0.00 0.00 0.40 0.08 -- -- -- -- 0.00 0.00 0.32 0.06 -- -- -- -- ns ns ns ns WPE0_HLD 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns WPE1_HLD 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns 315.00 MHz ns ns 4.08 ns * The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals. Note: The table shows worst-case delays. ispLEVER reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. WA4_SET WA_SET WA4_HLD WA_HLD WD_SET WD_HLD CIN, DIN[7, 5, 3, 1] DIN[6, 4, 2, 0] WE_SET WE_HLD ASWE (WREN) WPE0_SET WPE1_SET WPE0_HLD WPE1_HLD CE (WPE0), LSR (WPE1) TSCH TSCL CK MEM_DEL F[6, 4, 2, 0] 5-4621(F) Figure 65. Synchronous Memory Write Characteristics Lattice Semiconductor 107 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 45. Synchronous Memory Read Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter (TJ = 85 C, VDD = min) Read Operation: Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0]) Data Valid After Address (F5[A:D] to F[6, 4, 2, 0]) Symbol RA_DEL RA4_DEL Read Operation, Clocking Data into Latch/FF: RA_SET Address to Clock Setup Time (Kz[3:0] to CLK) RA4_SET Address to Clock Setup Time (F5[A:D] to CLK) RA_HLD Address from Clock Hold Time (Kz[3:0] from CLK) RA4_HLD Address from Clock Hold Time (F5[A:D] from CLK) Clock to PFU Output--Register (CLK to Q[6, 4, 2, 0]) REG_DEL SMRD_CYC Read Cycle Delay -4 -5 Min Max -- -- 2.34 2.11 -- 1.99 -- 1.79 -- 0.00 -- 0.00 2.38 -- -- 10.48 -6 Min Max Min Max -- -- 1.80 1.57 1.47 -- 1.33 -- 0.00 -- 0.00 -- -- 1.75 -- 7.66 -- -- 1.32 1.23 1.08 -- 1.03 -- 0.00 -- 0.00 -- -- 1.26 -- 7.53 Unit -7 Min Max -- -- 1.05 0.99 ns ns 0.85 0.81 0.00 0.00 -- -- -- -- -- -- 0.97 5.78 ns ns ns ns ns ns Note: The table shows worst-case delays. ispLEVER reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. Kz[3:0], F5[A:D] RA_DEL RA4_DEL F[6, 4, 2, 0] CLK RA_HLD RA4_HLD RA_SET RA4_SET REG_DEL SMRD_CYC Q[3:0] 5-4622(F) Figure 66. Synchronous Memory Read Cycle 108 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) PLC Timing Table 46. PFU Output MUX and Direct Routing Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter (TJ = 85 C, VDD = min) Symbol -4 -5 -7 -6 Unit Min Max Min Max Min Max Min Max OMUX_DEL COO9_DEL RCOO8_DEL -- -- -- 0.50 0.34 0.34 -- -- -- 0.39 0.26 0.26 -- -- -- 0.35 0.24 0.24 -- -- -- 0.28 0.18 0.18 ns ns ns FDBK_DEL ODIR_DEL DDIR_DEL -- -- -- 1.74 2.21 2.69 -- -- -- 1.41 1.77 2.19 -- -- -- 1.48 1.75 2.53 -- -- -- 1.14 1.39 1.98 ns ns ns PFU Output MUX (Fan-out = 1) Output MUX Delay (F[7:0]/Q[7:0] to O[9:0]) Carry-out MUX Delay (COUT to O9) Registered Carry-out MUX Delay (REGCOUT to O8) Direct Routing PFU Feedback (xSW)* PFU to Orthogonal PFU Delay (xSW to xSW) PFU to Diagonal PFU Delay (xBID to xSW) * This is general feedback using switching segments. See the combinatorial PFU timing table for softwired look-up table feedback timing. SLIC Timing Table 47. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter (TJ = 85 C, VDD = min) Symbol -4 -5 -6 -7 Unit Min Max Min Max Min Max Min Max BUF_DEL OBUF_DEL TRI_DEL DECTRI_DEL -- -- -- -- 0.84 0.72 2.55 3.59 -- -- -- -- 0.70 0.61 1.90 2.65 -- -- -- -- 0.94 0.87 1.31 1.91 -- -- -- -- 0.77 0.70 1.01 1.48 ns ns ns ns DEC98_DEL DEC_DEL -- -- 2.39 2.35 -- -- 1.85 1.82 -- -- 1.27 1.23 -- -- 1.02 0.99 ns ns 3-Statable BIDIs BIDI Delay (BRx to BLx, BLx to BRx) BIDI Delay (Ox to BRx, Ox to BLx) BIDI 3-state Enable/Disable Delay (TRI to BL, BR) BIDI 3-state Enable/Disable Delay (BL, BR via DEC, TRI to BL, BR) Decoder Decoder Delay (BR[9:8], BL[9:8] to DEC) Decoder Delay (BR[7:0], BL[7:0] to DEC) Lattice Semiconductor 109 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) PIO Timing Table 48. Programmable I/O (PIO) Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max IN_RIS -- 500 -- 500 -- 500 -- 500 ns IN_FAL -- 500 -- 500 -- 500 -- 500 ns PIO Direct Delays: Pad to In (pad to CLK IN) Pad to In (pad to IN1, IN2) Pad to In Delayed (pad to IN1, IN2) CKIN_DEL IN_DEL IND_DEL -- -- -- 1.41 2.16 9.05 -- -- -- 1.26 1.87 7.83 -- -- -- 0.64 1.28 6.64 -- -- -- 0.41 0.90 7.27 ns ns ns PIO Transparent Latch Delays: Pad to In (pad to IN1, IN2) Pad to In Delayed (pad to IN1, IN2) LATCH_DEL LATCHD_DEL -- -- 4.11 10.58 -- -- 3.25 9.05 -- -- 2.52 7.67 -- -- 1.82 7.65 ns ns -- -- 4.82 11.03 -- -- 3.63 9.18 -- -- 3.23 9.68 -- -- ns ns -- -- -- -- 1.42 7.36 1.64 1.45 -- -- -- -- 0.71 5.91 1.29 1.14 -- -- -- -- 0.50 7.06 1.00 0.89 -- -- -- -- ns ns ns ns Input Delays (TJ = 85 C, VDD = min) Input Rise Time Input Fall Time Input Latch/FF Setup Timing: INREGE_SET 5.93 Pad to ExpressCLK (fast-capture latch/FF) INREGED_SET 12.86 Pad Delayed to ExpressCLK (fast-capture latch/FF) INREG_SET 1.62 Pad to Clock (input latch/FF) INREGD_SET 8.57 Pad Delayed to Clock (input latch/FF) INCE_SET 2.03 Clock Enable to Clock (CE to CLK) INLSR_SET 1.79 Local Set/Reset (sync) to Clock (LSR to CLK) Input FF/Latch Hold Timing: Pad from ExpressCLK (fast-capture latch/FF) Pad Delayed from ExpressCLK (fast-capture latch/FF) Pad from Clock (input latch/FF) Pad Delayed from Clock (input latch/FF) Clock Enable from Clock (CE from CLK) Local Set/Reset (sync) from Clock (LSR from CLK) Clock-to-in Delay (FF CLK to IN1, IN2) Clock-to-in Delay (latch CLK to IN1, IN2) Local S/R (async) to IN (LSR to IN1, IN2) Local S/R (async) to IN (LSR to IN1, IN2) LatchFF in Latch Mode Global S/R to In (GSRN to IN1, IN2) INREGE_HLD INREGED_HLD 0.00 0.00 -- -- 0.00 0.00 -- -- 0.00 0.00 -- -- 0.00 0.00 -- -- ns ns INREG_HLD INREGD_HLD INCE_HLD INLSR_HLD 0.00 0.00 0.00 0.00 -- -- -- -- 0.00 0.00 0.00 0.00 -- -- -- -- 0.00 0.00 0.00 0.00 -- -- -- -- 0.00 0.00 0.00 0.00 -- -- -- -- ns ns ns ns INREG_DEL INLTCH_DEL INLSR_DEL INLSRL_DEL -- -- -- -- 4.05 4.08 6.11 5.89 -- -- -- -- 3.14 3.19 4.76 4.66 -- -- -- -- 2.53 2.62 3.81 3.57 -- -- -- -- 2.05 2.14 3.17 2.98 ns ns ns ns INGSR_DEL -- 5.38 -- 4.22 -- 3.44 -- 2.88 ns Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns. 110 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 48. Programmable I/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter Symbol -4 -5 -6 -7 Unit Min Max Min Max Min Max Min Max OUTF_DEL OUTSL_DEL OUTSI_DEL -- -- -- 5.09 7.86 9.41 -- -- -- 4.21 6.49 7.98 -- -- -- 2.63 3.49 8.08 -- -- -- 2.17 2.91 7.32 ns ns ns TSF_DEL TSSL_DEL TSSI_DEL -- -- -- 4.93 7.70 9.25 -- -- -- 4.09 6.37 7.86 -- -- -- 2.33 3.00 7.95 -- -- -- 1.88 2.41 7.23 ns ns ns OUTLSRF_DEL OUTLSRSL_DEL OUTLSRSI_DEL -- -- -- 9.03 11.79 13.35 -- -- -- 7.25 9.53 11.02 -- -- -- 4.96 5.82 10.38 -- -- -- 3.94 4.67 9.10 ns ns ns OUTGSRF_DEL OUTGSRSL_DEL OUTGSRSI_DEL -- -- -- 8.30 11.06 12.62 -- -- -- 6.69 8.97 10.46 -- -- -- 4.39 5.07 10.02 -- -- -- 3.46 3.99 8.81 ns ns ns OUTE_SET OUT_SET OUTCE_SET OUTLSR_SET 0.00 0.00 0.91 0.41 -- -- -- -- 0.00 0.00 0.67 0.32 -- -- -- -- 0.00 0.00 0.56 0.26 -- -- -- -- 0.00 0.00 0.45 0.24 -- -- -- -- ns ns ns ns OUTE_HLD OUT_HLD OUTCE_HLD OUTLSR_HLD 0.73 0.73 0.00 0.00 -- -- -- -- 0.58 0.58 0.00 0.00 -- -- -- -- 0.36 0.36 0.00 0.00 -- -- -- -- 0.29 0.29 0.00 0.00 -- -- -- -- ns ns ns ns OUTREGF_DEL OUTREGSL_DEL OUTREGSI_DEL -- -- -- -- 6.71 9.47 11.03 0.20 -- -- -- -- 5.44 7.71 9.20 0.16 -- -- -- -- 3.56 4.42 8.98 0.10 -- -- -- -- 2.78 3.52 7.94 0.08 ns ns ns ns Output Delays (TJ = 85 C, VDD = min, CL = 50 pF) Output to Pad (OUT2, OUT1 direct to pad): Fast Slewlim Sinklim 3-state Enable/Disable Delay (TS to pad): Fast Slewlim Sinklim Local Set/Reset (async) to Pad (LSR to pad): Fast Slewlim Sinklim Global Set/Reset to Pad (GSRN to pad): Fast Slewlim Sinklim Output FF Setup Timing: Out to ExpressCLK (OUT[2:1] to ECLK) Out to Clock (OUT[2:1] to CLK) Clock Enable to Clock (CE to CLK) Local Set/Reset (sync) to Clock (LSR to CLK) Output FF Hold Timing: Out from ExpressCLK (OUT[2:1] from ECLK) Out from Clock (OUT[2:1] from CLK) Clock Enable from Clock (CE from CLK) Local Set/Reset (sync) from Clock (LSR from CLK) Clock to Pad Delay (ECLK, SCLK to pad): Fast Slewlim Sinklim Additional Delay If Using Open Drain OD_DEL Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns. Lattice Semiconductor 111 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 48. Programmable I/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter PIO Logic Block Delays Out to Pad (OUT[2:1] via logic to pad): Fast Slewlim Sinklim Outreg to Pad (OUTREG via logic to pad): Fast Slewlim Sinklim Clock to Pad (ECLK, CLK via logic to pad): Fast Slewlim Sinklim 3-State FF Delays 3-state Enable/Disable Delay (TS direct to pad): Fast Slewlim Sinklim Local Set/Reset (async) to Pad (LSR to pad): Fast Slewlim Sinklim Global Set/Reset to Pad (GSRN to pad): Fast Slewlim Sinklim 3-State FF Setup Timing: TS to ExpressCLK (TS to ECLK) TS to Clock (TS to CLK) Local Set/Reset (sync) to Clock (LSR to CLK) 3-State FF Hold Timing: TS from ExpressCLK (TS from ECLK) TS from Clock (TS from CLK) Local Set/Reset (sync) from Clock (LSR from CLK) Clock to Pad Delay (ECLK, SCLK to pad): Fast Slewlim Sinklim Symbol -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max OUTLF_DEL OUTLSL_DEL OUTLSI_DEL -- -- -- 5.09 7.86 9.41 -- -- -- 4.21 6.49 7.98 -- -- -- 2.63 3.49 8.08 -- -- -- 2.17 2.91 7.32 ns ns ns OUTRF_DEL OUTRSL_DEL OUTRSI_DEL -- -- -- 6.71 9.47 11.03 -- -- -- 5.44 7.71 9.20 -- -- -- 3.56 4.42 8.98 -- -- -- 2.78 3.52 7.94 ns ns ns OUTCF_DEL OUTCSL_DEL OUTCSI_DEL -- -- -- 6.97 9.74 11.29 -- -- -- 5.68 7.96 9.45 -- -- -- 3.71 4.57 9.13 -- -- -- 2.91 3.64 8.07 ns ns ns TSF_DEL TSSL_DEL TSSI_DEL -- -- -- 4.93 7.70 9.25 -- -- -- 4.09 6.37 7.86 -- -- -- 2.33 3.00 7.95 -- -- -- 1.88 2.41 7.23 ns ns ns TSLSRF_DEL TSLSRSL_DEL TSLSRSI_DEL -- -- -- 8.25 11.01 12.57 -- -- -- 6.65 8.92 10.41 -- -- -- 4.24 4.92 9.87 -- -- -- 3.39 3.92 8.74 ns ns ns TSGSRF_DEL TSGSRSL_DEL TSGSRSI_DEL -- -- -- 7.52 10.28 11.84 -- -- -- 6.09 8.36 9.85 -- -- -- 3.88 4.55 9.51 -- -- -- 3.11 3.64 8.45 ns ns ns TSE_SET TS_SET TSLSR_SET 0.00 0.00 0.28 -- -- -- 0.00 0.00 0.21 -- -- -- 0.00 0.00 0.17 -- -- -- 0.00 0.00 0.18 -- -- -- ns ns ns TSE_HLD TS_HLD TSLSR_HLD 0.85 0.85 0.00 -- -- -- 0.68 0.68 0.00 -- -- -- 0.44 0.44 0.00 -- -- -- 0.34 0.34 0.00 -- -- -- ns ns ns TSREGF_DEL TSREGSL_DEL TSREGSI_DEL -- -- -- 5.94 8.70 10.26 -- -- -- 4.82 7.10 8.59 -- -- -- 2.84 3.52 8.47 -- -- -- 2.23 2.76 7.58 ns ns ns Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns. 112 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Special Function Blocks Timing Table 49. Microprocessor Interface (MPI) Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol -4 -5 -6 -7 Unit Min Max Min Max Min Max Min Max PowerPC Interface Timing (TJ = 85 C, VDD = min) Transfer Acknowledge Delay (CLK to TA) Burst Inhibit Delay (CLK to BIN) Transfer Acknowledge Delay to High Impedance Burst Inhibit Delay to High Impedance Write Data Setup Time (data to TS) Write Data Hold Time (data from CLK while MPI_ACK low) Address Setup Time (addr to TS) Address Hold Time (addr from CLK while MPI_ACK low) Read/Write Setup Time (R/W to TS) Read/Write Hold Time (R/W from CLK while MPI_ACK low) Chip Select Setup Time (CS0, CS1 to TS) Chip Select Hold Time (CS0, CS1 from CLK) User Address Delay (pad to UA[3:0]) User Read/Write Delay (pad to URDWR_DEL) TA_DEL BI_DEL TA_DELZ BI_DELZ WD_SET WD_HLD A_SET A_HLD RW_SET RW_HLD CS_SET CS_HLD UA_DEL URDWR_DEL -- 11.6 -- -- 11.6 -- (2) -- -- (2) -- -- 0.0 -- 0.0 0.0 -- 0.0 0.0 -- 0.0 0.0 -- 0.0 0.0 -- 0.0 0.0 -- 0.0 0.3 -- .25 0.0 -- 0.0 -- 3.3 -- -- 7.0 -- 9.3 9.3 2.0 -- 0.0 -- -- 11.6 (2) -- (3) -- (4) -- 2.0 -- 2.0 -- 2.0 -- 2.0 -- (3) -- (4) -- 2.0 -- 0.0 -- -- 6.6 -- 7.0 1.8 0.0 -- -- -- -- 9.3 (3) -- -- -- -- -- -- -- -- -- -- 4.3 5.4 (2) (2) -- -- -- -- -- -- -- -- 2.6 5.4 -- -- -- -- 0.0 0.0 0.0 0.0 0.0 0.0 .14 0.0 -- -- 8.0 8.0 1.6 0.0 -- -- -- -- 8.0 (3) -- -- -- -- -- -- -- -- -- -- 4.1 4.2 (2) (2) -- -- -- -- -- -- -- -- 2.3 4.2 -- -- -- -- 0.0 0.0 0.0 0.0 0.0 0.0 .12 0.0 -- -- 6.8 6.8 1.4 0.0 -- -- -- -- 6.8 (2) (2) -- -- -- -- -- -- -- -- 1.9 3.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns i960 Interface Timing (TJ = 85 C, VDD = min) Addr/Data Select to ALE (ADS, to ALE low) Addr/Data Select to ALE (ADS, from ALE low) Ready/Receive Delay (CLK to RDYRCV) Ready/Receive Delay to High Impedance Write Data Setup Time Write Data Hold Time Address Setup Time (addr to ALE low) Address Hold Time (addr from ALE low) Byte Enable Setup Time (BE0, BE1 to ALE low) Byte Enable Hold Time (BE0, BE1 from ALE low) Read/Write Setup Time Read/Write Hold Time Chip Select Setup Time (CS0, CS1 to CLK)(1) Chip Select Hold Time (CS0, CS1 from CLK)(1) User Address Delay (CLK low to UA[3:0]) User Read/Write Delay (pad to URDWR_DEL) ADSN_SET ADSN_HLD RDYRCV_DEL RDYRCV_DELZ WD_SET WD_HLD A_SET A_HLD BE_SET BE_HLD RW_SET RW_HLD CS_SET CS_HLD UA_DEL URDWR_DEL (4) 1.8 1.8 1.8 1.8 (3) (4) 1.8 0.0 -- -- (2) (4) 0.50 0.51 0.50 0.51 (3) (4) 0.45 0.0 -- -- (2) (2) (3) -- (4) -- -- 0.42 -- 0.44 -- 0.42 -- 0.44 (3) -- (4) -- -- 0.38 0.0 -- -- 3.5 -- 3.6 1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go inactive before the end of the read/write cycle. 2. 0.5 MPI_CLK. 3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized. 4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV. Notes: Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA. PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK). Lattice Semiconductor 113 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 49. Microprocessor Interface (MPI) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter Symbol -4 -5 -6 -7 Unit Min Max Min Max Min Max Min Max (5) User Logic Delay User Start Delay (MPI_CLK falling to USTART)(6) User Start Clear Delay (MPI_CLK to USTART) User End Delay (USTART low to UEND low)(7) Synchronous User Timing: User End Setup (UEND to MPI_CLK) User End Hold (UEND to MPI_CLK) Data Setup for Read (D[7:0] to MPI_CLK)(9) Data Hold for Read (D[7:0] from MPI_CLK)(9) Asynchronous User Timing: User End to Read Data Delay (UEND to D[7:0])(10) Data Hold from User Start (low)(9) Interrupt Request Pulse Width(8) User Logic Delay USTART_DEL USTARTCLR_DEL UEND_DEL -- -- -- -- -- 3.6 7.5 -- -- -- -- -- -- 3.4 7.3 -- -- -- -- -- -- 3.3 7.1 -- -- -- -- -- -- 2.8 6.0 -- ns ns ns ns UEND_SET UEND_HLD RDS_SET RDS_HLD 0.00 1.0 -- -- -- -- -- -- 0.00 0.95 -- -- -- -- -- -- 0.00 0.88 -- -- -- -- -- -- 0.00 0.75 -- -- -- -- -- -- ns ns ns ns RDA_DEL -- -- -- -- -- -- -- -- ns RDA_HLD TUIRQ_PW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns 1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go inactive before the end of the read/write cycle. 2. 0.5 MPI_CLK. 3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized. 4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV. 5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle. 6. USTART_DEL is based on the falling clock edge. 7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle. 8. The user must assert interrupt request low until a service routine is executed. 9. This should be at least one MPI_CLK cycle. 10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing. Notes: Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA. PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK). 114 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) UEND_SET CS_SET RDS_HLD CS_HLD RW_SET A_HLD RW_HLD RDS_SET A_SET SE L D E IS C C T O D N E TI VI N C U E ED S MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 RDA_DEL RDA_HLD D[7:0] MPI_STRB (TS) UA_DEL UA[3:0] URDWR_DEL URDWRN USTARTCLR_DEL USTART_DEL USTART USER LOGIC DELAY UEND UEND_DEL TA_DELZ TA_DEL TA_DEL BI_DEL BI_DEL MPI_ACK (TA) MPI_BI (BI) BI_DELZ 5-5832(F) Figure 67. MPI PowerPC User Space Read Timing CS_SET RW_SET WD_HLD UEND_SET CS_HLD RW_HLD A_SET A_HLD MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 WD_SET D[7:0] MPI_STRB (TS) UA_DEL UA[3:0] URDWR_DEL URDWRN USTARTCLR_DEL USTART_DEL USTART USER LOGIC DELAY UEND UEND_DEL TA_DELZ TA_DEL TA_DEL BI_DEL BI_DEL MPI_ACK (TA) MPI_BI (BI) BI_DELZ 5-5840(F) Figure 68. MPI PowerPC User Space Write Timing Lattice Semiconductor 115 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) UEND_SET CS_SET RDS_HLD CS_HLD RW_SET A_HLD RW_HLD RDS_SET A_SET SE L D E IS C C T O D N E TI VI N C U E ED S MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 RDA_DEL RDA_HLD D[7:0] MPI_STRB (TS) UA_DEL UA[3:0] URDWR_DEL URDWRN TA_DELZ TA_DEL TA_DEL BI_DEL BI_DEL MPI_ACK (TA) MPI_BI (BI) BI_DELZ 5-5832(F).c Figure 69. MPI PowerPC Internal Read Timing CS_SET WD_HLD RW_SET CS_HLD A_SET RW_HLD A_HLD MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 WD_SET D[7:0] MPI_STRB (TS) UA_DEL UA[3:0] URDWR_DEL URDWRN TA_DELZ TA_DEL TA_DEL BI_DEL BI_DEL MPI_ACK (TA) MPI_BI (BI) BI_DELZ 5-5840(F).e Figure 70. MPI PowerPC Internal Write Timing 116 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) CS_SET A_HLD A_SET ADSN_HLD RDS_HLD ADSN_SET RDS_SET UEND_SET CS_HLD SE L D E IS C C T O D N E TI VI N C U E ED S RW_SET RW_HLD MPI_CLK RDA_HLD RDA_DEL ADDR D[7:0] DATA MPI_RW (W/R) CS0, CS1 BE0, BE1 BE_SET BE_HLD MPI_ALE (ALE) MPI_STRB (ADS) UA_DEL UA[3:0] URDWR_DEL URDWRN USTARTCLR_DEL USTART_DEL USTART UEND_DEL USER LOGIC DELAY UEND RDYRCV_DELZ RDYRCV_DEL RDYRCV_DEL MPI_ACK (RDYRCV) 5-5831(F).b Figure 71. MPI i960 User Space Read Timing CS_SET A_HLD WD_HLD A_SET ADSN_HLD RW_HLD ADSN_SET WD_SET RW_SET UEND_SET CS_HLD MPI_CLK D[7:0] ADDR DATA MPI_RW (W/R) CS0, CS1 MPI_ALE (ALE) MPI_STRB (ADS) UA_DEL UA[3:0] URDWR_DEL URDWRN USTART_DEL USTARTCLR_DEL USTART USER LOGIC DELAY UEND_DEL UEND RDYRCV_DEL RDYRCV_DEL MPI_ACK (RDYRCV) RDYRCV_DELZ 5-5830(F).b Figure 72. MPI i960 User Space Write Timing Lattice Semiconductor 117 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) CS_SET A_HLD A_SET ADSN_HLD RDS_HLD ADSN_SET RDS_SET RW_HLD CS_HLD SE L D E IS C C T O D N E TI VI N C U E ED S RW_SET MPI_CLK RDA_HLD RDA_DEL ADDR D[7:0] DATA MPI_RW (W/R) CS0, CS1 BE0, BE1 BE_SET BE_HLD MPI_ALE (ALE) MPI_STRB (ADS) UA_DEL UA[3:0] URDWR_DEL URDWRN RDYRCV_DELZ RDYRCV_DEL RDYRCV_DEL MPI_ACK (RDYRCV) 5-5831(F).c Figure 73. MPI i960 Internal Read Timing CS_SET A_HLD WD_HLD ADSN_HLD A_SET RW_HLD ADSN_SET WD_SET RW_SET CS_HLD MPI_CLK D[7:0] ADDR DATA MPI_RW (W/R) CS0, CS1 MPI_ALE (ALE) MPI_STRB (ADS) UA_DEL UA[3:0] URDWR_DEL URDWRN RDYRCV_DEL RDYRCV_DEL MPI_ACK (RDYRCV) RDYRCV_DELZ 5-5830(F).c Figure 74. MPI i960 Internal Write Timing 118 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 50. Programmable Clock Manager (PCM) Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Parameter Symbol Input Clock Frequency: OR3Cxx OR3Txxx Output Clock Frequency: OR3Cxx OR3Txxx Input Clock Duty Cycle Output Clock Duty Cycle Input Frequency Tolerance* PCM Acquisition Time (CLK In to LOCK) PCM Off Delay (config. Done-L, WE to PCM power off) PCM Delay in DLL Mode (propagation delay) PCM Delay in PLL Mode (propagation delay) PCM Clock In to PCM Clock Out (CLK In to ECLK) PCM Clock In to PCM Clock Out (CLK In to SCLK) Routed Clock-in Delay (routing to PCM phase detect, using DIV0) FPCMI Parameter -5 -6 -7 Unit Min Max Min Max Min Max Min Max 5 -- 133 -- 5 5 133 133 -- 5 -- 133 -- 5 -- 133 MHz MHz FPCMO PCMI_DUTY PCMO_DUTY FTOL PCM_ACQ 5 135 5 135 -- -- -- -- MHz -- -- 5 100 5 100 5 100 MHz 30.00 70.00 30.00 70.00 30.00 70.00 30.00 70.00 % 3.13 96.90 3.13 96.90 3.13 96.90 3.13 96.90 % -- 26400 -- 26400 -- 26400 -- 26400 ppm 36 100 36 100 36 100 36 100 s PCMOFF_DEL -- 100.0 -- 100.0 -- 100.0 -- 100.0 ns PCMDLL-DEL -- 1.95 -- 1.82 -- 1.63 -- 1.50 ns PCMPLL_DEL -- 0.00 -- 0.00 -- 0.00 -- 0.00 ns PCMBYE_DEL -- 0.47 -- 0.36 -- 0.26 -- 0.24 ns PCMBYS_DEL -- 0.47 -- 0.36 -- 0.26 -- 0.24 ns RTCKD_DEL -- 1.30 -- 1.10 -- 0.90 -- TBD ns -- 2.70 -- 2.20 -- 1.90 -- TBD ns System Clock-out Delay (PCM oscilla- PCMSCK_DEL tor to SCLK output at PCM) Output Jitter -4 Symbol fOUT (MHz) PLL Mode DLL Mode Unit OUTJIT 5--20 21--30 31--40 41--50 51--60 61--70 71--80 81--90 91--100 250 210 180 155 130 110 95 80 70 200 170 145 123 105 90 75 65 55 ps ps ps ps ps ps ps ps ps * Input frequency tolerance is the allowed input clock frequency change in parts per million. See Table 29 and Table 30 for acquisition times for individual frequencies. PLL mode, divider reg = 1111111 (input freq. = output freq.). Lattice Semiconductor 119 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 51. Boundary-Scan Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol TS Min Max Unit SE L D E IS C C T O D N E TI VI N C U E ED S Parameter TDI/TMS to TCK Setup Time TDI/TMS Hold Time from TCK TCK Low Time TCK High Time TCK to TDO Delay TCK Frequency 25.0 0.0 50.0 50.0 -- -- TH TCL TCH TD TTCK -- -- -- -- 20.0 10.0 ns ns ns ns ns MHz TCK TS TH TMS TDI TD TDO 5-6764(F) Figure 75. Boundary-Scan Timing Diagram 120 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Clock Timing Table 52. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Device (TJ = 85 C, VDD = min) Clock Control Timing Delay Through CLKCNTRL (input from corner) Delay Through CLKCNTRL (input from internal clock controller PAD) Clock Shutoff Timing: Setup from Middle ECLK (shut off to CLK) Hold from Middle ECLK (shut off from CLK) Setup from Corner ECLK (shut off to CLK) Hold from Corner ECLK (shut off from CLK) ECLK Delay (middle pad): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 ECLK Delay (corner pad): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 FCLK Delay (middle pad): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 FCLK Delay (corner pad): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 Speed Symbol -4 -5 -6 -7 Unit ECLKC_DEL Min 0.31 Max -- Min 0.31 Max -- Min 0.31 Max -- Min 0.31 Max -- ns ECLKM_DEL 1.54 -- 1.17 -- 1.00 -- 0.92 -- ns OFFM_SET OFFM_HLD OFFC_SET OFFC_HLD 0.77 0.00 0.77 0.00 -- -- -- -- 0.51 0.00 0.51 0.00 -- -- -- -- 0.44 0.00 0.44 0.00 -- -- -- -- 0.41 0.00 0.41 0.00 -- -- -- -- ns ns ns ns -- -- -- -- -- -- -- 3.50 3.67 -- -- -- -- -- -- 2.56 2.62 2.74 2.86 3.06 -- -- -- -- -- 2.05 2.08 2.13 2.19 2.29 -- -- -- -- -- 1.78 1.80 1.85 1.90 1.98 ns ns ns ns ns -- -- -- -- -- -- -- 5.47 5.64 -- -- -- -- -- -- 4.48 4.53 4.64 4.77 4.96 -- -- -- -- -- 3.85 3.97 4.22 4.47 4.85 -- -- -- -- -- 3.36 3.47 3.69 3.92 4.27 ns ns ns ns ns -- -- -- -- -- -- -- 8.24 8.87 -- -- -- -- -- -- 5.91 6.12 6.59 7.11 7.98 -- -- -- -- -- 4.59 4.66 4.83 5.01 5.33 -- -- -- -- -- 3.81 3.89 4.06 4.26 4.59 ns ns ns ns ns -- -- -- -- -- -- -- 10.34 11.01 -- -- -- -- -- -- 7.88 8.11 8.60 9.15 10.07 -- -- -- -- -- 6.41 6.58 6.95 7.34 7.96 -- -- -- -- -- 5.40 5.58 5.94 6.33 6.94 ns ns ns ns ns ECLKM_DEL ECLKC_DEL FCLKM_DEL FCLKC_DEL Notes: The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIC clock input. The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used. Lattice Semiconductor 121 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 53. General-Purpose Clock Timing Characteristics (Internally Generated Clock) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Symbol OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 CLK_DEL CLK_DEL CLK_DEL CLK_DEL CLK_DEL SE L D E IS C C T O D N E TI VI N C U E ED S Device (TJ = 85 C, VDD = min) -4 Min -- -- -- -- -- -5 Max -- -- 5.34 5.49 -- Min -- -- -- -- -- -6 Max 4.22 4.29 4.41 4.52 4.80 Min -- -- -- -- -- Unit -7 Max 3.46 3.48 3.53 3.57 3.71 Min -- -- -- -- -- Max 2.84 2.87 2.93 2.98 3.13 ns ns ns ns ns Notes: This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the results reported by ispLEVER. This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not used. See pin-to-pin timing in Table 56 for clock delays of clocks input on general I/O pins. 122 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C; CL = 50 pF. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C;CL = 50 pF. SE L D E IS C C T O D N E TI VI N C U E ED S Speed Description (TJ = 85 C, VDD = min) Device -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max ECLK Middle Input PinOUTPUT Pin (Fast) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 9.93 10.10 -- -- -- -- -- -- 7.78 7.84 7.96 8.08 8.28 -- -- -- -- -- 5.40 5.43 5.48 5.54 5.64 -- -- -- -- -- 4.38 4.40 4.44 4.49 4.58 ns ns ns ns ns ECLK Middle Input PinOUTPUT Pin (Slewlim) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 12.37 12.54 -- -- -- -- -- -- 9.77 9.83 9.95 10.07 10.27 -- -- -- -- -- 6.07 6.10 6.15 6.21 6.31 -- -- -- -- -- 4.91 4.93 4.97 5.02 5.11 ns ns ns ns ns ECLK Middle Input PinOUTPUT Pin (Sinklim) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 13.73 13.90 -- -- -- -- -- -- 11.12 11.18 11.30 11.42 11.62 -- -- -- -- -- 10.92 10.95 11.00 11.06 11.16 -- -- -- -- -- 9.65 9.67 9.71 9.76 9.85 ns ns ns ns ns Additional Delay if ECLK Corner Pin Used OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 1.97 1.97 -- -- -- -- -- -- 1.91 1.91 1.91 1.91 1.90 -- -- -- -- -- 1.80 1.90 2.09 2.28 2.57 -- -- -- -- -- 1.58 1.67 1.84 2.02 2.29 ns ns ns ns ns Notes: Timing is without the use of the programmable clock manager (PCM). This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input buffer delay, the clock routing to the PIO CLK input, the clockQ of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device, and that a PIO FF be used. PIO FF D Q OUTPUT (50 pF LOAD) CLKCNTRL ECLK ECLK 5-4846(F).a Figure 76. ExpressCLK to Output Delay Lattice Semiconductor 123 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 55. OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin) SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C; CL = 50 pF. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C; CL = 50 pF. Speed Description (TJ = 85 C, VDD = min) Device -4 Min -5 Max Min -6 Max Min Unit -7 Max Min Max Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs) ECLK Middle Input Pin OUTPUT Pin (Fast) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 14.68 15.30 -- -- -- -- -- -- 11.13 11.35 11.81 12.33 13.20 -- -- -- -- -- 7.94 8.01 8.18 8.36 8.68 -- -- -- -- -- 6.40 6.48 6.66 6.85 7.19 ns ns ns ns ns ECLK Middle Input Pin OUTPUT Pin (Slewlim) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 17.11 17.74 -- -- -- -- -- -- 13.12 13.33 13.80 14.32 15.19 -- -- -- -- -- 8.61 8.68 8.85 9.04 9.35 -- -- -- -- -- 6.93 7.01 7.19 7.38 7.72 ns ns ns ns ns ECLK Middle Input Pin OUTPUT Pin (Sinklim) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 18.47 19.10 -- -- -- -- -- -- 14.47 14.68 15.15 15.67 16.54 -- -- -- -- -- 13.46 13.53 13.70 13.88 14.20 -- -- -- -- -- 11.67 11.75 11.93 12.12 12.46 ns ns ns ns ns Additional Delay if ECLK Corner Pin Used OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 2.10 2.14 -- -- -- -- -- -- 1.97 1.99 2.01 2.04 2.09 -- -- -- -- -- 1.82 1.92 2.12 2.33 2.63 -- -- -- -- -- 1.60 1.69 1.88 2.07 2.39 ns ns ns ns ns Notes: Timing is without the use of the programmable clock manager (PCM). This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the PIO CLK input, the clockQ of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used. PIO FF D Q OUTPUT (50 pF LOAD) CLKCNTRL ECLK FCLK 5-4846(F).b Figure 77. Fast Clock to Output Delay 124 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 56. OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin) SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C; CL = 50 pF. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C; CL = 50 pF. Speed Description (TJ = 85 C, VDD = min) Device -4 Min -5 Max Min -6 Max Min -7 Max Min Unit Max Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs) Clock Input Pin (mid-PIC) OUTPUT Pin (Fast) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 14.91 15.71 -- -- -- -- -- -- 11.35 11.63 12.17 12.80 13.69 -- -- -- -- -- 7.74 7.93 8.28 8.66 9.24 -- -- -- -- -- 6.10 6.27 6.59 6.95 7.49 ns ns ns ns ns Clock Input Pin (mid-PIC) OUTPUT Pin (Slewlim) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 17.34 18.14 -- -- -- -- -- -- 13.34 13.62 14.16 14.79 15.68 -- -- -- -- -- 8.42 8.60 8.95 9.34 9.91 -- -- -- -- -- 6.63 6.80 7.12 7.48 8.02 ns ns ns ns ns Clock Input Pin (mid-PIC) OUTPUT Pin (Sinklim) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 18.70 19.51 -- -- -- -- -- -- 14.69 14.97 15.51 16.14 17.03 -- -- -- -- -- 13.26 13.45 13.80 14.18 14.76 -- -- -- -- -- 11.37 11.54 11.86 12.22 12.76 ns ns ns ns ns Additional Delay if Non-mid-PIC Used as Clock Pin OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 0.41 0.63 -- -- -- -- -- -- 0.16 0.20 0.36 0.55 1.11 -- -- -- -- -- 0.18 0.21 0.37 0.57 1.05 -- -- -- -- -- 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns 0.17 0.20 0.35 0.55 1.02 ns ns ns ns ns Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs) Additional Delay if Output Not on Same Side as Input Clock Pin OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- -- -- -- -- -- 0.41 0.63 -- -- -- -- -- -- 0.16 0.20 0.36 0.55 1.11 -- -- -- -- -- 0.18 0.21 0.37 0.57 1.05 -- -- -- -- -- Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the PIO CLK input, the clockQ of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be used. For clock pins located at any other PIO, see the results reported by ispLEVER. PIO FF D Q OUTPUT (50 pF LOAD) SCLK 5-4846(F) Figure 78. System Clock to Output Delay Lattice Semiconductor 125 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed SE L D E IS C C T O D N E TI VI N C U E ED S Description (TJ = 85 C, VDD = min) Device -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max Input to ECLK Setup Time (middle ECLK pin) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 1.36 1.25 -- -- -- -- -- -- 1.34 1.30 1.22 1.14 1.03 -- -- -- -- -- 0.88 0.86 0.83 0.80 0.76 -- -- -- -- -- 0.83 0.82 0.80 0.77 0.74 -- -- -- -- -- ns ns ns ns ns Input to ECLK Setup Time (middle ECLK pin, delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 6.91 6.79 -- -- -- -- -- -- 6.30 6.27 6.19 6.11 6.00 -- -- -- -- -- 5.32 5.30 5.27 5.24 5.20 -- -- -- -- -- 5.98 5.97 5.95 5.93 5.90 -- -- -- -- -- ns ns ns ns ns Input to ECLK Setup Time (corner ECLK pin) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Input to ECLK Setup Time (corner ECLK pin, delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 4.94 4.82 -- -- -- -- -- -- 4.39 4.35 4.28 4.21 4.10 -- -- -- -- -- 3.51 3.40 3.18 2.98 2.63 -- -- -- -- -- 4.41 4.31 4.11 3.91 3.61 -- -- -- -- -- ns ns ns ns ns Input to ECLK Hold Time (middle ECLK pin) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Input to ECLK Hold Time (middle ECLK pin, delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Note: The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER. The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input. 126 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed SE L D E IS C C T O D N E TI VI N C U E ED S Description (TJ = 85 C, VDD = min) Device -4 -5 -6 -7 Unit Min Max Min Max Min Max Min Max Input to ECLK Hold Time (corner ECLK pin) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.80 0.00 0.00 -- -- -- -- -- 0.00 0.00 1.10 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Input to ECLK Hold Time (corner ECLK pin, delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER. The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input. PIO ECLK LATCH INPUT D Q CLKCNTRL CLK ECLK 5-4847(F).b Figure 79. Input to ExpressCLK Setup/Hold Time Lattice Semiconductor 127 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed SE L D E IS C C T O D N E TI VI N C U E ED S Description (TJ = 85 C, VDD = min) Device -4 Min -5 Max Min -6 Max Min Unit -7 Max Min Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs) Input to FCLK Setup Time (middle 0.00 -- 0.00 -- 0.00 -- -- OR3T20 ECLK pin) 0.00 -- 0.00 -- 0.00 -- -- OR3T30 0.00 -- 0.00 -- 0.00 -- 0.00 OR3T55 0.00 -- 0.00 -- 0.00 -- 0.00 OR3C/T80 0.00 -- 0.00 -- 0.00 -- -- OR3T125 Input to FCLK Setup Time (middle 2.20 -- 0.58 -- 0.80 -- -- OR3T20 ECLK pin, delayed data input) 2.17 -- 0.55 -- 0.74 -- -- OR3T30 2.11 -- 0.51 -- 0.62 -- 0.29 OR3T55 2.06 -- 0.46 -- 0.50 -- 0.14 OR3C/T80 1.90 -- 0.33 -- 0.22 -- -- OR3T125 Input to FCLK Setup Time (corner 0.00 -- 0.00 -- 0.00 -- -- OR3T20 ECLK pin) 0.00 -- 0.00 -- 0.00 -- -- OR3T30 0.00 -- 0.00 -- 0.00 -- 0.00 OR3T55 0.00 -- 0.00 -- 0.00 -- 0.00 OR3C/T80 0.00 -- 0.00 -- 0.00 -- -- OR3T125 Input to FCLK Setup Time (corner -- 0.00 0.00 -- -- -- 0.00 OR3T20 ECLK pin, delayed data input) -- 0.00 0.00 -- -- -- 0.00 OR3T30 0.00 0.00 -- -- 0.00 0.00 OR3T55 -- 0.00 0.00 -- -- 0.00 0.00 OR3C/T80 -- 0.00 0.00 -- -- -- 0.00 OR3T125 -- Input to FCLK Hold Time (middle 3.27 -- 3.72 -- 4.29 -- -- OR3T20 ECLK pin) 3.35 -- 3.80 -- 4.50 -- -- OR3T30 3.52 -- 3.96 -- 4.97 -- 6.33 OR3T55 3.72 -- 4.15 -- 5.49 -- 6.95 OR3C/T80 4.05 -- 4.47 -- 6.36 -- -- OR3T125 Max -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- ns ns ns ns ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER. The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used. 128 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed SE L D E IS C C T O D N E TI VI N C U E ED S Description (TJ = 85 C, VDD = min) Device -4 -5 -6 -7 Unit Min Max Min Max Min Max Min Max Input to FCLK Hold Time (middle ECLK pin, delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Input to FCLK Hold Time (corner ECLK pin) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 8.43 9.09 -- -- -- -- -- -- 6.26 6.49 6.98 7.53 8.45 -- -- -- -- -- 5.54 5.72 6.09 6.47 7.10 -- -- -- -- -- 4.88 5.04 5.40 5.79 6.40 -- -- -- -- -- ns ns ns ns ns Input to FCLK Hold Time (corner ECLK pin, delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER. The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used. PIO FF INPUT D Q CLKCNTRL ECLK FCLK 5-4847(F).a Figure 80. Input to Fast Clock Setup/Hold Time Lattice Semiconductor 129 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 59. OR3C/Txxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed SE L D E IS C C T O D N E TI VI N C U E ED S Description (TJ = 85 C, VDD = min) Device -4 -5 -6 Unit -7 Min Max Min Max Min Max Min Max Input to SCLK Setup Time OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Input to SCLK Setup Time (delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.99 0.79 -- -- -- -- -- -- 1.33 1.22 1.09 0.93 0.78 -- -- -- -- -- 1.47 1.40 1.33 1.26 1.19 -- -- -- -- -- 3.09 3.03 2.97 2.91 2.86 -- -- -- -- -- ns ns ns ns ns Input to SCLK Hold Time OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 6.82 7.62 -- -- -- -- -- -- 4.74 5.01 5.56 6.19 7.07 -- -- -- -- -- 3.64 3.83 4.18 4.56 5.14 -- -- -- -- -- 3.04 3.22 3.54 3.89 4.44 -- -- -- -- -- ns ns ns ns ns Input to SCLK Hold Time (delayed data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.00 0.00 -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 -- -- -- -- -- ns ns ns ns ns Additional Hold Time if Nonmid-PIC Used as SCLK Pin (no delay on data input) OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 -- -- 0.41 0.63 -- -- -- -- -- -- 0.16 0.20 0.36 0.55 1.11 -- -- -- -- -- 0.18 0.21 0.37 0.57 1.05 -- -- -- -- -- 0.17 0.20 0.35 0.55 1.02 -- -- -- -- -- ns ns ns ns ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ispLEVER. This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer delay and the clock routing to the PIO FF CLK input. The delay will be reduced if any of the clock branches are not used. The given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF is used. If the clock pin is located elsewhere, then the last parameter in the table must be added to the hold (no delay) timing. PIO FF INPUT D Q SCLK 5-4847(F) Figure 81. Input to System Clock Setup/Hold Time 130 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Configuration Timing Table 60. General Configuration Mode Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit All Configuration Modes M[3:0] Setup Time to INIT High TSMODE 0.00 -- ns M[3:0] Hold Time from INIT High THMODE 600.00 -- ns RESET Pulse Width Low to Start Reconfiguration TRW 50.00 -- ns PRGM Pulse Width Low to Start Reconfiguration TPGW 50.00 -- ns TPO TCCLK 15.70 60.00 480.00 52.40 200.00 1600.00 ms ns ns 11.50 92.10 15.10 121.00 23.20 185.00 33.70 270.00 52.30 418.00 38.40* 307.00* 50.40* 403.30* 77.40* 619.00* 113.00* 900.00* 175.00* 1395.00* ms ms ms ms ms ms ms ms ms ms 15.70 52.40 ms 27413 35445 53341 76317 116581 -- -- -- -- -- write cycles write cycles write cycles write cycles write cycles 32 36 43 51 62 -- -- -- -- -- write cycles write cycles write cycles write cycles write cycles 3.90 13.10 ms 40 15 -- -- ns ns 2.80 3.80 5.80 22.50 8.40 13.09 -- -- -- -- -- -- ms ms ms ms ms ms Master and Asynchronous Peripheral Modes Power-on Reset Delay CCLK Period (M3 = 0) (M3 = 1) Configuration Latency (autoincrement mode): OR3T20 (M3 = 0) (M3 = 1) OR3T30 (M3 = 0) (M3 = 1) OR3T55 (M3 = 0) (M3 = 1) OR3C/T80 (M3 = 0) (M3 = 1) OR3T125 (M3 = 0) (M3 = 1) TCL Microprocessor (MPI) Mode Power-on Reset Delay Configuration Latency (autoincrement mode): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 TPO TCL Partial Reconfiguration (explicit mode): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 TPR Slave Serial Mode Power-on Reset Delay CCLK Period OR3Cxx OR3Txxx Configuration Latency (autoincrement mode): OR3T20 OR3T30 OR3T55 OR3C80 OR3T80 OR3T125 TPO TCCLK TCL * Not applicable to asynchronous peripheral mode. Lattice Semiconductor 131 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 60. General Configuration Mode Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol Min Max Unit TPO TCCLK 3.90 13.10 ms 40.00 15.00 -- -- ns ns 0.36 0.47 0.72 2.81 1.05 1.64 -- -- -- -- -- -- ms ms ms ms ms ms 0.48 0.54 0.65 2.04 0.77 0.93 -- -- -- -- -- -- s/frame s/frame s/frame s/frame s/frame s/frame 1.00 1.00 -- -- s s 1.00 0.50 3.40 2.00 s s 4.80 1.00 16.20 3.60 s s 0.21 0.24 0.30 0.36 0.45 2.00 0.68 0.79 1.00 1.20 1.50 -- ms ms ms ms ms SE L D E IS C C T O D N E TI VI N C U E ED S Parameter Slave Parallel Mode Power-on Reset Delay CCLK Period: OR3Cxx OR3Txxx Configuration Latency (normal mode): OR3T20 OR3T30 OR3T55 OR3C80 OR3T80 OR3T125 Partial Reconfiguration (explicit mode): OR3T20 OR3T30 OR3T55 OR3C80 OR3T80 OR3T125 TCL TPR INIT Timing INIT High to CCLK Delay: TINIT_CCLK Slave Parallel Slave Serial Master Serial: (M3 = 1) (M3 = 0) Master Parallel: (M3 = 1) (M3 = 0) Initialization Latency (PRGM high to INIT high): OR3T20 OR3T30 OR3T55 OR3C/T80 OR3T125 INIT High to WR, Asynchronous Peripheral TIL TINIT_WR s Note: TPO is triggered when VDD reaches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx. 132 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) VDD SE L D E IS C C T O D N E TI VI N C U E ED S TPO + T IL PRGM TPGW TIL INIT TINIT_CLK TCCLK CCLK THMODE TSMODE M[3:0] TCL DONE 5-4531(F) Figure 82. General Configuration Mode Timing Diagram Lattice Semiconductor 133 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 61. Master Serial Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol Min Max Unit SE L D E IS C C T O D N E TI VI N C U E ED S Parameter DIN Setup Time* TS 60.00 -- ns DIN Hold Time TH 0.00 -- ns CCLK Frequency (M3 = 0) FC 5.00 16.67 MHz CCLK Frequency (M3 = 1) FC 0.63 2.08 MHz CCLK to DOUT Delay TD -- 5.00 ns * Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge. Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN. CCLK TS DIN TH BIT N TD DOUT BIT N 5-4532(F) Figure 83. Master Serial Configuration Mode Timing Diagram 134 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 62. Master Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol Min Max Unit SE L D E IS C C T O D N E TI VI N C U E ED S Parameter RCLK to Address Valid TAV -- 60.00 ns D[7:0] Setup Time to RCLK High TS 60.00 -- ns D[7:0] Hold Time to RCLK High TH 0.00 -- ns RCLK Low Time (M3 = 0) TCL 7.00 7.00 CCLK cycles RCLK High Time (M3 = 0) TCH 1.00 1.00 CCLK cycles RCLK Low Time (M3 = 1) TCL 7.00 7.00 CCLK cycles RCLK High Time (M3 = 1) TCH 1.00 1.00 CCLK cycles CCLK to DOUT TD -- 5.00 ns Notes: The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high. Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input on D[7:0]. A[17:0] TAV TCH TCL RCLK TS D[7:0] TH BYTE N + 1 BYTE N CCLK DOUT D0 D1 D2 D3 D4 D5 D6 D7 TD 5-6764(F) Figure 84. Master Parallel Configuration Mode Timing Diagram Lattice Semiconductor 135 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 63. Asynchronous Peripheral Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol Min Max Unit SE L D E IS C C T O D N E TI VI N C U E ED S Parameter WR, CS0, and CS1 Pulse Width D[7:0] Setup Time: 3Cxx 3Txxx TWR 50.00 -- ns 20.00 10.50 -- -- ns ns TS TH 0.00 -- ns TRDY -- 40.00 ns TB 1.00 8.00 CCLK Periods Earliest WR After RDY Goes High* TWR2 0.00 -- ns RD to D7 Enable/Disable TDEN -- 40.00 ns TD -- 5.00 ns D[7:0] Hold Time RDY Delay RDY Low CCLK to DOUT * This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin. Notes: Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0]. D[6:0] timing is the same as the write data portion of the D7 waveform because D[6:0] are not enabled by RD. CS0 CS1 TWR WR TS D7 TH TWR2 WRITE DATA TDEN TDEN RD RDY TB TRDY CCLK TD DOUT PREVIOUS BYTE D7 D0 D1 D2 D3 5-4533(F) Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram 136 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 64. Slave Serial Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol Min Max Unit SE L D E IS C C T O D N E TI VI N C U E ED S Parameter DIN Setup Time: 3Cxx 3Txxx TS DIN Hold Time TH CCLK High Time: 3Cxx 3Txxx TCH CCLK Low Time: 3Cxx 3Txxx TCL CCLK Frequency: 3Cxx 3Txxx FC CCLK to DOUT TD 20.00 10.50 -- -- ns ns 0.00 -- ns 20.00 7.00 -- -- ns ns 20.00 7.00 -- -- ns ns -- -- 25.00 66.00 MHz MHz -- 20.00 ns Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN. BIT N DIN TS TH CCLK TD DOUT TCL TCH BIT N 5-4535(F). Figure 86. Slave Serial Configuration Mode Timing Diagram Lattice Semiconductor 137 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 65. Slave Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Symbol Min Max Unit SE L D E IS C C T O D N E TI VI N C U E ED S Parameter CS0, CS1, WR Setup Time TS1 40.00 -- ns CS0, CS1, WR Hold Time TH1 20.00 -- ns D[7:0] Setup Time: 3Cxx 3Txxx TS2 20.00 7.00 -- -- ns ns D[7:0] Hold Time TH2 0.00 -- ns CCLK High Time: 3Cxx 3Txxx TCH 20.00 7.00 -- -- ns ns CCLK Low Time: 3Cxx 3Txxx TCL 20.00 7.00 -- -- ns ns CCLK Frequency: 3Cxx 3Txxx FC -- -- 25.00 66.00 MHz MHz Note: Daisy-chaining of FPGAs is not supported in this mode. CS0 CS1 WR TS1 TH1 TCH TCL CCLK TS2 TH2 D[7:0] 5-2848(F) Figure 87. Slave Parallel Configuration Mode Timing Diagram 138 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Microprocessor Interface (MPI) Configuration Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S For configuration timing using the MPI, consult Table 49. See Figures 67 through 74 for MPI timing diagrams. Lattice Semiconductor 139 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Readback Timing Table 66. Readback Timing Characteristics SE L D E IS C C T O D N E TI VI N C U E ED S OR3Cxx Commercial: VDD = 5.0 V 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit TS 50.00 -- ns TRBA 2 -- CCLK cycles CCLK Low Time TCL 40.00 -- ns CCLK High Time TCH 40.00 -- ns CCLK Frequency FC -- 12.50 MHz CCLK to RD_DATA Delay TD -- 40.00 ns RD_CFG to CCLK Setup Time RD_CFG High Width to Abort Readback TRBA RD_CFG TCL TS CCLK TCH TD RD_DATA BIT 0 BIT 1 BIT 0 5-4536(F) Figure 88. Readback Timing Diagram 140 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Input/Output Buffer Measurement Conditions VCC GND 1 k SE L D E IS C C T O D N E TI VI N C U E ED S TO THE OUTPUT UNDER TEST 50 pF TO THE OUTPUT UNDER TEST 50 pF B. Load Used to Measure Rising/Falling Edges A. Load Used to Measure Propagation Delay Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH. 5-3234(F) Figure 89. ac Test Loads ts[i] PAD ac TEST LOADS (SHOWN ABOVE) OUT out[i] VDD out[i] VDD/2 VSS PAD 1.5 V OUT 0.0 V TPLL TPHH 5-3233.a(F) Figure 90. Output Buffer Delays PAD IN in[i] 3.0 V PAD IN 1.5 V 0.0 V VDD in[i] VDD/2 VSS TPLL TPHH 5-3235(F) Figure 91. Input Buffer Delays Lattice Semiconductor 141 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Output Buffer Characteristics OR3Cxx 70 50 IOL IOL OUTPUT CURRENT, IO (mA) OUTPUT CURRENT, IO (mA) SE L D E IS C C T O D N E TI VI N C U E ED S 60 50 40 30 IOH 20 40 30 20 IOH 10 10 0 0 0 1 2 3 4 0 5 1 2 3 4 5 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V) 5-4634(F) Figure 92. Sinklim (TJ = 25 C, V DD = 5.0 V) 5-4635(C) Figure 95. Sinklim (TJ = 125 C, V DD = 4.5 V) 150 250 IOL IOL 125 200 OUTPUT CURRENT, IO (mA) OUTPUT CURRENT, IO (mA) 225 175 150 125 100 IOH 75 50 100 75 50 IOH 25 25 0 0 0 1 2 3 4 0 5 1 2 3 4 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V) 5-4636(F) Figure 93. Slewlim (TJ = 25 C, V DD = 5.0 V) 5-4637(F) Figure 96. Slewlim (TJ = 125 C, V DD = 4.5 V) 250 175 IOL 150 200 OUTPUT CURRENT, IO (mA) OUTPUT CURRENT, IO (mA) 225 175 150 125 100 IOH 75 50 100 75 50 IOH 25 25 0 0 1 2 3 4 0 5 0 OUTPUT VOLTAGE, VO (V) 5-4638(F) Figure 94. Fast (TJ = 25 C, V DD = 5.0 V) 142 IOL 125 1 2 3 4 OUTPUT VOLTAGE, VO (V) 5-4639(F) Figure 97. Fast (TJ = 125 C, V DD = 4.5 V) Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Output Buffer Characteristics (continued) OR3Txxx 90 110 80 IOL IOL OUTPUT CURRENT, IO (mA) 90 70 SE L D E IS C C T O D N E TI VI N C U E ED S OUTPUT CURRENT, IO (mA) 100 80 70 60 IOH 50 40 30 20 60 50 40 IOH 30 20 10 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V) 5-6865(F) Figure 98. Sinklim (TJ = 25 C, V DD = 3.3 V) Figure 101. Sinklim (TJ = 125 C, V DD = 3.0 V) 120 140 IOL IOL 120 100 OUTPUT CURRENT, IO (mA) OUTPUT CURRENT, IO (mA) 5-6866(F) 100 80 60 IOH 40 80 60 IOH 40 20 20 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V) 5-6967(F) Figure 99. Slewlim (TJ = 25 C, V DD = 3.3 V) 5-6868(F) Figure 102. Slewlim (TJ = 125 C, V DD = 3.0 V) 140 120 IOL IOL 100 OUTPUT CURRENT, IO (mA) OUTPUT CURRENT, IO (mA) 120 100 80 60 IOH 40 80 60 IOH 40 20 20 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 OUTPUT VOLTAGE, VO (V) 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE, VO (V) 5-6867(F) Figure 100. Fast (TJ = 25 C, V DD = 3.3 V) Lattice Semiconductor 5-6868(F) Figure 103. Fast (TJ = 125 C, V DD = 3.0 V) 143 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Estimating Power Dissipation The power dissipated by an input buffer is estimated as: OR3Cxx PCMOS = 0.17 mW/MHz The ac power dissipation from an output or bidirectional is estimated by the following: POUT = (CL + 8.8 pF) x VDD2 x F Watts SE L D E IS C C T O D N E TI VI N C U E ED S The total operating power dissipated is estimated by summing the standby (IDDSB), internal, and external power dissipated. The internal and external power is the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The total operating power is as follows: PT = PPLC + PPIC The internal operating power is made up of two parts: clock generation and PFU output power. The PFU output power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two: PPFU = 0.136 mW/MHz For each PFU output that switches, 0.136 mW/MHz needs to be multiplied times the frequency (in MHz) that the output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and the power from the subset of those PFUs that are configured as synchronous memory. Therefore, the clock power can be calculated for the four parts using the following equations: OR3C80 Clock Power P = [0.224 mW/MHz + (0.288 mW/MHz/Branch) (# Branches) + (0.033 mW/MHz/PFU) (# PFUs) + (0.008 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3C80 clock power 21.06 mW/MHz. where the unit for CL is farads, and the unit for F is Hz. As an example of estimating power dissipation, suppose that a fully utilized OR3C80 has an average of six outputs for each of the 484 PFUs, that 10 clock brances are used so that the clock is driven to the entire PLC array, that 150 of the 484 PFUs have FFs clocked at 40 MHz, and that the PFUoutputs have an average activity factor of 20%. Twenty TTL-configured inputs, 20 CMOS-configured inputs, 32 outputs driving 30 pF loads, and 16 biderectional I/Os driving 50 pF loads are also generated from the 40 MHz clock with an average activity factor of 20%. All of the ouptut PIOs are registered, and 30 of the input PIOs are registered. The worst-case (VDD = 5.25 V) power dissipation is estimated as follows: PPFU = 484 x 6 (0.136 mW/MHz x 20 MHz x 20%) = 1579.78 mW PCLK = [40 X [0.224 mW/MHz + (0.288 mW/MHz/Branch) (10 Branches) + (0.033 mW/MHz/PFU) (150 PFUs) + (0.008 mW/MHz/PIO) (58 PIOs)] = 340.72 mW = 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz x 20%)] = 57.6 mW PTTL PCMOS = 20 x [0.17 mW x 20 MHz x 20%] = 13.6 mW POUT = 32 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%] = 136.89 mW PBID = 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%] = 103.72 mW Total = 2.23 W The power dissipated in a PIC is the sum of the power dissipated in the four PIOs in the PIC. This consists of power dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or input/ output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as POUT. This is because the output feeds back to the input. The power dissipated by a TTL input buffer is estimated as: PTTL = 2.2 mW + 0.17 mW/MHz 144 Lattice Semiconductor Data Sheet November 2006 Estimating Power Dissipation (continued) ORCA Series 3C and 3T FPGAs OR3T55 Clock Power P OR3Txxx For a quick estimate, the worst-case (typical circuit) OR3T55 clock power 6.58 mW/MHz. SE L D E IS C C T O D N E TI VI N C U E ED S The total operating power dissipated is estimated by summing the standby (IDDSB), internal, and external power dissipated. The internal and external power is the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The total operating power is as follows: = [0.88 mW/MHz + (0.102 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] PT = PPLC + PPIC The internal operating power is made up of two parts: clock generation and PFU output power. The PFU output power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two: PPFU = 0.068 mW/MHz For each PFU output that switches, 0.068 mW/MHz needs to be multiplied times the frequency (in MHz) that the output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and the power from the subset of those PFUs configured as synchronous memory. Therefore, the clock power can be calculated for the four parts using the following equations. OR3T20 Clock Power P = [0.38 mW/MHz + (0.045 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T20 clock power 2.92 mW/MHz. OR3T30 Clock Power P = [0.53 mW/MHz + (0.061 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] OR3T80 Clock Power P = [0.107 mW/MHz + (0.124 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T80 clock power 9.47 mW/MHz. OR3T125 Clock Power P = [0.167 mW/MHz + (0.193 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T125 clock power 15.44 mW/MHz. The power dissipated in a PIC is the sum of the power dissipated in the four PIOs in the PIC. This consists of power dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or input/ output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as POUT. This is because the output feeds back to the input. The power dissipated by an input buffer (VIH = VDD - 0.3 V or higher) is estimated as: PIN = 0.09 mW/MHz The ac power dissipation from an output or bidirectional is estimated by the following: POUT = (CL + 8.8 pF) x VDD2 x F Watts where the unit for CL is farads, and the unit for F is Hz. For a quick estimate, the worst-case (typical circuit) OR3T30 clock power 3.98 mW/MHz. Lattice Semiconductor 145 ORCA Series 3C and 3T FPGAs Data Sheet November 2006 Estimating Power Dissipation (continued) As an example of estimating power dissipation, suppose that a fully utilized OR3T80 has an average of six outputs for each of the 484 PFUs, that 12 clock branches are used so that the clock is driven to the entire PLC array, that 250 of the 484 PFUs have FFs clocked at 40 MHz, and that the PFU outputs have an average activity factor of 20%. SE L D E IS C C T O D N E TI VI N C U E ED S Eighty inputs, 40 of them used as 5 V tolerant inputs, 50 outputs driving 30 pF loads, and 30 bidirectional I/Os driving 50 pF loads are also generated from the 40 MHz clock with an average activity factor of 20%. All of the output PIOs are registered, and 30 of the input PIOs are registered. The worst-case (VDD = 3.6 V) power dissipation is estimated as follows: PPFU = 484 x 6 (0.068 mW/MHz x 20 MHz x 20%) = 789.9 mW PCLK = [0.107 mW/MHz + (0.09 mW/MHz - Branch) (12 Branches) + (0.015 mW/MHz - PFU) (250 PFUs) + (0.004 mW/MHz/PIO) (110 PIOs)] = 230.43 mW = 80 x [0.09 mW/MHz x 20 MHz x 20%] PIN = 28.8 mW POUT = 50 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%] = 100.57 mW = 30 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%] PBID = 91.45 mW TOTAL = 1.241 W 146 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin Information Pin Descriptions SE L D E IS C C T O D N E TI VI N C U E ED S This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after configuration. Table 67. Pin Descriptions Symbol I/O Description Dedicated Pins VDD -- Positive power supply. GND -- Ground supply. VDD5 -- 5 V tolerant select. VDD5 pin locations are shown for package compatibility with OR2TxxA devices. Connections to 5 V power sources are not used for 5 V tolerant I/Os in the OR3Txxx devices. RESET I During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. CCLK I In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or synchronous peripheral mode, CCLK is input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK is used internally and output for daisy-chain operation. DONE I As an input, a low level on DONE delays FPGA start-up after configuration (see Note). O As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor. PRGM I PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. This pin always has an active pull-up. RD_CFG I This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary scan, TDO is test data out. I During powerup and initialization, M0--M2 are used to select the configuration mode with their values latched on the rising edge of INIT; see Table 34 for the configuration modes. During configuration, a pull-up is enabled. Special-Purpose Pins M0, M1, M2 I/O After configuration, these pins are user-programmable I/O (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Lattice Semiconductor 147 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol I/O Description Special-Purpose Pins (continued) I During powerup and initialization, M3 is used to select the speed of the internal oscillator during configuration with their values latched on the rising edge of INIT. When M3 is low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During configuration, a pull-up is enabled. SE L D E IS C C T O D N E TI VI N C U E ED S M3 I/O After configuration, this pin is a user-programmable I/O pin (see Note). TDI, TCK, TMS I If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration. I/O After configuration, these pins are user-programmable I/O (see Note). RDY/RCLK/ MPI_ALE O O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. In i960 microprocessor mode, this pin acts as the address latch enable (ALE) input. I I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). HDC LDC O High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin (see Note). O Low During Configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin (see Note). INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an activelow input, INIT holds the FPGA in the wait-state before the start of configuration. I/O After configuration, this pin is a user-programmable I/O pin (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. 148 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol I/O Description Special-Purpose Pins (continued) I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. SE L D E IS C C T O D N E TI VI N C U E ED S CS0, CS1 I/O After configuration, these pins are user-programmable I/O pins (see Note). RD/ MPI_STRB WR I RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into a status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. I This pin is also used as the microprocessor interface (MPI) data transfer strobe. For PowerPC, it is the transfer start (TS). For i960, it is the address/data strobe (ADS). I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). I WR is used in the asynchronous peripheral configuration mode. When the FPGA is selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR and RD should not be used simultaneously. If they are, the write strobe overrides. I/O After configuration, this pin is a user-programmable I/O pin (see Note). A[17:0] O During master parallel configuration mode, A[17:0] address the configuration EPROM. In microprocessor interface (MPI) mode, many of the A[n] pins have alternate uses as described below. See the Special Function Blocks section for more MPI information. During configuration, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pullup enabled. I/O After configuration, the pins are user-programmable I/O pins (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Lattice Semiconductor 149 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol I/O Description Special-Purpose Pins (continued) O MPI active-low interrupt request output. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A10/MPI_BI O PowerPC mode MPI burst inhibit output. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A9/MPI_ACK In PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) output. For i960 MPI operation, it is the active-low ready/record (RDYRCV) output. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A8/MPI_RW In PowerPC mode MPI operation, this is the active-low write/active-high read control signals. For i960 operation, it is the active-high write/active-low read control signal. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A7/MPI_CLK This is the clock used for the synchronous MPI interface. For PowerPC, it is the CLKOUT signal. For i960, it is the system clock that is chosen for the i960 external bus interface. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A[4:0] For PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in i960 MPI mode. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A[1:0]/ For i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are used as address bits A[1:0] in i960 byte-wide operation. I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). SE L D E IS C C T O D N E TI VI N C U E ED S A11/MPI_IRQ MPI_BE[1:0] D[7:0] DIN DOUT O I I I I I During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the address/data pins for i960 microprocessor mode. I/O After configuration, the pins are user-programmable I/O pins (see Note). I During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. I/O After configuration, this pin is a user-programmable I/O pin (see Note). O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK. I/O After configuration, DOUT is a user-programmable I/O pin (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. 150 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin Information (continued) Package Compatibility Table 68 provides the number of user I/Os available for the ORCA Series 3 FPGAs for each available package. Each package has six dedicated configuration pins. SE L D E IS C C T O D N E TI VI N C U E ED S Tables 70--75 provide the package pin and pin function for the ORCA Series 3 FPGAs and packages. The bond pad name is identified in the PIC nomenclature used in the ispLEVER design editor. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column for the FPGA. The tables provide no information on unused pads. Table 68. ORCA I/Os Summary Device 144-Pin TQFP OR3T20 User I/Os* VDD/VSS Configuration Unused OR3T30 User I/Os* VDD/VSS Configuration Unused OR3T55 User I/Os* VDD/VSS Configuration Unused OR3C/T80 User I/Os* VDD/VSS Configuration Unused OR3T125 User I/Os* VDD/VSS Configuration Unused 208-Pin 240-Pin SQFP/SQPF2 SQFP/SQFP2 256-Pin PBGA 352-Pin PBGA 432-Pin EBGA 114 24 6 0 171 31 6 0 -- -- -- -- 192 26 6 32 -- -- -- -- -- -- -- -- -- -- -- -- 171 31 6 0 192 40 6 2 221 26 6 3 -- -- -- -- -- -- -- -- -- -- -- -- 171 31 6 0 192 42 6 0 223 26 6 1 288 48 6 10 -- -- -- -- -- -- -- -- 171 31 6 0 192 42 6 0 -- -- -- -- 298 48 6 0 342 84 6 0 -- -- -- -- 171 31 6 0 192 42 6 0 -- -- -- -- 298 48 6 0 342 84 6 0 *User I/O count includes four ExpressCLK inputs. Lattice Semiconductor 151 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin Information (continued) Compatibility with OR2C/TxxA Series SE L D E IS C C T O D N E TI VI N C U E ED S The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices offered in the same packages. This includes the following pins: VDD, VSS, VDD5 (OR2TxxA Series only), and all configuration pins. The following restrictions apply: 1. There are two configuration modes supported in the OR2C/TxxA Series that are not supported in Series 3: master parallel down and synchronous peripheral modes. The Series 3 FPGAs have two new microprocessor interface (MPI) configuration modes that are unavailable in the OR2C/TxxA Series. 2. There are four pins--one per each device side--that are user I/O in the OR2C/TxxA Series which can only be used as fast dedicated clocks or global inputs in Series 3. These pins are also used to drive the ExpressCLK to the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to connect to a programmable clock manager (PCM). A corner ExpressCLK input should be used instead (see item 3 below). See Table 69 for a list of these pins in each package. 3. There are two other pins that are user I/O in both the OR2C/TxxA and Series 3 but also have optional added functionality. Each of these pins drives the ExpressCLKs on two sides of the device. They also have fast connectivity to the programmable clock manager (PCM). See Table 69 for a list of these pins in each package. Table 69. Series 3 ExpressCLK Pins Pin Name/ Package 144-Pin TQFP I-ECKL I-ECKB I-ECKR I-ECKT I/O-SECKLL I/O-SECKUR 15 55 92 124 33 111 152 208-Pin 240-Pin SQFP/SQFP2 SQFP/SQFP2 22 80 131 178 49 159 26 91 152 207 56 184 256-Pin PBGA 352-Pin PBGA 432-Pin EBGA K3 W11 K18 B11 W1 A19 N2 AE14 N23 B14 AB4 A25 R29 AH16 T2 C15 AG29 D5 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table 70. OR3T20 144-Pin TQFP Pinout Pin VDD VSS PL1A PL2D PL2A PL3D PL3A PL4D PL4C PL4A PL5D PL5C PL5A VSS PECKL PL6C PL6A VDD PL7D PL7C PL7A VSS PL8D PL8A PL9D PL9C PL9A PL10D PL10C PL10A PL11A PL12D PL12B PL12A VSS PCCLK VDD VSS PB1A PB1D PB2A PB3A Function VDD VSS I/O-A0/MPI_BE0 I/O I/O-A1/MPI_BE1 I/O-A2 I/O-A3 I/O I/O I/O-A4 I/O-A5 I/O I/O-A6 VSS I-ECKL I/O I/O-A7/MPI_CLK VDD I/O I/O I/O-A8/MPI_RW VSS I/O-A9/MPI_ACK I/O-A10/MPI_BI I/O I/O I/O-A11/MPI_IRQ I/O-A12 I/O I/O-A13 I/O-A14 I/O I/O-SECKLL I/O-A15 VSS CCLK VDD VSS I/O-A16 I/O I/O-A17 I/O SE L D E IS C C T O D N E TI VI N C U E ED S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 OR3T20 Pad Lattice Semiconductor 153 ORCA Series 3C and 3T FPGAs Pin OR3T20 Pad Data Sheet November 2006 Function PB3B PB3D VDD PB4A PB4D PB5A PB5C PB5D PB6A PB6C PB6D VSS PECKB PB7C PB7D PB8A PB8D PB9A PB9C PB9D VDD PB10A I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O VSS I-ECKB I/O I/O I/O I/O I/O-HDC I/O I/O VDD I/O-LDC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 PB10C PB10D PB11A PB11D PB12A VSS PDONE VDD VSS PRESETN PPRGMN PR12A PR12D PR11A PR10A PR10C PR10D PR9A PR9B PR9D PR8A I/O I/O I/O-INIT I/O I/O VSS DONE VDD VSS RESET PRGM I/O-M0 I/O I/O I/O-M1 I/O I/O I/O-M2 I/O I/O I/O-M3 SE L D E IS C C T O D N E TI VI N C U E ED S 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 154 Lattice Semiconductor Data Sheet November 2006 Pin PR8D VSS PR7A PR7C PR7D VDD PECKR PR6C PR6D VSS PR5A PR5C PR5D PR4A PR4D PR3A PR3D PR2A PR2C PR2D PR1A VSS PRD_CFGN VDD VSS PT12D PT12A Function I/O VSS I/O I/O I/O VDD I-ECKR I/O I/O VSS I/O I/O I/O I/O-CS1 I/O I/O-CS0 I/O I/O-RD/MPI_STRB I/O I/O I/O-WR VSS RD_CFG VDD VSS I/O-SECKUR I/O-RDY/RCLK/ MPI_ALE I/O I/O-D7 I/O I/O I/O-D6 VDD I/O I/O-D5 I/O I/O I/O-D4 I-ECKT I/O I/O-D3 VSS I/O SE L D E IS C C T O D N E TI VI N C U E ED S 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 OR3T20 Pad ORCA Series 3C and 3T FPGAs 113 PT11D 114 PT11A 115 PT10D 116 PT10C 117 PT10A 118 VDD 119 PT9D 120 PT9A 121 PT8D 122 PT8B 123 PT8A 124 PECKT 125 PT7C 126 PT7A 127 VSS 128 PT6D Lattice Semiconductor 155 ORCA Series 3C and 3T FPGAs OR3T20 Pad 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PT6C PT6A PT5D PT5C PT5A PT4D PT4A VDD PT3D PT3C PT3A PT2A PT1D PT1A VSS PRD_DATA Function I/O I/O-D2 I/O-D1 I/O I/O-D0/DIN I/O I/O-DOUT VDD I/O I/O I/O-TDI I/O-TMS I/O I/O-TCK VSS RD_DATA/TDO SE L D E IS C C T O D N E TI VI N C U E ED S Pin Data Sheet November 2006 156 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table 71. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout OR3T20 Pad OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 1 2 3 4 5 6 7 8 9 10 11 12 VSS VSS PL1D PL1A PL2D PL2C PL2A PL3D PL3C PL3B PL3A VDD VSS VSS PL1D PL2D PL3D PL3C PL3A PL4D PL4C PL4B PL4A VSS VSS PL1D PL2D PL3D PL3A PL4A PL5A PL6D PL6B PL6A VSS VSS PL1D PL2D PL4D PL4A PL5A PL6A PL7D PL7B PL7A VSS VSS PL1D PL2D PL4D PL5D PL7D PL8A PL9D PL9B PL9A VSS VSS I/O I/O-A0/MPI_BE0 I/O I/O I/O-A1/MPI_BE1 I/O-A2 I/O I/O I/O-A3 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 PL4D PL4C PL4B PL4A PL5D PL5C PL5B PL5A VSS PECKL PL6C PL6B PL6A VDD PL7D PL7C PL7B PL7A VSS PL8D PL8C PL8B PL8A PL9D PL9C PL9B PL9A VDD PL10D PL10C VDD PL5D PL5C PL5B PL5A PL6D PL6C PL6B PL6A VSS PECKL PL7C PL7B PL7A VDD PL8D PL8C PL8B PL8A VSS PL9D PL9C PL9B PL9A PL10D PL10C PL10B PL10A VDD PL11D PL11C VDD PL7D PL7C PL7B PL7A PL8D PL8C PL8B PL8A VSS PECKL PL9C PL9B PL9A VDD PL10D PL10C PL10B PL10A VSS PL11D PL11C PL11B PL11A PL12D PL12C PL12B PL12A VDD PL13D PL13B VDD PL8D PL8A PL9D PL9B PL9A PL10C PL10B PL10A VSS PECKL PL11C PL11B PL11A VDD PL12D PL12C PL12B PL12A VSS PL13D PL13B PL13A PL14C PL14B PL15C PL15B PL15A VDD PL16D PL16B VDD PL10D PL10A PL11D PL11A PL12D PL12A PL13D PL13A VSS PECKL PL14C PL14B PL14A VDD PL15D PL15C PL15B PL15A VSS PL16D PL16A PL17D PL17A PL18D PL18A PL19D PL19A VDD PL20D PL20B VDD I/O I/O I/O I/O-A4 I/O-A5 I/O I/O I/O-A6 VSS I-ECKL I/O I/O I/O-A7/MPI_CLK VDD I/O I/O I/O I/O-A8/MPI_RW VSS I/O-A9/MPI_ACK I/O I/O I/O-A10/MPI_BI I/O I/O I/O I/O-A11/MPI_IRQ VDD I/O-A12 I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 157 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T20 Pad OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 PL10B PL10A PL11D PL11A PL12D PL12C PL12B PL12A VSS PCCLK VSS VSS PB1A PB1B PB1C PB1D PB2A PB2D PB3A PB3B PB3C PB3D VDD PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D VSS PB6A PB6B PB6C PB6D VSS PECKB PB7B PB7C PB7D VSS PB8A PL11B PL11A PL12D PL12A PL13D PL13A PL14C PL14A VSS PCCLK VSS VSS PB1A PB1D PB2A PB2D PB3A PB3D PB4A PB4B PB4C PB4D VDD PB5A PB5B PB5C PB5D PB6A PB6B PB6C PB6D VSS PB7A PB7B PB7C PB7D VSS PECKB PB8B PB8C PB8D VSS PB9A PL14D PL14B PL15D PL16D PL17D PL17A PL18C PL18A VSS PCCLK VSS VSS PB1A PB1D PB2A PB2D PB3D PB4D PB5B PB5D PB6B PB6D VDD PB7A PB7B PB7C PB7D PB8A PB8B PB8C PB8D VSS PB9A PB9B PB9C PB9D VSS PECKB PB10B PB10C PB10D VSS PB11A PL17D PL17B PL18D PL19D PL20D PL21D PL21A PL22A VSS PCCLK VSS VSS PB1A PB2A PB2D PB3D PB4D PB5D PB6B PB6D PB7B PB7D VDD PB8A PB8D PB9A PB9C PB9D PB10A PB10B PB10D VSS PB11A PB11B PB11C PB11D VSS PECKB PB12B PB12C PB12D VSS PB13A PL21D PL21B PL22D PL24A PL26D PL27D PL27A PL28A VSS PCCLK VSS VSS PB1A PB2A PB2D PB3D PB4D PB5D PB6D PB7D PB8D PB9D VDD PB10A PB10D PB11A PB11D PB12A PB12D PB13A PB13D VSS PB14A PB14B PB14C PB14D VSS PECKB PB15B PB15C PB15D VSS PB16A I/O I/O-A13 I/O I/O-A14 I/O I/O I/O-SECKLL I/O-A15 VSS CCLK VSS VSS I/O-A16 I/O I/O I/O I/O-A17 I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O VSS I/O I/O I/O I/O VSS I-ECKB I/O I/O I/O VSS I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin 158 Lattice Semiconductor Data Sheet November 2006 Pin OR3T20 Pad OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function PB8B PB8C PB8D PB9A PB9B PB9C PB9D VDD PB10A PB10B PB10C PB10D PB11A PB11C PB11D PB12A PB12D VSS PDONE VSS PB9B PB9C PB9D PB10A PB10B PB10C PB10D VDD PB11A PB11D PB12A PB12B PB12C PB12D PB13A PB13D PB14D VSS PDONE VSS PB11B PB11C PB11D PB12A PB12B PB12C PB12D VDD PB13A PB13D PB14A PB14D PB15A PB16A PB17A PB18A PB18D VSS PDONE VSS PB13B PB13C PB14A PB14B PB14D PB15A PB15D VDD PB16A PB16D PB17A PB17D PB18A PB19A PB20A PB21D PB22D VSS PDONE VSS PB16D PB17A PB17D PB18A PB18D PB19A PB19D VDD PB20A PB21D PB22A PB23D PB24A PB25A PB26A PB27D PB28D VSS PDONE VSS I/O I/O I/O I/O-HDC I/O I/O I/O VDD I/O-LDC I/O I/O I/O I/O-INIT I/O I/O I/O I/O VSS DONE VSS PRESETN PRESETN PRESETN PRESETN PRESETN RESET PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM PR12A PR12D PR11A PR11B PR10A PR10B PR10C PR10D VDD PR9A PR9B PR9C PR9D PR8A PR8B PR8C PR8D VSS PR7A PR7B PR14A PR13A PR13D PR12A PR11A PR11B PR11C PR11D VDD PR10A PR10B PR10C PR10D PR9A PR9B PR9C PR9D VSS PR8A PR8B PR18A PR18D PR17B PR16A PR15D PR14A PR14D PR13A VDD PR12A PR12B PR12C PR12D PR11A PR11B PR11C PR11D VSS PR10A PR10B PR22A PR21A PR20A PR19A PR18D PR17A PR17D PR16A VDD PR15A PR15D PR14A PR14C PR14D PR13A PR13B PR13D VSS PR12A PR12B PR28A PR27A PR26A PR25A PR22D PR21A PR21D PR20A VDD PR19A PR19D PR18A PR18D PR17A PR17D PR16A PR16D VSS PR15A PR15B I/O-M0 I/O I/O I/O I/O-M1 I/O I/O I/O VDD I/O-M2 I/O I/O I/O I/O-M3 I/O I/O I/O VSS I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 ORCA Series 3C and 3T FPGAs Lattice Semiconductor 159 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function PR7C PR7D VDD PECKR PR6B PR6C PR6D VSS PR5A PR5B PR5C PR5D PR4A PR4B PR4C PR4D VDD PR3A PR3B PR3C PR3D PR2A PR2C PR2D PR1A PR1C PR1D VSS PR8C PR8D VDD PECKR PR7B PR7C PR7D VSS PR6A PR6B PR6C PR6D PR5A PR5B PR5C PR5D VDD PR4A PR4B PR4C PR4D PR3A PR3C PR3D PR2A PR2D PR1A VSS PR10C PR10D VDD PECKR PR9B PR9C PR9D VSS PR8A PR8B PR8C PR8D PR7A PR7B PR7C PR7D VDD PR6A PR6B PR5B PR5D PR4A PR4D PR3A PR2A PR2C PR1A VSS PR12C PR12D VDD PECKR PR11B PR11C PR11D VSS PR10A PR10C PR10D PR9B PR9C PR9D PR8A PR8D VDD PR7A PR7B PR6B PR6D PR5A PR5D PR4A PR3A PR2A PR1A VSS PR15C PR15D VDD PECKR PR14B PR14C PR14D VSS PR13A PR13D PR12A PR12D PR11A PR11D PR10A PR10D VDD PR9A PR9B PR8B PR8D PR7A PR5A PR4A PR3A PR2A PR1A VSS I/O I/O VDD I-ECKR I/O I/O I/O VSS I/O I/O I/O I/O I/O-CS1 I/O I/O I/O VDD I/O-CS0 I/O I/O I/O I/O-RD/MPI_STRB I/O I/O I/O-WR I/O I/O VSS PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG VSS VSS PT12D PT12A PT11D PT11C PT11A PT10D PT10C PT10B PT10A VDD PT9D PT9C VSS VSS PT14D PT13D PT13A PT12D PT12C PT12A PT11D PT11C PT11B VDD PT10D PT10C VSS VSS PT18D PT17D PT16D PT16A PT15D PT14D PT14A PT13D PT13B VDD PT12D PT12C VSS VSS PT22D PT21A PT19D PT19A PT18D PT17D PT17A PT16D PT16B VDD PT15D PT15B VSS VSS PT28D PT27A PT25D PT25A PT24D PT23D PT22D PT21D PT20D VDD PT19D PT19A VSS VSS I/O-SECKUR SE L D E IS C C T O D N E TI VI N C U E ED S 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 OR3T20 Pad 160 I/O-RDY/RCLK/MPI_ALE I/O I/O I/O-D7 I/O I/O I/O I/O-D6 VDD I/O I/O Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T20 Pad OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PT9B PT9A PT8D PT8C PT8B PT8A VSS PECKT PT7C PT7B PT7A VSS PT6D PT6C PT6B PT6A VSS PT5D PT5C PT5B PT5A PT4D PT4C PT4B PT4A VDD PT3D PT3C PT3B PT3A PT2D PT2A PT1D PT1C PT1B PT1A VSS PRD_DATA PT10B PT10A PT9D PT9C PT9B PT9A VSS PECKT PT8C PT8B PT8A VSS PT7D PT7C PT7B PT7A VSS PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT5A VDD PT4D PT4C PT4B PT4A PT3D PT3A PT2D PT2A PT1D PT1A VSS PT12B PT12A PT11D PT11C PT11B PT11A VSS PECKT PT10C PT10B PT10A VSS PT9D PT9C PT9B PT9A VSS PT8D PT8C PT8B PT8A PT7D PT7C PT7B PT7A VDD PT6D PT6A PT5C PT5A PT4A PT3A PT2C PT2A PT1D PT1A VSS PT15A PT14C PT14B PT13D PT13C PT13A VSS PECKT PT12C PT12B PT12A VSS PT11D PT11C PT11B PT11A VSS PT10D PT10B PT10A PT9C PT9B PT8D PT8C PT8A VDD PT7D PT7A PT6C PT6A PT5A PT4A PT3A PT2A PT1D PT1A VSS PT18D PT18A PT17D PT17A PT16D PT16A VSS PECKT PT15C PT15B PT15A VSS PT14D PT14C PT14B PT14A VSS PT13D PT13A PT12D PT12A PT11D PT11A PT10D PT10A VDD PT9D PT8A PT7A PT6A PT5A PT4A PT3A PT2A PT1D PT1A VSS I/O I/O-D5 I/O I/O I/O I/O-D4 VSS I-ECKT I/O I/O I/O-D3 VSS I/O I/O I/O I/O-D2 VSS I/O-D1 I/O I/O I/O-D0/DIN I/O I/O I/O I/O-DOUT VDD I/O I/O I/O I/O-TDI I/O I/O-TMS I/O I/O I/O I/O-TCK VSS PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 161 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table 72. OR3T30, OR3T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 VSS VDD PL1D PL1B PL1A PL2D VSS PL3D PL3C PL3B PL3A PL4D PL4C PL4B PL4A VDD PL5D PL5C PL5B PL5A PL6D PL6C PL6B PL6A VSS PECKL PL7C PL7B PL7A VDD PL8D PL8C PL8B PL8A VSS PL9D PL9C PL9B PL9A PL10D PL10C VSS VDD PL1D PL1C PL1B PL2D VSS PL3D PL3A PL4D PL4A PL5A PL6D PL6B PL6A VDD PL7D PL7C PL7B PL7A PL8D PL8C PL8B PL8A VSS PECKL PL9C PL9B PL9A VDD PL10D PL10C PL10B PL10A VSS PL11D PL11C PL11B PL11A PL12D PL12C VSS VDD PL1D PL1C PL1B PL2D VSS PL4D PL4A PL5D PL5A PL6A PL7D PL7B PL7A VDD PL8D PL8A PL9D PL9B PL9A PL10C PL10B PL10A VSS PECKL PL11C PL11B PL11A VDD PL12D PL12C PL12B PL12A VSS PL13D PL13B PL13A PL14C PL14B PL15C VSS VDD PL1D PL1C PL1B PL2D VSS PL4D PL5D PL6D PL7D PL8A PL9D PL9B PL9A VDD PL10D PL10A PL11D PL11A PL12D PL12A PL13D PL13A VSS PECKL PL14C PL14B PL14A VDD PL15D PL15C PL15B PL15A VSS PL16D PL16A PL17D PL17A PL18D PL18A VSS VDD I/O I/O I/O I/O-A0/MPI_BE0 VSS I/O I/O I/O I/O-A1/MPI_BE1 I/O-A2 I/O I/O I/O-A3 VDD I/O I/O I/O I/O-A4 I/O-A5 I/O I/O I/O-A6 VSS I-ECKL I/O I/O I/O-A7/MPI_CLK VDD I/O I/O I/O I/O-A8/MPI_RW VSS I/O-A9/MPI_ACK I/O I/O I/O-A10/MPI_BI I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin 162 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PL10B PL10A VDD PL11D PL11C PL11B PL11A PL12D PL12C PL12B PL12A VSS PL13D PL13A PL14C PL14A VSS PCCLK VDD VSS VSS PB1A PB1D PB2A PB2D VSS PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D VDD PB5A PB5B PB5C PB5D PB6A PB6B PB6C PB6D PL12B PL12A VDD PL13D PL13B PL14D PL14B PL14A PL15D PL15B PL16D VSS PL17D PL17A PL18C PL18A VSS PCCLK VDD VSS VSS PB1A PB1D PB2A PB2D VSS PB3D PB4D PB5A PB5B PB5D PB6A PB6B PB6D VDD PB7A PB7B PB7C PB7D PB8A PB8B PB8C PB8D PL15B PL15A VDD PL16D PL16B PL17D PL17B PL17A PL18D PL18B PL19D VSS PL20D PL21D PL21A PL22A VSS PCCLK VDD VSS VSS PB1A PB2A PB2D PB3D VSS PB4D PB5D PB6A PB6B PB6D PB7A PB7B PB7D VDD PB8A PB8D PB9A PB9C PB9D PB10A PB10B PB10D PL19D PL19A VDD PL20D PL20B PL21D PL21B PL21A PL22D PL23D PL24A VSS PL26D PL27D PL27A PL28A VSS PCCLK VDD VSS VSS PB1A PB2A PB2D PB3D VSS PB4D PB5D PB6A PB6D PB7D PB8A PB8D PB9D VDD PB10A PB10D PB11A PB11D PB12A PB12D PB13A PB13D I/O I/O-A11/MPI_IRQ VDD I/O-A12 I/O I/O I/O-A13 I/O I/O I/O I/O-A14 VSS I/O I/O I/O-SECKLL I/O-A15 VSS CCLK VDD VSS VSS I/O-A16 I/O I/O I/O VSS I/O-A17 I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 163 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function VSS PB7A PB7B PB7C PB7D VSS PECKB PB8B PB8C PB8D VSS PB9A PB9B PB9C PB9D PB10A PB10B PB10C PB10D VDD PB11A PB11D PB12A PB12B PB12C PB12D PB13A PB13B -- PB13D PB14A PB14B PB14D VSS PDONE VDD VSS VSS PB9A PB9B PB9C PB9D VSS PECKB PB10B PB10C PB10D VSS PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D VDD PB13A PB13D PB14A PB14D PB15A PB15D PB16A PB16D VSS PB17A PB17D PB18A PB18D VSS PDONE VDD VSS VSS PB11A PB11B PB11C PB11D VSS PECKB PB12B PB12C PB12D VSS PB13A PB13B PB13C PB14A PB14B PB14D PB15A PB15D VDD PB16A PB16D PB17A PB17D PB18A PB18D PB19A PB19D VSS PB20A PB21A PB21D PB22D VSS PDONE VDD VSS VSS PB14A PB14B PB14C PB14D VSS PECKB PB15B PB15C PB15D VSS PB16A PB16D PB17A PB17D PB18A PB18D PB19A PB19D VDD PB20A PB21D PB22A PB23D PB24A PB24D PB25A PB25D VSS PB26A PB27A PB27D PB28D VSS PDONE VDD VSS VSS I/O I/O I/O I/O VSS I-ECKB I/O I/O I/O VSS I/O I/O I/O I/O I/O-HDC I/O I/O I/O VDD I/O-LDC I/O I/O I/O I/O-INIT I/O I/O I/O VSS I/O I/O I/O I/O VSS DONE VDD VSS PRESETN PRESETN PRESETN PRESETN RESET PPRGMN PPRGMN PPRGMN PPRGMN PRGM PR14A PR14D PR13A PR13D PR18A PR18C PR18D PR17B PR22A PR22D PR21A PR20A PR28A PR28D PR27A PR26A I/O-M0 I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 OR3T30 Pad 164 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 VSS PR12A PR12B PR12C PR12D PR11A PR11B PR11C PR11D VDD PR10A PR10B PR10C PR10D PR9A PR9B PR9C PR9D VSS VSS PR16A PR16D PR15A PR15C PR15D PR14A PR14D PR13A VDD PR12A PR12B PR12C PR12D PR11A PR11B PR11C PR11D VSS PR19A PR19D PR18A PR18C PR18D PR17A PR17D PR16A VDD PR15A PR15D PR14A PR14C PR14D PR13A PR13B PR13D VSS PR25A PR24A PR23A PR23D PR22D PR21A PR21D PR20A VDD PR19A PR19D PR18A PR18D PR17A PR17D PR16A PR16D VSS I/O I/O I/O I/O I/O-M1 I/O I/O I/O VDD I/O-M2 I/O I/O I/O I/O-M3 I/O I/O I/O 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 PR8A PR8B PR8C PR8D VDD PECKR PR7B PR7C PR7D VSS PR6A PR6B PR6C PR6D PR5A PR5B PR5C PR5D VDD PR4A PR4B PR4C PR4D PR3A VSS PR10A PR10B PR10C PR10D VDD PECKR PR9B PR9C PR9D VSS PR8A PR8B PR8C PR8D PR7A PR7B PR7C PR7D VDD PR6A PR6B PR5B PR5D PR4A VSS PR12A PR12B PR12C PR12D VDD PECKR PR11B PR11C PR11D VSS PR10A PR10C PR10D PR9B PR9C PR9D PR8A PR8D VDD PR7A PR7B PR6B PR6D PR5A VSS PR15A PR15B PR15C PR15D VDD PECKR PR14B PR14C PR14D VSS PR13A PR13D PR12A PR12D PR11A PR11D PR10A PR10D VDD PR9A PR9B PR8B PR8D PR7A VSS I/O I/O I/O I/O VDD I-ECKR I/O I/O I/O VSS I/O I/O I/O I/O I/O-CS1 I/O I/O I/O VDD I/O-CS0 I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor I/O-RD/MPI_STRB 165 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function PR3B PR3C PR3D VSS PR2A PR2D PR1A PR1D VSS PR4B PR4D PR3A VSS PR2A PR2C PR1A PR1D VSS PR5B PR5D PR4A VSS PR3A PR2A PR1A PR1D VSS PR6A PR5A PR4A VSS PR3A PR2A PR1A PR1D VSS I/O I/O I/O VSS I/O-WR I/O I/O I/O VSS PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG VSS VDD VSS PT14D PT14C PT14A PT13D -- PT13B PT13A PT12D PT12C PT12A PT11D PT11C PT11B VDD PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A VSS PECKT PT8C PT8B PT8A VSS PT7D VSS VDD VSS PT18D PT18B PT18A PT17D VSS PT16D PT16C PT16A PT15D PT14D PT14A PT13D PT13B VDD PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A VSS PECKT PT10C PT10B PT10A VSS PT9D VSS VDD VSS PT22D PT22A PT21D PT21A VSS PT19D PT19C PT19A PT18D PT17D PT17A PT16D PT16B VDD PT15D PT15B PT15A PT14C PT14B PT13D PT13C PT13A VSS PECKT PT12C PT12B PT12A VSS PT11D VSS VDD VSS PT28D PT28A PT27D PT27A VSS PT25D PT25C PT25A PT24D PT23D PT22D PT21D PT20D VDD PT19D PT19A PT18D PT18A PT17D PT17A PT16D PT16A VSS PECKT PT15C PT15B PT15A VSS PT14D VSS VDD VSS I/O-SECKUR I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 OR3T30 Pad 166 I/O-RDY/RCLK/MPI_ALE VSS I/O I/O I/O I/O-D7 I/O I/O I/O I/O-D6 VDD I/O I/O I/O I/O-D5 I/O I/O I/O I/O-D4 VSS I-ECKT I/O I/O I/O-D3 VSS I/O Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T30 Pad OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PT7C PT7B PT7A VSS PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT5A VDD PT4D PT4C PT4B PT4A PT3D PT3C PT3B PT3A VSS PT2D PT2A PT1D PT1A VSS PRD_DATA PT9C PT9B PT9A VSS PT8D PT8C PT8B PT8A PT7D PT7C PT7B PT7A VDD PT6D PT6A PT5C PT5A PT4D PT4A PT3D PT3A VSS PT2C PT2A PT1D PT1A VSS PRD_DATA PT11C PT11B PT11A VSS PT10D PT10B PT10A PT9C PT9B PT8D PT8C PT8A VDD PT7D PT7A PT6C PT6A PT5D PT5A PT4D PT4A VSS PT3A PT2A PT1D PT1A VSS PRD_DATA PT14C PT14B PT14A VSS PT13D PT13A PT12D PT12A PT11D PT11A PT10D PT10A VDD PT9D PT8A PT7A PT6A PT5D PT5A PT4D PT4A VSS PT3A PT2A PT1D PT1A VSS PRD_DATA I/O I/O I/O-D2 VSS I/O-D1 I/O I/O I/O-D0/DIN I/O I/O I/O I/O-DOUT VDD I/O I/O I/O I/O-TDI I/O I/O I/O I/O-TMS VSS I/O I/O I/O I/O-TCK VSS RD_DATA/TDO SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 167 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table 73. OR3T20, OR3T30, and OR3T55 256-Pin PBGA Pinout OR3T20 Pad OR3T30 Pad OR3T55 Pad B1 C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 G4 F2 F1 G3 G2 G1 H3 H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 L2 L3 L4 M1 M2 M3 M4 N1 N2 N3 P1 P2 R1 P3 R2 T1 VDD PL1D PL1C PL1B PL1A -- -- -- PL2D PL2C PL2B PL2A -- PL3D PL3C PL3B PL3A PL4D PL4C PL4B PL4A PL5D PL5C PL5B PL5A PECKL PL6C PL6B PL6A PL7D PL7C PL7B PL7A PL8D PL8C PL8B PL8A PL9D PL9C PL9B PL9A PL10D PL10C PL10B VDD PL1D PL1B PL1A PL2D PL2C PL2B PL2A PL3D PL3C PL3B PL3A -- PL4D PL4C PL4B PL4A PL5D PL5C PL5B PL5A PL6D PL6C PL6B PL6A PECKL PL7C PL7B PL7A PL8D PL8C PL8B PL8A PL9D PL9C PL9B PL9A PL10D PL10C PL10B PL10A PL11D PL11C PL11B VDD PL1D PL1C PL1B PL2D PL2C PL2B PL2A PL3D PL3A PL4D PL4A PL5D PL5A PL6D PL6B PL6A PL7D PL7C PL7B PL7A PL8D PL8C PL8B PL8A PECKL PL9C PL9B PL9A PL10D PL10C PL10B PL10A PL11D PL11C PL11B PL11A PL12D PL12C PL12B PL12A PL13D PL13B PL14D Function VDD I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin 168 I/O-A0/MPI_BE0 I/O I/O I/O I/O I/O I/O I/O-A1/MPI_BE1 I/O I/O-A2 I/O I/O I/O-A3 I/O I/O I/O I/O-A4 I/O-A5 I/O I/O I/O-A6 I-ECKL I/O I/O I/O-A7/MPI_CLK I/O I/O I/O I/O-A8/MPI_RW I/O-A9/MPI_ACK I/O I/O I/O-A10/MPI_BI I/O I/O I/O I/O-A11/MPI_IRQ I/O-A12 I/O I/O Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T20 Pad OR3T30 Pad OR3T55 Pad Function P4 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 W2 Y1 W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 U7 W6 Y6 V7 W7 Y7 V8 W8 Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 V11 U11 PL10A PL11D PL11C PL11B PL11A -- PL12D PL12C -- -- PL12B -- PL12A PCCLK -- PB1A -- PB1B PB1C PB1D -- -- PB2A PB2B PB2C PB2D PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB6A PB6B PB6C PB6D PECKB PB7B PB7C PL11A PL12D PL12C PL12B PL12A PL13D PL13C PL13B PL13A PL14D PL14C PL14B PL14A PCCLK -- PB1A PB1C PB1D PB2A PB2B PB2C PB2D PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB6A PB6B PB6C PB6D PB7A PB7B PB7C PB7D PECKB PB8B PB8C PL14B PL14A PL15D PL15B PL16D PL17D PL17C PL17B PL17A PL18D PL18C PL18B PL18A PCCLK -- PB1A PB1C PB1D PB2A PB2B PB2C PB2D PB3D PB4D PB5A PB5B PB5D PB6A PB6B PB6D PB7A PB7B PB7C PB7D PB8A PB8B PB8C PB8D PB9A PB9B PB9C PB9D PECKB PB10B PB10C I/O-A13 I/O I/O I/O I/O-A14 I/O I/O I/O I/O I/O I/O-SECKLL I/O I/O-A15 CCLK NC I/O-A16 I/O I/O I/O I/O I/O I/O I/O-A17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I-ECKB I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 169 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin OR3T30 Pad OR3T55 Pad Function PB7D PB8A PB8B PB8C PB8D PB9A PB9B PB9C PB9D PB10A PB10B PB10C PB10D -- -- PB11A -- -- PB11B PB11C PB11D PB12A PB12B PB12C PB12D -- PDONE PB8D PB9A PB9B PB9C PB9D PB10A PB10B PB10C PB10D PB11A PB11B PB11C PB11D PB12A PB12B PB12C -- PB12D PB13A PB13B PB13C PB13D PB14A PB14B PB14C PB14D PDONE PB10D PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B PB13C PB13D PB14A PB14D PB15A PB15D PB16A PB16D PB17A PB17C PB17D PB18A PB18B PB18C PB18D PDONE I/O I/O I/O I/O I/O I/O-HDC I/O I/O I/O I/O-LDC I/O I/O I/O I/O I/O I/O-INIT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DONE PRESETN PRESETN PRESETN RESET PPRGMN PPRGMN PPRGMN PRGM PR12A -- -- -- PR12B PR12C PR12D PR11A PR11B PR11C PR11D PR10A PR10B PR10C PR10D PR9A PR14A PR14C PR14D PR13A PR13B PR13C PR13D PR12A PR12B PR12C PR12D PR11A PR11B PR11C PR11D PR10A PR18A PR18C PR18D PR17A PR17B PR17C PR17D PR16A PR16D PR15A PR15C PR15D PR14A PR14D PR13A PR12A I/O-M0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-M1 I/O I/O I/O I/O-M2 SE L D E IS C C T O D N E TI VI N C U E ED S Y12 W12 V12 U12 Y13 W13 V13 Y14 W14 Y15 V14 W15 Y16 U14 V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 Y20 W20 V19 U19 U18 T17 V20 U20 T18 T19 T20 R18 P17 R19 R20 P18 P19 P20 N18 OR3T20 Pad 170 Lattice Semiconductor Data Sheet November 2006 Pin OR3T20 Pad OR3T30 Pad OR3T55 Pad PR9B PR9C PR9D PR8A PR8B PR8C PR8D PR7A PR7B PR7C PR7D PECKR PR6B PR6C PR6D PR5A PR5B PR5C PR5D PR4A PR4B PR4C PR4D PR3A PR3B PR3C PR3D PR2A PR2B PR2C PR2D PR1A PR1B PR1C PR1D -- -- -- -- PR10B PR10C PR10D PR9A PR9B PR9C PR9D PR8A PR8B PR8C PR8D PECKR PR7B PR7C PR7D PR6A PR6B PR6C PR6D PR5A PR5B PR5C PR5D PR4A PR4B PR4C PR4D PR3A PR3B PR3C PR3D PR2A PR2B PR2C PR2D PR1A PR1B PR1C PR1D PR12B PR12C PR12D PR11A PR11B PR11C PR11D PR10A PR10B PR10C PR10D PECKR PR9B PR9C PR9D PR8A PR8B PR8C PR8D PR7A PR7B PR7C PR7D PR6A PR6B PR5B PR5D PR4A PR4B PR4D PR3A PR2A PR2B PR2C PR2D PR1A PR1B PR1C PR1D PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG PT12D -- PT12C PT12B PT12A -- PT14D PT14C PT14B PT14A PT13D PT13C PT18D PT18C PT18B PT18A PT17D PT17A I/O-SECKUR I/O I/O I/O Function I/O I/O I/O I/O-M3 I/O I/O I/O I/O I/O I/O I/O I-ECKR I/O I/O I/O I/O I/O I/O I/O I/O-CS1 I/O I/O I/O I/O-CS0 I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S N19 N20 M17 M18 M19 M20 L19 L18 L20 K20 K19 K18 K17 J20 J19 J18 J17 H20 H19 H18 G20 G19 F20 G18 F19 E20 G17 F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 A19 B18 B17 C17 D16 A18 ORCA Series 3C and 3T FPGAs Lattice Semiconductor I/O-RD/MPI_STRB I/O I/O I/O I/O-WR I/O I/O I/O I/O I/O I/O I/O I/O-RDY/RCLK/MPI_ALE I/O 171 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T20 Pad OR3T30 Pad OR3T55 Pad Function A17 C16 B16 A16 C15 D14 B15 A15 C14 B14 A14 C13 B13 A13 D12 C12 B12 A12 B11 C11 A11 A10 B10 C10 D10 A9 B9 C9 D9 A8 B8 C8 A7 B7 A6 C7 B6 A5 D7 C6 B5 A4 C5 B4 A3 D5 PT11D PT11C PT11B PT11A -- PT10D PT10C PT10B PT10A PT9D PT9C -- PT9B PT9A PT8D PT8C PT8B PT8A PECKT PT7C PT7B PT7A PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A -- PT1D PT1C PT1B PT13B PT13A PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A PECKT PT8C PT8B PT8A PT7D PT7C PT7B PT7A PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A PT16D PT16C PT16A PT15D PT15A PT14D PT14A PT13D PT13B PT13A PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A PECKT PT10C PT10B PT10A PT9D PT9C PT9B PT9A PT8D PT8C PT8B PT8A PT7D PT7C PT7B PT7A PT6D PT6A PT5C PT5A PT4D PT4A PT3D PT3A PT2D PT2C PT2B PT2A I/O I/O I/O I/O-D7 I/O I/O I/O I/O I/O-D6 I/O I/O I/O I/O I/O-D5 I/O I/O I/O I/O-D4 I-ECKT I/O I/O I/O-D3 I/O I/O I/O I/O-D2 I/O-D1 I/O I/O I/O-D0/DIN I/O I/O I/O I/O-DOUT I/O I/O I/O I/O-TDI I/O I/O I/O I/O-TMS I/O I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin 172 Lattice Semiconductor Data Sheet November 2006 Pin OR3T20 Pad OR3T30 Pad OR3T55 Pad Function -- -- -- PT1A PT1D PT1C PT1B PT1A PT1D PT1C PT1B PT1A I/O I/O I/O I/O-TCK PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SE L D E IS C C T O D N E TI VI N C U E ED S C4 B3 B2 A2 C3 A1 D4 D8 D13 D17 H4 H17 N4 N17 U4 U8 U13 U17 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 ORCA Series 3C and 3T FPGAs Lattice Semiconductor 173 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table 74. OR3T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function B1 C2 C1 D2 D3 D1 E2 E4 E3 E1 F2 G4 F3 F1 G2 G1 G3 H2 J4 H1 H3 J2 J1 K2 J3 K1 K4 L2 K3 L1 M2 M1 L3 N2 M4 N1 M3 P2 P4 P1 N3 R2 P3 R1 T2 PL1D PL1C PL1B PL1A PL2D PL2C PL2B -- PL2A PL3D PL3C PL3B PL3A PL4D PL4C PL4B PL4A PL5D PL5C PL5B PL5A PL6D PL6C PL6B PL6A PL7D PL7C PL7B PL7A PL8D PL8C PL8B PL8A PECKL PL9C PL9B PL9A PL10D PL10C PL10B PL10A PL11D PL11C PL11B PL11A PL1D PL1C PL1B PL1A PL2D PL2A PL3D PL3B PL3A PL4D PL4C PL4B PL4A PL5D PL5C PL5B PL5A PL6D PL6C PL6B PL6A PL7D PL7C PL7B PL7A PL8D PL8A PL9D PL9B PL9A PL10C PL10B PL10A PECKL PL11C PL11B PL11A PL12D PL12C PL12B PL12A PL13D PL13B PL13A PL14C PL1D PL1C PL1B PL1A PL2D PL2A PL3D PL3B PL3A PL4D PL4C PL4B PL5D PL6D PL6C PL6B PL7D PL8D PL8C PL8B PL8A PL9D PL9C PL9B PL9A PL10D PL10A PL11D PL11A PL12D PL12A PL13D PL13A PECKL PL14C PL14B PL14A PL15D PL15C PL15B PL15A PL16D PL16A PL17D PL17A I/O I/O I/O I/O I/O-A0/MPI_BE0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A1/MPI_BE1 I/O I/O I/O I/O-A2 I/O I/O I/O I/O-A3 I/O I/O I/O I/O-A4 I/O-A5 I/O I/O I/O-A6 I-ECKL I/O I/O I/O-A7/MPI_CLK I/O I/O I/O I/O-A8/MPI_RW I/O-A9/MPI_ACK I/O I/O I/O-A10/MPI_BI SE L D E IS C C T O D N E TI VI N C U E ED S Pin 174 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function R3 T1 R4 U2 T3 U1 U4 V2 U3 V1 W2 W1 V3 Y2 W4 Y1 W3 AA2 Y4 AA1 Y3 AB2 AB1 AA3 AC2 AB4 AC1 AB3 AD2 AC3 AD1 AF2 AE3 AF3 AE4 AD4 AF4 AE5 AC5 AD5 AF5 AE6 AC7 AD6 AF6 AE7 PL12D PL12C PL12B PL12A PL13D PL13C PL13B PL13A PL14D PL14C PL14B PL14A PL15D PL15C PL15B PL15A PL16D PL16C PL16B PL16A PL17D PL17C PL17B PL17A PL18D PL18C PL18B -- -- PL18A PCCLK PB1A -- PB1B PB1C PB1D PB2A PB2B PB2C PB2D PB3A PB3B PB3C PB3D PB4A PB4B PL14B PL15C PL15B PL15A PL16D PL16C PL16B PL16A PL17D PL17C PL17B PL17A PL18D PL18C PL18B PL18A PL19D PL19C PL19B PL19A PL20D PL20C PL20A PL21D PL21C PL21A PL22D PL22C PL22B PL22A PCCLK PB1A PB1B PB1C PB1D PB2A PB2D PB3A PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PL18D PL18A PL19D PL19A PL20D PL20C PL20B PL20A PL21D PL21C PL21B PL21A PL22D PL22C PL23D PL24D PL24A PL25C PL25B PL25A PL26D PL26C PL26A PL27D PL27C PL27A PL28D PL28C PL28B PL28A PCCLK PB1A PB1B PB1C PB1D PB2A PB2D PB3A PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B I/O I/O I/O I/O-A11/MPI_IRQ I/O-A12 I/O I/O I/O I/O I/O I/O-A13 I/O I/O I/O I/O I/O I/O-A14 I/O I/O I/O I/O I/O I/O I/O I/O I/O-SECKLL I/O I/O I/O I/O-A15 CCLK I/O-A16 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A17 I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 175 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function AF7 AD7 AE8 AC9 AF8 AD8 AE9 AF9 AE10 AD9 AF10 AC10 AE11 AD10 AF11 AE12 AF12 AD11 AE13 AC12 AF13 AD12 AE14 AC14 AF14 AD13 AE15 AD14 AF15 AE16 AD15 AF16 AC15 AE17 AD16 AF17 AC17 AE18 AD17 AF18 AE19 AF19 AD18 AE20 AC19 AF20 PB4C PB4D PB5A PB5B PB5C PB5D PB6A PB6B PB6C PB6D PB7A PB7B PB7C PB7D PB8A PB8B PB8C PB8D PB9A PB9B PB9C PB9D PECKB PB10B PB10C PB10D PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B PB13C PB13D PB14A PB14B PB14C PB14D PB15A PB15B PB15C PB15D PB5C PB5D PB6A PB6B PB6C PB6D PB7A PB7B PB7C PB7D PB8A PB8D PB9A PB9C PB9D PB10A PB10B PB10D PB11A PB11B PB11C PB11D PECKB PB12B PB12C PB12D PB13A PB13B PB13C PB14A PB14B PB14D PB15A PB15D PB16A PB16B PB16C PB16D PB17A PB17B PB17C PB17D PB18A PB18B PB18C PB18D PB5C PB5D PB6A PB6D PB7A PB7D PB8A PB8D PB9A PB9D PB10A PB10D PB11A PB11D PB12A PB12D PB13A PB13D PB14A PB14B PB14C PB14D PECKB PB15B PB15C PB15D PB16A PB16D PB17A PB17D PB18A PB18D PB19A PB19D PB20A PB20D PB21A PB21D PB22A PB23A PB23C PB23D PB24A PB24B PB24C PB24D I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I-ECKB I/O I/O I/O I/O I/O I/O I/O I/O-HDC I/O I/O I/O I/O-LDC I/O I/O I/O I/O I/O I/O I/O I/O-INIT I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin 176 Lattice Semiconductor Data Sheet November 2006 Pin OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function PB16A PB16B PB16C PB16D PB17A PB17B PB17C PB17D -- PB18A PB18B PB18C -- PB18D PDONE PB19A PB19B PB19C PB19D PB20A PB20B PB20D PB21A PB21B PB21D PB22A PB22B PB22C PB22D PDONE PB25A PB25B PB25C PB25D PB26A PB26B PB26D PB27A PB27B PB27D PB28A PB28B PB28C PB28D PDONE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DONE PRESETN PRESETN PRESETN RESET PPRGMN PPRGMN PPRGMN PRGM PR18A PR18B PR18C PR18D PR17A PR17B PR17C PR17D PR16A PR16B PR16C PR16D PR15A PR15B PR15C PR15D PR14A PR14B PR14C PR14D PR13A PR13B PR13C PR13D PR12A PR12B PR12C PR12D PR11A PR22A PR22C PR22D PR21A PR21D PR20A PR20B PR20D PR19A PR19B PR19C PR19D PR18A PR18B PR18C PR18D PR17A PR17B PR17C PR17D PR16A PR16B PR16C PR16D PR15A PR15D PR14A PR14C PR14D PR28A PR28C PR28D PR27A PR27D PR26A PR26B PR26D PR25A PR25B PR25C PR24A PR23A PR23B PR23D PR22D PR21A PR21B PR21C PR21D PR20A PR20B PR20C PR20D PR19A PR19D PR18A PR18D PR17A I/O-M0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-M1 I/O I/O I/O I/O I/O I/O I/O I/O I/O-M2 I/O I/O I/O I/O-M3 SE L D E IS C C T O D N E TI VI N C U E ED S AD19 AE21 AC20 AF21 AD20 AE22 AF22 AD21 AE23 AC22 AF23 AD22 AE24 AD23 AF24 AE26 AD25 AD26 AC25 AC24 AC26 AB25 AB23 AB24 AB26 AA25 Y23 AA24 AA26 Y25 Y26 Y24 W25 V23 W26 W24 V25 V26 U25 V24 U26 U23 T25 U24 T26 R25 ORCA Series 3C and 3T FPGAs Lattice Semiconductor 177 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin OR3C/T80 Pad OR3T125 Pad Function PR11B PR11C PR11D PR10A PR10B PR10C PR10D PECKR PR9B PR9C PR9D PR8A PR8B PR8C PR8D PR7A PR7B PR7C PR7D PR6A PR6B PR6C PR6D PR5A PR5B PR5C PR5D PR4A PR4B PR4C PR4D PR3A PR3B PR3C PR3D PR2A PR2B -- PR2C PR2D PR1A PR1B PR1C PR1D PR13A PR13B PR13D PR12A PR12B PR12C PR12D PECKR PR11B PR11C PR11D PR10A PR10C PR10D PR9B PR9C PR9D PR8A PR8D PR7A PR7B PR7C PR7D PR6A PR6B PR6C PR6D PR5A PR5B PR5C PR5D PR4A PR4B PR4C PR4D PR3A PR3B PR3D PR2A PR2D PR1A PR1B PR1C PR1D PR17D PR16A PR16D PR15A PR15B PR15C PR15D PECKR PR14B PR14C PR14D PR13A PR13D PR12A PR12D PR11A PR11D PR10A PR10D PR9A PR9B PR9C PR9D PR8A PR8B PR8C PR8D PR7A PR6A PR6C PR5A PR4A PR4B PR4C PR4D PR3A PR3B PR3D PR2A PR2D PR1A PR1B PR1C PR1D I/O I/O I/O I/O I/O I/O I/O I-ECKR I/O I/O I/O I/O I/O I/O I/O I/O-CS1 I/O I/O I/O I/O-CS0 I/O I/O I/O I/O I/O I/O I/O I/O-RD/MPI_STRB I/O I/O I/O I/O I/O I/O I/O I/O-WR I/O I/O I/O I/O I/O I/O I/O I/O PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG PT18D PT22D PT28D I/O-SECKUR SE L D E IS C C T O D N E TI VI N C U E ED S R26 T24 P25 R23 P26 R24 N25 N23 N26 P24 M25 N24 M26 L25 M24 L26 M23 K25 L24 K26 K23 J25 K24 J26 H25 H26 J24 G25 H23 G26 H24 F25 G23 F26 G24 E25 E26 F24 D25 E23 D26 E24 C25 D24 C26 A25 OR3T55 Pad 178 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T55 Pad OR3C/T80 Pad OR3T125 Pad B24 A24 B23 C23 A23 PT18C -- PT18B PT18A PT17D PT22C PT22B PT22A PT21D PT21A PT28C PT28B PT28A PT27D PT27A B22 PT17C D22 PT17B C22 PT17A A22 PT16D B21 PT16C D20 PT16B C21 PT16A A21 PT15D B20 PT15C A20 PT15B C20 PT15A B19 PT14D D18 PT14C A19 PT14B C19 PT14A B18 PT13D A18 PT13C B17 PT13B C18 PT13A A17 PT12D D17 PT12C B16 PT12B C17 PT12A A16 PT11D B15 PT11C A15 PT11B C16 PT11A B14 PECKT D15 PT10C A14 PT10B C15 PT10A B13 PT9D D13 PT9C A13 PT9B C14 PT9A B12 PT8D C13 PT8C A12 PT8B B11 PT8A C12 PT7D A11 PT7C Lattice Semiconductor PT20D PT20C PT20A PT19D PT19C PT19B PT19A PT18D PT18C PT18B PT18A PT17D PT17C PT17B PT17A PT16D PT16C PT16B PT16A PT15D PT15B PT15A PT14C PT14B PT13D PT13C PT13A PECKT PT12C PT12B PT12A PT11D PT11C PT11B PT11A PT10D PT10B PT10A PT9C PT9B PT8D PT26D PT26C PT26A PT25D PT25C PT25B PT25A PT24D PT24C PT24B PT24A PT23D PT23C PT23B PT22D PT21D PT21A PT20D PT20A PT19D PT19A PT18D PT18A PT17D PT17A PT16D PT16A PECKT PT15C PT15B PT15A PT14D PT14C PT14B PT14A PT13D PT13A PT12D PT12A PT11D PT11A Function I/O I/O I/O I/O I/O-RDY/RCLK/ MPI_ALE SE L D E IS C C T O D N E TI VI N C U E ED S Pin I/O I/O I/O I/O I/O I/O I/O I/O-D7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-D6 I/O I/O I/O I/O I/O-D5 I/O I/O I/O I/O-D4 I-ECKT I/O I/O I/O-D3 I/O I/O I/O I/O-D2 I/O-D1 I/O I/O I/O-D0/DIN I/O I/O 179 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function D12 B10 C11 A10 D10 B9 C10 A9 B8 A8 C9 B7 D8 A7 C8 B6 D7 A6 C7 B5 A5 C6 B4 D5 A4 C5 B3 C4 A3 A1 A2 A26 AC13 AC18 AC23 AC4 AC8 AD24 AD3 AE1 AE2 AE25 AF1 AF25 AF26 PT7B PT7A PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3C PT3B PT3A PT2D PT2C PT2B -- -- PT2A PT1D PT1C PT1B PT1A PRD_DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PT8C PT8A PT7D PT7C PT7B PT7A PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3A PT2D PT2C PT2B PT2A PT1D PT1C PT1B PT1A PRD_DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PT10D PT10A PT9D PT9A PT8D PT8A PT7D PT7A PT6D PT6A PT5D PT5C PT5B PT5A PT4D PT4C PT4B PT4A PT3D PT3A PT2D PT2C PT2B PT2A PT1D PT1C PT1B PT1A PRD_DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O I/O-DOUT I/O I/O I/O I/O I/O I/O I/O I/O-TDI I/O I/O I/O I/O I/O I/O I/O I/O-TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-TCK RD_DATA/TDO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SE L D E IS C C T O D N E TI VI N C U E ED S Pin 180 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function B2 B25 B26 C24 C3 D14 D19 D23 D4 D9 H4 J23 N4 P23 V4 W23 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R11 R12 R13 R14 R15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* VSS* SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 181 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3T55 Pad OR3C/T80 Pad OR3T125 Pad Function R16 T11 T12 T13 T14 T15 T16 AA23 AA4 AC11 AC16 AC21 AC6 D11 D16 D21 D6 F23 F4 L23 L4 T23 T4 VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS* VSS* VSS* VSS* VSS* VSS* VSS* VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SE L D E IS C C T O D N E TI VI N C U E ED S Pin *Thermally enhanced connection. 182 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Table 75. OR3C/T80 and OR3T125 432-Pin EBGA Pinout Pin OR3T125 Pad Function PRD_CFGN PRD_CFGN RD_CFG PR1D PR1C PR1B PR1A PR2D PR2C PR2B PR2A PR3D PR3C PR3B PR3A PR4D PR4C PR4B PR4A PR5D PR5C PR5B PR5A PR6D PR6C PR6B PR6A PR7D PR7C PR7B PR7A PR8D PR8A PR9D PR9C PR9B PR9A PR10D PR10C PR10B PR10A PR11D PR11C PR11B PECKR PR12D PR12C PR12B PR12A PR13D PR1D PR1C PR1B PR1A PR2D PR2C PR2B PR2A PR3D PR3C PR3B PR3A PR4D PR4C PR4B PR4A PR5A PR6C PR6A PR7A PR8D PR8C PR8B PR8A PR9D PR9C PR9B PR9A PR10D PR10A PR11D PR11A PR12D PR12C PR12A PR13D PR13C PR13A PR14D PR14C PR14B PECKR PR15D PR15C PR15B PR15A PR16D I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-WR I/O I/O I/O I/O I/O I/O I/O I/O-RD/MPI_STRB I/O I/O I/O I/O I/O I/O I/O I/O-CS0 I/O I/O I/O I/O-CS1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I-ECKR I/O I/O I/O I/O I/O V1 V2 V3 W1 V4 W2 W3 Y2 W4 Y3 AA1 AA2 Y4 AA3 AB1 AB2 AB3 AC1 AC2 AB4 AC3 AD2 AD3 AC4 AE1 AE2 AE3 AD4 AF1 AF2 AF3 AG1 AG2 AG3 AF4 AH1 AH2 AH3 AG4 AH5 AJ4 AK4 AL4 AH6 AJ5 AK5 AL5 AJ6 AK6 AL6 OR3C/T80 Pad OR3T125 Pad Function PR13C PR13B PR13A PR14D PR14C PR14B PR14A PR15D PR15A PR16D PR16C PR16B PR16A PR17D PR17C PR17B PR17A PR18D PR18C PR18B PR18A PR19D PR19C PR19B PR19A PR20D PR20C PR20B PR20A PR21D PR21C PR21B PR21A PR22D PR22C PR22B PR22A PR16B PR16A PR17D PR17A PR18D PR18B PR18A PR19D PR19A PR20D PR20C PR20B PR20A PR21D PR21C PR21B PR21A PR22D PR23D PR23B PR23A PR24A PR25C PR25B PR25A PR26D PR26C PR26B PR26A PR27D PR27C PR27B PR27A PR28D PR28C PR28B PR28A I/O I/O I/O I/O-M3 I/O I/O I/O I/O I/O-M2 I/O I/O I/O I/O I/O I/O I/O I/O I/O-M1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-M0 PPRGMN PPRGMN PRGM PRESETN PRESETN RESET PDONE PB22D PB22C PB22B PB22A PB21D PB21C PB21B PB21A PB20D PB20C PDONE PB28D PB28C PB28B PB28A PB27D PB27C PB27B PB27A PB26D PB26C DONE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S E4 D3 D2 D1 F4 E3 E2 E1 F3 F2 F1 H4 G3 G2 G1 J4 H3 H2 J3 K4 J2 J1 K3 K2 K1 L3 M4 L2 L1 M3 N4 M2 N3 N2 P4 N1 P3 P2 P1 R3 R2 R1 T2 T4 T3 U1 U2 U3 OR3C/T80 Pad Pin Lattice Semiconductor 183 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3C/T80 Pad OR3T125 Pad Function Pin OR3C/T80 Pad OR3T125 Pad Function AH8 AJ7 AK7 AL7 AH9 AJ8 AK8 AJ9 AH10 AK9 AL9 AJ10 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 AH13 AK12 AJ13 AK13 AH14 AL13 AJ14 AK14 AL14 AJ15 AK15 AL15 AK16 AH16 AJ16 AL17 AK17 AJ17 AL18 AK18 AJ18 AL19 AH18 AK19 AJ19 AK20 AH19 AJ20 AL21 PB20B PB20A PB19D PB19C PB19B PB19A PB18D PB18C PB18B PB18A PB17D PB17C PB17B PB17A PB16D PB16C PB16B PB16A PB15D PB15B PB15A PB14D PB14C PB14B PB14A PB13D PB13C PB13B PB13A PB12D PB12C PB12B PECKB PB11D PB11C PB11B PB11A PB10D PB10C PB10B PB10A PB9D PB9C PB9B PB9A PB8D PB8B PB8A PB26B PB26A PB25D PB25C PB25B PB25A PB24D PB24C PB24B PB24A PB23D PB23C PB23A PB22A PB21D PB21A PB20D PB20A PB19D PB19B PB19A PB18D PB18B PB18A PB17D PB17B PB17A PB16D PB16A PB15D PB15C PB15B PECKB PB14D PB14C PB14B PB14A PB13D PB13B PB13A PB12D PB12A PB11D PB11B PB11A PB10D PB10B PB10A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-INIT I/O I/O I/O I/O I/O I/O I/O I/O-LDC I/O I/O I/O I/O I/O I/O-HDC I/O I/O I/O I/O I/O I/O I/O I/O I-ECKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AK21 AH20 AJ21 AL22 AK22 AJ22 AL23 AK23 AH22 AJ23 AK24 AJ24 AH23 AL25 AK25 AJ25 AH24 AL26 AK26 AJ26 AL27 AK27 AJ27 AH26 AL28 AK28 AJ28 AH27 AG28 AH29 AH30 AH31 AF28 AG29 AG30 AG31 AF29 AF30 AF31 AD28 AE29 AE30 AE31 AC28 AD29 AD30 AC29 AB28 PB7D PB7C PB7B PB7A PB6D PB6C PB6B PB6A PB5D PB5C PB5B PB5A PB4D PB4C PB4B PB4A PB3D PB3C PB3B PB3A PB2D PB2C PB2B PB2A PB1D PB1C PB1B PB1A PCCLK PL22A PL22B PL22C PL22D PL21A PL21B PL21C PL21D PL20A PL20B PL20C PL20D PL19A PL19B PL19C PL19D PL18A PL18B PL18C PB9D PB9A PB8D PB8A PB7D PB7A PB6D PB6A PB5D PB5C PB5B PB5A PB4D PB4C PB4B PB4A PB3D PB3C PB3B PB3A PB2D PB2C PB2B PB2A PB1D PB1C PB1B PB1A PCCLK PL28A PL28B PL28C PL28D PL27A PL27B PL27C PL27D PL26A PL26B PL26C PL26D PL25A PL25B PL25C PL24A PL24D PL23D PL22C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A16 CCLK I/O-A15 I/O I/O I/O I/O-SECKLL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A14 I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin 184 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs OR3C/T80 Pad OR3T125 Pad Function Pin OR3C/T80 Pad OR3T125 Pad Function AC30 AC31 AB29 AB30 AB31 AA29 Y28 AA30 AA31 Y29 W28 Y30 W29 W30 V28 W31 V29 V30 V31 U29 U30 U31 T30 T28 T29 R31 R30 R29 P31 P30 P29 N31 P28 N30 N29 M30 N28 M29 L31 L30 M28 L29 K31 K30 K29 J31 J30 K28 J29 H30 PL18D PL17A PL17B PL17C PL17D PL16A PL16B PL16C PL16D PL15A PL15B PL15C PL14A PL14B PL14C PL14D PL13A PL13B PL13C PL13D PL12A PL12B PL12C PL12D PL11A PL11B PL11C PECKL PL10A PL10B PL10C PL10D PL9A PL9B PL9C PL9D PL8A PL8C PL8D PL7A PL7B PL7C PL7D PL6A PL6B PL6C PL6D PL5A PL5B PL5C PL22D PL21A PL21B PL21C PL21D PL20A PL20B PL20C PL20D PL19A PL19D PL18A PL18C PL18D PL17A PL17C PL17D PL16A PL16C PL16D PL15A PL15B PL15C PL15D PL14A PL14B PL14C PECKL PL13A PL13D PL12A PL12C PL12D PL11A PL11C PL11D PL10A PL10C PL10D PL9A PL9B PL9C PL9D PL8A PL8B PL8C PL8D PL7D PL6B PL6C I/O I/O I/O-A13 I/O I/O I/O I/O I/O I/O-A12 I/O-A11/MPI_IRQ I/O I/O I/O I/O I/O-A10/MPI_BI I/O I/O I/O I/O I/O-A9/MPI_ACK I/O-A8/MPI_RW I/O I/O I/O I/O-A7/MPI_CLK I/O I/O I-ECKL I/O-A6 I/O I/O I/O I/O-A5 I/O-A4 I/O I/O I/O I/O I/O I/O-A3 I/O I/O I/O I/O-A2 I/O I/O I/O I/O-A1/MPI_BE1 I/O I/O H29 J28 G31 G30 G29 H28 F31 F30 F29 E31 E30 E29 F28 D31 D30 D29 E28 D27 C28 B28 A28 D26 C27 B27 A27 C26 B26 A26 D24 C25 B25 A25 D23 C24 B24 C23 D22 B23 A23 C22 B22 A22 C21 D20 B21 A21 C20 D19 B20 C19 PL5D PL4A PL4B PL4C PL4D PL3A PL3B PL3C PL3D PL2A PL2B PL2C PL2D PL1A PL1B PL1C PL1D PRD_DATA PT1A PT1B PT1C PT1D PT2A PT2B PT2C PT2D PT3A PT3B PT3C PT3D PT4A PT4B PT4C PT4D PT5A PT5B PT5C PT5D PT6A PT6B PT6C PT6D PT7A PT7B PT7C PT7D PT8A PT8C PT8D PT9A PL6D PL5D PL4B PL4C PL4D PL3A PL3B PL3C PL3D PL2A PL2B PL2C PL2D PL1A PL1B PL1C PL1D PRD_DATA PT1A PT1B PT1C PT1D PT2A PT2B PT2C PT2D PT3A PT3B PT3C PT3D PT4A PT4B PT4C PT4D PT5A PT5B PT5C PT5D PT6A PT6D PT7A PT7D PT8A PT8D PT9A PT9D PT10A PT10D PT11A PT11C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A0/MPI_BE0 I/O I/O I/O I/O RD_DATA/TDO I/O-TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-TMS I/O I/O I/O I/O I/O I/O I/O I/O-TDI I/O I/O I/O I/O I/O I/O I/O I/O-DOUT I/O I/O I/O SE L D E IS C C T O D N E TI VI N C U E ED S Pin Lattice Semiconductor 185 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Pin OR3T125 Pad PT9B PT9C PT9D PT10A PT10B PT10C PT10D PT11A PT11B PT11C PT11D PT12A PT12B PT12C PECKT PT13A PT13B PT13C PT13D PT14A PT14B PT14C PT14D PT15A PT15B PT15D PT16A PT16B PT16C PT16D PT17A PT17B PT17C PT17D PT18A PT18B PT18C PT18D PT19A PT19B PT19C PT19D PT20A PT20B PT20C PT20D PT21A PT21B PT21C PT21D PT11D PT12A PT12C PT12D PT13A PT13C PT13D PT14A PT14B PT14C PT14D PT15A PT15B PT15C PECKT PT16A PT16B PT16D PT17A PT17B PT17D PT18A PT18B PT18D PT19A PT19D PT20A PT20D PT21A PT21D PT22D PT23B PT23C PT23D PT24A PT24B PT24C PT24D PT25A PT25B PT25C PT25D PT26A PT26B PT26C PT26D PT27A PT27B PT27C PT27D Function Pin I/O I/O-D0/DIN I/O I/O I/O I/O I/O-D1 I/O-D2 I/O I/O I/O I/O-D3 I/O I/O I-ECKT I/O-D4 I/O I/O I/O I/O I/O I/O-D5 I/O I/O I/O I/O I/O I/O-D6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-D7 I/O I/O I/O I/O I/O I/O I/O I/O A4 B4 C4 D5 A12 A16 A2 A20 A24 A29 A3 A30 A8 AD1 AD31 AJ1 AJ2 AJ30 AJ31 AK1 AK29 AK3 AK31 AL12 AL16 AL2 AL20 AL24 AL29 AL3 AL30 AL8 B1 B29 B3 B31 C1 C2 C30 C31 H1 H31 M1 M31 T1 T31 Y1 Y31 A1 A31 OR3C/T80 Pad PT22A PT22B PT22C PT22D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD OR3T125 Function Pad PT28A I/O PT28B I/O PT28C I/O PT28D I/O-SECKUR VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD Lattice Semiconductor SE L D E IS C C T O D N E TI VI N C U E ED S B19 D18 A19 C18 B18 A18 C17 B17 A17 B16 D16 C16 A15 B15 C15 A14 B14 C14 A13 D14 B13 C13 B12 D13 C12 A11 B11 D12 C11 A10 B10 C10 A9 B9 D10 C9 B8 C8 D9 A7 B7 C7 D8 A6 B6 C6 A5 B5 C5 D6 186 OR3C/T80 Pad I/O-RDY/RCLK/MPI_ALE I/O I/O I/O Data Sheet November 2006 Pin OR3T125 Pad VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Function VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SE L D E IS C C T O D N E TI VI N C U E ED S AA28 AA4 AE28 AE4 AH11 AH15 AH17 AH21 AH25 AH28 AH4 AH7 AJ29 AJ3 AK2 AK30 AL1 AL31 B2 B30 C29 C3 D11 D15 D17 D21 D25 D28 D4 D7 G28 G4 L28 L4 R28 R4 U28 U4 OR3C/T80 Pad VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD ORCA Series 3C and 3T FPGAs Lattice Semiconductor 187 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Thermal Characteristics There are four thermal parameters that are in common use: JA, JC, JC, and JB. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. SE L D E IS C C T O D N E TI VI N C U E ED S Table 76 contains the currently available thermal specifications for FPGA packages mounted on both JEDEC and non-JEDEC test boards. The thermal values for the newer package types correspond to those packages mounted on a JEDEC four-layer board. The values for the older packages, however, correspond to those packages mounted on a non-JEDEC, single-layer, sparse copper board (see Note 2). It should also be noted that the values for the older packages are considered conservative. JA This is the thermal resistance from junction to ambient (a.k.a. theta-JA, R-theta, etc.). TJ - TA JA = ------------------Q where TJ is the junction temperature, TA is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/watt. 188 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs JC This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance, and it is defined by: SE L D E IS C C T O D N E TI VI N C U E ED S TJ - TC JC = ------------------Q where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/watt. JC This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by: TJ - TC JC = ------------------Q The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink so as to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/watt. JB This is the thermal resistance from junction to board (a.k.a. JL). It is defined by: TJ - TB JB = ------------------Q where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board so as to draw most of the heat out of the leads. Note that JB is expressed in units of C/watt, and that this parameter and the way it is measured is still in JEDEC committee. Lattice Semiconductor 189 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Thermal Characteristics (continued) FPGA Maximum Junction Temperature SE L D E IS C C T O D N E TI VI N C U E ED S Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q * JA) Table 76 lists the plastic package thermal characteristics for the ORCA Series FPGAs. Table 76. Plastic Package Thermal Characteristics for the ORCA Series1 Package 144-Pin TQFP1 208-Pin SQFP1 208-Pin SQFP21 240-Pin SQFP1 240-Pin SQFP21 256-Pin PBGA1, 2 256-Pin PBGA1, 3 352-Pin PBGA1, 2 352-Pin PBGA1, 3 432-Pin EBGA1 0 fpm 52.0 26.5 12.8 25.5 13.0 22.5 26.0 19.0 25.5 11.0 JA (C/W) 200 fpm 39.0 23.0 10.3 22.5 10.0 19.0 22.0 16.0 22.0 8.5 500 fpm - 21.0 9.1 21.0 9.0 17.5 20.5 15.0 20.5 7.5 TA = 70 C max TJ = 125 C max @ 0 fpm (W) 1.1 2.1 4.3 2.2 4.2 2.4 2.1 2.9 2.1 5.0 1. Mounted on 4-layer JEDEC standard test board with two power/ground planes. 2. With thermal balls connected to board ground plane. 3. Without thermal balls connected to board ground plane. 190 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Coplanarity The coplanarity limits of the ORCA Series 3 packages are as follows. Table 77. Package Coplanarity Coplanarity Limit (mils) SE L D E IS C C T O D N E TI VI N C U E ED S Package Type EBGA PBGA SQFP/SQFP2 8.0 8.0 4.0 3.15 3.15 TQFP Package Parasitics The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 78 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. The lead resistance value, RW, is in M. The parasitic values in Table 78 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. Table 78. Package Parasitics Package Type 144-Pin TQFP 208-Pin SQFP 208-Pin SQFP2 240-Pin SQFP 240-Pin SQFP2 256-Pin PBGA 352-Pin PBGA 432-Pin EBGA Lattice Semiconductor LSW LMW RW C1 C2 CM LSL LML 3 4 4 4 4 5 5 4 1 2 2 2 2 2 2 1.5 140 200 200 200 200 220 220 500 1 1 1 1 1 1 1.5 1 1 1 1 1 1 1 1.5 1 0.6 1 1 1 1 1 1.5 0.3 4--6 7--10 6--9 8--12 7--11 5--8 7--12 3--5.5 2--2.5 4--6 4--6 5--8 4--7 2--4 3--6 0.5--1 191 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs LSW RW LSL BOARD PAD PAD N C1 C2 LML SE L D E IS C C T O D N E TI VI N C U E ED S LMW CM PAD N + 1 LSW RW LSL C1 C2 5-3862(F).a Figure 104. Package Parasitics Package Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): 192 Indicates the minimum or maximum allowable size of a dimension. Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 144-Pin TQFP Dimensions are in millimeters. 22.00 0.20 SE L D E IS C C T O D N E TI VI N C U E ED S 20.00 0.20 PIN #1 IDENTIFIER ZONE 144 109 1 108 20.00 0.20 22.00 0.20 36 73 37 72 DETAIL A DETAIL B 1.40 0.05 1.60 MAX SEATING PLANE 0.08 0.05/0.15 0.50 TYP 1.00 REF 0.25 0.106/0.200 GAGE PLANE 0.19/0.27 SEATING PLANE 0.45/0.75 DETAIL A Lattice Semiconductor 0.08 M DETAIL B 193 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 208-Pin SQFP Dimensions are in millimeters. 30.60 0.20 28.00 0.20 SE L D E IS C C T O D N E TI VI N C U E ED S 1.30 REF PIN #1 IDENTIFIER ZONE 208 157 0.25 1 156 GAGE PLANE SEATING PLANE 0.50/0.75 DETAIL A 28.00 0.20 30.60 0.20 0.090/0.200 0.17/0.27 0.10 105 52 53 DETAIL B 104 DETAIL A M DETAIL B 3.40 0.20 4.10 MAX SEATING PLANE 0.08 0.50 TYP 0.25 MIN Note: The dimensions in this outline diagram are intended for informational purposes only. 194 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 208-Pin SQFP2 Dimensions are in millimeters. SE L D E IS C C T O D N E TI VI N C U E ED S 30.60 0.20 28.00 0.20 21.0 REF PIN #1 IDENTIFIER ZONE 208 1.30 REF 157 156 0.25 GAGE PLANE SEATING PLANE 21.0 REF 28.00 0.20 0.50/0.75 DETAIL A 30.60 0.20 0.090/0.200 0.17/0.2 105 53 0.10 M DETAIL B 104 EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.) DETAIL A DETAIL B 3.40 0.20 4.10 MAX SEATING PLANE 0.08 0.50 TYP 5-3828(F) 0.25 MIN CHIP BONDED FACE UP CHIP COPPER HEAT SINK DETAIL C (SQFP2 CHIP-UP) 5-3828(F).a Lattice Semiconductor 195 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 240-Pin SQFP Dimensions are in millimeters. SE L D E IS C C T O D N E TI VI N C U E ED S 34.60 0.20 32.00 0.20 1.30 REF PIN #1 IDENTIFIER ZONE 240 181 1 180 0.25 GAGE PLANE SEATING PLANE 0.50/0.75 DETAIL A 32.00 0.20 34.60 0.20 0.090/0.200 0.17/0.27 0.10 M DETAIL B 121 60 61 120 DETAIL A DETAIL B 3.40 0.20 4.10 MAX SEATING PLANE 0.08 0.50 TYP 0.25 MIN Note: The dimensions in this outline diagram are intended for informational purposes only. 196 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 240-Pin SQFP2 Dimensions are in millimeters. 34.60 0.20 32.00 0.20 SE L D E IS C C T O D N E TI VI N C U E ED S 24.2 REF 240 1.30 REF PIN #1 IDENTIFIER ZONE 181 1 180 0.25 GAGE PLANE SEATING PLANE 24.2 REF 0.50/0.75 DETAIL A 32.00 0.20 34.60 0.20 0.090/0.200 0.17/0.27 0.10 M DETAIL B 60 121 61 120 EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.) DETAIL B DETAIL A 3.40 0.20 4.10 MAX SEATING PLANE 0.08 0.50 TYP 0.25 MIN CHIP BONDED FACE UP CHIP COPPER HEAT SINK DETAIL C (SQFP2 CHIP-UP) 5-3825(F).a Lattice Semiconductor 197 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 256-Pin PBGA SE L D E IS C C T O D N E TI VI N C U E ED S Dimensions are in millimeters. 27.00 0.20 +0.70 24.00 -0.00 A1 BALL IDENTIFIER ZONE +0.70 24.00 -0.00 27.00 0.20 MOLD COMPOUND PWB 1.17 0.05 0.36 0.04 2.13 0.19 SEATING PLANE 0.20 SOLDER BALL 0.60 0.10 19 SPACES @ 1.27 = 24.13 CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL) (SEE NOTE BELOW) A1 BALL CORNER Y W V U T R P N M L K J H G F E D C B A 0.75 0.15 19 SPACES @ 1.27 = 24.13 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 5-4406(F) Note: Although the 16 thermal enhancement balls are stated as an option, they are standard on the 256 FPGA package. 198 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 352-Pin PBGA Dimensions are in millimeters. 35.00 0.20 SE L D E IS C C T O D N E TI VI N C U E ED S +0.70 30.00 -0.00 A1 BALL IDENTIFIER ZONE 30.00 +0.70 -0.00 35.00 0.20 MOLD COMPOUND PWB 1.17 0.05 0.56 0.06 2.33 0.21 SEATING PLANE 0.20 0.60 0.10 SOLDER BALL 25 SPACES @ 1.27 = 31.75 CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL) (SEE NOTE BELOW) A1 BALL CORNER AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 0.75 0.15 25 SPACES @ 1.27 = 31.75 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25 5-4407(F) Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package. Lattice Semiconductor 199 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 432-Pin EBGA Dimensions are in millimeters. 40.00 0.10 SE L D E IS C C T O D N E TI VI N C U E ED S A1 BALL IDENTIFIER ZONE 40.00 0.10 0.91 0.06 1.54 0.13 SEATING PLANE 0.20 SOLDER BALL 0.63 0.07 30 SPACES @ 1.27 = 38.10 AL AK AJ AH AG AF AD AB Y AE 0.75 0.15 AC AA W V U T P M K H F 30 SPACES @ 1.27 = 38.10 R N L J G E D C B A A1 BALL CORNER 1 3 2 5 4 7 6 9 8 11 10 12 13 15 17 19 21 23 25 27 29 31 14 16 18 20 22 24 26 28 30 5-4409(F) 200 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Ordering Information OR3XXXX X XX XXX X XX Packing Designator DB = Dry Packed Tray Device Family OR3T20 OR3T30 OR3T55 OR3C80 OR3T80 OR3T125 SE L D E IS C C T O D N E TI VI N C U E ED S Grade Blank = Commercial I = Industrial Pin/Ball Count Speed Grade Package Type BA = Plastic Ball Grid Array (PBGA) BC = Enhanced Ball Grid Array (EBGA) PS = Power Quad Shrink Flat Package (SQFP2) S = Shrink Quad Flat Package (SQFP) T = Thin Quad Flat Package (TQFP) Table 79. Ordering Information Commercial Device Family OR3C80 OR3T20 OR3T30 Part Number OR3C805PS208-DB2 OR3C805BA352-DB2 OR3C804PS208-DB2 OR3C804BA352-DB2 OR3T207S208-DB OR3T207BA256-DB OR3T206S208-DB OR3T206T144-DB OR3T206BA256-DB OR3T307S208-DB OR3T307S240-DB OR3T307BA256-DB OR3T306S208-DB OR3T306S240-DB OR3T306BA256-DB Lattice Semiconductor Speed Grade Package Type Pin/Ball Count Grade Packing Designator 5 5 4 4 7 7 6 6 6 7 7 7 6 6 6 SQFP2 PBGA SQFP2 PBGA SQFP PBGA SQFP TQFP PBGA SQFP SQFP PBGA SQFP SQFP PBGA 208 352 208 352 208 256 208 144 256 208 240 256 208 240 256 C C C C C C C C C C C C C C C DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 201 Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Commercial Device Family OR3T557PS208-DB1 OR3T557S208-DB OR3T557PS240-DB3 OR3T557BA256-DB OR3T557BA352-DB OR3T556PS208-DB1 OR3T556S208-DB OR3T556PS240-DB3 OR3T556BA256-DB OR3T556BA352-DB OR3T807PS208-DB1 OR3T807S208-DB OR3T807PS240-DB3 OR3T807BA352-DB OR3T807BC432-DB OR3T806PS208-DB1 OR3T806S208-DB OR3T806PS240-DB3 OR3T806BA352-DB OR3T806BC432-DB OR3T1257PS208-DB3 OR3T1257PS240-DB3 OR3T1257BA352-DB OR3T1257BC432-DB OR3T1256PS208-DB3 OR3T1256PS240-DB3 OR3T1256BA352-DB OR3T1256BC432-DB Speed Grade Package Type Pin/Ball Count Grade Packing Designator 7 7 7 7 7 6 6 6 6 6 7 7 7 7 7 6 6 6 6 6 7 7 7 7 6 6 6 6 SQFP2 SQFP SQFP2 PBGA PBGA SQFP2 SQFP SQFP2 PBGA PBGA SQFP2 SQFP SQFP2 PBGA EBGA SQFP2 SQFP SQFP2 PBGA EBGA SQFP2 SQFP2 PBGA EBGA SQFP2 SQFP2 PBGA EBGA 208 208 240 256 352 208 208 240 256 352 208 208 240 352 432 208 208 240 352 432 208 240 352 432 208 240 352 432 C C C C C C C C C C C C C C C C C C C C C C C C C C C C DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB SE L D E IS C C T O D N E TI VI N C U E ED S OR3T55 Part Number OR3T80 OR3T125 202 Lattice Semiconductor Data Sheet November 2006 ORCA Series 3C and 3T FPGAs Industrial Device Family OR3C80 OR3C804PS208I-DB2 OR3C804BA352I-DB2 OR3T206S208I-DB OR3T306S208I-DB OR3T306S240I-DB OR3T306BA256I-DB OR3T556PS208I-DB1 OR3T556S208I-DB OR3T556PS240I-DB3 OR3T556BA256I-DB OR3T556BA352I-DB OR3T806PS208I-DB1 OR3T806S208I-DB OR3T806PS240I-DB3 OR3T806BA352I-DB OR3T806BC432I-DB OR3T1256PS208I-DB3 OR3T1256PS240I-DB3 OR3T1256BA352I-DB OR3T1256BC432I-DB Speed Grade Package Type Pin/Ball Count Grade Packing Designator 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 SQFP2 PBGA SQFP SQFP SQFP PBGA SQFP2 SQFP SQFP2 PBGA PBGA SQFP2 SQFP SQFP2 PBGA EBGA SQFP2 SQFP2 PBGA EBGA 208 352 208 208 240 256 208 208 240 256 352 208 208 240 352 432 208 240 352 432 I I I I I I I I I I I I I I I I I I I I DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB SE L D E IS C C T O D N E TI VI N C U E ED S OR3T20 OR3T30 Part Number OR3T55 OR3T80 OR3T125 1. Converted to S208 package device per PCN#11A-06. 2. Discontinued per PCN#02-06. Contact Rochester Electronics for available inventory. 2. Discontinued per PCN#06-07. Contact Rochester Electronics for available inventory. Lattice Semiconductor 203