Hitachi Single-Chip Microcomputer
H8/338 Series
H8/338
HD6473388, HD6433388, HD6413388
H8/337
HD6473378, HD6433378, HD6413378
H8/336
HD6433368
Hardware Manual
OMC 942723036
Preface
The H8/338 Series is a series of high-performance single-chip microcomputers having a fast
H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control.
These include ROM, RAM, three types of timers, a serial communication interface, an A/D
converter, a D/A converter, I/O ports, and other functions needed in control system configurations,
so that compact, high-performance systems can be realized easily. The H8/338 Series includes
three chips: the H8/338 with 48K-byte ROM and 2K-byte RAM; the H8/337 with 32K-byte ROM
and 1K-byte RAM; and the H8/336 with 24K-byte ROM and 1K-byte RAM.
The H8/338 and H8/337 are available in a masked ROM version, a ZTAT™*(Zero Turn-Around
Time) version, and a ROMless version, providing a quick and flexible response to conditions from
ramp-up through full-scale volume producion, even for applications with frequently-changing
specifications.
This manual describes the hardware of the H8/338 Series. Refer to the
H8/300 Series
Programming Manual for a detailed description of the instruction set.
Note: ZTAT is a registered trademark of Hitachi, Ltd.
Contents
Section 1. Overview............................................................................................................... 1
1.1 Overview............................................................................................................................... 1
1.2 Block Diagram...................................................................................................................... 5
1.3 Pin Assignments and Functions............................................................................................ 6
1.3.1 Pin Arrangement...................................................................................................... 6
1.3.2 Pin Functions........................................................................................................... 9
Section 2. MCU Operating Modes and Address Space................................................ 17
2.1 Overview............................................................................................................................... 17
2.1.1 Mode Selection........................................................................................................ 17
2.1.2 Mode and System Control Registers (MDCR and SYSCR) ................................... 18
2.2 System Control Register (SYSCR)—H'FFC4...................................................................... 18
2.3 Mode Control Register (MDCR)—H'FFC5 ......................................................................... 20
2.4 Address Space Map .............................................................................................................. 21
Section 3. CPU........................................................................................................................ 25
3.1 Overview............................................................................................................................... 25
3.1.1 Features.................................................................................................................... 25
3.2 Register Configuration.......................................................................................................... 26
3.2.1 General Registers..................................................................................................... 26
3.2.2 Control Registers..................................................................................................... 27
3.2.3 Initial Register Values.............................................................................................. 28
3.3 Addressing Modes ................................................................................................................ 29
3.3.1 Addressing Modes................................................................................................... 29
3.3.2 How to Calculate Where the Excution Starts.......................................................... 30
3.4 Data Formats......................................................................................................................... 34
3.4.1 Data Formats in General Registers.......................................................................... 35
3.4.2 Memory Data Formats............................................................................................. 36
3.5 Instruction Set....................................................................................................................... 37
3.5.1 Data Transfer Instructions ....................................................................................... 39
3.5.2 Arithmetic Operations ............................................................................................. 41
3.5.3 Logic Operations ..................................................................................................... 42
3.5.4 Shift Operations....................................................................................................... 42
3.5.5 Bit Manipulations.................................................................................................... 44
3.5.6 Branching Instructions............................................................................................. 48
3.5.7 System Control Instructions .................................................................................... 50
3.5.8 Block Data Transfer Instruction .............................................................................. 51
i
3.6 CPU States............................................................................................................................ 52
3.6.1 Program Execution State......................................................................................... 53
3.6.2 Exception-Handling State........................................................................................ 53
3.6.3 Power-Down State................................................................................................... 54
3.7 Access Timing and Bus Cycle.............................................................................................. 54
3.7.1 Access to On-Chip Memory (RAM and ROM) ...................................................... 54
3.7.2 Access to On-Chip Register Field and External Devices........................................ 56
Section 4. Exception Handling............................................................................................ 59
4.1 Overview............................................................................................................................... 59
4.2 Reset ..................................................................................................................................... 59
4.2.1 Overview ................................................................................................................. 59
4.2.2 Reset Sequence........................................................................................................ 59
4.2.3 Disabling of Interrupts after Reset........................................................................... 62
4.3 Interrupts............................................................................................................................... 62
4.3.1 Overview ................................................................................................................. 62
4.3.2 Interrupt-Related Registers...................................................................................... 64
4.3.3 External Interrupts................................................................................................... 66
4.3.4 Internal Interrupts.................................................................................................... 66
4.3.5 Interrupt Handling ................................................................................................... 67
4.3.6 Interrupt Response Time.......................................................................................... 72
4.3.7 Precaution................................................................................................................ 72
4.4 Note on Stack Handling........................................................................................................ 73
Section 5. I/O Ports................................................................................................................ 75
5.1 Overview............................................................................................................................... 75
5.2 Port 1..................................................................................................................................... 78
5.3 Port 2..................................................................................................................................... 81
5.4 Port 3..................................................................................................................................... 85
5.5 Port 4..................................................................................................................................... 89
5.6 Port 5..................................................................................................................................... 93
5.7 Port 6..................................................................................................................................... 98
5.8 Port 7.....................................................................................................................................104
5.9 Port 8.....................................................................................................................................106
5.10 Port 9.....................................................................................................................................113
Section 6. 16-Bit Free-Running Timer..............................................................................121
6.1 Overview...............................................................................................................................121
6.1.1 Features....................................................................................................................121
ii
6.1.2 Block Diagram.........................................................................................................122
6.1.3 Input and Output Pins..............................................................................................123
6.1.4 Register Configuration ............................................................................................123
6.2 Register Descriptions............................................................................................................124
6.2.1 Free-Running Counter (FRC)—H'FF92..................................................................124
6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94.......................125
6.2.3 Input Capture Registers A to D (ICRA to ICRD)—
H'FF98, H'FF9A, H'FF9C, H'FF9E.........................................................................125
6.2.4 Timer Interrupt Enable Register (TIER)—H'FF90 .................................................128
6.2.5 Timer Control/Status Register (TCSR)—H'FF91 ...................................................130
6.2.6 Timer Control Register (TCR)—H'FF96 ................................................................133
6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97..................................135
6.3 CPU Interface .......................................................................................................................136
6.4 Operation ..............................................................................................................................138
6.4.1 FRC Incrementation Timing....................................................................................138
6.4.2 Output Compare Timing..........................................................................................140
6.4.3 Input Capture Timing ..............................................................................................141
6.4.4 Setting of FRC Overflow Flag (OVF).....................................................................144
6.5 Interrupts...............................................................................................................................145
6.6 Sample Application...............................................................................................................145
6.7 Application Notes.................................................................................................................146
Section 7. 8-Bit Timers .........................................................................................................151
7.1 Overview...............................................................................................................................151
7.1.1 Features....................................................................................................................151
7.1.2 Block Diagram.........................................................................................................151
7.1.3 Input and Output Pins..............................................................................................152
7.1.4 Register Configuration ............................................................................................153
7.2 Register Descriptions............................................................................................................153
7.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1)...............................153
7.2.2 Time Constant Registers A and B (TCORA and TCORB)—
H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1)..............................154
7.2.3 Timer Control Register (TCR)—H'FFC8 (TMR0), H'FFD0 (TMR1) ....................154
7.2.4 Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1).......157
7.2.5 Serial/Timer Control Register (STCR)—H'FFC3...................................................159
7.3 Operation ..............................................................................................................................160
7.3.1 TCNT Incrementation Timing.................................................................................160
7.3.2 Compare Match Timing...........................................................................................161
iii
7.3.3 External Reset of TCNT..........................................................................................163
7.3.4 Setting of TCSR Overflow Flag (OVF) ..................................................................164
7.4 Interrupts...............................................................................................................................165
7.5 Sample Application...............................................................................................................165
7.6 Application Notes.................................................................................................................166
Section 8. PWM Timers........................................................................................................171
8.1 Overview...............................................................................................................................171
8.1.1 Features....................................................................................................................171
8.1.2 Block Diagram.........................................................................................................171
8.1.3 Input and Output Pins..............................................................................................172
8.1.4 Register Configuration ............................................................................................172
8.2 Register Descriptions............................................................................................................172
8.2.1 Timer Counter (TCNT)—H'FFA2 (PWM0), H'FFA6 (PWM1)..............................172
8.2.2 Duty Register (DTR)—H'FFA1 (PWM0), H'FFA5 (PWM1) .................................173
8.2.3 Timer Control Register (TCR)—H'FFA0 (PWM0), H'FFA4 (PWM1)...................173
8.3 Operation ..............................................................................................................................175
8.3.1 Timer Incrementation ..............................................................................................175
8.3.2 PWM Operation.......................................................................................................176
8.4 Application Notes.................................................................................................................177
Section 9. Serial Communication Interface.....................................................................179
9.1 Overview...............................................................................................................................179
9.1.1 Features....................................................................................................................179
9.1.2 Block Diagram.........................................................................................................180
9.1.3 Input and Output Pins..............................................................................................180
9.1.4 Register Configuration ............................................................................................181
9.2 Register Descriptions............................................................................................................182
9.2.1 Receive Shift Register (RSR)..................................................................................182
9.2.2 Receive Data Register (RDR)—H'FFDD, H'FF8D.................................................182
9.2.3 Transmit Shift Register (TSR).................................................................................182
9.2.4 Transmit Data Register (TDR)—H'FFDB, H'FF8B................................................183
9.2.5 Serial Mode Register (SMR)—H'FFD8, H'FF88....................................................183
9.2.6 Serial Control Register (SCR)—H'FFDA, H'FF8A ................................................186
9.2.7 Serial Status Register (SSR)—H'FFDC, H'FF8C....................................................189
9.2.8 Bit Rate Register (BRR)—H'FFD9, H'FF89...........................................................192
9.2.9 Serial/Timer Control Register (STCR)—H'FFC3...................................................196
9.3 Operation ..............................................................................................................................197
iv
9.3.1 Overview .................................................................................................................197
9.3.2 Asynchronous Mode................................................................................................199
9.3.3 Synchronous Mode..................................................................................................212
9.4 Interrupts...............................................................................................................................221
9.5 Application Notes.................................................................................................................221
Section 10. A/D Converter.....................................................................................................225
10.1 Overview...............................................................................................................................225
10.1.1 Features....................................................................................................................225
10.1.2 Block Diagram.........................................................................................................226
10.1.3 Input Pins.................................................................................................................227
10.1.4 Register Configuration ............................................................................................227
10.2 Register Descriptions............................................................................................................228
10.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE6.................................................228
10.2.2 A/D Control/Status Register (ADCSR)—H'FFE8 ..................................................228
10.2.3 A/D Control Register (ADCR)—H'FFEA...............................................................231
10.3 Operation ..............................................................................................................................232
10.3.1 Single Mode (SCAN = 0)........................................................................................232
10.3.2 Scan Mode (SCAN = 1) ..........................................................................................235
10.3.3 Input Sampling Time and A/D Conversion Time....................................................238
10.3.4 External Trigger Input Timing.................................................................................239
10.4 Interrupts...............................................................................................................................240
Section 11. D/A Converter.....................................................................................................241
11.1 Overview...............................................................................................................................241
11.1.1 Features....................................................................................................................241
11.1.2 Block Diagram.........................................................................................................241
11.1.3 Input and Output Pins..............................................................................................242
11.1.4 Register Configuration ............................................................................................242
11.2 Register Descriptions............................................................................................................243
11.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) H'FFA8, H'FFA9 ........................243
11.2.2 D/A Control Register (DACR) H'FFAA .................................................................243
11.3 Operation ..............................................................................................................................245
Section 12. RAM.......................................................................................................................247
12.1 Overview...............................................................................................................................247
12.2 Block Diagram......................................................................................................................247
12.3 RAM Enable Bit (RAME) in System Control Register (SYSCR) .......................................248
v
12.4 Operation ..............................................................................................................................248
12.4.1 Expanded Modes (Modes 1 and 2)..........................................................................248
12.4.2 Single-Chip Mode (Mode 3) ...................................................................................248
Section 13. ROM.......................................................................................................................249
13.1 Overview...............................................................................................................................249
13.1.1 Block Diagram.........................................................................................................250
13.2 PROM Mode (H8/338, H8/337)...........................................................................................250
13.2.1 PROM Mode Setup .................................................................................................250
13.2.2 Socket Adapter Pin Assignments and Memory Map...............................................251
13.3 Programming ........................................................................................................................254
13.3.1 Writing and Verifying..............................................................................................254
13.3.2 Notes on Writing......................................................................................................258
13.3.3 Reliability of Written Data ......................................................................................258
13.3.4 Erasing of Data........................................................................................................259
13.4 Handling of Windowed Packages.........................................................................................260
Section 14. Power-Down State..............................................................................................261
14.1 Overview...............................................................................................................................261
14.2 System Control Register: Power-Down Control Bits...........................................................262
14.3 Sleep Mode...........................................................................................................................264
14.3.1 Transition to Sleep Mode.........................................................................................264
14.3.2 Exit from Sleep Mode .............................................................................................264
14.4 Software Standby Mode........................................................................................................265
14.4.1 Transition to Software Standby Mode.....................................................................265
14.4.2 Exit from Software Standby Mode..........................................................................265
14.4.3 Sample Application of Software Standby Mode.....................................................266
14.4.4 Application Note .....................................................................................................266
14.5 Hardware Standby Mode......................................................................................................267
14.5.1 Transition to Hardware Standby Mode....................................................................267
14.5.2 Recovery from Hardware Standby Mode................................................................267
14.5.3 Timing Relationships...............................................................................................268
Section 15. Clock Pulse Generator.......................................................................................269
15.1 Overview...............................................................................................................................269
15.1.1 Block Diagram.........................................................................................................269
15.2 Oscillator Circuit...................................................................................................................269
15.3 System Clock Divider...........................................................................................................272
vi
Section 16. Electrical Specifications....................................................................................273
16.1 Absolute Maximum Ratings.................................................................................................273
16.2 Electrical Characteristics ......................................................................................................273
16.2.1 DC Characteristics...................................................................................................273
16.2.2 AC Characteristics...................................................................................................279
16.2.3 A/D Converter Characteristics.................................................................................283
16.2.4 D/A Converter Characteristics.................................................................................284
16.3 MCU Operational Timing.....................................................................................................284
16.3.1 Bus Timing ..............................................................................................................285
16.3.2 Control Signal Timing.............................................................................................286
16.3.3 16-Bit Free-Running Timer Timing ........................................................................289
16.3.4 8-Bit Timer Timing..................................................................................................290
16.3.5 Pulse Width Modulation Timer Timing...................................................................291
16.3.6 Serial Communication Interface Timing .................................................................291
16.3.7 I/O Port Timing........................................................................................................292
Appendices
Appendix A. CPU Instruction Set......................................................................................293
A.1 Instruction Set List................................................................................................................293
A.2 Operation Code Map.............................................................................................................300
A.3 Number of States Required for Execution............................................................................302
Appendix B. Register Field.................................................................................................308
B.1 Register Addresses and Bit Names.......................................................................................308
B.2 Register Descriptions............................................................................................................312
Appendix C. Pin States.........................................................................................................351
C.1 Pin States in Each Mode.......................................................................................................351
Appendix D. Timing of Transition to and Recovery from Hardware
Standby Mode................................................................................................353
Appendix E. Package Dimensions ....................................................................................354
vii
Section 1. Overview
1.1 Overview
The H8/338 Series of single-chip microcomputers features an H8/300 CPU core and a complement
of on-chip supporting modules implementing a variety of system functions.
The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-
manipulation instructions, ideally suited for realtime control applications. The on-chip supporting
modules implement peripheral functions needed in system configurations. These include ROM,
RAM, three types of timers (16-bit free-running timer, 8-bit timers, pulse-width modulation timers),
a serial communication interface (SCI), an A/D converter, a D/A converter, and I/O ports.
The H8/338 Series can operate in a single-chip mode or in two expanded modes, depending on the
requirements of the application. (The operating mode will be referred to as the MCU mode in this
manual.)
The entire H8/338 Series is available with masked ROM. The H8/338 and H8/337 are also
available in ZTAT™ versions* that can be programmed at the user site, and in ROMless versions.
Note: ZTAT is a registered trademark of Hitachi, Ltd.
Table 1-1 lists the features of the H8/338 Series.
1
Table 1-1. Features
Item Specification
CPU Two-way general register configuration
• Eight 16-bit registers, or
• Sixteen 8-bit registers
High-speed operation
• Maximum clock rate: 10MHz
• Add/subtract: 0.2µs
• Multiply/divide: 1.4µs
Streamlined, concise instruction set
• Instruction length: 2 or 4 bytes
• Register-register arithmetic and logic operations
• MOV instruction for data transfer between registers and memory
Instruction set features
• Multiply instruction (8 bits
×8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
Memory • H8/338: 48k-byte ROM; 2k-byte RAM
• H8/337: 32k-byte ROM; 1k-byte RAM
• H8/336: 24k-byte ROM; 1k-byte RAM
16-bit free- • One 16-bit free-running counter (can also count external events)
running timer • Two output-compare lines
(1 channel) • Four input capture lines (can be buffered)
8-bit timer Each channel has
(2 channels) • One 8-bit up-counter (can also count external events)
• Two time constant registers
PWM timer • Duty cycle can be set from 0 to 100%
(2 channels) • Resolution: 1/250
Serial • Asynchronous or clocked synchronous mode (selectable)
communication • Full duplex: can transmit and receive simultaneously
interface (SCI) • On-chip baud rate generator
(2 channels)
2
Table 1-1. Features (cont.)
Item Specification
A/D converter • 8-bit resolution
• Eight channels: single or scan mode (selectable)
• Start of A/D conversion can be externally triggered
• Sample-and-hold function
D/A converter • 8-bit resolution
• Two channels
I/O ports • 58 input/output lines (16 of which can drive LEDs)
• 8 input-only lines
Interrupts • Nine external interrupt lines: NMI, IRQ0to IRQ7
• 22 on-chip interrupt sources
Operating • Expanded mode with on-chip ROM disabled (mode 1)
modes • Expanded mode with on-chip ROM enabled (mode 2)
• Single-chip mode (mode 3)
Power-down • Sleep mode
modes • Software standby mode
• Hardware standby mode
Other features • On-chip oscillator
3
Table 1-1. Features (cont.)
Item Specification
Series lineup
5-V version 3-V version Package ROM
HD6473388CG HD6473388VCG 84-pin windowed LCC (CG-84) PROM
HD6473388CP HD6473388VCP 84-pin PLCC (CP-84)
HD6473388F HD6473388VF 80-pin QFP (FP-80A)
HD6433388CP HD6433388VCP 84-pin PLCC (CP-84) Masked ROM
HD6433388F HD6433388VF 80-pin QFP (FP-80A)
HD6413388CP HD6413388VCP 84-pin PLCC (CP-84) ROMless
HD6413388F HD6413388VF 80-pin QFP (FP-80A)
HD6473378CG HD6473378VCG 84-pin windowed LCC (CG-84) PROM
HD6473378CP HD6473378VCP 84-pin PLCC (CP-84)
HD6473378F HD6473378VF 80-pin QFP (FP-80A)
HD6433378CP HD6433378VCP 84-pin PLCC (CP-84) Masked ROM
HD6433378F HD6433378VF 80-pin QFP (FP-80A)
HD6413378CP HD6413378VCP 84-pin PLCC (CP-84) ROMless
HD6413378F HD6413378VF 80-pin QFP (FP-80A)
HD6433368CP HD6433368VCP 84-pin PLCC (CP-84) Masked ROM
HD6433368F HD6433368VF 80-pin QFP (FP-80A)
4
1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/338 Series.
Figure 1-1. Block Diagram
Clock
pulse
gener-
ator
Port 4 Port 7 Port 5
Port 8 Port 3 Port 9
Port 6 Port 2 Port 1
CPU
H8/300
RAM
16-bit free-
running timer
PROM
(or masked ROM)
Serial
communication
(2 channels)
8-bit A/D converter
(8 channels)
8-bit D/A converter
(2 channels)
8-bit timer
(2 channels)
PWM timer
(2 channels)
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77 /AN7/DA1
AVCC
AVSS
P60/FTCI
P61/FTOA
P62/FTIA
P63/FTIB
P64/FTIC
P65/FTID
P66/FTOB/IRQ6
P67/IRQ7
P52/SCK0
P51/RxD0
P50/TxD0
P86/SCK1/IRQ5
P85/RxD1/IRQ4
P84/TxD1/IRQ3
P83
P82
P81
P80
P37/D7
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
P40/TMCI0
P41/TMO0
P42/TMRI0
P43/TMCI1
P44/TMO1
P45/TMRI1
P46/PW0
P47/PW1
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
RES
MD0
MD1
VCC
STBY
NMI
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
XTAL
EXTAL
P97/WAIT
P96/Ø
P95/AS
P94/WR
P93/RD
P92/IRQ0
P91/IRQ1
0/ADTRG
P9 /IRQ2
*1
*2
Notes: *
*
Memory Sizes
H8/338
48k bytes
2k bytes
H8/337
32k bytes
1k byte
H8/336
24k bytes
1k byte
ROM
RAM
1 CP-84 and CG-84 only.
2 PROM is available in the H8/338 and H8/337 only.
Data bus (Low)
Data bus (High)
Address bus
5
1.3 Pin Assignments and Functions
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the CG-84 package. Figure 1-3 shows the pin
arrangement of the CP-84 package. Figure 1-4 shows the pin arrangement of the FP-80A package.
Figure 1-2. Pin Arrangement (CG-84, Top View)
H161 H8/337 H.M '91
Fig. 1-2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
11
33
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
VCC
P52/SCK0
P51/RxD0
P50/TxD0
VSS
VSS
P97/WAIT
P96/Ø
P95/AS
P94/WR
P93/RD
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P14/A4
P15/A5
P16/A6
P17/A7
VSS
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
VSS
P26/A14
P27/A15
VCC
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0
P86/SCK1/IRQ5
P85/RxD1/IRQ4
P84/TxD1/IRQ3
P83
P82
P81
P80
VSS
P37/D7
VSS
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
P10/A0
P11/A1
P12/A2
P13/A3
P60/FTCI
P61/FTOA
P62/FTIA
P63/FTIB
P64/FTIC
P65/FTID
P66/FTOB/IRQ6
P67/IRQ7
VSS
AVCC
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P40/TMCI0
P41/TMO0
10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
P25/A13
6
Figure 1-3. Pin Arrangement (CP-84, Top View)
H161 H8/337 H.M '91
Fig. 1-3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
11
33
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
VCC
P52/SCK0
P51/RxD0
P50/TxD0
VSS
VSS
P97/WAIT
P96/Ø
P95/AS
P94/WR
P93/RD
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P14/A4
P15/A5
P16/A6
P17/A7
VSS
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
VSS
P26/A14
P27/A15
VCC
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0
P86/SCK1/IRQ5
P85/RxD1/IRQ4
P84/TxD1/IRQ3
P83
P82
P81
P80
VSS
P37/D7
VSS
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
P10/A0
P11/A1
P12/A2
P13/A3
P60/FTCI
P61/FTOA
P62/FTIA
P63/FTIB
P64/FTIC
P65/FTID
P66/FTOB/IRQ6
P67/IRQ7
VSS
AVCC
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P40/TMCI0
P41/TMO0
10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
7
Figure 1-4. Pin Arrangement (FP-80A, Top View)
H161 H8/337 H.M '91
Fig. 1-4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
VCC
P52/SCK0
P51/RxD0
P50/TxD0
VSS
P97/WAIT
P96/Ø
P95/AS
P94/WR
P93/RD
P92/IRQ0
P91/IRQ1
P9 /ADTRG/IRQ0 2
P14/A4
P15/A5
P16/A6
P17/A7
VSS
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
VCC
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0
P86/SCK1/IRQ5
P85/RxD1/IRQ4
P84/TxD1/IRQ3
P83
P82
P81
P80
VSS
P37/D7
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
P10/A0
P11/A1
P12/A2
P13/A3
P60/FTCI
P61/FTOA
P62/FTIA
P63/FTIB
P64/FTIC
P65/FTID
P66/FTOB/IRQ6
P67/IRQ7
AVCC
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P40/TMCI0
P41/TMO0
8
1.3.2 Pin Functions
(1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the
FP-80A, CP-84, and CG-84 packages in each operating mode.
Table 1-2. Pin Assignments in Each Operating Mode (1)
Pin No. Expanded modes Single-chip mode
CP-84 FP- PROM
CG-84 80A Mode 1 Mode 2 Mode 3 mode
1 71 D6D6P36EO6
2 — VSS VSS VSS VSS
3 72 D7D7P37EO7
4 73 VSS VSS VSS VSS
5 74 P80P80P80NC
6 75 P81P81P81NC
7 76 P82P82P82NC
8 77 P83P83P83NC
9 78 P84 / TxD1/IRQ3P84 / TxD1/IRQ3P84 / TxD1/IRQ3NC
10 79 P85 / RxD1/IRQ4P85 / RxD1/IRQ4P85 / RxD1/IRQ4NC
11 80 P86 / SCK1/IRQ5P86 / SCK1/IRQ5P86 / SCK1/IRQ5NC
12 1 RES RES RES VPP
13 2 XTAL XTAL XTAL NC
14 3 EXTAL EXTAL EXTAL NC
15 4 MD1MD1MD1VSS
16 5 MD0MD0MD0VSS
17 6 NMI NMI NMI EA9
18 7 STBY STBY STBY VSS
19 8 VCC VCC VCC VCC
20 9 P52/ SCK0P52/ SCK0P52/ SCK0NC
21 10 P51/ RxD0P51/ RxD0P51/ RxD0NC
22 11 P50/ TxD0P50/ TxD0P50/ TxD0NC
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 14.2, “PROM Mode.”
9
Table 1-2. Pin Assignments in Each Operating Mode (2)
Pin No. Expanded modes Single-chip mode
CP-84 FP- PROM
CG-84 80A Mode 1 Mode 2 Mode 3 mode
23 12 VSS VSS VSS VSS
24 — VSS VSS VSS VSS
25 13 WAIT WAIT P97NC
26 14 Ø Ø P96/ Ø NC
27 15 AS AS P95NC
28 16 WR WR P94NC
29 17 RD RD P93NC
30 18 P92 / IRQ0P92 / IRQ0P92 / IRQ0PGM
31 19 P91/ IRQ1P91/ IRQ1P91/ IRQ1EA15
32 20 P90/ ADTRG / IRQ2P90/ ADTRG / IRQ2P90/ ADTRG / IRQ2EA16
33 21 P60/ FTCI P60/ FTCI P60/ FTCI NC
34 22 P61/ FTOA P61/ FTOA P61/ FTOA NC
35 23 P62/ FTIA P62/ FTIA P62/ FTIA NC
36 24 P63/ FTIB P63/ FTIB P63/ FTIB VCC
37 25 P64/ FTIC P64/ FTIC P64/ FTIC VCC
38 26 P65/ FTID P65/ FTID P65/ FTID NC
39 27 P66/ FTOB /IRQ6P66/ FTOB /IRQ6P66/ FTOB /IRQ6NC
40 28 P67/IRQ7P67/IRQ7P67/IRQ7NC
41 — VSS VSS VSS VSS
42 29 AVCC AVCC AVCC VCC
43 30 P70/ AN0P70/ AN0P70/ AN0NC
44 31 P71/ AN1P71/ AN1P71/ AN1NC
45 32 P72/ AN2P72/ AN2P72/ AN2NC
46 33 P73/ AN3P73/ AN3P73/ AN3NC
47 34 P74/ AN4P74/ AN4P74/ AN4NC
48 35 P75/ AN5P75/ AN5P75/ AN5NC
49 36 P76/ AN6/DA0P76/ AN6/DA0P76/ AN6/DA0NC
50 37 P77/ AN7/DA1P77/ AN7/DA1P77/ AN7/DA1NC
51 38 AVSS AVSS AVSS VSS
52 39 P40/ TMCI0P40/ TMCI0P40/ TMCI0NC
53 40 P41/ TMO0P41/ TMO0P41/ TMO0NC
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 14.2, “PROM Mode.”
10
Table 1-2. Pin Assignments in Each Operating Mode (3)
Pin No. Expanded modes Single-chip mode
CP-84 FP- PROM
CG-84 80A Mode 1 Mode 2 Mode 3 mode
54 41 P42/ TMRI0P42/ TMRI0P42/ TMRI0NC
55 42 P43/ TMCI1P43/ TMCI1P43/ TMCI1NC
56 43 P44/ TMO1P44/ TMO1P44/ TMO1NC
57 44 P45/ TMRI1P45/ TMRI1P45/ TMRI1NC
58 45 P46/ PW0P46/ PW0P46/ PW0NC
59 46 P47/ PW1P47/ PW1P47/ PW1NC
60 47 VCC VCC VCC VCC
61 48 A15 P27/ A15 P27CE
62 49 A14 P26/ A14 P26EA14
63 50 A13 P25/ A13 P25EA13
64 — VSS VSS VSS VSS
65 51 A12 P24/ A12 P24EA12
66 52 A11 P23/ A11 P23EA11
67 53 A10 P22/ A10 P22EA10
68 54 A9P21/ A9P21OE
69 55 A8P20/ A8P20EA8
70 56 VSS VSS VSS VSS
71 57 A7P17/ A7P17EA7
72 58 A6P16/ A6P16EA6
73 59 A5P15/ A5P15EA5
74 60 A4P14/ A4P14EA4
75 61 A3P13/ A3P13EA3
76 62 A2P12/ A2P12EA2
77 63 A1P11/ A1P11EA1
78 64 A0P10/ A0P10EA0
79 65 D0D0P30EO0
80 66 D1D1P31EO1
81 67 D2D2P32EO2
82 68 D3D3P33EO3
83 69 D4D4P34EO4
84 70 D5D5P35EO5
Note: Pins marked NC should be left unconnected.
For details on PROM mode, refer to 14.2, “PROM Mode.”
11
(2) Pin Functions: Table 1-3 gives a concise description of the function of each pin.
Table 1-3. Pin Functions (1)
Pin No.
CG-84
Type Symbol CP-84 FP-80A I/O Name and function
Power VCC 19, 60 8, 47 I Power: Connected to the power supply (+5V).
Connect both VCC pins to the system power
supply (+5V).
VSS 2, 4, 23, 12, 56, I Ground: Connected to ground (0V). Connect
24, 41, 73 all VSS pins to the system power supply (0V).
64, 70
Clock XTAL 13 2 I Crystal: Connected to a crystal oscillator. The
crystal frequency should be double the desired
system clock frequency. If an external clock is
input at the EXTAL pin, a reverse-phase clock
should be input at the XTAL pin.
EXTAL 14 3 I External crystal: Connected to a crystal
oscillator or external clock. The frequency of the
external clock should be double the desired
system clock frequency. See section 15.2,
“Oscillator Circuit,” for examples of connections
to a crystal and external clock.
Ø 26 14 O System clock: Supplies the system clock to
peripheral devices.
System
RES
12 1 I Reset: A Low input causes the chip to reset.
control
STBY
18 7 I Standby: A transition to the hardware standby
mode (a power-down state) occurs when a Low
input is received at the
STBY
pin.
Address A15 to A061 to 63, 48 to 55, O Addres.s bus: Address output pins.
bus 65 to 69, 57 to 64
71 to 78
Data bus D7to D03, 1, 72 to 65 I/O Data bus: 8-Bit bidirectional data bus.
84 to 79
12
Table 1-3. Pin Functions (2)
Pin No.
CG-84
Type Symbol CP-84 FP-80A I/O Name and function
Bus
WAIT
25 13 I Wait: Requests the CPU to insert TWstates into
control the bus cycle when an external address is
accessed.
RD
29 17 O Read: Goes Low to indicate that the CPU is
reading an external address.
WR
28 16 O Write: Goes Low to indicate that the CPU is
writing to an external address.
AS
27 15 O Address Strobe: Goes Low to indicate that
there is a valid address on the address bus.
Interrupt
NMI
17 6 I NonMaskable Interrupt: Highest-priority
signals interrupt request. The NMIEG bit in the system
control register determines whether the interrupt
is requested on the rising or falling edge of the
NMI input.
IRQ0to 30 to 32, 18 to 20, I Interrupt Request 0 to 7: Maskable interrupt
IRQ79 to 11, 78 to 80, request pins.
39, 40 27, 28
Operating MD1, 15 4 I Mode: Input pins for setting the MCU operating
mode MD016 5 mode according to the table below.
control
MD1MD0Mode Description
0 1 Mode 1 Expanded mode with
on-chip ROM disabled
1 0 Mode 2 Expanded mode with
on-chip ROM enabled
1 1 Mode 3 Single-chip mode
Serial TxD0, 22 11 O Transmit Data (channels 0 and 1): Data output
communi- TxD19 78 pins for the serial communication interface.
cation RxD0, 21 10 I Receive Data (channels 0 and 1): Data input
interface RxD110 79 pins for the serial communication interface.
SCK0, 20 9 I/O Serial ClocK (channels 0 and 1): Input/output
SCK111 80 pins for the serial clock.
13
Table 1-3. Pin Functions (3)
Pin No.
CG-84
Type Symbol CP-84 FP-80A I/O Name and function
16-Bit FTOA, 34 22 O FRT Output compare A and B: Output pins
free- FTOB 39 27 controlled by comparators A and B of the free-
running running timer.
timer FTCI 33 21 I FRT counter Clock Input: Input pin for an
external clock signal for the free-running timer.
FTIA to 35 to 38 23 to 26 I FRT Input capture A to D: Input capture pins
FTID for the free-running timer.
8-Bit TMO0, 53 40 O 8-bit TiMer Output (channels 0 and 1):
timer TMO156 43 Compare-match output pins for the 8-bit timers.
TMCI0, 52 39 I 8-bit TiMer counter Clock Input (channels 0
TMCI155 42 and 1): External clock input pins for the 8-bit
timer counters.
TMRI0, 54 41 I 8-bit TiMer counter Reset Input (channels 0
TMRI157 44 and 1): A High input at these pins resets the 8-
bit timer counters.
PWM PW0, 58 45 O PWM timer output (channels 0 and 1): Pulse-
timer PW159 46 width modulation timer output pins.
A/D AN7to 50 to 43 37 to 30 I ANalog input: Analog signal input pins for
converter AN0the A/D converter.
ADTRG
32 20 I A/D Trigger: External trigger input for starting
the A/D converter.
D/A DA049 36 O Analog output: Analog signal output pins for
converter DA150 37 the D/A converter.
A/D and AVCC 42 29 I Analog reference Voltage: Reference voltage
D/A pin for the A/D and D/A converters. If the A/D
converters and D/A converters are not used, connect AVCC
to the system power supply (+5V).
AVSS 51 38 I Analog ground: Ground pin for the A/D and
D/A converters.Connect to system ground (0V).
14
Table 1-3. Pin Functions (4)
Pin No.
CG-84
Type Symbol CP-84 FP-80A I/O Name and function
General- P17to P1071 to 78 57 to 64 I/O Port 1: An 8-bit input/output port with
purpose programmable MOS input pull-ups and LED
I/O driving capability. The direction of each bit can
be selected in the port 1 data direction register
(P1DDR).
P27to P2061 to 63, 48 to 55 I/O Port 2: An 8-bit input/output port with
65 to 69 programmable MOS input pull-ups and LED
driving capability. The direction of each bit can
be selected in the port 2 data direction register
(P2DDR).
P37to P303, 1, 72 to 65 I/O Port 3: An 8-bit input/output port with
84 to 79 programmable MOS input pull-ups. The
direction of each bit can be selected in the port
3data direction register (P3DDR).
P47to P4059 to 52 46 to 39 I/O Port 4: An 8-bit input/output port. The
direction of each bit can be selected in the port 4
data direction register (P4DDR).
P52to P5020 to 22 9 to 11 I/O Port 5: A 3-bit input/output port. The direction
of each bit can be selected in the port 5 data
direction register (P5DDR).
P67to P6040 to 33 28 to 21 I/O Port 6: An 8-bit input/output port. The
direction of each bit can be selected in the port 6
data direction register (P6DDR).
P77to P7050 to 43 37 to 30 I Port 7: An 8-bit input port.
P86to P8011 to 5 80 to 74 I/O Port 8: A 7-bit input/output port. The direction
of each bit can be selected in the port 8 data
direction register (P8DDR).
P97to P9025 to 32 13 to 20 I/O Port 9: An 8-bit input/output port. The
direction of each bit (except for P96) can be
selected in the port 9 data direction register
(P9DDR).
15
Section 2. MCU Operating Modes and Address Space
2.1 Overview
2.1.1 Mode Selection
The H8/338 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the
inputs at the mode pins (MD1and MD0) when the chip comes out of a reset. See table 2-1.
The ROMless versions of the H8/338 Series (HD6413388, HD6413378) can be used only in mode
1 (expanded mode with on-chip ROM disabled).
Table 2-1. Operating Modes
Mode MD1MD0Address space On-chip ROM On-chip RAM
Mode 0 Low Low — — —
Mode 1 Low High Expanded Disabled Enabled*
Mode 2 High Low Expanded Enabled Enabled*
Mode 3 High High Single-chip Enabled Enabled
Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory
can be accessed instead.
Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices.
The maximum address space supported by these externally expanded modes is 64K bytes.
In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used.
All ports are available for general-purpose input and output.
Mode 0 is inoperative in the H8/338 Series. Avoid setting the mode pins to mode 0.
17
2.1.2 Mode and System Control Registers (MDCR and SYSCR)
Table 2-2 lists the registers related to the chip’s operating mode: the system control register
(SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the
mode pins MD1and MD0.
Table 2-2. Mode and System Control Registers
Name Abbreviation Read/Write Address
System control register SYSCR R/W H'FFC4
Mode control register MDCR R H'FFC5
2.2 System Control Register (SYSCR)—H'FFC4
Bit 76543210
SSBY STS2 STS1 STS0 — NMIEG DPME RAME
Initial value 0 0 0 0 1 0 0 1
Read/Write R/W R/W R/W R/W — R/W R/W* R/W
Note: * Do not write “1” in this bit.
The system control register (SYSCR) is an eight-bit register that controls the operation of the chip.
Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,
see section 14, “Power-Down State.”
On recovery from software standby mode by an external interrupt, the SSBY bit remains set to “1.”
It can be cleared by writing “0.”
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to software standby mode.
18
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time the CPU and on-chip supporting modules continue to stand by. These bits should be
set according to the clock frequency so that the settling time is at least 10ms. For specific settings,
see section 14.2, “System Control Register: Power-Down Control Bits.”
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Settling time = 8192 states (Initial value)
0 0 1 Settling time = 16384 states
0 1 0 Settling time = 32768 states
0 1 1 Settling time = 65536 states
1 — — Settling time = 131072 states
Bit 3—Reserved: This bit cannot be modified and is always read as “1.”
Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0 An interrupt is requested on the falling edge of the NMI input. (Initial value)
1 An interrupt is requested on the rising edge of the NMI input.
Bit 1—Dual-Port RAM Mode Enable (DPME): Reserved. Do not write “1” in this bit.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized
by a reset, but is not initialized in the software standby mode.
Bit 0
RAME Description
0 The on-chip RAM is disabled.
1 The on-chip RAM is enabled. (Initial value)
19
2.3 Mode Control Register (MDCR)—H'FFC5
Bit 76543210
— — — — — — MDS1 MDS0
Initial value 1 1 1 0 0 1 * *
Read/Write R R R R R R R R
Note: * Initialized according to MD1and MD0inputs.
The mode control register (MDCR) is an eight-bit register that indicates the operating mode of the
chip.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as “1.”
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as “0.”
Bit 2—Reserved: This bit cannot be modified and is always read as “1.”
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD1and MD0), thereby indicating the current operating mode of the chip. MDS1
corresponds to MD1and MDS0 to MD0. These bits can be read but not written. When the mode
control register is read, the levels at the mode pins (MD1and MD0) are latched in these bits.
20
2.4 Address Space Map
Figures 2-1 to 2-3 show memory maps of the H8/338, H8/337, and H8/336 in modes 1, 2, and 3.
Figure 2-1. H8/338 Address Space Map
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'F780
H'F77F
H'0048
H'0047
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'F780
H'C000
H'BFFF
H'0048
H'0047
H'0000
H'0048
H'0047
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector Table
On-Chip ROM,
48k bytes
Vector TableVector Table
External Address Space
On-Chip RAM ,
2k bytes On-Chip RAM,
2k bytes
External Address Space
External Address Space
External Address Space
On-Chip RAM ,
*
2k bytes
On-Chip Register Field On-Chip Register Field On-Chip Register Field
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Note: *
H'BFFF
On-Chip ROM,
48k bytes
*
21
Figure 2-2. H8/337 Address Space Map
H161 H8/337 H.M '91
Fig. 2-1
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'0048
H'0047
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'FB80
H'C000
H'BFFF
H'8000
H'7FFF
H'0048
H'0047
H'0000
H'0048
H'0047
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector Table
On-Chip ROM,
32k bytes
Vector TableVector Table
Reserved*1
Reserved*1, *2Reserved*1, *2
External Address Space
On-Chip RAM*2,
1k byte On-Chip RAM, 1k byte
External Address Space
External Address Space
External Address Space
On-Chip RAM*2,
1k byte
On-Chip Register Field On-Chip Register Field On-Chip Register Field
Do not access these reserved areas.
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Notes: *1
*2
H'7FFF
On-Chip ROM,
32k bytes
22
Figure 2-3. H8/336 Address Space Map
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'0048
H'0047
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'FB80
H'C000
H'BFFF
H'6000
H'5FFF
H'0048
H'0047
H'0000
H'0048
H'0047
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector Table
On-Chip ROM,
24k bytes
Vector TableVector Table
Reserved*1
Reserved*1, *2Reserved*1, *2
External Address Space
On-Chip RAM*2,
1k byte On-Chip RAM, 1k byte
External Address Space
External Address Space
External Address Space
On-Chip RAM*2,
1k byte
On-Chip Register Field On-Chip Register Field On-Chip Register Field
Do not access these reserved areas.
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Notes: *1
*2
H'5FFF
On-Chip ROM,
24k bytes
23
Section 3. CPU
3.1 Overview
The H8/338 Series has the H8/300 CPU: a fast central processing unit with eight 16-bit general
registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-
speed operation.
3.1.1 Features
The main features of the H8/300 CPU are listed below.
• Two-way register configuration
— Sixteen 8-bit general registers, or
— Eight 16-bit general registers
• Instruction set with 57 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct (Rn)
— Register indirect (@Rn)
— Register indirect with displacement (@(d:16, Rn))
— Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn)
— Absolute address (@aa:8 or @aa:16)
— Immediate (#xx:8 or #xx:16)
— PC-relative (@(d:8, PC))
— Memory indirect (@@aa:8)
• Maximum 64K-byte address space
• High-speed operation
— All frequently-used instructions are executed in two to four states
— The maximum clock rate is 10MHz
— 8- or 16-bit register-register add or subtract: 0.2µs
— 8
×8-bit multiply: 1.4µs
— 16 ÷ 8-bit divide: 1.4µs
• Power-down mode
— SLEEP instruction
25
3.2 Register Configuration
Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general
registers and control registers.
Figure 3-1. CPU Registers
3.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed
separately as 8-bit registers (R0H to R7H and R0L to R7L).
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As
indicated in figure 3-2, R7 (SP) points to the top of the stack.
0
7
R0H
R0L
R1H
R1L
R2H
R2L
R3L
R3H
R4L
R4H
R5H
R5L
R6H
R6L
R7H
R7L
(SP)
0
15
PC
0
2
3
5
C
V
Z
H
0
7
CCR
N
I
1
7
SP: Stack Pointer
PC: Program Counter
CCR: Condition Code Register
Carry flag
Overflow flag
Zero flag
Half-carry flag
Interrupt mask bit
User bit
Negative flag
U
U
User bit
Fig. 3-1
6
4
26
Figure 3-2. Stack Pointer
3.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the
PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register contains internal status information,
including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt
mask bit (I).
Bit 7—Interrupt Mask Bit (I): When this bit is set to “1,” all interrupts except NMI are masked.
This bit is set to “1” automatically by a reset and at the start of interrupt handling.
Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,
ORC, and XORC instructions).
Bit 5—Half-Carry Flag (H): This flag is set to “1” when the ADD.B, ADDX.B, SUB.B, SUBX.B,
NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to “0” otherwise.
Similarly, it is set to “1” when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow
out of bit 11, and cleared to “0” otherwise. It is used implicitly in the DAA and DAS instructions.
Bit 4—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC,
ORC, and XORC instructions).
SP
Unused area
Stack area
(R7)
Fig. 3-2
27
Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): This flag is set to “1” to indicate a zero result and cleared to “0” to indicate
a nonzero result.
Bit 1—Overflow Flag (V): This flag is set to “1” when an arithmetic overflow occurs, and cleared
to “0” at other times.
Bit 0—Carry Flag (C): This flag is used by:
• Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the
result
• Shift and rotate instructions, to store the value shifted out of the most significant or least
significant bit
• Bit manipulation and bit load instructions, as a bit accumulator
The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR,
and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in
conditional branching instructions (BCC).
For the action of each instruction on the flag bits, see the
H8/300 Series Programming Manual.
3.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt
mask bit (I) in the CCR is set to “1.” The other CCR bits and the general registers are not
initialized.
In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer
should be initialized by software, by the first instruction executed after a reset.
28
3.3 Addressing Modes
3.3.1 Addressing Mode
The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these
addressing modes.
Table 3-1. Addressing Modes
No. Addressing mode Symbol
(1) Register direct Rn
(2) Register indirect @Rn
(3) Register indirect with displacement @(d:16, Rn)
(4) Register indirect with post-increment @Rn+
Register indirect with pre-decrement @–Rn
(5) Absolute address @aa:8 or @aa:16
(6) Immediate #xx:8 or #xx:16
(7) Program-counter-relative @(d:8, PC)
(8) Memory indirect @@aa:8
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits ×8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment is
1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
29
• Register Indirect with Pre-Decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is decremented before the operand is accessed. The size of the
decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For
MOV.W, the original contents of the 16-bit general register must be even.
(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx.
The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to
65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or
a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit
immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the
instruction, specifying a bit number.
(7) Program-Counter-Relative—@(d:8, PC): This mode is used to generate branch addresses in
the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-
extended value to the program counter contents. The result must be an even number. The possible
branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to
255). The word located at this address contains the branch address. The upper 8 bits of the
absolute address are an “0” (H'00), thus the branch address is limited to values from 0 to 255
(H'0000 to H'00FF). Note that addresses H'0000 to H'0047 (0 to 71) are located in the vector table.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as “0,” causing word access to be performed at the
address preceding the specified address. See section 3.4.2, “Memory Data Formats,” for further
information.
3.3.2 How to Calculate Where the Execution Starts
Table 3-2 shows how to calculate the Effective Address (EA: Effective Address) for each
addressing mode.
In the operation instruction, 1) register direct, as well as 6) immediate (for each instruction,
ADD.B, ADDX, SUBX, CMP.B, AND, OR, XOR) are used.
In the move instruction, 7) program counter relative and 8) all addressing mode to delete the
memory indirect can be used.
In the bit manipulation instruction for the operand specifications, 1) register direct, 2) register
indirect, as well as 5) absolute address (8 bit) can be used. Furthermore, to specify the bit number
within the operand, 1) register direct (for each instruction, BSET, BCLR, BNOT, BTST) as well as
6) immediate (3 bit) can be used independently.
30
Table 3-2. Effective Address Calculation (1)
Addressing mode and
instruction format
op reg
7 6 34 015
No. Effective address calculation Effective address
1 Register direct, Rn
Operands are contained in registers regm
and regn
Register indirect, @Rn 16-bit register contents 015
Register indirect with displacement,
@(d:16, Rn)
op regm regn
8 7 34 015
op reg
7 6 34 015
disp
op reg
7 6 34 015
Register indirect with
post-increment, @Rn+
op reg
7 6 34 015
Register indirect with pre-decrement,
@–Rn
2
3
4
1 for a byte operand, 2 for a word operand
015
disp
015
015
015
1 or 2
015
015
1 or 2
015
regm
3 0 regn
3 0
16-bit register contents
16-bit register contents
16-bit register contents
*
*
*Note:
31
Table 3-2. Effective Address Calculation (2)
Addressing mode and
instruction format No. Effective address calculation Effective address
5 Absolute address
@aa:8
Operand is 1- or 2-byte immediate data
@aa:16
op 8 7 015
op 015
IMM
op disp
7 015
PC-relative
@(d:8, PC)
6
7
015
PC contents 015
015
abs
H'FF 8 7 015
015
abs
op
#xx:16
op 8 7 015 IMM
Immediate
#xx:8
8Sign extension disp
32
Table 3-2. Effective Address Calculation (3)
Addressing mode and
instruction format No. Effective address calculation Effective address
8 Memory indirect, @@aa:8
op 8 7 015
Memory contents (16 bits) 015
abs
H'00
8 7 015
Notation
reg:
op:
disp:
IMM:
abs:
General register
Operation code
Displacement
Immediate data
Absolute address
33
3.4 Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte
operand.
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed
BCD form. Each nibble of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits ×8 bits), and DIVXU
(16 bits ÷ 8 bits) instructions operate on word data.
34
3.4.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 3-3.
Figure 3-3. Register Data Formats
Note: RnH: Upper digit of general register
RnL: Lower digit of general register
MSB: Most significant bit
LSB: Least significant bit
4-Bit BCD data
1-Bit data
1-Bit data
Byte data
Byte data
Word data
4-Bit BCD data
Data type
RnL
RnH
RnL
RnH
RnL
Rn
RnH
Register No.
Don't-care 4 3
7 0
Data format
7 0
7 6 5 4 3 2 1 0 Don't-care
Don't-care 76543210
Don't-care
7 0
Don't-care 7 0
015
Don't-care
4 3
7 0
7 0
M
S
B
L
S
B
M
S
B
L
S
B
Upper digit Lower digit
Upper digit Lower digit
M
S
B
L
S
B
35
3.4.2 Memory Data Formats
Figure 3-4 indicates the data formats in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as “0.” If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored in the
vector table.
Figure 3-4. Memory Data Formats
When the stack is addressed by register R7, it must always be accessed a word at a time. When the
CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word.
When they are returned, the lower byte is ignored.
7 0
76543210
1-Bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Data type Data formatAddress
Address n
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
M
S
B
L
S
B
M
S
BL
S
B
Upper 8 bits
Lower 8 bits
M
S
B
M
S
B
L
S
B
L
S
B
CCR
CCR*
M
S
BL
S
B
CCR: Condition Code Register
Note: *Ignored when returned
36
3.5 Instruction Set
Table 3-3 lists the H8/300 instruction set.
Table 3-3. Instruction Classification
Notes: *1 PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
*2 Bcc is a conditional branch instruction in which cc represents a condition code.
*3 Not supported by the H8/338 Series.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
Function Instructions Types
Data transfer
MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*1 3
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, 14
DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8
ROTXR
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, 14
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Branch Bcc*2, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8
Block data transfer EEPMOV 1
Total 57
37
Operation Notation
Rd General register (destination)
Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
SP Stack pointer
PC Program counter
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
#imm Immediate data
#xx:3 3-Bit immediate data
#xx:8 8-Bit immediate data
#xx:16 16-Bit immediate data
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷ Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Move
¬ Not
38
3.5.1 Data Transfer Instructions
Table 3-4 describes the data transfer instructions. Figure 3-5 shows their object code formats.
Table 3-4. Data Transfer Instructions
Note: * Size: operand size
B: Byte
W: Word
Instruction Size* Function
MOV B/W (EAs) →Rd, Rs →(EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and
@Rn+ addressing modes are available for byte or word data. The
@aa:8 addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
MOVTPE B Not supported by the H8/338 Series.
MOVFPE B Not supported by the H8/338 Series.
PUSH W Rn →@–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.
POP W @SP+ →Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
39
Figure 3-5. Data Transfer Instruction Codes
15
8
7
0
MOV
r
r
Rm
→
Rn
Rn
→
@Rm, or @Rm
→
Rn
@(d:16, Rm)
→
Rn, or
disp.
Rn
→
@(d:16, Rm)
@Rm+
→
Rn, or Rn
→
@–Rm
abs.
@aa:8
→
Rn, or Rn
→
@aa:8
@aa:16
→
Rn, or
abs.
Rn
→
@aa:16
r
#imm.
#xx:8
→
Rn
#xx:16
→
Rn
#imm.
r
MOVFPE, MOVTPE
abs.
m
n
r
r
m
n
r
n
n
r
n
n
Op
Op
Op
Op
Op
Op
Op
Op
r
n
Op
PUSH, POP
r
r
m
n
r
r
m
n
r
n
Op
Op: Operation field
rm, rn: Register field
disp.: Displacement
abs.: Absolute address
#imm.: Immediate data
40
3.5.2 Arithmetic Operations
Table 3-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations”
for their object codes.
Table 3-5. Arithmetic Instructions
Note: * Size: operand size
B: Byte
W: Word
Instruction Size* Function
ADD B/W Rd ± Rs →Rd, Rd + #imm →Rd
SUB Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data can
be added or subtracted only when both words are in general registers.
ADDX B Rd ± Rs ± C →Rd, Rd ± #imm ± C →Rd
SUBX Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.
INC B Rd ± #1 →Rd
DEC Increments or decrements a general register.
ADDS W Rd ± #imm →Rd
SUBS Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.
DAA B Rd decimal adjust →Rd
DAS Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
MULXU B Rd ×Rs →Rd
Performs 8-bit ×8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
DIVXU B Rd ÷ Rs →Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
CMP B/W Rd – Rs, Rd – #imm
Compares data in a general register with data in another general register
or with immediate data. Word data can be compared only between two
general registers.
NEG B 0 – Rd →Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
41
3.5.3 Logic Operations
Table 3-6 describes the four instructions that perform logic operations. See figure 3-6 in
section 3.5.4, “Shift Operations,” for their object codes.
Table 3-6. Logic Operation Instructions
Note: * Size: operand size
B: Byte
3.5.4 Shift Operations
Table 3-7 describes the eight shift instructions. Figure 3-6 shows the object code formats of the
arithmetic, logic, and shift instructions.
Table 3-7. Shift Instructions
Note: * Size: operand size
B: Byte
Instruction Size* Function
AND B Rd ∧Rs →Rd, Rd ∧#imm →Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B Rd ∨Rs →Rd, Rd ∨#imm →Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B Rd ⊕Rs →Rd, Rd ⊕#imm →Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B ¬ (Rd) →(Rd)
Obtains the one’s complement (logical complement) of general register
contents.
Instruction Size* Function
SHAL B Rd shift →Rd
SHAR Performs an arithmetic shift operation on general register contents.
SHLL B Rd shift →Rd
SHLR Performs a logical shift operation on general register contents.
ROTL B Rd rotate →Rd
ROTR Rotates general register contents.
ROTXL B Rd rotate through carry → Rd
ROTXR Rotates general register contents through the C (carry) bit.
42
Figure 3-6. Arithmetic, Logic, and Shift Instruction Codes
15
8
7
0
ADD, SUB, CMP
ADDX, SUBX (Rm), MULXU, DIVXU
Op
ADDS, SUBS, INC, DEC, DAA,
DAS, NEG, NOT
Op
#imm.
ADD, ADDX, SUBX, CMP
(#xx:8)
AND, OR, XOR (Rm)
#imm.
AND, OR, XOR (#xx:8)
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
Op
Op
Op
Op
r
m
r
n
r
n
r
n
r
m
r
n
r
n
r
n
Op: Operation field
rm, rn: Register field
#imm.: Immediate data
43
3.5.5 Bit Manipulations
Table 3-8 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats.
Table 3-8. Bit-Manipulation Instructions (1)
Note: * Size: operand size
B: Byte
Instruction Size* Function
BSET B 1 →(<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to “1.” The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
BCLR B 0 →(<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to “0.” The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
BNOT B¬(<bit-No.> of <EAd>) →(<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register
BTST B ¬ (<bit-No.> of <EAd>) →Z
Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit is specified by a bit number, given in
3-bit immediate data or the lower three bits of a general register.
BAND B C ∧(<bit-No.> of <EAd>) →C
ANDs the C flag with a specified bit in a general register or memory.
BIAND C∧[¬ (<bit-No.> of <EAd>)] →C
ANDs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
BOR B C ∨(<bit-No.> of <EAd>) →C
ORs the C flag with a specified bit in a general register or memory.
BIOR C∨[¬ (<bit-No.> of <EAd>)] →C
ORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕(<bit-No.> of <EAd>) →C
XORs the C flag with a specified bit in a general register or memory.
44
Table 3-8. Bit-Manipulation Instructions (2)
Note: * Size: operand size
B: Byte
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modify-
write instructions. They read a byte of data, modify one bit in the byte, then write the byte back.
Care is required when these instructions are applied to registers with write-only bits and to the I/O
port registers.
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under
the following conditions.
P47: Input pin, Low
P46: Input pin, High
P45– P40: Output pins, Low
The intended purpose of this BCLR instruction is to switch P40from output to input.
Instruction Size* Function
BIXOR B C ⊕¬ [(<bit-No.> of <EAd>)] →C
XORs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) →C
Copies a specified bit in a general register or memory to the C flag.
BILD ¬ (<bit-No.> of <EAd>) →C
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
BST B C →(<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
BIST ¬ C →(<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
Step Description
1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address
45
Before Execution of BCLR Instruction
Execution of BCLR Instruction
BCLR #0, @P4DDR ;clear bit 0 in data direction register
After Execution of BCLR Instruction
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to “0,” making P40an input pin. In addition, P47DDR and P46DDR
are set to “1,” making P47and P46output pins.
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
DDR 0 0 1 1 1 1 1 1
DR 1 0 0 0 0 0 0 0
P47P46P45P44P43P42P41P40
Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High
DDR 1 1 1 1 1 1 1 0
DR 1 0 0 0 0 0 0 0
46
Figure 3-7. Bit Manipulation Instruction Codes
15
8
7
0
BSET, BCLR, BNOT, BTST
#imm.
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
n
Op
r
0
0
0
0
Operand: register indirect (@Rn)
#imm.
0
0
0
0
Bit No.: immediate (#xx:3)
n
Op
Op
r
0
0
0
0
Operand: register indirect (@Rn)
r
0
0
0
0
Bit No.: register direct (Rm)
m
n
Op
Op
abs.
Operand: absolute (@aa:8)
#imm.
0
0
0
0
Bit No.: immediate (#xx:3)
Op
Op
r
0
0
0
0
Operand: register indirect (@Rn)
#imm.
0
0
0
0
Bit No.: immediate (#xx:3)
n
Op
Op
abs.
Operand: absolute (@aa:8)
#imm.
0
0
0
0
Bit No.: immediate (#xx:3)
Op
Op
r
0
0
0
0
Operand: register indirect (@Rn)
#imm.
0
0
0
0
Bit No.: immediate (#xx:3)
n
Op
Op
BAND, BOR, BXOR, BLD, BST
#imm.
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
n
Op
BIAND, BIOR, BIXOR, BILD, BIST
#imm.
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
n
Op
abs.
Operand: absolute (@aa:8)
0
0
0
0
Bit No.: immediate (#xx:3)
#imm.
Op
Op
Operand: register direct (Rn)
Bit No.: register direct (Rm)
Op
r
n
r
m
abs.
Operand: absolute (@aa:8)
0
0
0
0
Bit No.: register direct (Rm)
Op
Op
r
m
Op: Operation field
rm, rn: Register field
abs.: Absolute address
#imm.: Immediate data
47
3.5.6 Branching Instructions
Table 3-9 describes the branching instructions. Figure 3-8 shows their object code formats.
Table 3-9. Branching Instructions
Instruction Size Function
Bcc — Branches if condition cc is true.
Mnemonic cc field Description Condition
BRA (BT) 0 0 0 0 Always (True) Always
BRN (BF) 0 0 0 1 Never (False) Never
BHI 0 0 1 0 High C ∨Z = 0
BLS 0 0 1 1 Low or Same C ∨Z = 1
BCC (BHS) 0 1 0 0 Carry Clear C = 0
(High or Same)
BCS (BLO) 0 1 0 1 Carry Set (Low) C = 1
BNE 0 1 1 0 Not Equal Z = 0
BEQ 0 1 1 1 Equal Z = 1
BVC 1 0 0 0 Overflow Clear V = 0
BVS 1 0 0 1 Overflow Set V = 1
BPL 1 0 1 0 Plus N = 0
BMI 1 0 1 1 Minus N = 1
BGE 1 1 0 0 Greater or Equal N ⊕V = 0
BLT 1 1 0 1 Less Than N ⊕V = 1
BGT 1 1 1 0 Greater Than Z ∨(N ⊕V) = 0
BLE 1 1 1 1 Less or Equal Z ∨(N ⊕V) = 1
JMP — Branches unconditionally to a specified address.
JSR — Branches to a subroutine at a specified address.
BSR — Branches to a subroutine at a specified displacement from the current
address.
RTS — Returns from a subroutine
48
Figure 3-8. Branching Instruction Codes
15
8
7
0
cc
disp.
Bcc
0
0
0
0
JMP (@Rm)
JMP (@aa:16)
abs.
abs.
JMP (@@aa:8)
disp.
BSR
r
0
0
0
0
JSR (@Rm)
JSR (@aa:16)
abs.
JSR (@@aa:8)
RTS
m
r
m
Op
Op
Op
Op
Op
Op
Op
Op
abs.
Op
Op: Operation field
cc: Condition field
rm: Register field
disp.: Displacement
abs.: Absolute address
49
3.5.7 System Control Instructions
Table 3-10 describes the system control instructions. Figure 3-9 shows their object code formats.
Table 3-10. System Control Instructions
Instruction Size Function
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to the power-down state.
LDC B Rs →CCR, #imm →CCR
Moves immediate data or general register contents to the condition code
register.
STC B CCR →Rd
Copies the condition code register to a specified general register.
ANDC B CCR ∧#imm →CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨#imm →CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕#imm →CCR
Logically exclusive-ORs the condition code register with immediate
data.
NOP — PC + 2 →PC
Only increments the program counter.
Note: * Size: operand size
B: Byte
50
Figure 3-9. System Control Instruction Codes
3.5.8 Block Data Transfer Instruction
Table 3-11 describes the EEPMOV instruction. Figure 3-10 shows its object code format.
Table 3-11. Block Data Transfer Instruction/EEPROM Write Operation
15 8 7 0
RTE, SLEEP, NOP
Op
rLDC, STC (Rn)
#imm. ANDC, ORC, XORC, LDC
(#xx:8)
n
Op
Op
Op: Operation field
rn: Register field
#imm.: Immediate data
Instruction Size Function
EEPMOV — if R4L ≠0 then
repeat @R5+ →@R6+
R4L – 1 →R4L
until R4L = 0
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: size of block (bytes)
R5: starting source address
R6: starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
51
Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
3.6 CPU States
The CPU has three states: the program execution state, exception-handling state, and power-down
state. The power-down state is further divided into three modes: the sleep mode, software standby
mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a
map of the state transitions.
Figure 3-11. Operating States
15 8 7 0
Op
Op
EEPROM
State Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes a hardware
sequence that includes loading the program counter from the vector table.
Power-down state Sleep mode
A state in which some or all of the chip Software standby mode
functions are stopped to conserve power. Hardware standby mode
R5
→
R5 + R4L
→
←
R6
←
R6 + R4L
H'FFFF
Not allowed
R5
→
R5 + R4L
→
←
R6
←
R6 + R4L
52
Op: Operation field
Figure 3-12. State Transitions
3.6.1 Program Execution State
In this state the CPU executes program instructions.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
(1) Saves the program counter and condition code register to the stack (except in the case of a
reset).
(2) Sets the interrupt mask (I) bit in the condition code register to “1.”
(3) Fetches the start address of the exception-handling routine from the vector table.
(4) Branches to that address, returning to the program execution state.
See section 4, “Exception Handling,” for further information on the exception-handling state.
Fig. 3-12
Reset state
Hardware
standby mode
Interrupt request
RES = 1
Power-down state
Sleep mode
Exception -
handling state
Program
execution state
Exception
handing
request
Exception
handing
SLEEP instruction
with SSBY bit set
STBY=1, RES=0
SLEEP
instruction
Software
standby mode
NMI or IRQ0
to IRQ 2
Notes:
A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware
standby mode.
A transition from any state to the hardware standby mode occurs when STBY goes Low.
*1
*2
53
3.6.3 Power-Down State
The power-down state includes three modes: the sleep mode, the software standby mode, and the
hardware standby mode.
(1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU
halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to
function.
(2) Software Standby Mode: The software standby mode is entered if the SLEEP instruction is
executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set.
The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized,
but the contents of the on-chip RAM and CPU registers remain unchanged. I/O port outputs also
remain unchanged.
(3) Hardware Standby Mode: The hardware standby mode is entered when the input at the
STBY pin goes Low. All chip functions halt, including I/O port output. The on-chip supporting
modules are initialized, but on-chip RAM contents are held.
See section 14, “Power-Down State,” for further information.
3.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (Ø). The period from one rising edge of the system clock to
the next is referred to as a “state.”
Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip
supporting modules, and external devices are accessed in different bus cycles as described below.
3.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1and T2. Either byte or
word data can be accessed, via a 16-bit data bus. Figure 3-13 shows the on-chip memory access
cycle. Figure 3-14 shows the associated pin states.
54
Figure 3-13. On-Chip Memory Access Cycle
Figure 3-14. Pin States during On-Chip Memory Access Cycle
Bus cycle
T1 state T2 state
Internal address bus Address
Write data
Internal Read signal
Internal data bus (read) Read data
Internal Write signal
Internal data bus (write)
Ø
T2 state
Bus cycle
T1 state
Ø
Address bus Address
Data bus: high impedance state
AS: High
RD: High
WR: High
55
3.7.2 Access to On-Chip Register Field and External Devices
The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and
external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of
data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes
requires two consecutive cycles (six states).
Figure 3-15 shows the access cycle for the on-chip register field. Figure 3-16 shows the associated
pin states. Figures 3-17 (a) and (b) show the read and write access timing for external devices.
Figure 3-15. On-Chip Register Field Access Cycle
Write data
Bus cycle
T1 state T2 state T3 state
Internal address bus
Ø
Address
Internal Read signal
Internal data bus (read) Read data
Internal Write signal
Internal data bus (write)
56
Figure 3-16. Pin States during On-Chip Register Field Access Cycle
Figure 3-17 (a). External Device Access Timing (Read)
Bus cycle
T1 state T2 state T3 state
Address bus
Ø
Address
AS: High
RD: High
WR: High
Data bus: high impedance state
Read cycle
T1 state T2 state T3 state
Address bus
Ø
Address
Read data
AS
RD
WR: High
Data bus
57
Figure 3-17 (b). External Device Access Timing (Write)
Write cycle
T1 state T2 state T3 state
Address bus
Ø
Address
Write data
AS
RD: High
WR
Data bus
58
Section 4. Exception Handling
4.1 Overview
The H8/338 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1
indicates their priority and the timing of their hardware exception-handling sequence.
Table 4-1. Hardware Exception-Handling Sequences and Priority
Type of
Priority exception Timing of exception-handling sequence
High Reset The hardware exception-handling sequence begins as soon as RES
changes from Low to High.
Interrupt When an interrupt is requested, the hardware exception-handling
sequence begins at the end of the current instruction, or at the end of
Low the current hardware exception-handling sequence.
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the RES pin goes Low, all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. When RES returns from Low to High, the reset
exception-handling sequence starts.
4.2.2 Reset Sequence
The reset state begins when RES goes Low. To ensure correct resetting, at power-on the RES pin
should be held Low for at least 20ms. In a reset during operation, the RES pin should be held Low
for at least 10 system clock cycles. For the pin states during a reset, see appendix C, “Pin States.”
When RES returns from Low to High, hardware carries out the following reset exception-handling
sequence.
59
(1) The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit in the condition code register (CCR) is set to “1.”
(2) The CPU loads the program counter with the first word in the vector table (stored at addresses
H'0000 and H'0001) and starts program execution.
The RES pin should be held Low when power is switched off, as well as when power is switched
on.
Figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4-2 indicates the
timing in mode 1.
Figure 4-1. Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)
(1)
(2)
(3)
Ø
RES
(2)
Internal address
bus
Internal Read
signal
Internal Write
signal
Internal data bus
(16 bits)
(1) Reset vector address (H'0000)
(2) Starting address of program (contents of H'0000–H'0001)
(3) First instruction of program
Vector
fetch
Internal
processing
Instruction
prefetch
Figure. 4-1
60
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1),(3) Reset vector address: (1)=H'0000, (3)=H'0001
(2),(4) Starting address of program (contents of reset vector): (2)=upper byte, (4)=lower byte
(5),(7) Starting address of program: (5)=(2)(4), (7)=(2)(4)+1
(6),(8) First instruction of program: (6)=first byte, (8)=second byte
Vector fetch
Internal
process-
ing Instruction prefetch
RES
D7 to D0
(8 bits)
A15 to A0
Ø
RD
WR
Figure. 4-2
Figure 4-2. Reset Sequence (Mode 1)
61
4.2.3 Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7),
the program counter and condition code register might not be saved correctly, leading to a program
crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The
first program instruction is therefore always executed. This instruction should initialize the stack
pointer (example: MOV.W #xx:16, SP).
4.3 Interrupts
4.3.1 Overview
The interrupt sources include nine input pins for external interrupts (NMI, IRQ0to IRQ7) and 22
internal sources in the on-chip supporting modules. Table 4-2 lists the interrupt sources in priority
order and gives their vector addresses. When two or more interrupts are requested, the interrupt
with highest priority is served first.
The features of these interrupts are:
• NMI has the highest priority and is always accepted. All internal and external interrupts except
NMI can be masked by the I bit in the CCR. When the I bit is set to “1,” interrupts other than
NMI are not accepted.
• IRQ0to IRQ7can be sensed on the falling edge of the input signal, or level-sensed. The type of
sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the
rising or falling edge can be selected.
• All interrupts are individually vectored. The software interrupt-handling routine does not have
to determine what type of interrupt has occurred.
62
Table 4-2. Interrupts
Address of entry
Interrupt source No. in vector table Priority
NMI 3 H'0006 – H'0007 High
IRQ04 H'0008 – H'0009
IRQ15 H'000A – H'000B
IRQ26 H'000C – H'000D
IRQ37 H'000E – H'000F
IRQ48 H'0010 – H'0011
IRQ59 H'0012 – H'0013
IRQ610 H'0014 – H'0015
IRQ711 H'0016 – H'0017
16-Bit free- ICIA (Input capture A) 12 H'0018 – H'0019
running timer ICIB (Input capture B) 13 H'001A – H'001B
ICIC (Input capture C) 14 H'001C – H'001D
ICID (Input capture D) 15 H'001E – H'001F
OCIA (Output compare A) 16 H'0020 – H'0021
OCIB (Output compare B) 17 H'0022 – H'0023
FOVI (Overflow) 18 H'0024 – H'0025
8-Bit timer 0 CMI0A (Compare-match A) 19 H'0026 – H'0027
CMI0B (Compare-match B) 20 H'0028 – H'0029
OVI0 (Overflow) 21 H'002A – H'002B
8-Bit timer 1 CMI1A (Compare-match A) 22 H'002C – H'002D
CMI1B (Compare-match B) 23 H'002E – H'002F
OVI1 (Overflow) 24 H'0030 – H'0031
Reserved 25 H'0032 – H'0033
26 H'0034 – H'0035
Serial ERI0 (Receive error) 27 H'0036 – H'0037
communication RXI0 (Receive end) 28 H'0038 – H'0039
interface 0 TXI0 (TDR empty) 29 H'003A – H'003B
TEI0 (TSR empty) 30 H'003C – H'003D
Serial ERI1 (Receive error) 31 H'003E – H'003F
communication RXI1 (Receive end) 32 H'0040 – H'0041
interface 1 TXI1 (TDR empty) 33 H'0042 – H'0043
TEI1 (TSR empty) 34 H'0044 – H'0045
A/D converter ADI (Conversion end) 35 H'0046 – H'0047 Low
Notes: 1. H'0000 and H'0001 contain the reset vector.
2. H'0002 to H'0005 are reserved in the H8/338 Series and are not available to the user.
63
4.3.2 Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), and IRQ enable register (IER).
Table 4-3. Registers Read by Interrupt Controller
Name Abbreviation Read/write Address
System control register SYSCR R/W H'FFC4
IRQ sense control register ISCR R/W H'FFC6
IRQ enable register IER R/W H'FFC7
System Control Register (SYSCR)—H'FFC4
Bit 76543210
SSBY STS2 STS1 STS0 — NMIEG DPME RAME
Initial value 0 0 0 0 1 0 0 1
Read/Write R/W R/W R/W R/W — R/W R/W R/W
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2
NMIEG Description
0 An interrupt is generated on the falling edge of NMI. (Initial state)
1 An interrupt is generated on the rising edge of NMI.
See section 2.2, “System Control Register,” for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)—H'FFC6
Bit 76543210
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
64
Bits 0 to 7—IRQ0to IRQ7Sense Control (IRQ0SC to IRQ7SC): These bits determine whether
IRQ0to IRQ7are level-sensed or sensed on the falling edge.
Bits 0 to 7
IRQ0SC to IRQ7SC Description
0 An interrupt is generated when IRQ0to IRQ7(Initial state)
inputs are Low.
1 An interrupt is generated by the falling edge of the IRQ0to IRQ7inputs.
IRQ Enable Register (IER)—H'FFC7
Bit 76543210
IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0 to 7—IRQ0to IRQ7Enable (IRQ0E to IRQ7E): These bits enable or disable the IRQ0to
IRQ7interrupts individually.
Bits 0 to 7
IRQ0E to IRQ7E Description
0 IRQ0to IRQ7interrupt requests are disabled. (Initial state)
1 IRQ0to IRQ7interrupt requests are enabled.
When edge sensing is selected (by setting bits IRQ0SC to IRQ7SC to “1”), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ0E to
IRQ7E) is cleared to “0” and the interrupt is disabled. If an interrupt is requested while the enable
bit (IRQ0E to IRQ7E) is set to “1,” the request will be held pending until served. If the enable bit is
cleared to “0” while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to “0,” the
interrupt-handling routine can be executed even though the enable bit is now “0.”
If execution of interrupt-handling routines under these conditions is not desired, it can be avoided
by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to “1” in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
when execution jumps to an interrupt vector.
65
2. Clear the desired bits from IRQ0E to IRQ7E to “0” to disable new interrupt requests.
3. Clear the corresponding IRQ0SC to IRQ7SC bits to “0,” then set them to “1” again. Pending
IRQn interrupt requests are cleared when I = “1” in the CCR, IRQnSC = “0,” and IRQnE =
“0.”
4.3.3 External Interrupts
The nine external interrupts are NMI and IRQ0to IRQ7. NMI, IRQ0, IRQ1, and IRQ2can be used
to recover from software standby mode.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected
by the NMIEG bit in the system control register. The NMI vector number is 3. In the NMI
hardware exception-handling sequence the I bit in the CCR is set to “1.”
(2) IRQ0to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the
input, as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by
the I bit in the CCR, and can be enabled and disabled individually by setting and clearing bits
IRQ0E to IRQ7E in the IRQ enable register.
When one of these interrupts is accepted, the I bit is set to “1.” IRQ0to IRQ7have interrupt vector
numbers 4 to 11. They are prioritized in order from IRQ7(Low) to IRQ0(High). For details, see
table 4-2.
Interrupts IRQ0to IRQ7do not depend on whether pins IRQ0to IRQ7are input or output pins.
When using external interrupts IRQ0to IRQ7, clear the corresponding DDR bits to “0” to set these
pins to the input state, and do not use these pins as input or output pins for the timers, serial
communication interface, or A/D converter.
4.3.4 Internal Interrupts
Twenty-two internal interrupts can be requested by the on-chip supporting modules. Each interrupt
source has its own vector number, so the interrupt-handling routine does not have to determine
which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to
“1.” When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except
NMI). The vector numbers are 12 to 35. For the priority order, see table 4-2.
66
4.3.5 Interrupt Handling
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt
requests, commands the CPU to start the hardware interrupt exception-handling sequence, and
furnishes the necessary vector number. Figure 4-3 shows a block diagram of the interrupt
controller.
Figure 4-3. Block Diagram of Interrupt Controller
The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding
enable bits. When the enable bit is cleared to “0,” the interrupt signal is not sent to the interrupt
controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU’s
interrupt mask bit (I) to “1.” Accordingly, these interrupts are accepted only when their enable bit
is set to “1” and the I bit is cleared to “0.”
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware
standby mode.
H161 H8/337 H.M '91
Fig. 4-3
IRQ flag
0
IRQ0E
ADF
ADIE
CPU
I (CCR)
NMI interrupt Interrupt
controller
Priority
decision
IRQ0
interrupt Interrupt request
Vector number
ADI
interrupt
Note: *
*
For edge-sensed interrupts, these AND gates change to the circuit shown below.
IRQ edge
IRQ E
0
0S Q
IRQ flag
0
IRQ interrupt0
67
When an NMI or another enabled interrupt is requested, the interrupt controller transfers the
interrupt request to the CPU and indicates the corresponding vector number. (When two or more
interrupts are requested, the interrupt controller selects the vector number of the interrupt with the
highest priority.) When notified of an interrupt request, at the end of the current instruction or
current hardware exception-handling sequence, the CPU starts the hardware exception-handling
sequence for the interrupt and latches the vector number.
Figure 4-4 is a flowchart of the interrupt (and reset) operations. Figure 4-6 shows the interrupt
timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM
and the stack is in on-chip RAM.
(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when
an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the
enable bit of that interrupt is set to “1.”
(2) The interrupt controller checks the I bit in the CCR and accepts the interrupt request if the I bit
is cleared to “0.” If the I bit is set to “1” only NMI requests are accepted; other interrupt
requests remain pending.
(3) Among all accepted interrupt requests, the interrupt controller selects the request with the
highest priority and passes it to the CPU. Other interrupt requests remain pending.
(4) When it receives the interrupt request, the CPU waits until completion of the current instruction
or hardware exception-handling sequence, then starts the hardware exception-handling
sequence for the interrupt and latches the interrupt vector number.
(5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the
stack. See figure 4-5. The stacked PC indicates the address of the first instruction that will be
executed on return from the software interrupt-handling routine.
(6) Next the I bit in the CCR is set to “1,” masking all further interrupts except NMI.
(7) The vector address corresponding to the vector number is generated, the vector table entry at
this vector address is loaded into the program counter, and execution branches to the software
interrupt-handling routine at the address indicated by that entry.
68
Figure 4-4. Hardware Interrupt-Handling Sequence
H161 H8/337 H.M '91
Fig. 4-4
Program execution
No
No
No
Yes
No
Yes
Yes
Yes
No
Yes
NMI?
I = 0?
IRQ0?
IRQ1?
ADI?
Reset
I← 1
Interrupt
requested?
Pending
Latch vector No.
Save PC
Save CCR
Read vector address
Branch to software
interrupt-handling
routine
Yes
69
Figure 4-5. Usage of Stack in Interrupt Handling
SP(R7)
SP-4
SP-3
SP-2
SP-1
SP(R7)
Stack area
SP+1
SP+2
SP+3
SP+4
Even address
CCR
CCR*
PC (upper byte)
PC (lower byte)
Before interrupt
is accepted
After interrupt
is accepted
Pushed onto stack
Program counter
Condition code register
Stack pointer
PC:
CCR:
SP:
1.
2.
The PC contains the address of the first instruction
executed after return.
Registers must be saved and restored by word
access at an even address.
Notes:
*Ignored on return.
Figure. 4-5
70
Figure 4-6. Timing of Interrupt Sequence
(3)
(5)
(6)
(8)
(9)
(1)
Interrupt priority
decision. Wait for
end of instruction.
Interrupt
accepted
Internal
process-
ing
Stack
Vector
fetch
Internal
process-
ing
Instruction fetch
(first instruction of
interrupt-handling
routine)
Interrupt request
signal
Internal address
bus
Internal Write
signal
Internal Read
signal
Internal 16-bit
data bus
Ø
(1)
(2)
(4)
(7)
(9)
(10)
Instruction
fetch
Figure. 4-6
(1)
(2) (4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
interrupt-handling routine.)
Instruction code (Not executed)
Instruction prefetch address (Not executed)
SP–2
SP–4
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
71
4.3.6 Interrupt Response Time
Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since on-chip memory is
accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling
routines in on-chip ROM and the stack in on-chip RAM.
Table 4-4. Number of States before Interrupt Service
Number of states
No. Reason for wait On-chip memory External memory
1 Interrupt priority decision 2*3 2*3
2 Wait for completion of 1 to 13 5 to 17*2
current instruction*1
3 Save PC and CCR 4 12*2
4 Fetch vector 2 6*2
5 Fetch instruction 4 12*2
6 Internal processing 4 4
Total 17 to 29 41 to 53 *2
Notes: *1 These values do not apply if the current instruction is EEPMOV.
*2 If wait states are inserted in external memory access, add the number of wait states.
*3 1 for internal interrupts.
4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
Contention between Interrupt Request and Disable: When software clears the enable bit of an
interrupt to “0” to disable the interrupt, the interrupt becomes disabled after execution of the
clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and
the interrupt is requested during execution of that instruction, at the instant when the instruction
ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-
handling sequence is executed for the interrupt. If a higher-priority interrupt is requested at the
same time, however, the hardware exception-handling sequence is executed for the higher-priority
interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to “0.”
72
Figure 4-7 shows an example in which the OCIAE bit is cleared to “0.”
Figure 4-7. Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to “0” while the interrupt
mask bit (I) is set to “1.”
4.4 Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is
always accessed by word access. Care should be taken to keep an even value in the stack pointer
(general register R7). Use the PUSH and POP (or MOV.W Rn, @–SP and MOV.W @SP+, Rn)
instructions to push and pop registers on the stack.
Setting the stack pointer to an odd value can cause programs to crash. Figure 4-8 shows an
example of damage caused when the stack pointer contains an odd address.
Ø
Internal address bus
OCIAE
H161 H8/337 H.M '91
Fig. 4-7
OCIA interrupt handling
OCIA interrupt signal
OCFA
CPU write
cycle to TIER
Internal write signal
TIER address
73
Figure 4-8. Example of Damage Caused by Setting an Odd Address in R7
Although the CCR consists of only one byte, it is treated as word data when pushed on the stack.
In the hardware interrupt exception-handling sequence, two identical CCR bytes are pushed onto
the stack to make a complete word. When popped from the stack by an RTE instruction, the CCR
is loaded from the byte stored at the even address. The byte stored at the odd address is ignored.
PC
H
R1
SP
SP
SP
L
PC
L
PC
H'FECD
H'FECF
H'FECC
BSR instruction
MOV.B R1L, @–R7
PC is improperly stored
beyond top of stack
H'FECF set in SP
PC is lost
H
PC :
Upper byte of program counter
Lower byte of program counter
General register
Stack pointer
PC :
R1 :
SP :
H
L
L
L
Figure. 4-7
74
Section 5. I/O Ports
5.1 Overview
The H8/338 Series has nine parallel I/O ports, including:
• Six 8-bit input/output ports—ports 1, 2, 3, 4, 6, and 9
• One 8-bit input port—port 7
• One 7-bit input/output port—port 8
• One 3-bit input/output port—port 5
Ports 1, 2, and 3 have programmable input pull-up transistors. Ports 1 to 6, 8, and 9 can drive a
Darlington pair. Ports 1 to 4, 6, and 9 can drive one TTL load and a 90pF capacitive load. Ports 5
and 8 can drive one TTL load and a 30pF capacitive load. Ports 1 and 2 can drive LEDs (10mA
current sink).
Input and output are memory-mapped. The CPU views each port as a data register (DR) located in
the register field at the high end of the address space. Each port (except port 7) also has a data
direction register (DDR) which determines which pins are used for input and which for output.
Output: To send data to an output port, the CPU selects output in the data direction register and
writes the desired data in the data register, causing the data to be held in a latch. The latch output
drives the pin through a buffer amplifier. If the CPU reads the data register of an output port, it
obtains the data held in the latch rather than the actual level of the pin.
Input: To read data from an I/O port, the CPU selects input in the data direction register and reads
the data register. This causes the input logic level at the pin to be placed directly on the internal
data bus. There is no intervening input latch.
The data direction registers are write-only registers; their contents are invisible to the CPU. If the
CPU reads a data direction register all bits are read as “1,” regardless of their true values. Care is
required if bit manipulation instructions are used to set and clear the data direction bits. See the
note on bit manipulation instructions in section 3.5.5, “Bit Manipulations.”
Auxiliary Functions: In addition to their general-purpose input/output functions, all of the I/O
ports have auxiliary functions. Most of the auxiliary functions are software-selectable and must be
enabled by setting bits in control registers. When selected, an auxiliary function usually replaces
the general-purpose input/output function, but in some cases both functions can operate
simultaneously. Table 5-1 summarizes the functions of the ports.
75
Table 5-1. Port Functions
Expanded modes Single-chip mode
Port Description Pins Mode 1 Mode 2 Mode 3
Port 1 •8-bit input-output P17to P10/Address output General input General input/
port A7to A0(low) when DDR = “0” output
•Can drive LEDs (initial state)
•Input pull-ups Address output
(low) when
DDR = “1”
Port 2 •8-bit input-output P27to P20/Address output General input General input/
port A15 to A8(high) when DDR = “0” output
•Can drive LEDs (initial state)
•Input pull-ups Address output
(high) when
DDR = “1”
Port 3 •8-bit input-output P37to P30/Data bus Data bus General input/
port D7to D0output
•Input pull-ups
Port 4 •8-bit input-output P47to P40General input/output, 8-bit timer 0/1 input/output
port (TMCI0, TMO0, TMRI0, TMCI1, TMO1, TMRI1), or
PWM timer 0/1 output (PW0, PW1)
Port 5 •3-bit input-output P52to P50General input/output or serial communication interface
port 0 input/output (TxD0, RxD0, SCK0)
Port 6 •8-bit input-output P67to P60General input/output, 16-bit free-running timer
port input/output (FTCI, FTOA, FT OB, FTIA, FTIB, FTIC,
FTID), or external interrupt input (IRQ6, IRQ7)
76
Table 5-1. Port Functions (cont.)
Expanded modes Single-chip mode
Port Description Pins Mode 1 Mode 2 Mode 3
Port 7 •8-bit input port P77to P70General input, analog input to A/D converter (AN7to
AN0), or analog output from D/A converter (DA0, DA1)
Port 8 •7-bit input-output P86/SCK1/IRQ5General input/output, serial communication interface 1
port P85/RxD1/IRQ4input/output (TxD1, RxD1, SCK1), or external interrupt
P84/TxD1/IRQ3input (IRQ3, IRQ4, IRQ5)
P83to P80General input/output
Port 9 •8-bit input-output P97/WAIT WAIT input General input/
port output
P96/Ø System clock General input
output when DDR = “0”
(initial state)
System clock
output when
DDR = “1”
P95/AS AS output General input/
P94/WR WR output output
P93/RD RD output
P92/IRQ0General input/output or external interrupt input
P91/IRQ1(IRQ0, IRQ1)
P90/ADTRG/ General input/output, A/D converter trigger input
IRQ2(ADTRG), or external interrupt input (IRQ2)
77
5.2 Port 1
Port 1 is an 8-bit input/output port that also provides the low bits of the address bus. The function
of port 1 depends on the MCU mode as indicated in table 5-2.
Table 5-2. Functions of Port 1
Note: * Depending on the bit settings in the data direction register: 0—input pin; 1—address pin
Pins of port 1 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input
pins, they have programmable MOS transistor pull-ups.
Table 5-3 details the port 1 registers.
Table 5-3. Port 1 Registers
Port 1 Data Direction Register (P1DDR)—H'FFB0
Mode 1 Mode 2 Mode 3
Address bus (Low) Input port or Input/output port
(A7to A0) Address bus (Low)
(A7to A0)*
Name Abbreviation Read/Write Initial value Address
Port 1 data direction register P1DDR W H'FF (mode 1) H'FFB0
H'00 (modes 2 and 3)
Port 1 data register P1DR R/W H'00 H'FFB2
Port 1 input pull-up control P1PCR R/W H'00 H'FFAC
register
Bit 76543210
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value 1 1 1 1 1 1 1 1
Read/Write — — — — — — — —
Modes 2 and 3
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
78
P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an
output pin if the corresponding bit in P1DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 1 Data Register (P1DR)—H'FFB2
P1DR is an 8-bit register containing the data for pins P17to P10. When the CPU reads P1DR, for
output pins it reads the value in the P1DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P1DR latch.
Port 1 Input Pull-Up Control Register (P1PCR)—H'FFAC
Bit 76543210
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If a
bit in P1DDR is cleared to “0” (designating input) and the corresponding bit in P1PCR is set to “1,”
the input pull-up transistor for that bit is turned on.
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 1 is automatically used for
address output. The port 1 data direction register is unwritable. All bits in P1DDR are
automatically set to “1” and cannot be cleared to “0.”
Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 1 can be selected on a
pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to “0,”
or for address output if its data direction bit is set to “1.”
Mode 3: In the single-chip mode port 1 is a general-purpose input/output port.
Bit 76543210
P17P16P15P14P13P12P11P10
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
79
Reset: A reset clears P1DDR, P1DR, and P1PCR to all “0,” placing all pins in the input state with
the pull-up transistors off. In mode 1, when the chip comes out of reset, P1DDR is set to all “1.”
Hardware Standby Mode: All pins are placed in the high-impedance state with the pull-up
transistors off. P1DR and P1PCR are initialized to H'00. In modes 2 and 3, P1DDR is initialized to
H'00.
Software Standby Mode: In the software standby mode, P1DDR, P1DR, and P1PCR remain in
their previous state. Address output pins are Low. General-purpose output pins continue to output
the data in P1DR.
Input Pull-Up Transistors: Port 1 has built-in programmable input pull-up transistors that are
available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn
on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to “1” and clear the
corresponding P1DDR bit to “0.” P1PCR is cleared to H'00 by a reset and in the hardware standby
mode, turning all input pull-ups off. In software standby mode, the previous state is maintained.
Table 5-4 indicates the states of the input pull-up transistors in each operating mode.
Table 5-4. States of Input Pull-Up Transistors (Port 1)
Mode Reset Hardware standby Software standby Other operating modes
1 Off Off Off Off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P1PCR = “1” and P1DDR = “0,” but off
otherwise.
Figure 5-1 shows a schematic diagram of port 1.
80
Figure 5-1. Port 1 Schematic Diagram
5.3 Port 2
Port 2 is an 8-bit input/output port that also provides the high bits of the address bus. The function
of port 2 depends on the MCU mode as indicated in table 5-5.
Table 5-5. Functions of Port 2
Mode 1 Mode 2 Mode 3
Address bus (High) Input port or Input/output port
(A15 to A8) Address bus (High)
(A15 to A8)*
Note: * Depending on the bit settings in the data direction register: 0—input pin; 1—address pin
H161 '91
Fig. 5-1
P1n
Hardware standby
Mode 3
Mode 1 or 2
RP1
Reset
ResetMode 1
Reset
WP1
WP1D
WP1P
R
RS
R
Q
Q
Q
D
D
D
P1n DR
P1n DDR
P1n PCR
C
C
C
*
RP1P
Internal address bus
WP1P:
WP1D:
WP1:
RP1P :
RP1:
n = 0 to 7
Note: Set-priority*
Write Port 1 PCR
Write Port 1 DDR
Write Port 1
Read Port 1 PCR
Read Port 1
Internal data bus
81
Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input
pins, they have programmable MOS transistor pull-ups.
Table 5-6 details the port 2 registers.
Table 5-6. Port 2 Registers
Name Abbreviation Read/Write Initial value Address
Port 2 data direction P2DDR W H'FF (mode 1) H'FFB1
register H'00 (modes 2 and 3)
Port 2 data register P2DR R/W H'00 H'FFB3
Port 2 input pull-up P2PCR R/W H'00 H'FFAD
control register
Port 2 Data Direction Register (P2DDR)—H'FFB1
P2DDR is an 8-bit register that selects the direction of each pin in port 2. A pin functions as an
output pin if the corresponding bit in P2DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 2 Data Register (P2DR)—H'FFB3
P2DR is an 8-bit register containing the data for pins P27to P20. When the CPU reads P2DR, for
output pins it reads the value in the P2DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P2DR latch.
Bit 76543210
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Mode 1
Initial value 1 1 1 1 1 1 1 1
Read/Write — — — — — — — —
Modes 2 and 3
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Bit 76543210
P27P26P25P24P23P22P21P20
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
82
Port 2 Input Pull-Up Control Register (P2PCR)—H'FFAD
Bit 76543210
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a
bit in P2DDR is cleared to “0” (designating input) and the corresponding bit in P2PCR is set to “1,”
the input pull-up transistor for that bit is turned on.
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 2 is automatically used for
address output. The port 2 data direction register is unwritable. All bits in P2DDR are
automatically set to “1” and cannot be cleared to “0.”
Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 2 can be selected on a
pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to “0,”
or for address output if its data direction bit is set to “1.”
Mode 3: In the single-chip mode port 2 is a general-purpose input/output port.
Reset: A reset clears P2DDR, P2DR, and P2PCR to all “0,” placing all pins in the input state with
the pull-up transistors off. In mode 1, when the chip comes out of reset, P2DDR is set to all “1.”
Hardware Standby Mode: All pins are placed in the high-impedance state with the pull-up
transistors off. P2DR and P2PCR are initialized to H'00. In modes 2 and 3, P2DDR is initialized to
H'00.
Software Standby Mode: In the software standby mode, P2DDR, P2DR, and P2PCR remain in
their previous state. Address output pins are Low. General-purpose output pins continue to output
the data in P2DR.
Input Pull-Up Transistors: Port 2 has built-in programmable input pull-up transistors that are
available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn
on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to “1” and clear the
corresponding P2DDR bit to “0.” P2PCR is cleared to H'00 by a reset and in the hardware standby
mode, turning all input pull-ups off. In software standby mode, the previous state is maintained.
83
Table 5-7 indicates the states of the input pull-up transistors in each operating mode.
Table 5-7. States of Input Pull-Up Transistors (Port 2)
Mode Reset Hardware standby Software standby Other operating modes
1 Off Off Off Off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P2PCR = “1” and P2DDR = “0,” but off
otherwise.
Figure 5-2 shows a schematic diagram of port 2.
Figure 5-2. Port 2 Schematic Diagram
H161 '91
Fig. 5-2
P2n
Hardware
standby
Mode 3
Mode 1 or 2
RP2
Reset
ResetMode 1
Reset
WP2
WP2D
WP2P
R
RS
R
Q
Q
Q
D
D
D
P2n DR
P2n DDR
P2n PCR
C
C
C
*
RP2P
Internal address bus
WP2P:
WP2D:
WP2:
RP2P :
RP2:
n = 0 to 7
Note: Set-priority*
Write Port 2 PCR
Write Port 2 DDR
Write Port 2
Read Port 2 PCR
Read Port 2
Internal data bus
84
5.4 Port 3
Port 3 is an 8-bit input/output port that also provides the external data bus. The function of port 3
depends on the MCU mode as indicated in table 5-8.
Table 5-8. Functions of Port 3
Mode 1 Mode 2 Mode 3
Data bus Data bus Input/output port
Pins of port 3 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When they are used as input pins, they have program-
mable MOS transistor pull-ups.
Table 5-9 details the port 3 registers.
Table 5-9. Port 3 Registers
Name Abbreviation Read/Write Initial value Address
Port 3 data direction register P3DDR W H'00 H'FFB4
Port 3 data register P3DR R/W H'00 H'FFB6
Port 3 input pull-up control P3PCR R/W H'00 H'FFAE
register
Port 3 Data Direction Register (P3DDR)—H'FFB4
P3DDR is an 8-bit register that selects the direction of each pin in port 3. A pin functions as an
output pin if the corresponding bit in P3DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Bit 76543210
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
85
Port 3 Data Register (P3DR)—H'FFB6
P3DR is an 8-bit register containing the data for pins P37to P30. When the CPU reads P3DR, for
output pins it reads the value in the P3DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P3DR latch.
Port 3 Input Pull-Up Control Register (P3PCR)—H'FFAE
Bit 76543210
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If a
bit in P3DDR is cleared to “0” (designating input) and the corresponding bit in P3PCR is set to “1,”
the input pull-up transistor for that bit is turned on.
Modes 1 and 2: In the expanded modes, port 3 is automatically used as the data bus. The values
in P3DDR, P3DR, and P3PCR are ignored.
Mode 3: In the single-chip mode, port 3 can be used as a general-purpose input/output port.
Bit 76543210
P37P36P35P34P33P32P31P30
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
86
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P3DDR, P3DR, and P3PCR to all “0.” All pins are placed in the high-impedance state with the
pull-up transistors off.
Software Standby Mode: In the software standby mode, P3DDR, P3DR, and P3PCR remain in
their previous state. In modes 1 and 2, all pins are placed in the data input (high-impedance) state.
In mode 3, all pins remain in their previous input or output state.
Input Pull-Up Transistors: Port 3 has built-in programmable input pull-up transistors that are
available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an
input pull-up in mode 3, set the corresponding P3PCR bit to “1” and clear the corresponding
P3DDR bit to “0.” P3PCR is cleared to H'00 by a reset and in the hardware standby mode, turning
all input pull-ups off. In software standby mode, the previous state is maintained.
Table 5-10 indicates the states of the input pull-up transistors in each operating mode.
Table 5-10. States of Input Pull-Up Transistors (Port 3)
Mode Reset Hardware standby Software standby Other operating modes
1 Off Off Off Off
2 Off Off Off Off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P3PCR = “1” and P3DDR = “0,” but off
otherwise.
Figure 5-3 shows a schematic diagram of port 3.
87
Figure 5-3. Port 3 Schematic Diagram
P3n
Reset
Reset
Reset
WP3
WP3D
WP3P
R
R
R
Q
Q
Q
D
D
D
P3n DR
P3n DDR
P3n PCR
C
C
C
Internal data bus
RP3
H161 '91
Fig. 5-3
External
address
write
Mode 1 or 2
External address
read
WP3P:
WP3D:
WP3:
RP3P :
RP3:
n = 0 to 7
Write Port 3 PCR
Write Port 3 DDR
Write Port 3
Read Port 3 PCR
Read Port 3
Mode 3
Mode 3
RP3P
Mode 3
88
5.5 Port 4
Port 4 is an 8-bit input/output port that also provides the input and output pins for the 8-bit timers
and the output pins for the PWM timers. The pin functions depend on control bits in the control
registers of the timers. Pins not used by the timers are available for general-purpose input/output.
Table 5-11 lists the pin functions, which are the same in both the expanded and single-chip modes.
Table 5-11. Port 4 Pin Functions (Modes 1 to 3)
Usage Pin functions
I/O port P40P41P42P43P44P45P46P47
Timer TMCI0TMO0TMRI0TMCI1TMO1TMRI1PW0PW1
See section 7, “8-Bit Timers” and section 8, “PWM Timers,” for details of the timer control bits.
Pins of port 4 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-12 details the port 4 registers.
Table 5-12. Port 4 Registers
Name Abbreviation Read/Write Initial value Address
Port 4 data direction register P4DDR W H'00 H'FFB5
Port 4 data register P4DR R/W H'00 H'FFB7
Port 4 Data Direction Register (P4DDR)—H'FFB5
P4DDR is an 8-bit register that selects the direction of each pin in port 4. A pin functions as an
output pin if the corresponding bit in P4DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Bit 76543210
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
89
Port 4 Data Register (P4DR)—H'FFB7
P4DR is an 8-bit register containing the data for pins P47to P40. When the CPU reads P4DR, for
output pins (P4DDR = “1”) it reads the value in the P4DR latch, but for input pins (P4DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P4DR latch. This also applies to pins
used for timer input or output.
Pins P40, P42, P43, and P45: As indicated in table 5-11, these pins can be used for general-
purpose input or output, or input of 8-bit timer clock and reset signals. When a pin is used for timer
signal input, its P4DDR bit should normally be cleared to “0;” otherwise the timer will receive the
value in P4DR.
Pins P41, P44, P46, and P47: As indicated in table 5-11, these pins can be used for general-
purpose input or output, or for 8-bit timer output (P41and P44) or PWM timer output (P46and
P47). Pins used for timer output are unaffected by the values in P4DDR and P4DR.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P4DDR and P4DR to all “0” and makes all pins into input port pins.
Software Standby Mode: In the software standby mode, the control registers of the 8-bit and
PWM timers are initialized but P4DDR and P4DR remain in their previous states. All pins become
input or output port pins depending on the setting of P4DDR. Output pins output the values in
P4DR.
Figures 5-4 and 5-5 show schematic diagrams of port 4.
Bit 76543210
P47P46P45P44P43P42P41P40
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
90
Figure 5-4. Port 4 Schematic Diagram (Pins P40, P42, P43, and P45)
H161 '91
Fig. 5-4
P4n
RP4
Reset
Reset
WP4
WP4D
R
R
Q
Q
D
D
P4n DR
P4n DDR
C
C
Internal data bus
WP4D:
WP4:
RP4:
n = 0, 2, 3, 5
Write Port 4 DDR
Write Port 4
Read Port 4
8-bit timer module
Counter clock input
Counter reset input
91
Figure 5-5. Port 4 Schematic Diagram (Pins P41, P44, P46, and P47)
H161 '91
Fig. 5-5
RP4
Reset
Reset
WP4
WP4D
R
R
Q
Q
D
D
P4n DR
P4n DDR
C
C
WP4D:
WP4:
RP4:
n = 1, 4, 6, 7
Write Port 4 DDR
Write Port 4
Read Port 4
8-bit timer module,
PWM timer module
Output enable
8-bit timer output
or PWM timer output
P4n
Internal data bus
92
5.6 Port 5
Port 5 is a 3-bit input/output port that also provides the input and output pins for serial communi-
cation interface 0 (SCI0). The pin functions depend on control bits in the serial control register
(SCR). Pins not used for serial communication are available for general-purpose input/output.
Table 5-13 lists the pin functions, which are the same in both the expanded and single-chip modes.
Table 5-13. Port 5 Pin Functions (Modes 1 to 3)
Usage Pin functions
I/O port P50P51P52
Serial communication interface 0 TxD0RxD0SCK0
See section 9, “Serial Communication Interface,” for details of the serial control bits. Pins used by
the serial communication interface are switched between input and output without regard to the
values in the data direction register.
Pins of port 5 can drive a single TTL load and a 30pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-14 details the port 5 registers.
Table 5-14. Port 5 Registers
Name Abbreviation Read/Write Initial value Address
Port 5 data direction register P5DDR W H'F8 H'FFB8
Port 5 data register P5DR R/W H'F8 H'FFBA
Port 5 Data Direction Register (P5DDR)—H'FFB8
P5DDR is an 8-bit register that selects the direction of each pin in port 5. A pin functions as an
output pin if the corresponding bit in P5DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Bit 76543210
— — — — — P52DDR P51DDR P50DDR
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — W W W
93
Port 5 Data Register (P5DR)—H'FFBA
P5DR is an 8-bit register containing the data for pins P52to P50. When the CPU reads P5DR, for
output pins (P5DDR = “1”) it reads the value in the P5DR latch, but for input pins (P5DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P5DR latch. This also applies to pins
used for serial communication.
Pin P50: This pin can be used for general-purpose input or output, or for output of serial transmit
data (TxD0). When used for TxD0output, this pin is unaffected by the values in P5DDR and
P5DR.
Pin P51: This pin can be used for general-purpose input or output, or for input of serial receive
data (RxD0). When used for RxD0input, this pin is unaffected by P5DDR and P5DR.
Pin P52: This pin can be used for general-purpose input or output, or for serial clock input or
output (SCK0). When used for SCK0input or output, this pin is unaffected by P5DDR and P5DR.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode makes all
pins of port 5 into input port pins.
Software Standby Mode: In the software standby mode, the serial control register is initialized
but P5DDR and P5DR remain in their previous states. All pins become input or output port pins
depending on the setting of P5DDR. Output pins output the values in P5DR.
Figures 5-6 to 5-8 show schematic diagrams of port 5.
Bit 76543210
— — — — — P52P51P50
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — R/W R/W R/W
94
Figure 5-6. Port 5 Schematic Diagram (Pin P50)
H161 '91
Fig. 5-6
RP5
Reset
Reset
WP5
WP5D
R
R
Q
Q
D
D
P50 DR
P50 DDR
C
C
WP5D:
WP5:
RP5:
Write Port 5 DDR
Write Port 5
Read Port 5
SCI module
Transmit enable
Transmit data
P50
Internal data bus
95
Figure 5-7. Port 5 Schematic Diagram (Pin P51)
H161 '91
Fig. 5-7
P51
RP5
Reset
Reset
WP5
WP5D
R
R
Q
Q
D
D
P51 DR
P51DDR
C
C
Internal data bus
WP5D:
WP5:
RP5:
Write Port 5 DDR
Write Port 5
Read Port 5
SCI module
Receive enable
Receive data
96
Figure 5-8. Port 5 Schematic Diagram (Pin P52)
H161 '91
Fig. 5-8
RP5
Reset
Reset
WP5
WP5D
R
R
Q
Q
D
D
P52 DR
P52 DDR
C
C
WP5D:
WP5:
RP5:
Write Port 5 DDR
Write Port 5
Read Port 5
SCI module
Clock input enable
Clock output enable
Clock output
Clock input
P52
Internal data bus
97
5.7 Port 6
Port 6 is an 8-bit input/output port that also provides the input and output pins for the free-running
timer and the IRQ6and IRQ7input/output pins. The pin functions depend on control bits in the
free-running timer control registers, and on bit 6 or 7 of the interrupt enable register. Pins not used
for timer or interrupt functions are available for general-purpose input/output. Table 5-15 lists the
pin functions, which are the same in both the expanded and single-chip modes.
Table 5-15. Port 6 Pin Functions
Usage Pin functions (Modes 1 to 3)
I/O port P60P61P62P63P64P65P66P67
Timer/interrupt FTCI FTOA FTIA FTIB FTIC FTID FTOB/IRQ6IRQ7
See section 4 “Exception Handling” and section 6, “16-Bit Free-Running Timer” for details of the
free-running timer and interrupts.
Pins of port 6 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-16 details the port 6 registers.
Table 5-16. Port 6 Registers
Name Abbreviation Read/Write Initial value Address
Port 6 data direction register P6DDR W H'00 H'FFB9
Port 6 data register P6DR R/W H'00 H'FFBB
Port 6 Data Direction Register (P6DDR)—H'FFB9
P6DDR is an 8-bit register that selects the direction of each pin in port 6. A pin functions as an
output pin if the corresponding bit in P6DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Bit 76543210
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
98
Port 6 Data Register (P6DR)—H'FFBB
P6DR is an 8-bit register containing the data for pins P67to P60. When the CPU reads P6DR, for
output pins (P6DDR = “1”) it reads the value in the P6DR latch, but for input pins (P6DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P6DR latch. This also applies to pins
used for input and output of timer and interrupt signals.
Pins P60, P62, P63, P64and P65: As indicated in table 5-15, these pins can be used for general-
purpose input or output, or for input of free-running timer clock and input capture signals. When a
pin is used for free-running timer input, its P6DDR bit should be cleared to “0;” otherwise the free-
running timer will receive the value in P6DR.
Pin P61: This pin can be used for general-purpose input or output, or for the output compare A
signal (FTOA) of the free-running timer. When used for FTOA output, this pin is unaffected by the
values in P6DDR and P6DR.
Pin P66: This pin can be used for general-purpose input or output, for the output compare B signal
(FTOB) of the free-running timer, or for IRQ6input. When used for FTOB output, this pin is
unaffected by the values in P6DDR and P6DR. When this pin is used for IRQ6input, P66DDR
should normally be cleared to “0,” so that the value in P6DR will not generate interrupts.
Pin P67: This pin can be used for general-purpose input or output, or IRQ7input. When it is used
for IRQ7input, P67DDR should normally be cleared to “0,” so that the value in P6DR will not
generate interrupts.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P6DDR and P6DR to all “0” and makes all pins into input port pins.
Software Standby Mode: In the software standby mode, the free-running timer control registers
are initialized but P6DDR and P6DR remain in their previous states. All pins become input or
output port pins depending on the setting of P6DDR. Output pins output the values in P6DR.
Figures 5-9 to 5-12 shows schematic diagrams of port 6.
Bit 76543210
P67P66P65P64P63P62P61P60
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
99
Figure 5-9. Port 6 Schematic Diagram (Pins P60, P62, P63, P64, and P65)
H161 '91
Fig. 5-9
P6n
RP6
Reset
Reset
WP6
WP6D
R
R
Q
Q
D
D
P6n DR
P6n DDR
C
C
Internal data bus
WP6D:
WP6:
RP6:
n = 0, 2 – 5
Write Port 6 DDR
Write Port 6
Read Port 6
Free-running
timer module
Input capture
input,
counter clock
input
100
Figure 5-10. Port 6 Schematic Diagram (Pin P61)
H161 '91
Fig. 5-10
RP6
Reset
Reset
WP6
WP6D
R
R
Q
Q
D
D
P61 DR
P61 DDR
C
C
WP6D:
WP6:
RP6:
Write Port 6 DDR
Write Port 6
Read Port 6
Free-running
timer module
Output enable
Output-compare
output
P61
Internal data bus
101
Figure 5-11. Port 6 Schematic Diagram (Pin P66)
H161 '91
Fig. 5-11
RP6
Reset
Reset
WP6
WP6D
R
R
Q
Q
D
D
P66 DR
P66 DDR
C
C
WP6D:
WP6:
RP6:
Write Port 6 DDR
Write Port 6
Read Port 6
Free-running
timer module
Output enable
Output-compare
output
P66
Internal data bus
IRQ6 enable
register
IRQ6 enable
IRQ6 input
102
Figure 5-12. Port 6 Schematic Diagram (Pin P67)
H161 '91
Fig. 5-12
P67
RP6
Reset
Reset
WP6
WP6D
R
R
Q
Q
D
D
P67 DR
P67 DDR
C
C
Internal data bus
WP6D:
WP6:
RP6:
Write Port 6 DDR
Write Port 6
Read Port 6
IRQ enable
register
IRQ7 enable
IRQ7 input
103
5.8 Port 7
Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module,
and analog output pins for the D/A converter module. The pin functions are the same in both the
expanded and single-chip modes.
Table 5-17 lists the pin functions. Table 5-18 describes the port 7 data register, which simply
consists of connections of the port 7 pins to the internal data bus. Figure 5-13 and 5-14 show
schematic diagrams of port 7.
Table 5-17. Port 7 Pin Functions (Modes 1 to 3)
Usage Pin functions
I/O port P70P71P72P73P74P75P76P77
Analog input AN0AN1AN2AN3AN4AN5AN6AN7
Analog output — — — — — — DA0DA1
Table 5-18. Port 7 Register
Name Abbreviation Read/Write Initial value Address
Port 7 data register P7DR R Undetermined H'FFBE
Port 7 Data Register (P7DR)—H'FFBE
Note: * Depends on the levels of pins P77 to P70.
Bit 76543210
P77P76P75P74P73P72P71P70
Initial value * * * * * * * *
Read/Write R R R R R R R R
104
Figure 5-13. Port 7 Schematic Diagram (Pins P70to P75)
Figure 5-14. Port 7 Schematic Diagram (Pins P76and P77)
H161 '91
Fig. 5-14
P7n
RP7: Read port 7
n = 6 or 7
A/D converter
module
Analog output
Internal data bus
RP7
Output enable
Analog input
D/A converter module
105
H161 '91
Fig. 5-13
P7n
RP7: Read port 7
n = 0 to 5
A/D converter
module
Analog input
Internal data bus
RP7
5.9 Port 8
Port 8 is a 7-bit input/output port that also provides pins for interrupt input and serial communica-
tion. Table 5-19 lists the pin functions.
Table 5-19. Port 8 Pin Functions
Pin I/O Port Serial communication Interrupt input
P80Input/output — —
P81Input/output — —
P82Input/output — —
P83Input/output — —
P84Input/output TxD1output IRQ3input
P85Input/output RxD1input IRQ4input
P86Input/output SCK1input/output IRQ5input
Pins of port 8 can drive a single TTL load and a 30pF capacitive load when they are used as output
pins. They can also drive a Darlington pair.
Table 5-20 details the port 8 registers.
Table 5-20. Port 8 Registers
Name Abbreviation Read/Write Initial value Address
Port 8 data direction register P8DDR W H'80 H'FFBD
Port 8 data register P8DR R/W H'80 H'FFBF
106
Port 8 Data Direction Register (P8DDR)—H'FFBD
P8DDR is an 8-bit register that selects the direction of each pin in port 8. A pin functions as an
output pin if the corresponding bit in P8DDR is set to “1,” and as in input pin if the bit is cleared to
“0.”
Bit 7 is reserved. It cannot be modified, and is always read as “1.”
Port 8 Data Register (P8DR)—H'FFBF
P8DR is an 8-bit register containing the data for pins P86to P80. When the CPU reads P8DR, for
output pins (P8DDR = “1”) it reads the value in the P8DR latch, but for input pins (P8DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P8DR latch. This also applies to pins
used for interrupt input and serial communication.
Bit 7 is reserved. It cannot be modified, and is always read as “1.”
Pins 80to P83:These pins are available for general-purpose input or output.
Bit 76543210
— P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Initial value 1 0 0 0 0 0 0 0
Read/Write — W W W W W W W
Bit 76543210
— P86P85P84P83P82P81P80
Initial value 1 0 0 0 0 0 0 0
Read/Write — R/W R/W R/W R/W R/W R/W R/W
107
Pin P84: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for output of serial transmit data (TxD1), or for IRQ3input. When used for TxD1output,
this pin is unaffected by the values in P8DDR and P8DR. When this pin is used for IRQ3input,
P84DDR should normally be cleared to “0,” so that the value in P8DR will not generate interrupts.
Pin P85: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for input of serial receive data (RxD1), or for IRQ4input. When used for RxD1input, this
pin is unaffected by the values in P8DDR and P8DR. When this pin is used for IRQ4input,
P85DDR should normally be cleared to “0,” so that the value in P8DR will not generate interrupts.
Pin P86: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for serial clock input or output (SCK1), or for IRQ5input. When this pin is used for IRQ5
input, P86DDR should normally be cleared to “0,” so that the value in P8DR will not generate
interrupts.
When used for SCK1input or output, this pin is unaffected by the values in P8DDR and P8DR.
Reset: A reset clears bits P86DDR to P80DDR to “0” and clears the serial control bits and interrupt
enable bits to “0,” making P86to P80into input port pins.
Hardware Standby Mode: All pins are placed in the high-impedance state.
Software Standby Mode: In the software standby mode, the serial control register is initialized,
but the interrupt enable register, P8DDR, and P8DR remain in their previous states. Pins that were
being used for serial communication revert to general-purpose input or output, depending on the
value in P8DDR. Other pins remain in their previous state. Output pins output the values in P8DR.
Figures 5-15 to 5-18 show schematic diagrams of port 8.
108
Figure 5-15. Port 8 Schematic Diagram (Pins P80to P83)
H161 '91
Fig. 5-15
P8n
RP8
Reset
Reset
WP8
WP8D
R
R
Q
Q
D
D
P8n DR
P8n DDR
C
C
Internal data bus
WP8D:
WP8:
RP8:
n = 0 to 3
Write Port 8 DDR
Write Port 8
Read Port 8
109
Figure 5-16. Port 8 Schematic Diagram (Pin P84)
H161 '91
Fig. 5-16
RP8
Reset
Reset
WP8
WP8D
R
R
Q
Q
D
D
P84 DR
P84 DDR
C
C
WP8D:
WP8:
RP8:
Write Port 8 DDR
Write Port 8
Read Port 8
SCI module
Transmit enable
Transmit data
P84
Internal data bus
IRQ enable
register
IRQ3 enable
IRQ3 input
110
Figure 5-17. Port 8 Schematic Diagram (Pin P85)
H161 '91
Fig. 5-17
RP8
Reset
WP8
R
Q D
P85 DR
C
WP8D:
WP8:
RP8:
Write Port 8 DDR
Write Port 8
Read Port 8
SCI module
Receive enable
P85
Internal data bus
IRQ enable
register
IRQ4 enable
IRQ4 input
Receive data
Reset
WP8D
R
Q D
P85 DDR
C
111
Figure 5-18. Port 8 Schematic Diagram (Pin P86)
H161 '91
Fig. 5-18
RP8
Reset
Reset
WP8
WP8D
R
R
Q
Q
D
D
P86 DR
P86 DDR
C
C
WP8D:
WP8:
RP8:
Write Port 8 DDR
Write Port 8
Read Port 8
SCI module
Clock input enable
P86
Internal data bus
IRQ enable
register
IRQ5 enable
IRQ5 input
Clock input
Clock output enable
Clock output
112
5.10 Port 9
Port 9 is an 8-bit input/output port that also provides pins for interrupt input (IRQ0to IRQ2), A/D
trigger input, system clock (Ø) output, and bus control signals (in the expanded modes).
Pins P97to P93have different functions in different modes. Pins P92to P90have the same
functions in all modes. Table 5-21 lists the pin functions.
Table 5-21. Port 9 Pin Functions
Pin Expanded modes Single-chip mode
P90P90input/output , IRQ2input, and ADTRG input (simultaneously)
P91P91input/output and IRQ1input (simultaneously)
P92P92input/output and IRQ0input (simultaneously)
P93RD output P93input/output
P94WR output P94input/output
P95AS output P95input/output
P96Ø output P96input or Ø output
P97WAIT input P97input/output
Pins of port 9 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins.
Table 5-22 details the port 9 registers.
Table 5-22. Port 9 Registers
Name Abbreviation Read/Write Initial value Address
Port 9 data direction register P9DDR W H'40 (modes 1 and 2) H'FFC0
H'00 (mode 3)
Port 9 data register P9DR R/W*1 Undetermined*2 H'FFC1
Notes: *1 Bit 6 is read-only.
*2 Bit 6 is undetermined. Other bits are initially “0.”
113
Port 9 Data Direction Register (P9DDR)—H'FFC0
P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an
output pin if the corresponding bit in P9DDR is set to “1,” and as in input pin if the bit is cleared to
“0.”
Port 9 Data Register (P9DR)—H'FFC1
Note: * Determined by the level at pin P96.
P9DR is an 8-bit register containing the data for pins P97to P90. When the CPU reads P9DR, for
output pins (P9DDR = “1”) it reads the value in the P9DR latch, but for input pins (P9DDR = “0”),
it obtains the logic level directly from the pin, bypassing the P9DR latch. This also applies to pins
used for interrupt input, A/D trigger input, clock output, and control signal input or output.
Pins P90, P91, and P92: Can be used for general-purpose input or output, interrupt request input,
or A/D trigger input. See table 5-21. If a pin is used for interrupt or A/D trigger input, its data
direction bit should be cleared to “0,” so that the output from P9DR will not generate an interrupt
request or A/D trigger signal.
Pins P93, P94, and P95: In modes 1 and 2 (the expanded modes), these pins are used for output of
the RD, WR, and AS bus control signals. They are unaffected by the values in P9DDR and P9DR.
Bit 76543210
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Modes 1 and 2
Initial value 0 1 0 0 0 0 0 0
Read/Write W — W W W W W W
Mode 3
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Bit 76543210
P97P96P95P94P93P92P91P90
Initial value 0 * 0 0 0 0 0 0
Read/Write R/W R R/W R/W R/W R/W R/W R/W
114
In mode 3 (single-chip mode), these pins can be used for general-purpose input or output.
Pin P96: In modes 1 and 2, this pin is used for system clock (Ø) output.
In mode 3, this pin is used for general-purpose input if P96DDR is cleared to “0,” or system clock
output if P96DDR is set to “1.”
Pin P97: In modes 1 and 2, this pin is used for input of the WAIT bus control signal. It is
unaffected by the values in P9DDR and P9DR.
In mode 3 (single-chip mode), this pin can be used for general-purpose input or output.
Reset: In the single-chip mode (mode 3), a reset initializes all pins of port 9 to the general-purpose
input function. In the expanded modes (modes 1 and 2), P90to P92are initialized as input port
pins, and P93to P97are initialized to their bus control and system clock output functions.
Hardware Standby Mode: All pins are placed in the high-impedance state.
115
Software Standby Mode: All pins remain in their previous state. For RD, WR, AS, and Ø this
means the High output state.
Figures 5-19 to 5-23 show schematic diagrams of port 9.
Figure 5-19. Port 9 Schematic Diagram (Pin P90)
H161 '91
Fig. 5-19
P90
RP9
Reset
Reset
WP9
WP9D
R
R
Q
Q
D
D
P90 DR
P90 DDR
C
C
Internal data bus
WP9D:
WP9:
RP9:
Write Port 9 DDR
Write Port 9
Read Port 9
IRQ enable
register
IRQ2 enable
IRQ2 input
A/D converter
module
ADTRG
116
Figure 5-20. Port 9 Schematic Diagram (Pins P91and P92)
H161 '91
Fig. 5-20
P9n
RP9
Reset
Reset
WP9
WP9D
R
R
Q
Q
D
D
P9n DR
P9n DDR
C
C
WP9D:
WP9:
RP9:
n = 1, 2
Write Port 9 DDR
Write Port 9
Read Port 9
IRQ enable
register
IRQ0 enable
IRQ1 enable
IRQ0 input
IRQ1 input
Internal data bus
117
Figure 5-21. Port 9 Schematic Diagram (Pins P93, P94, and P95)
H161 '91
Fig. 5-21
RP9
Reset
Reset
WP9
WP9D
R
R
Q
Q
D
D
P9n DR
P9n DDR
C
C
WP9D:
WP9:
RP9:
n = 3, 4, 5
Write Port 9 DDR
Write Port 9
Read Port 9
RD output
WR output
AS ouput
P9 n
Internal data bus
Hardware standby Mode 1 or 2
Mode 3
Mode 1 or 2
118
Figure 5-22. Port 9 Schematic Diagram (Pin P96)
H161 '91
Fig. 5-22
P96
RP9
Reset
WP9D
R
Q D
P96DDR
C
Internal data bus
WP9D:
WP9:
RP9:
Note: Set-priority *
Write Port 9 DDR
Write Port 9
Read Port 9
Hardware standby Mode 1, 2
*
Ø
S
119
Figure 5-23. Port 9 Schematic Diagram (Pin P97)
H161 '91
Fig. 5-23
P97
RP9
Reset
Reset
WP9
WP9D
R
R
Q
Q
D
D
P97 DR
P97DDR
C
C
Internal data bus
WP9D:
WP9:
RP9:
Write Port 9 DDR
Write Port 9
Read Port 9
Mode 1 or 2
WAIT input
120
Section 6. 16-Bit Free-Running Timer
6.1 Overview
The H8/338 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-
running counter as a time base. Applications of the FRT module include rectangular-wave output
(up to two independent waveforms), input pulse width measurement, and measurement of external
clock periods.
6.1.1 Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
The free-running counter can be driven by an internal clock source (Ø/2, Ø/8, or Ø/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
Each comparator can generate an independent waveform.
• Four input capture channels
The current count can be captured on the rising or falling edge (selectable) of an input signal.
The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
Compare-match A and B, input capture A to D, and overflow interrupts are requested
independently.
121
6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the free-running timer.
Figure 6-1. Block Diagram of 16-Bit Free-Running Timer
External
clock source
Internal
clock sources
Clock select
Comparator A
OCRA (H/L)
Comparator B
OCRB (H/L)
Bus interface
Internal
data bus
Ø/2
Ø/8
Ø/32
FTCI
Compare-
Clear
Clock
FTOA
FTOB
Overflow
ICRA (H/L)
match A
Compare-
match B
Capture
FRC (H/L)
TCSR
FTIA
FTIB
FTIC
FTID
Control
logic
Module data bus
TIER
TCR
TOCR
OCIB
OCIA
FOVI
Interrupt signals
ICIA
ICIB
ICIC
ICID
FRC:
OCRA, B:
ICRA, B, C, D:
TCSR:
Free-Running Counter (16 bits)
Output Compare Register A, B (16 bits)
Input Capture Register A, B, C, D (16 bits)
Timer Control/Status Register (8 bits)
TIER:
TCR:
TOCR:
Timer Interrupt Enable Register (8 bits)
Timer Control Register (8 bits)
Timer Output Compare Control
Register (8 bits)
ICRB (H/L)
ICRC (H/L)
ICRD (H/L)
122
6.1.3 Input and Output Pins
Table 6-1 lists the input and output pins of the free-running timer module.
Table 6-1. Input and Output Pins of Free-Running Timer Module
6.1.4 Register Configuration
Table 6-2 lists the registers of the free-running timer module.
Table 6-2. Register Configuration
Notes: *1 Software can write a “0” to clear bits 7 to 1, but cannot write a “1” in these bits.
*2 OCRA and OCRB share the same addresses. Access is controlled by the OCRS
bit in TOCR.
Name Abbreviation I/O Function
Counter clock input FTCI Input Input of external free-running counter clock
signal
Output compare A FTOA Output Output controlled by comparator A
Output compare B FTOB Output Output controlled by comparator B
Input capture A FTIA Input Trigger for capturing current count into input
capture register A
Input capture B FTIB Input Trigger for capturing current count into input
capture register B
Input capture C FTIC Input Trigger for capturing current count into input
capture register C
Input capture D FTID Input Trigger for capturing current count into input
capture register D
Initial
Name Abbreviation R/W value Address
Timer interrupt enable register TIER R/W H'01 H'FF90
Timer control/status register TCSR R/(W)*1 H'00 H'FF91
Free-running counter (High) FRC (H) R/W H'00 H'FF92
Free-running counter (Low) FRC (L) R/W H'00 H'FF93
Output compare register A/B (High)*2 OCRA/B (H) R/W H'FF H'FF94*2
Output compare register A/B (Low)*2 OCRA/B (L) R/W H'FF H'FF95*2
Timer control register TCR R/W H'00 H'FF96
Timer output compare control register TOCR R/W H'E0 H'FF97
Input capture register A (High) ICRA (H) R H'00 H'FF98
Input capture register A (Low) ICRA (L) R H'00 H'FF99
123
Table 6-2. Register Configuration (cont.)
6.2 Register Descriptions
6.2.1 Free-Running Counter (FRC)—H'FF92
The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written
or read. See section 6.3, “CPU Interface,” for details.
The FRC is initialized to H'0000 at a reset and in the standby modes. It can also be cleared by
compare-match A.
Initial
Name Abbreviation R/W value Address
Input capture register B (High) ICRB (H) R H'00 H'FF9A
Input capture register B (Low) ICRB (L) R H'00 H'FF9B
Input capture register C (High) ICRC (H) R H'00 H'FF9C
Input capture register C (Low) ICRC (L) R H'00 H'FF9D
Input capture register D (High) ICRD (H) R H'00 H'FF9E
Input capture register D (Low) ICRD (L) R H'00 H'FF9F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
124
6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TOCR) is set to “1,” when the output compare register and FRC values match, the logic level
selected by the output level bit (OLVLA or OLVLB) in the TOCR is output at the output compare
pin (FTOA or FTOB).
OCRA and OCRB share the same address. They are differentiated by the OCRS bit in the TOCR.
A temporary register (TEMP) is used for write access, as explained in
section 6.3, “CPU Interface.”
OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes.
6.2.3 Input Capture Registers A to D (ICRA to ICRD)—H'FF98, H'FF9A, H'FF9C, H'FF9E
Each input capture register is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the
current value of the FRC is copied to the corresponding input capture register (ICRA to ICRD).*
At the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to “1.” The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer control register (TCR).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
value
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value
Read/ R R R R R R R R R R R R R R R R
Write
125
Note: * The FRC contents are transferred to the input capture register regardless of the value of
the input capture flag (ICFA/B/C/D).
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as shown
in figure 6-2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and
the new FRC count is copied into ICRA.
Figure 6-2. Input Capture Buffering
Similarly, when the BUFEB bit in TIER is set to “1,” ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠IEDGD), then input capture is triggered on both the rising and falling edges of
the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge.
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Buffer Enable A
Input Edge Select A
Input Edge Select C
Input Capture Register C
Input Capture Register A
Free-Running Counter
BUFEA
IEDGA
IEDGC
FTIA
Edge detect and
capture signal
generating circuit
FRC
ICRC
ICRA
Fig. 6-2
126
Table 6-3. Buffered Input Capture Edge Selection (Example)
IEDGA IEDGC Input capture edge
0 0 Captured on falling edge of input capture A (FTIA) (Initial value)
0 1 Captured on both rising and falling edges of input capture A (FTIA)
1 0
1 1 Captured on rising edge of input capture A (FTIA)
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when
they are read. See section 6.3, “CPU Interface,” for details.
To ensure input capture, the width of the input capture pulse (FTIA, FTIB, FTIC, FTID) should be
at least 1.5 system clock periods (1.5·Ø). When triggering is enabled on both edges, the input
capture pulse width should be at least 2.5 system clock periods.
Figure 6-3. Minimum Input Capture Pulse Width
Ø
FTIA, FTIB,
FTIC, or FTID
127
The input capture registers are initialized to H'0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the input capture register
even if the input capture flag is already set.
6.2.4 Timer Interrupt Enable Register (TIER)—H'FF90
The TIER is an 8-bit readable/writable register that enables and disables interrupts.
The TIER is initialized to H'01 (all interrupts disabled) at a reset and in the standby modes.
Bit 7—Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to “1.”
Bit 6—Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in the timer status/control register
(TCSR) is set to “1.”
Bit 5—Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in the timer status/control register
(TCSR) is set to “1.”
Bit 76543210
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE —
Initial value 0 0 0 0 0 0 0 1
Read/Write R/W R/W R/W R/W R/W R/W R/W —
Bit 7
ICIAE Description
0 Input capture interrupt request A (ICIA) is disabled. (Initial value)
1 Input capture interrupt request A (ICIA) is enabled.
Bit 6
ICIBE Description
0 Input capture interrupt request B (ICIB) is disabled. (Initial value)
1 Input capture interrupt request B (ICIB) is enabled.
128
Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register
(TCSR) is set to “1.”
Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control
register (TCSR) is set to “1.”
Bit 2—Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control
register (TCSR) is set to “1.”
Bit 1—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
Bit 5
ICICE Description
0 Input capture interrupt request C (ICIC) is disabled. (Initial value)
1 Input capture interrupt request C (ICIC) is enabled.
Bit 4
ICIDE Description
0 Input capture interrupt request D (ICID) is disabled. (Initial value)
1 Input capture interrupt request D (ICID) is enabled.
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled. (Initial value)
1 Output compare interrupt request A (OCIA) is enabled.
Bit 2
OCIBE Description
0 Output compare interrupt request B (OCIB) is disabled. (Initial value)
1 Output compare interrupt request B (OCIB) is enabled.
129
Bit 0—Reserved: This bit cannot be modified and is always read as “1.”
6.2.5 Timer Control/Status Register (TCSR)—H'FF91
The TCSR is an 8-bit readable and partially writable* register that contains the seven interrupt flags
and specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
Note: * Software can write a “0” in bits 7 to 1 to clear the flags, but cannot write a “1” in these
bits.
The TCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to “1” to flag an input capture A
event. If BUFEA = “0,” ICFA indicates that the FRC value has been copied to ICRA. If BUFEA =
“1,” ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value
has been copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled. (Initial value)
1 Timer overflow interrupt request (FOVI) is enabled.
Bit 76543210
ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
Initial value 0 0 0 0 0 0 0 0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W
Bit 7
ICFA Description
0 To clear ICFA, the CPU must read ICFA after it (Initial value)
has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when an FTIA input signal causes the FRC
value to be copied to ICRA.
130
Bit 6—Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B
event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB =
“1,” ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value
has been copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5—Input Capture Flag C (ICFC): This status bit is set to “1” to flag input of a rising or
falling edge of FTIC as selected by the IEDGC bit. When BUFEA = “0,” this indicates capture of
the FRC count in ICRC. When BUFEA = “1,” however, the FRC count is not captured, so ICFC
becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a
general-purpose interrupt signal (which can be enabled or disabled by the ICICE bit).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4—Input Capture Flag D (ICFD): This status bit is set to “1” to flag input of a rising or
falling edge of FTID as selected by the IEDGD bit. When BUFEB = “0,” this indicates capture of
the FRC count in ICRD. When BUFEB = “1,” however, the FRC count is not captured, so ICFD
becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a
general-purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB Description
0 To clear ICFB, the CPU must read ICFB after it (Initial value)
has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when an FTIB input signal causes the FRC value
to be copied to ICRB.
Bit 5
ICFC Description
0 To clear ICFC, the CPU must read ICFC after it (Initial value)
has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when an FTIC input signal is received.
131
Bit 3—Output Compare Flag A (OCFA): This status flag is set to “1” when the FRC value
matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 2—Output Compare Flag B (OCFB): This status flag is set to “1” when the FRC value
matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 1—Timer Overflow Flag (OVF): This status flag is set to “1” when the FRC overflows
(changes from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 4
ICFD Description
0 To clear ICFD, the CPU must read ICFD after it (Initial value)
has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when an FTID input signal is received.
Bit 3
OCFA Description
0 To clear OCFA, the CPU must read OCFA after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when FRC = OCRA.
Bit 2
OCFB Description
0 To clear OCFB, the CPU must read OCFB after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when FRC = OCRB.
Bit 1
OVF Description
0 To clear OVF, the CPU must read OVF after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when FRC changes from H'FFFF to H'0000.
132
Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
6.2.6 Timer Control Register (TCR)—H'FF96
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized on
the selected edge of the input capture A signal (FTIA).
Bit 6—Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized on
the selected edge of the input capture B signal (FTIB).
Bit 0
CCLRA Description
0 The FRC is not cleared. (Initial value)
1 The FRC is cleared at compare-match A.
Bit 76543210
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
IEDGA Description
0 Input capture A events are recognized on the falling edge of FTIA. (Initial value)
1 Input capture A events are recognized on the rising edge of FTIA.
Bit 6
IEDGB Description
0 Input capture B events are recognized on the falling edge of FTIB. (Initial value)
1 Input capture B events are recognized on the rising edge of FTIB.
133
Bit 5—Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on
the selected edge of the input capture C signal (FTIC).
Bit 4—Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized on
the selected edge of the input capture D signal (FTID).
Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 5
IEDGC Description
0 Input capture C events are recognized on the falling edge of FTIC. (Initial value)
1 Input capture C events are recognized on the rising edge of FTIC.
Bit 4
IEDGD Description
0 Input capture D events are recognized on the falling edge of FTID. (Initial value)
1 Input capture D events are recognized on the rising edge of FTID.
Bit 3
BUFEA Description
0 ICRC is used for input capture C. (Initial value)
1 ICRC is used as a buffer register for input capture A. Input C is not captured.
Bit 2
BUFEB Description
0 ICRD is used for input capture D. (Initial value)
1 ICRD is used as a buffer register for input capture B. Input D is not captured.
134
6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97
The TOCR is an 8-bit readable/writable register that controls the output compare function.
The TOCR is initialized to H'E0 at a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as “1.”
Bit 4—Output Compare Register Select (OCRS): When the CPU accesses addresses H'FF94
and H'FF95, this bit directs the access to either OCRA or OCRB. These two registers share the
same addresses as follows:
Upper byte of OCRA and upper byte of OCRB: H'FF94
Lower byte of OCRA and lower byte of OCRB: H'FF95
Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA).
Bit 1 Bit 0
CKS1 CKS0 Description
0 0 Ø/2 Internal clock source (Initial value)
0 1 Ø/8 Internal clock source
1 0 Ø/32 Internal clock source
1 1 External clock source (rising edge)
Bit 76543210
— — — OCRS OEA OEB OLVLA OLVLB
Initial value 1 1 1 0 0 0 0 0
Read/Write — — — R/W R/W R/W R/W R/W
Bit 4
OCRS Description
0 The CPU can access OCRA. (Initial value)
1 The CPU can access OCRB.
Bit 3
OEA Description
0 Output compare A output is disabled. (Initial value)
1 Output compare A output is enabled.
135
Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B
signal (FTOB).
Bit 1—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 0—Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
6.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture
registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When
the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the
access is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows:
• Register Write
When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when
the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16
bits are written in the register simultaneously.
Bit 2
OEB Description
0 Output compare B output is disabled. (Initial value)
1 Output compare B output is enabled.
Bit 1
OLVLA Description
0 A “0” logic level (Low) is output for compare-match A. (Initial value)
1 A “1” logic level (High) is output for compare-match A.
Bit 0
OLVLB Description
0 A “0” logic level (Low) is output for compare-match B. (Initial value)
1 A “1” logic level (High) is output for compare-match B.
136
• Register Read
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte
is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
(As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes
directly, without using TEMP.)
Programs that access these registers should normally use word access. Equivalently, they may
access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be
transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed.
Coding Examples
To write the contents of general register R0 to OCRA:
MOV.W R0, @OCRA
To transfer the contents of ICRA to general register R0: MOV.W @ICRA, R0
Figure 6-4 shows the data flow when the FRC is accessed. The other registers are accessed in the
same way.
Figure 6-4 (a). Write Access to FRC (when CPU Writes H'AA55)
Module data bus
(1) Upper byte write
Bus interface
CPU writes
data H'AA
FRC H
[ ]
FRC L
[ ]
TEMP
[H'AA]
(2) Lower byte write
Bus interface
Module data bus
CPU writes
data H'55
TEMP
[H'AA]
FRC H
[H'AA]
FRC L
[H'55]
H161 H8/337 '91
Fig. 6-4 (a)
137
Figure 6-4 (b). Read Access to FRC (when FRC Contains H'AA55)
6.4 Operation
6.4.1 FRC Incrementation Timing
The FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source. The clock source is selected by bits CKS0 and CKS1 in the TCR.
Internal Clock: The internal clock sources (Ø/2, Ø/8, Ø/32) are created from the system clock (Ø)
by a prescaler. The FRC increments on a pulse generated from the falling edge of the prescaler
output. See figure 6-5.
(1) Upper byte read
Bus interface
Module data bus
CPU reads
data H'AA
TEMP
[H'55]
FRC H
[H'AA]
FRC L
[H'55]
(2) Lower byte read
Bus interface
Module data bus
CPU reads
data H'55
TEMP
[H'55]
FRC H
[ ]
FRC L
[ ]
Fig. 6-4 (b)
138
Figure 6-5. Increment Timing for Internal Clock Source
External Clock: If external clock input is selected, the FRC increments on the rising edge of the
FTCI clock signal. Figure 6-6 shows the increment timing.
The pulse width of the external clock signal must be at least 1.5 system clock (Ø) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 6-6. Increment Timing for External Clock Source
Figure 6-7. Minimum External Clock Pulse Width
Ø
Internal
clock
FRC clock
pulse
FRC
N – 1
N
N + 1
Fig. 6-5
N
N + 1
Ø
FTCI
FRC
FRC clock pulse
Ø
FTCI
139
6.4.2 Output Compare Timing
(1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags
are set to “1” by an internal compare-match signal generated when the FRC value matches the
OCRA or OCRB value. This compare-match signal is generated at the last state in which the two
values match, just before the FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 6-8 shows the timing of the setting of the output
compare flags.
Figure 6-8. Setting of Output Compare Flags
N
N
N + 1
Ø
FRC
OCRA or OCRB
Internal compare-
match signal
OCFA or OCFB
Fig. 6-8
OCRA or OCRB
140
(2) Output Timing: When a compare-match occurs, the logic level selected by the output level
bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB).
Figure 6-9 shows the timing of this operation for compare-match A.
Figure 6-9. Timing of Output Compare A
(3) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared when
compare-match A occurs. Figure 6-10 shows the timing of this operation.
Figure 6-10. Clearing of FRC by Compare-Match A
6.4.3 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 6-11 shows the usual input capture timing when the rising edge is
selected (IEDGx = “1”).
Ø
Internal compare-
match A signal
OLVLA
FTOA
Note: *Cleared by software
FRC
OCRA
N
N
N
N + 1
Clear*
N
N + 1
Figure 6-9
Ø
Internal compare-
match A signal
FRC
N
H'0000
141
Figure 6-11. Input Capture Timing (Usual Case)
If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives,
the internal input capture signal is delayed by one state. Figure 6-12 shows the timing for this case.
Figure 6-12. Input Capture Timing (1-State Delay)
In buffer mode, this delay occurs if the CPU is reading either of the two registers concerned. When
ICRA and ICRC are used in buffer mode, for example, if the upper byte of either ICRA or ICRC is
being read when the FTIA input arrives, the internal input capture signal is delayed by one state.
Figure 6-13 shows the timing for this case. The case of ICRB and ICRD is similar.
Figure 6-13. Input Capture Timing (1-State Delay, Buffer Mode)
Ø
Input at FTI pin
Internal input
capture signal
Read cycle: CPU reads upper byte of ICR
T
1
T
2
T
3
Ø
Input at FTI pin
Internal input
capture signal
Figure 6-13
T
T
T
Read cycle: CPU reads upper byte of ICRA or ICRC
Ø
Input at
FTIA pin
Internal input
capture signal
1
2
3
Figure 6-14
142
Figure 6-14 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Figure 6-14. Buffered Input Capture with Both Edges Selected
In this mode, input capture does not cause the FRC contents to be copied to ICRC. However, input
capture flag C still sets on the input capture edge selected by IEDGC, and if the interrupt enable bit
(ICICE) is set, a CPU interrupt is requested.
The situation when ICRB and ICRD are used in buffer mode is similar.
N
N + 1
n
n + 1
n
M
M
m
N
n
n
M
Ø
FTIA
Internal input
capture signal
FRC
ICRA
ICRC
Figure 6-15
143
(2) Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx (x = A, B, C, D) is
set to “1” by the internal input capture signal. Figure 6-15 shows the timing of this operation.
Figure 6-15. Setting of Input Capture Flag
6.4.4 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from H'FFFF to
H'0000). Figure 6-16 shows the timing of this operation.
Figure 6-16. Setting of Overflow Flag (OVF)
OVF
Ø
FRC
Internal overflow
signal
H'FFFF H'0000
Ø
Internal input
capture signal
ICF
FRC
ICR
N
N
144
6.5 Interrupts
The free-running timer can request seven types of interrupts: input capture A to D (ICIA, ICIB,
ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is
requested when the corresponding enable and flag bits are set. Independent signals are sent to the
interrupt controller for each type of interrupt. Table 6-4 lists information about these interrupts.
Table 6-4. Free-Running Timer Interrupts
6.6 Sample Application
In the example below, the free-running timer is used to generate two square-wave outputs with a
50% duty cycle and arbitrary phase relationship. The programming is as follows:
(1) The CCLRA bit in the TCSR is set to “1.”
(2) Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
Figure 6-17. Square-Wave Output (Example)
Interrupt Description Priority
ICIA Requested when ICFA and ICIAE are set High
ICIB Requested when ICFB and ICIBE are set
ICIC Requested when ICFC and ICICE are set
ICID Requested when ICFD and ICIDE are set
OCIA Requested when OCFA and OCIAE are set
OCIB Requested when OCFB and OCIBE are set
FOVI Requested when OVF and OVIE are set Low
FRC
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Clear counter
145
6.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timers.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 6-18 shows this type of contention.
Figure 6-18. FRC Write-Clear Contention
Write cycle: CPU write to lower byte of FRC
FRC address
N
H'0000
T1
T2
T3
Ø
Internal address bus
Internal write signal
FRC clear signal
FRC
Figure 6-21
146
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3state of a write cycle to the lower byte of the free-running counter, the write takes
priority and the FRC is not incremented.
Figure 6-19 shows this type of contention.
Figure 6-19. FRC Write-Increment Contention
Write cycle: CPU write to lower byte of FRC
FRC address
Ø
Internal address bus
Internal write signal
FRC clock pulse
FRC
N
M
T
T
T
Write data
1
2
3
Figure 6-22
147
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T3state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
compare-match signal is inhibited.
Figure 6-20 shows this type of contention.
Figure 6-20. Contention between OCR Write and Compare-Match
Write cycle: CPU write to lower byte of OCRA or OCRB
OCR address
N
N + 1
N
M
Inhibited
Write data
Ø
Internal address bus
Internal write signal
Compare-match
A or B signal
OCRA or OCRB
FRC
T
1
T
T
2
3
148
(4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the FRC to increment. This depends on the time at
which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 6-5.
The pulse that increments the FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is High and the new source is Low, as in case No. 3
in table 6-5, the changeover generates a falling edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock source can also cause the FRC to increment.
Table 6-5. Effect of Changing Internal Clock Sources
No. Description Timing chart
Low
→ Low:
CKS1 and CKS0 are
1 rewritten while both
clock sources are Low.
Low → High:
CKS1 and CKS0 are
2 rewritten while old
clock source is Low and
new clock source is High.
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N
N + 1
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N
N + 1
N + 2
149
Table 6-5. Effect of Changing Internal Clock Sources (cont.)
Note: * The switching of clock sources is regarded as a falling edge that increments the FRC.
No. Description Timing chart
High → Low:
CKS1 and CKS0 are
3 rewritten while old
clock source is High and
new clock source is Low.
High → High:
CKS1 and CKS0 are
4 rewritten while both
clock sources are High.
Old clock
source
New clock
source
FRC clock
pulse
FRC
N
N + 1
CKS rewrite
N + 2
Old clock
source
New clock
source
FRC clock
pulse
FRC
N
N + 1
N + 2
CKS rewrite
*
Figure 6-4-3
150
Section 7. 8-Bit Timers
7.1 Overview
The H8/338 Series includes an 8-bit timer module with two channels (TMR0 and TMR1). Each
channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that
are constantly compared with the TCNT value to detect compare-match events. One application of
the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle.
7.1.1 Features
The features of the 8-bit timer module are listed below.
• Selection of seven clock sources
The counters can be driven by one of six internal clock signals or an external clock input
(enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two time constants
The timer output signal in each channel is controlled by two independent time constants,
enabling the timer to generate output waveforms with an arbitrary duty factor.
• Three independent interrupts
Compare-match A and B and overflow interrupts can be requested independently.
7.1.2 Block Diagram
Figure 7-1 shows a block diagram of one channel in the 8-bit timer module. The other channel is
identical.
151
Figure 7-1. Block Diagram of 8-Bit Timer
7.1.3 Input and Output Pins
Table 7-1 lists the input and output pins of the 8-bit timer.
Table 7-1. Input and Output Pins of 8-Bit Timer
H161 H8/337 H.M '91
Fig. 7-1
External
clock source
TMCI
TMO
TMRI
Internal
clock sources Channel 0 Channel 1
Ø/2
Ø/8
Ø/32
Ø/64
Ø/256
Ø/1024
Ø/2
Ø/8
Ø/64
Ø/128
Ø/1024
Ø/2048
Clock
Overflow
Clear
Compare-match B
Control
logic
Clock select TCORA
Comparator A
TCNT
Comparator B
TCORB
TCSR
TCR
Module data bus
Bus interface
Internal
data bus
CMIA
CMIB
OVI
Interrupt signals
TCR:
TCSR:
TCORA:
TCORB:
TCNT:
Timer Control Register (8 bits)
Timer Control Status Register (8 bits)
Time Constant Register A (8 bits)
Time Constant Register B (8 bits)
Timer Counter
Compare-match A
Abbreviation
Name TMR0 TMR1 I/O Function
Timer output TMO0TMO1Output Output controlled by compare-match
Timer clock input TMCI0TMCI1Input External clock source for the counter
Timer reset input TMRI0TMRI1Input External reset signal for the counter
152
7.1.4 Register Configuration
Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of
registers.
Table 7-2. 8-Bit Timer Registers
Note: * Software can write a “0” to clear bits 7 to 5, but cannot write a “1” in these bits.
7.2 Register Descriptions
7.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1)
Bit 76543210
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an
internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer
control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Address
Name Abbreviation R/W Initial value TMR0 TMR1
Timer control register TCR R/W H'00 H'FFC8 H'FFD0
Timer control/status register TCSR R/(W)* H'10 H'FFC9 H'FFD1
Timer constant register A TCORA R/W H'FF H'FFCA H'FFD2
Timer constant register B TCORB R/W H'FF H'FFCB H'FFD3
Timer counter TCNT R/W H'00 H'FFCC H'FFD4
Serial/timer control register STCR R/W H'F8 H'FFD0 H'FFC3
153
The timer counters are initialized to H'00 at a reset and in the standby modes.
Bit 76543210
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 76543210
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
154
7.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFCA and H'FFCB
(TMR0), H'FFD2 and H'FFD3 (TMR1)
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO0 or TMO1) is controlled by these compare-match signals as
specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H'FF at a reset and in the standby modes.
Compare-match is not detected during the T3state of a write cycle to TCORA or TCORB. See
item (3) in section 7.6, “Application Notes.”
7.2.3 Timer Control Register (TCR)—H'FFC8 (TMR0), H'FFD0 (TMR1)
Each TCR is an 8-bit readable/writable register that selects the clock source and the time at which
Bit 7
CMIEB Description
0 Compare-match interrupt request B (CMIB) is disabled. (Initial value)
1 Compare-match interrupt request B (CMIB) is enabled.
Bit 6
CMIEA Description
0 Compare-match interrupt request A (CMIA) is disabled. (Initial value)
1 Compare-match interrupt request A (CMIA) is enabled.
Bit 5
OVIE Description
0 The timer overflow interrupt request (OVI) is disabled. (Initial value)
1 The timer overflow interrupt request (OVI) is enabled.
Bit 4 Bit 3
CCLR1 CCLR0 Description
0 0 Not cleared. (Initial value)
0 1 Cleared on compare-match A.
1 0 Cleared on compare-match B.
1 1 Cleared on rising edge of external reset input signal.
155
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and
ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the
timer counter. Six internal clock sources, derived by prescaling the system clock, are available for
each timer channel. For internal clock sources the counter is incremented on the falling edge of the
internal clock. For an external clock source, these bits can select whether to increment the counter
on the rising or falling edge of the clock input, or on both edges.
TCR STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 0 — — No clock source (timer stopped) (Initial value)
0 0 1 — 0 Ø/8 internal clock, counted on falling edge
0 0 1 — 1 Ø/2 internal clock, counted on falling edge
0 1 0 — 0 Ø/64 internal clock, counted on falling edge
0 1 0 — 1 Ø/32 internal clock, counted on falling edge
0 1 1 — 0 Ø/1024 internal clock, counted on falling edge
0 1 1 — 1 Ø/256 internal clock, counted on falling edge
1 0 0 — — No clock source (timer stopped)
1 0 1 — — External clock source, counted on rising edge
1 1 0 — — External clock source, counted on falling edge
1 1 1 — — External clock source, counted on both rising
and falling edges
1 0 0 0 — — No clock source (timer stopped) (Initial value)
0 0 1 0 — Ø/8 internal clock, counted on falling edge
0 0 1 1 — Ø/2 internal clock, counted on falling edge
0 1 0 0 — Ø/64 internal clock, counted on falling edge
0 1 0 1 — Ø/128 internal clock, counted on falling edge
0 1 1 0 — Ø/1024 internal clock, counted on falling edge
0 1 1 1 — Ø/2048 internal clock, counted on falling edge
1 0 0 — — No clock source (timer stopped)
1 0 1 — — External clock source, counted on rising edge
1 1 0 — — External clock source, counted on falling edge
1 1 1 — — External clock source, counted on both rising
and falling edges
156
the timer counter is cleared, and enables interrupts.
The TCRs are initialized to H'00 at a reset and in the standby modes.
For timing diagrams, see section 7.3, “Operation.”
Bit 7—Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to “1.”
Bit 76543210
CMFB CMFA OVF — OS3 OS2 OS1 OS0
Initial value 0 0 0 1 0 0 0 0
Read/Write R/(W)* R/(W)* R/(W)* — R/W R/W R/W R/W
Bit 7
CMFB Description
0 To clear CMFB, the CPU must read CMFB after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when TCNT = TCORB.
Bit 6
CMFA Description
0 To clear CMFA, the CPU must read CMFA after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when TCNT = TCORA.
157
Bit 6—Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
control/status register (TCSR) is set to “1.”
Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR)
is set to “1.”
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input.
Bit 5
OVF Description
0 To clear OVF, the CPU must read OVF after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 3 Bit 2
OS3 OS2 Description
0 0 No change when compare-match B occurs. (Initial value)
0 1 Output changes to “0” when compare-match B occurs.
1 0 Output changes to “1” when compare-match B occurs.
1 1 Output inverts (toggles) when compare-match B occurs.
Bit 1 Bit 0
OS1 OS0 Description
0 0 No change when compare-match A occurs. (Initial value)
0 1 Output changes to “0” when compare-match A occurs.
1 0 Output changes to “1” when compare-match A occurs.
1 1 Output inverts (toggles) when compare-match A occurs.
158
7.2.5 Serial/Timer Control Register (STCR)—H'FFC3
Bit 76543210
— — — — — MPE ICKS1 ICKS0
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — R/W R/W R/W
The STCR is an 8-bit readable/writable register that controls the serial communication interface
and selects internal clock sources for the timer counters.
The STCR is initialized to H'F8 at a reset.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as “1.”
Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of serial communication
interfaces 0 and 1. For details, see section 9, “Serial Communication Interface.”
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits
CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see
section 7.2.3, “Timer Control Register.”
159
7.2.4 Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1)
Note: * Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these
bits.
The TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
The TCSR is initialized to H'10 at a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to “1” when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to “1” when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Figure 7-2
Ø
N–1 N+1N
Internal
clock
TCNT clock
pulse
TCNT
160
Bit 5—Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 4—Reserved: This bit is always read as “1.” It cannot be written.
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match
events on the timer output signal (TCOR or TCNT). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
External clock
source
TCNT clock
pulse
TCNT
N
N + 1
Ø
N – 1
Ø
TMCI
Ø
TMCI
Minimum TMCI Pulse Width
(Single-Edge Incrementation)
Minimum TMCI Pulse Width
(Double-Edge Incrementation)
161
If compare-match A and B occur simultaneously, any conflict is resolved as explained in item (4) in
section 7.6, “Application Notes.”
After a reset, the timer output is “0” until the first compare-match event.
When all four output select bits are cleared to “0” the timer output signal is disabled.
TCNT
TCOR
Internal
compare-match
signal
CMF
N
N + 1
N
Ø
Figure 7-5
Ø
Internal
compare-match
A signal
Timer output
(TMO)
162
7.3 Operation
7.3.1 TCNT Incrementation Timing
The timer counter increments on a pulse generated once for each period of the selected (internal or
external) clock source.
Internal Clock: Internal clock sources are created from the system clock by a prescaler. The
counter increments on an internal TCNT clock pulse generated from the falling edge of the
prescaler output, as shown in figure 7-2. Bits CKS2 to CKS0 of the TCR and bits ICKS1 and
ICKS0 of the STCR can select one of the six internal clocks.
Figure 7-2. Count Timing for Internal Clock Input
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the
rising edge, the falling edge, or both edges of the external clock signal. Figure 7-3 shows
incrementation on both edges of the external clock signal.
The external clock pulse width must be at least 1.5 system clock periods for incrementation on a
N
H'00
Internal
compare-match
signal
TCNT
ø
Ø
External reset
input (TMRI)
Internal clear
pulse
TCNT
N
N – 1
H'00
ø
Ø
163
single edge, and at least 2.5 system clock periods for incrementation on both edges. See
figure 7-4. The counter will not increment correctly if the pulse width is shorter than these values.
H'00
TCNT
Internal overflow
signal
OVF
H'FF
ø
Ø
164
Figure 7-3. Count Timing for External Clock Input
Figure 7-4. Minimum External Clock Pulse Widths (Example)
7.3.2 Compare Match Timing
(1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags
are set to “1” by an internal compare-match signal generated when the timer count matches the time
constant in TCNT or TCOR. The compare-match signal is generated at the last state in which the
match is true, just before the timer counter increments to a new value.
Interrupt Description Priority
CMIA Requested when CMFA and CMIEA are set High
CMIB Requested when CMFB and CMIEB are set
OVI Requested when OVF and OVIE are set Low
H'FF
TCORA
TCORB
H'00
TMO pin
Clear counter
TCNT
Figure 7-10
165
Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting
of the compare-match flags.
Figure 7-5. Setting of Compare-Match Flags
(2) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)
changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits,
the output can remain the same, change to “0,” change to “1,” or toggle.
Figure 7-6 shows the timing when the output is set to toggle on compare-match A.
Figure 7-6. Timing of Timer Output
Ø
Internal Address
bus
Internal write
signal
Counter clear
signal
TCNT
N
H'00
TCNT address
Write cycle: CPU writes to TCNT
T1
T2
T3
Figure 7-11
166
(3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR,
the timer counter can be cleared when compare-match A or B occurs. Figure 7-7 shows the timing
of this operation.
Figure 7-7. Timing of Compare-Match Clear
7.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in the TCR are both set to “1,” the timer counter is cleared on
the rising edge of an external reset input. Figure 7-8 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock periods.
Figure 7-8. Timing of External Reset
Ø
Internal Address
bus
Internal write
signal
TCNT clock
pulse
TCNT
N
M
TCNT address
Write cycle: CPU writes to TCNT
T1
Write data
T2
T3
Figure 7-12
167
7.3.4 Setting of TCSR Overflow Flag (OVF)
The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H'FF to
H'00). Figure 7-9 shows the timing of this operation.
Figure 7-9. Setting of Overflow Flag (OVF)
Ø
Internal address
bus
Internal write
signal
TCNT
N
M
TCOR address
Write cycle: CPU writes to TCORA or TCORB
N
N + 1
TCORA or
TCORB
Compare-match
A or B signal
T1
Inhibited
TCOR write data
Figure 7-13
T2
T3
Output selection Priority
Toggle High
“1” Output
“0” Output
No change Low
168
7.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 7-3 lists information about these interrupts.
Table 7-3. 8-Bit Timer Interrupts
7.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle.
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to “0” and CCLR0 is set to “1” so that the timer counter is
cleared when its value matches the constant in TCORA.
No. Description Timing chart
Low
→ Low*1:
Clock select bits are
1 rewritten while both
clock sources are Low.
Low → High*2:
Clock select bits are
2 rewritten while old
clock source is Low and
new clock source is High.
N + 1
N
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N + 1
N
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N + 2
169
(2) In the TCSR, bits OS3 to OS0 are set to “0110,” causing the output to change to “1” on
compare-match A and to “0” on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
Figure 7-10. Example of Pulse Output
7.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit
timer.
(1) Contention between TCNT Write and Clear: If an internal counter clear signal is generated
during the T3state of a write cycle to the timer counter, the clear signal takes priority and the write
is not performed.
Figure 7-11 shows this type of contention.
No. Description Timing chart
High → Low*1:
Clock select bits are
3 rewritten while old
clock source is High and
new clock source is Low.
High → High:
Clock select bits are
4 rewritten while both
clock sources are High.
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N
N + 1
N + 2
*
3
*2
N + 1
N
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N + 2
170
Section 8. PWM Timers
8.1 Overview
The H8/338 Series has an on-chip pulse-width modulation (PWM) timer module with two
independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM
channel generates a rectangular output pulse with a duty cycle of 0 to 100%. The duty cycle is
specified in an 8-bit duty register (DTR).
8.1.1 Features
The PWM timer module has the following features:
• Selection of eight clock sources
• Duty cycles from 0 to 100% with 1/250 resolution
• Output with positive or negative logic and software enable/disable control
8.1.2 Block Diagram
Figure 8-1 shows a block diagram of one PWM timer channel.
Figure 8-1. Block Diagram of PWM Timer
Comparator
DTR
Bus interface
Internal
data bus
Pulse
TCR
TCNT
Compare-match
Ø/2
Ø/8
Ø/32
Ø/128
Ø/256
Ø/1024
Ø/2048
Ø/4096
Output
control
Clock
Clock
select
Internal clock sources
TCR:
DTR:
TCNT:
Timer Control Register (8 bits)
Duty Register (8 bits)
Timer Counter (8 bits)
Module data bus
Figure 8-1
171
8.1.3 Input and Output Pins
Table 8-1 lists the output pins of the PWM timer module. There are no input pins.
Table 8-1. Output Pins of PWM Timer Module
8.1.4 Register Configuration
The PWM timer module has three registers for each channel as listed in table 8-2.
Table 8-2. PWM Timer Registers
8.2 Register Descriptions
8.2.1 Timer Counter (TCNT)—H'FFA2 (PWM0), H'FFA6 (PWM1)
The PWM timer counters (TCNT) are 8-bit up-counters. When the output enable bit (OE) in the
timer control register (TCR) is set to “1,” the timer counter starts counting pulses of an internal
clock source selected by clock select bits 2 to 0 (CKS2 to CKS0). After counting from H'00 to
H'F9, the timer counter repeats from H'00.
Name Abbreviation I/O Function
PWM0 output PW0Output Pulse output from PWM timer channel 0.
PWM1 output PW1Output Pulse output from PWM timer channel 1.
Initial Address
Name Abbreviation R/W value PWM0 PWM1
Timer control register TCR R/W H'38 H'FFA0 H'FFA4
Duty register DTR R/W H'FF H'FFA1 H'FFA5
Timer counter TCNT R/W H'00 H'FFA2 H'FFA6
Bit 76543210
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
172
The PWM timer counters are initialized to H'00 at a reset and in the standby modes, and when the
OE bit is cleared to “0.”
8.2.2 Duty Register (DTR)—H'FFA1 (PWM0), H'FFA5 (PWM1)
The duty registers (DTR) are 8-bit readable/writable registers that specify the duty cycle of the
output pulse. Any duty cycle from 0 to 100% can be selected, with a resolution of 1/250. Writing
0 (H'00) in a DTR gives a 0% duty cycle; writing 125 (H'7D) gives a 50% duty cycle; writing 250
(H'FA) gives a 100% duty cycle.
The timer count is continually compared with the DTR contents. If the DTR value is not 0, when
the count increments from H'00 to H'01 the PWM output signal is set to “1.” When the count
increments past the DTR value, the PWM output returns to “0.” If the DTR value is 0 (0% duty),
the PWM output remains constant at “0.”
The DTRs are double-buffered. A new value written in a DTR while the timer counter is running
does not become valid until after the count changes from H'F9 to H'00. When the timer counter is
stopped (while the OE bit is “0”), new values become valid as soon as written. When a DTR is
read, the value read is the currently valid value.
The DTRs are initialized to H'FF at a reset and in the standby modes.
8.2.3 Timer Control Register (TCR)—H'FFA0 (PWM0), H'FFA4 (PWM1)
The TCRs are 8-bit readable/writable registers that select the clock source and control the PWM
outputs.
The TCRs are initialized to H'38 at a reset and in the standby modes.
Bit 76543210
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 76543210
OE OS — — — CKS2 CKS1 CKS0
Initial value 0 0 1 1 1 0 0 0
Read/Write R/W R/W — — — R/W R/W R/W
173
Bit 7—Output Enable (OE): This bit enables the timer counter and the PWM output.
Bit 6—Output Select (OS): This bit selects positive or negative logic for the PWM output.
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as “1.”
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal
clock sources obtained by dividing the system clock (Ø).
From the clock source frequency, the resolution, period, and frequency of the PWM output can be
calculated as follows.
Resolution = 1/clock source frequency
PWM period = resolution
× 250
PWM frequency = 1/PWM period
Bit 7
OE Description
0 PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value)
1 PWM output is enabled. TCNT runs.
Bit 6
OS Description
0 Positive logic; positive-going PWM pulse, “1” = High (Initial value)
1 Negative logic; negative-going PWM pulse, “1” = Low
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Description
0 0 0 Ø/2 (Initial value)
0 0 1 Ø/8
0 1 0 Ø/32
0 1 1 Ø/128
1 0 0 Ø/256
1 0 1 Ø/1024
1 1 0 Ø/2048
1 1 1 Ø/4096
174
If the system clock frequency is 10MHz, then the resolution, period, and frequency of the PWM
output for each clock source are given in table 8-3.
Table 8-3. PWM Timer Parameters for 10MHz System Clock
8.3 Operation
8.3.1 Timer Incrementation
The PWM clock source is created from the system clock (Ø) by a prescaler. The timer counter
increments on a TCNT clock pulse generated from the falling edge of the prescaler output as shown
in figure 8-2.
Figure 8-2. TCNT Increment Timing
Internal clock frequency Resolution PWM period PWM frequency
Ø/2 200ns 50µs 20kHz
Ø/8 800ns 200µs 5kHz
Ø/32 3.2µs 800µs 1.25kHz
Ø/128 12.8µs 3.2ms 312.5Hz
Ø/256 25.6µs 6.4ms 156.3Hz
Ø/1024 102.4µs 25.6ms 39.1Hz
Ø/2048 204.8µs 51.2ms 19.5Hz
Ø/4096 409.6µs 102.4ms 9.8Hz
Ø
TCNT clock
pulse
Prescaler
output
TCNT
N–1
N+1
N
175
8.3.2 PWM Operation
Figure 8-3 is a timing chart of the PWM operation.
N – 1 N + 1
(a) H'00 (b) H'01 H'02 NH'F9 (d) H'00 H'01
N(d) MH'FF
(c)
(a)*
(e)*
(b) (c)
N written in DTR M written in DTR
Ø
TCNT clock
pulses
OE
TCNT
DTR
(OS = “0”)
PWM output
(OS = “1”)
PWM 1 cycle
Note: * Used for port 4 input/output: state depends on values in data register and data direction register.
Figure 8-3
Figure 8-3. PWM Timing
176
(1) Positive Logic (OS = “0”)
①When (OE = “0”) – (a) in Figure 8-3: The timer count is held at H'00 and PWM output is
inhibited. [Pin 46(for PW0) or pin 47(for PW1) is used for port 4 input/output, and its state
depends on the corresponding port 4 data register and data direction register.] Any value (such as
N in figure 8-3) written in the DTR becomes valid immediately.
②When (OE = “1”)
i) The timer counter begins incrementing. The PWM output goes High when TCNT changes
from H'00 to H'01, unless DTR = H'00. [(b) in figure 8-3]
ii) When the count passes the DTR value, the PWM output goes Low. [(c) in figure 8-3]
iii) If the DTR value is changed (by writing the data “M” in figure 8-3), the new value
becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 8-3]
(2) Negative Logic (OS = “1”) – (e) in Figure 8-3: The operation is the same except that High
and Low are reversed in the PWM output. [(e) in figure 8-3]
8.4 Application Notes
Some notes on the use of the PWM timer module are given below.
(1) Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to “1.”
(2) If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at “0.”
If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant at
“1.”
(For positive logic, “0” is Low and “1” is High. For negative logic, “0” is High and “1” is
Low.)
177
Section 9. Serial Communication Interface
9.1 Overview
The H8/338 Series includes two serial communication interface channels (SCI0 and SCI1) for
transferring serial data to and from other chips. Either synchronous or asynchronous
communication can be selected.
9.1.1 Features
The features of the on-chip serial communication interface are:
• Asynchronous mode
The H8/338 Series can communicate with a UART (Universal Asynchronous
Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip
that employs standard asynchronous serial communication. It also has a multiprocessor
communication function for communication with other processors. Twelve data formats are
available.
— Data length: 7 or 8 bits
— Stop bit length: 1 or 2 bits
— Parity: Even, odd, or none
— Multiprocessor bit: “1” or “0”
— Error detection: Parity, overrun, and framing errors
— Break detection: When a framing error occurs, the break condition can be detected by
reading the level of the RxD line directly.
• Synchronous mode
The SCI can communicate with chips able to perform clocked synchronous data transfer.
— Data length: 8 bits
— Error detection: Overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so each channel can transmit and
receive simultaneously. Both the transmit and receive sections use double buffering, so
continuous data transfer is possible in either direction.
• Built-in baud rate generator
Any specified baud rate can be generated.
• Internal or external clock source
The SCI can operate on an internal clock signal from the baud rate generator, or an external
clock signal input at the SCK0 or SCK1 pin.
• Four interrupts
TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently.
179
9.1.2 Block Diagram
Figure 9-1 shows a block diagram of one serial communication interface channel.
Figure 9-1. Block Diagram of Serial Communication Interface
9.1.3 Input and Output Pins
Table 9-1 lists the input and output pins used by the SCI module.
TDR
Bus interface
Internal
data bus
Module data bus
Parity
generate
Clock
Parity check
TSR
Ø
Ø/4
Ø/16
Ø/64
RxD
TxD
TXI
RXI
ERI
Interrupt signals
External clock source
Internal
clock
RDR
RSR
SCK
BRR
Communi-
cation
control
SSR
SCR
SMR
Baud rate
generator
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Receive Shift Register (8 bits)
Receive Data Register (8 bits)
Transmit Shift Register (8 bits)
Transmit Data Register (8 bits)
Serial Mode Register (8 bits)
Serial Control Register (8 bits)
Serial Status Register (8 bits)
Bit Rate Register (8 bits)
Figure 9-1
TEI
180
Table 9-1. SCI Input/Output Pins
Channel Name Abbr. I/O Function
0 Serial clock SCK0Input/output Serial clock input and output.
Receive data RxD0Input Receive data input.
Transmit data TxD0Output Transmit data output.
1 Serial clock SCK1Input/output Serial clock input and output.
Receive data RxD1Input Receive data input.
Transmit data TxD1Output Transmit data output.
9.1.4 Register Configuration
Table 9-2 lists the SCI registers. These registers specify the operating mode (synchronous or
asynchronous), data format and bit rate, and control the transmit and receive sections.
Table 9-2. SCI Registers
Channel Name Abbr. R/W Value Address
0 Receive shift register RSR — — —
Receive data register RDR R H'00 H'FFDD
Transmit shift register TSR — — —
Transmit data register TDR R/W H'FF H'FFDB
Serial mode register SMR R/W H'00 H'FFD8
Serial control register SCR R/W H'00 H'FFDA
Serial status register SSR R/(W)* H'84 H'FFDC
Bit rate register BRR R/W H'FF H'FFD9
1 Receive shift register RSR — — —
Receive data register RDR R H'00 H'FF8D
Transmit shift register TSR — — —
Transmit data register TDR R/W H'FF H'FF8B
Serial mode register SMR R/W H'00 H'FF88
Serial control register SCR R/W H'00 H'FF8A
Serial status register SSR R/(W)* H'84 H'FF8C
Bit rate register BRR R/W H'FF H'FF89
0 and 1 Serial/timer control register STCR R/W H'F8 H'FFC3
Note: * Software can write a “0” to clear the flags in bits 7 to 3, but cannot write “1” in these bits.
181
9.2 Register Descriptions
9.2.1 Receive Shift Register (RSR)
Bit 76543210
Read/Write — — — — — — — —
The RSR is a shift register that converts incoming serial data to parallel data. When one data
character has been received, it is transferred to the receive data register (RDR).
The CPU cannot read or write the RSR directly.
9.2.2 Receive Data Register (RDR)—H'FFDD, H'FF8D
Bit 76543210
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
The RDR stores received data. As each character is received, it is transferred from the RSR to the
RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to
receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 at a reset and in the
standby modes.
9.2.3 Transmit Shift Register (TSR)
Bit 76543210
Read/Write — — — — — — — —
The TSR is a shift register that converts parallel data to serial transmit data. When transmission of
this character is completed, the next character is moved from the transmit data register (TDR) to the
TSR and transmission of that character begins. If the TDRE bit is still set to “1”, however, nothing
is transferred to the TSR.
The CPU cannot read or write the TSR directly.
182
9.2.4 Transmit Data Register (TDR)—H'FFDB, H'FF8B
Bit 76543210
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current byte
is being transmitted from the TSR.
The TDR is initialized to H'FF at a reset and in the standby modes.
9.2.5 Serial Mode Register (SMR)—H'FFD8, H'FF88
Bit 76543210
C/A CHR PE O/E STOP MP CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'00 at a reset and in the standby
modes. For further information on the SMR settings and communication formats, see tables 9-5
and 9-7 in section 9.3, “Operation.”
Bit 7—Communication Mode (C/A): This bit selects the asynchronous or clocked synchronous
communication mode.
Bit 7
C/A Description
0 Asynchronous communication. (Initial value)
1 Clocked synchronous communication.
183
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode.
It is ignored in synchronous mode.
Bit 6
CHR Description
0 8 bits per character. (Initial value)
1 7 bits per character. (Bits 0 to 6 of TDR and RDR are used for transmitting and
receiving, respectively.)
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.
It is ignored in synchronous mode, and when a multiprocessor format is used.
Bit 5
PE Description
0 Transmit: No parity bit is added. (Initial value)
Receive: Parity is not checked.
1 Transmit: A parity bit is added.
Receive: Parity is checked.
Bit 4—Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = “1”), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = “0,” or when a multiprocessor format is used. It is also ignored in
the synchronous mode.
Bit 4
O/E Description
0 Even parity. (Initial value)
1 Odd parity.
184
Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the
synchronous mode.
Bit 3
STOP Description
0 One stop bit. (Initial value)
Transmit: One stop bit is added.
Receive: One stop bit is checked to detect framing errors.
1 Two stop bits.
Transmit: Two stop bits are added.
Receive: The first stop bit is checked to detect framing errors. If the second stop bit is a
space (0), it is regarded as the next start bit.
Bit 2—Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous
communication. When multiprocessor format is selected, the parity settings of the parity enable bit
(PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication.
The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to “1.”
When the MPE bit is cleared to “0,” the multiprocessor communication function is disabled
regardless of the setting of the MP bit.
Bit 2
MP Description
0 Multiprocessor communication function is disabled. (Initial value)
1 Multiprocessor communication function is enabled.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source when the baud rate generator is clocked from within the chip.
Bit 1 Bit 0
CKS1 CKS0 Description
0 0 Ø clock (Initial value)
0 1 Ø/4 clock
1 0 Ø/16 clock
1 1 Ø/64 clock
185
9.2.6 Serial Control Register (SCR)—H'FFDA, H'FF8A
Bit 76543210
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions.
It is initialized to H'00 at a reset and in the standby modes.
Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt
(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR)
is set to “1.”
Bit 7
TIE Description
0 The TDR-empty interrupt request (TXI) is disabled. (Initial value)
1 The TDR-empty interrupt request (TXI) is enabled.
Bit 6—Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to “1,” and the receive error interrupt (ERI) requested when the overrun error (ORER), framing
error (FER), or parity error (PER) bit in the serial status register (SSR) is set to “1.”
Bit 6
RIE Description
0 The receive-end interrupt (RXI) and receive-error (ERI) requests are (Initial value)
disabled.
1 The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.
Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE Description
0 The transmit function is disabled. (Initial value)
The TxD pin can be used for general-purpose I/O.
1 The transmit function is enabled. The TxD pin is used for output.
186
Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the receive
function is enabled, the RxD pin is automatically used for input. When the receive function is
disabled, the RxD pin is available as a general-purpose I/O port.
Bit 4
RE Description
0 The receive function is disabled. The RxD pin can be (Initial value)
used for general-purpose I/O.
1 The receive function is enabled. The RxD pin is used for input.
Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data are received in a
multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-error
interrupt (ERI) until data with the multiprocessor bit set to “1” are received. It also enables or
disables the transfer of received data from the RSR to the RDR, and enables or disables setting of
the RDRF, FER, PER, and ORER bits in the serial status register (SSR).
The MPIE bit is ignored when the MP bit is cleared to “0,” and in synchronous mode.
Clearing the MPIE bit to “0” disables the multiprocessor receive interrupt function. In this
condition data are received regardless of the value of the multiprocessor bit in the receive data.
Setting the MPIE bit to “1” enables the multiprocessor receive interrupt function. In this condition,
if the multiprocessor bit in the receive data is “0,” the receive-end interrupt (RXI) and receive-error
interrupt (ERI) are disabled, the receive data are not transferred from the RSR to the RDR, and the
RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the
multiprocessor bit is “1,” however, the MPB bit in the SSR is set to “1,” the MPIE bit is cleared to
“0,” the receive data are transferred from the RSR to the RDR, the FER, PER, and ORER bits can
be set, and the receive-end and receive-error interrupts are enabled.
Bit 3
MPIE Description
0 The multiprocessor receive interrupt function is disabled. (Initial value)
(Normal receive operation)
1 The multiprocessor receive interrupt function is enabled. During the
interval before data with the multiprocessor bit set to “1” are received,
the receive interrupt request (RXI) and receive-error interrupt request
(ERI) are disabled, the RDRF, FER, PER, and ORER bits are not set in
the serial status register (SSR), and no data are transferred from the RSR
to the RDR. The MPIE bit is cleared at the following times:
(1) When “0” is written in MPIE.
(2) When data with the multiprocessor bit set to “1” are received.
187
Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty
interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set
to “1.”
Bit 2
TEIE Description
0 The TSR-empty interrupt request (TEI) is disabled. (Initial value)
1 The TSR-empty interrupt request (TEI) is enabled.
Bit 1—Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud
rate generator. When the external clock source is selected, the SCK pin is automatically used for
input of the external clock signal.
Bit 1
CKE1 Description
0 Internal clock source. (Initial value)
When C/A = “1,” the serial clock signal is output at the SCK pin.
When C/A = “0,” output depends on the CKE0 bit.
1 External clock source. The SCK pin is used for input.
Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the SCK pin.
This bit is ignored when the external clock is selected, or when synchronous mode is selected.
For further information on the communication format and clock source selection, see table 9-7 in
section 9.3, “Operation.”
Bit 0
CKE0 Description
0 The SCK pin is not used by the SCI (and is available as (Initial value)
a general-purpose I/O port).
1 The SCK pin is used for serial clock output.
188
9.2.7 Serial Status Register (SSR)—H'FFDC, H'FF8C
Bit 76543210
TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value 1 0 0 0 0 1 0 0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W
Note: * Software can write a “0” to clear the flags, but cannot write a “1” in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a
reset and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have
been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7
TDRE Description
0 To clear TDRE, the CPU must read TDRE after it has been set to “1,”
then write a “0” in this bit.
1 This bit is set to 1 at the following times: (Initial value)
(1) When TDR contents are transferred to the TSR.
(2) When the TE bit in the SCR is cleared to “0.”
Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to the RDR.
Bit 6
RDRF Description
0 To clear RDRF, the CPU must read RDRF after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 when one character is received without error and
transferred from the RSR to the RDR.
189
Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER Description
0 To clear ORER, the CPU must read ORER after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to “1” if reception of the next character ends while
the receive data register is still full (RDRF = “1”).
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4
FER Description
0 To clear FER, the CPU must read FER after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to “1” if a framing error occurs (stop bit = “0”).
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without parity
bits is used.
Bit 3
PER Description
0 To clear PER, the CPU must read PER after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to “1” when a parity error occurs (the parity of the received
data does not match the parity selected by the O/E bit in SMR).
190
Bit 2—Transmit End (TEND): This bit indicates that the serial communication interface has
stopped transmitting because there was no valid data in the TDR when the last bit of the current
character was transmitted. The TEND bit is also set to “1” when the TE bit in the serial control
register (SCR) is cleared to “0.”
The TEND bit can be read but not written. To clear TEND to “0,” software must read the serial
status register while TDRE = “1,” then write “0” in TDRE.
Bit 2
TEND Description
0 To clear TEND, the CPU must read TDRE after (Initial value)
it has been set to “1,” then write a “0” in TDRE.
1 This bit is set to “1” when:
(1) TE = “0”
(2) TDRE = “1” at the end of transmission of a character
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a
multiprocessor format in asynchronous communication mode. This bit is cleared to “0” in
synchronous mode, or when a multiprocessor format is not used. If the RE bit is cleared to “0”
when a multiprocessor format is used, the MPB bit retains its previous value.
MPB can be read but not written.
Bit 1
MPB Description
0 Multiprocessor bit = “0” in receive data. (Initial value)
1 Multiprocessor bit = “1” in receive data.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted
in transmit data when a multiprocessor format is used in asynchronous communication mode. The
MPBT bit has no effect in synchronous mode, or when a multiprocessor format is not used. It is
not used in receiving data.
Bit 0
MPBT Description
0 Multiprocessor bit = “0” in transmit data. (Initial value)
1 Multiprocessor bit = “1” in transmit data.
191
9.2.8 Bit Rate Register (BRR)—H'FFD9, H'FF89
Bit 76543210
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the baud rate output by the baud rate generator.
The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes.
Tables 9-3 and 9-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
Table 9-5 lists the maximum bit rates in asynchronous mode.
Table 9-3. Examples of BRR Settings in Asynchronous Mode (1)
XTAL Frequency (MHz)
2 2.4576 4 4.194304
Bit Error Error Error Error
rate n N (%) n N (%) n N (%) n N (%)
110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 –0.04
150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21
300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21
600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21
1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 –0.70
2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14
4800 — — — 0 7 0 0 12 +0.16 0 13 –2.48
9600 — — — 0 3 0 — — — 0 6 –2.48
19200 — — — 0 1 0 — — — — — —
31250 0 0 0 — — — 0 1 0 — — —
38400 — — — 0 0 0 — — — — — —
192
Table 9-3. Examples of BRR Settings in Asynchronous Mode (2)
XTAL Frequency (MHz)
4.9152 6 7.3728 8
Bit Error Error Error Error
rate n N (%) n N (%) n N (%) n N (%)
110 1 174 –0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03
150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16
300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16
600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16
1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16
2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16
4800 0 15 0 0 19 –2.34 0 23 0 0 25 +0.16
9600 0 7 0 0 9 –2.34 0 11 0 0 12 +0.16
19200 0 3 0 0 4 –2.34 0 5 0 — — —
31250 — — — 0 2 0 — — — 0 3 0
38400 0 1 0 — — — 0 2 0 — — —
Table 9-3. Examples of BRR Settings in Asynchronous Mode (3)
XTAL Frequency (MHz)
9.8304 10 12 12.288
Bit Error Error Error Error
rate n N (%) n N (%) n N (%) n N (%)
110 2 86 +0.31 2 88 –0.25 2 106 –0.44 2 108 +0.08
150 1 255 0 2 64 +0.16 2 77 0 2 79 0
300 1 127 0 1 129 +0.16 1 155 0 1 159 0
600 0 255 0 1 64 +0.16 1 77 0 1 79 0
1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0
2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0
4800 0 31 0 0 32 –1.36 0 38 +0.16 0 39 0
9600 0 15 0 0 15 +1.73 0 19 –2.34 0 19 0
19200 0 7 0 0 7 +1.73 — — — 0 4 0
31250 0 4 –1.70 0 4 0 0 5 0 0 5 +2.40
38400 0 3 0 0 3 +1.73 — — — — — —
193
Table 9-3. Examples of BRR Settings in Asynchronous Mode (4)
XTAL Frequency (MHz)
14.7456 16 19.6608 20
Bit Error Error Error Error
rate n N (%) n N (%) n N (%) n N (%)
110 2 130 –0.07 2 141 +0.03 2 174 –0.26 3 43 +0.88
150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16
300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16
600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16
1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16
2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16
4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16
9600 0 23 0 0 25 +0.16 0 31 0 0 32 –1.36
19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73
31250 — — — 0 7 0 0 9 –1.70 0 9 0
38400 0 5 0 — — — 0 7 0 0 7 +1.73
Note: If possible, the error should be within 1%.
B = OSC
× 106/[64 × 22n × (N + 1)]
N: BRR value (0 ≤N ≤255)
OSC: Crystal oscillator frequency in MHz
B: Baud rate (bits/second)
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n CKS1 CKS0 Clock
000Ø
1 0 1 Ø/4
2 1 0 Ø/16
3 1 1 Ø/64
194
Table 9-4. Examples of BRR Settings in Synchronous Mode
XTAL Frequency (MHz)
Bit 2 4 8 10 16 20
rate n N n N n N n N n N n N
100 — — — — — — — — — — — —
250 1 249 2 124 2 249 — — 3 124 — —
500 1 124 1 249 2 124 — — 2 249 — —
1k 0 249 1 124 1 249 — — 2 124 — —
2.5k 0 99 0 199 1 99 1 124 1 199 1 249
5k 0 49 0 99 0 199 0 249 1 99 1 124
10k 0 24 0 49 0 99 0 124 0 199 0 249
25k 0 9 0 19 0 39 0 49 0 79 0 99
50k 0 4 0 9 0 19 0 24 0 39 0 49
100k — — 0 4 0 9 — — 0 19 0 24
250k 0 0* 0 1 0 3 0 4 0 7 0 9
500k 0 0* 0 1 — — 0 3 0 4
1M 0 0* — — 0 1 — —
2.5M 0 0*
Notes: Blank: No setting is available.
—: A setting is available, but the bit rate is inaccurate.
*: Continuous transfer is not possible.
B = OSC ×106/[8 ×22n ×(N + 1)]
N: BRR value (0 ≤N ≤255)
OSC: Crystal oscillator frequency in MHz
B: Baud rate (bits per second)
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n CKS1 CKS0 Clock
000Ø
1 0 1 Ø/4
2 1 0 Ø/16
3 1 1 Ø/64
195
9.2.9 Serial/Timer Control Register (STCR)—H'FFC3
Bit 76543210
— — — — — MPE ICKS1 ICKS0
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — R/W R/W R/W
The STCR is an 8-bit readable/writable register that controls the operating mode of the serial
communication interface and selects input clock sources for the 8-bit timer counters (TCNT).
The STCR is initialized to H'F8 by a reset.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as “1.”
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1.
Bit 2
MPE Description
0 The multiprocessor communication function is disabled, (Initial value)
regardless of the setting of the MP bit in SMR.
1 The multiprocessor communication function is enabled. The multi-
processor format can be selected by setting the MP bit in SMR to “1.”
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the
clock input to the timer counters (TCNT) in the 8-bit timers. For further information see section 7,
“8-Bit Timers.”
196
9.3 Operation
9.3.1 Overview
The SCI supports serial data transfer in two modes. In asynchronous mode each character is
synchronized individually. In synchronous mode communication is synchronized with a clock
signal.
The selection of asynchronous or synchronous mode and the communication format depend on
settings in the SMR as indicated in table 9-5. The clock source depends on the settings of the C/A
bit in the SMR and the CKE1 and CKE0 bits in the SCR as indicated in table 9-6.
(1) Asynchronous Mode: Data lengths of seven or eight bits can be selected. A parity bit or
multiprocessor bit can be added, and stop bit lengths of one or two bits can be selected. These
selections determine the communication format and character length. Framing errors (FER), parity
errors (PER) and overrun errors (ORER) can be detected in receive data, and the line-break
condition can be detected.
An internal or external clock source can be selected for the serial clock. When an internal clock
source is selected, the SCI is clocked by the on-chip baud rate generator and can output a clock
signal at the bit-rate frequency. When the external clock source is selected, the on-chip baud rate
generator is not used. The external clock frequency must be 16 times the bit rate.
(2) Synchronous Mode: The transmit data length is eight bits. Overrun errors (ORER) can be
detected in receive data.
An internal or external clock source can be selected for the serial clock. When an internal clock
source is selected, the SCI is clocked by the on-chip baud rate generator and outputs a serial clock
signal. When the external clock source is selected, the on-chip baud rate generator is not used and
the SCI operates on the input serial clock.
197
Table 9-5. Communication Formats Used by SCI
SMR settings Communication format
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multipro- Parity Stop-bit
C/A CHR MP PE STOP Mode length cessor bit bit length
0 0 0 0 0 Asynchronous mode 8 bits None None 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
1 0 0 7 bits None 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
0 1 — 0 Asynchronous mode 8 bits Present None 1 bit
1 (multiprocessor 2 bits
1 0 format) 7 bits 1 bit
1 2 bits
1 — — — — Synchronous mode 8 bits None None
Table 9-6. SCI Clock Source Selection
SMR SCR
Bit 7 Bit 1 Bit 0 Serial transmit/receive clock
C/A CKE1 CKE0 Mode Clock source SCK Pin function
0 0 0 Async Internal Input/output port (not used by SCI)
1 Serial clock output at bit rate
1 0 External Serial clock input at 16 ×bit rate
1
1 0 0 Sync Internal Serial clock output
1
1 0 External Serial clock input
1
198
9.3.2 Asynchronous Mode
In asynchronous mode, each transmitted or received character is individually synchronized by
framing it with a start bit and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive sections.
Double buffering in both sections enables the SCI to be programmed for continuous data transfer.
Figure 9-2 shows the general format of one character sent or received in asynchronous mode. The
communication channel is normally held in the mark state (High). Character transmission or
reception starts with a transition to the space state (Low).
The first bit transmitted or received is the start bit (Low). It is followed by the data bits, in which
the least significant bit (LSB) comes first. The data bits are followed by the parity or
multiprocessor bit, if present, then the stop bit or bits (High) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Figure 9-2. Data Format in Asynchronous Mode
D0
D1
Dn
Start bit
1 bit
7 or 8 bits
One unit of data (one character or frame)
Parity or
multipro-
cessor bit
Stop bit
0 or 1 bit
1 or 2 bits
Idle state
(mark)
199
(1) Data Format: Table 9-7 lists the data formats that can be sent and received in asynchronous
mode. Twelve formats can be selected by bits in the SMR.
Table 9-7. Data Formats in Asynchronous Mode
Notes: SMR: Serial mode register
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
(2) Clock: In asynchronous mode it is possible to select either an internal clock created by the on-
chip baud rate generator, or an external clock input at the SCK pin. The selection is made by the
C/
A
bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register
(SCR). Refer to table 9-7.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used
for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the
center of the transmit data bits. Figure 9-3 shows the phase relationship between the output clock
and transmit data.
CHR
0
0
0
0
1
1
1
1
0
0
1
1
PE
0
0
1
1
0
0
1
1
—
—
—
—
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Bits
1 2 3 4 5 6 7 8 9 10 11 12
S
S
S
S
S
S
S
S
S
S
S
S
8-Bit data STOP
8-Bit data STOP STOP
8-Bit data PSTOP
8-Bit data PSTOP STOP
7-Bit data STOP
7-Bit data STOP STOP
7-Bit data PSTOP
7-Bit data PSTOP STOP
8-Bit data MPB STOP
8-Bit data MPB STOP STOP
7-Bit data MPB STOP
7-Bit data MPB STOP STOP
200
Figure 9-3. Phase Relationship between Clock Output and Transmit Data
(Asynchronous Mode)
(3) Transmitting and Receiving Data
• SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to
“0” in the serial control register (SCR), then initialize the SCI as follows.
Note: When changing the communication mode or format, always clear the TE and RE bits to “0”
before following the procedure given below. Clearing TE to “0” sets TDRE to “1” and
initializes the transmit shift register (TSR). Clearing RE to “0,” however, does not initialize
the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their
previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
“0” D0 D1 D2 D3 D4
One frame
D5 D6 D7 0/1 “1” “1”
201
Figure 9-4. Sample Flowchart for SCI Initialization
Clear TE and RE bits to
“0” in SCR
1 bit interval
elapsed?
Start transmitting or receiving
No
Yes
1. Select the communication format in the serial mode register (SMR).
2. Write the value corresponding to the bit rate in the bit rate register
(BRR). This step is not necessary when an external clock is used.
3. Select interrupts and the clock source in the serial control register
(SCR). Leave TE and RE cleared to “0.” If clock output is selected,
in asynchronous mode, clock output starts immediately after the
setting is made in SCR.
4. Wait for at least the interval required to transmit or receive one bit,
then set TE or RE in the serial control register (SCR).
Setting TE or RE enables the SCI to use the TxD or RxD pin.
Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable
interrupts. The initial states are the mark transmit state, and the
idle receive state (waiting for a start bit).
H8/338 U.M. '92
Fig. 9-4
Select communication
format in SMR
1
Set value in BRR
2
Set CKE1 and CKE0 bits in
SCR (leaving TE and RE
cleared to “0”)
3
Set TE or RE to “1” in SCR,
and set RIE, TIE, TEIE, and
MPIE as necessary
4
Initialization
202
• Transmitting Serial Data: Follow the procedure below for transmitting serial data.
Figure 9-5. Sample Flowchart for Transmitting Serial Data
Start transmitting
Read TDRE bit in SSR
TDRE = “1”?
Write transmit data in TDR
End of
transmission?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function of the TxD pin is
selected automatically.
(a)
(b)
To continue transmitting serial data: read the TDRE bit to check
whether it is safe to write; if TDRE = “1,” write data in TDR, then
clear TDRE to “0.”
To end serial transmission: end of transmission can be
confirmed by checking transition of the TEND bit from “0” to “1.”
This can be reported by a TEI interrupt.
To output a break signal at the end of serial transmission: set the
DDR bit to “1” and clear the DR bit to “0” (DDR and DR are I/O
port registers), then clear TE to “0” in SCR.
H8/338 U.M. '92
Fig. 9-5
If using multiprocessor format,
select MPBT value in SSR
Clear TDRE bit to “0” in SSR
Read TEND bit in SSR
TEND = “1”? No
Yes
Output break
signal? No
Yes
Clear TE bit in SCR to “0”
4
SCI status check and transmit data write: read the serial status
register (SSR), check that the TDRE bit is “1,” then write transmit
data in the transmit data register (TDR) and clear TDRE to “0.”
If a multiprocessor format is selected, after writing the transmit
data write “0” or “1” in the multiprocessor bit transfer (MPBT) in
SSR. Transition of the TDRE bit from “0” to “1” can be reported
by an interrupt.
1.
3.
4.
2.
Initialize
Set DR = “0,” DDR = “1”
Serial transmission
203
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) is set to “1” in SCR, the SCI requests
a TXI interrupt (TDR-empty interrupt) at this time.
Serial transmit data are transmitted in the following order from the TxD pin:
(a) Start bit: one “0” bit is output.
(b)Transmit data: seven or eight bits are output, LSB first.
(c) Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
(d)Stop bit: one or two “1” bits (stop bits) are output.
(e) Mark state: output of “1” bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is “0,” the SCI loads new
data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame.
If TDRE is “1,” the SCI sets the TEND bit to “1” in SSR, outputs the stop bit, then continues
output of “1” bits in the mark state. If the TEIE bit (TSR-empty interrupt enable) in SCR is set
to “1,” a TEI interrupt (TSR-empty interrupt) is requested.
204
Figure 9-6 shows an example of SCI transmit operation in asynchronous mode.
Figure 9-6. Example of SCI Transmit Operation
(8-Bit Data with Parity and One Stop Bit)
“1” Start
bit
“0” D0 D1 D7 0/1
Stop
bit
“1”
Data Parity
bit Start
bit
“0” D0 D1 D7 0/1
Stop
bit
“1”
Data Parity
bit “1”
Mark (idle)
state
TDRE
TEND
TXI
request TXI interrupt handler
writes data in TDR and
clears TDRE to “0”
TXI
request
1 frame
TEI request
H8/338 U.M. '92
Fig. 9-6
205
• Receiving Serial Data: Follow the procedure below for receiving serial data.
Figure 9-7. Sample Flowchart for Receiving Serial Data
Start receiving
Read RDRF bit in SSR
RDRF = “1”?
Read receive data from RDR,
and clear RDRF bit to “0”
in SSR
PER RER
ORER = “1”?
Clear RE to “0” in SCR
Finished
receiving?
End
Error handling
Start error handling
FER = “1”?
Clear error flags to
“0” in SCR
Return
Break?
Clear RE to “0”
in SCR
End
1
2
No
Yes
Yes
No
No
Yes
4
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
2. SCI status check and receive data read: read the serial status
register (SSR), check that RDRF is set to “1,” then read receive
data from the receive data register (RDR) and clear RDRF to “0.”
Transition of the RDRF bit from “0” to “1” can be reported by an
RXI interrupt.
4. Receive error handling and break detection: if a receive error
occurs, read the ORER, PER, and FER bits in SSR to identify
the error. After executing the necessary error handling, clear
ORER, PER, and FER all to “0.” Transmitting and receiving
cannot resume if ORER, PER, or FER remains set to “1.”
When a framing error occurs, the RxD pin can be read to detect
the break state.
Yes
No
Yes
No
H8/338 U.M. '92
Fig. 9-7
Read ORER, PER, and
FER in SSR
3
∨ ∨
3. To continue receiving serial data: read RDR and clear RDRF to
“0” before the stop bit of the current frame is received.
Initialize
206
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit.
2. Receive data are shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI makes the following checks:
(a) Parity check: the number of 1s in the receive data must match the even or odd parity setting
of the O/E bit in SMR.
(b)Stop bit check: the stop bit value must be “1.” If there are two stop bits, only the first stop
bit is checked.
(c) Status check: RDRF must be “0” so that receive data can be loaded from RSR into RDR.
If these checks all pass, the SCI sets RDRF to “1” and stores the received data in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 9-8.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to “1.”
Be sure to clear the error flags.
4. After setting RDRF to “1,” if the RIE bit (receive-end interrupt enable) is set to “1” in SCR, the
SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is
set to “1” and the RIE bit in SCR is also set to “1,” the SCI requests an ERI (receive-error)
interrupt.
207
Figure 9-8 shows an example of SCI receive operation in asynchronous mode.
Table 9-8. Receive Error Conditions and SCI Operation
Receive error Abbreviation Condition Data transfer
Overrun error ORER Receiving of next data ends Receive data not loaded from
while RDRF is still set to “1” RSR into RDR
in SSR
Framing error FER Stop bit is “0” Receive data loaded from
RSR into RDR
Parity error PER Parity of receive data differs Receive data loaded from
from even/odd parity setting RSR into RDR
in SMR
Figure 9-8. Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
“1” Start
bit
“0” D0 D1 D7 0/1
Stop
bit
“1”
Data Parity
bit Start
bit
“0” D0 D1 D7 0/1
Stop
bit
“0”
Data Parity
bit “1”
Mark (idle)
state
RDRF
FER
RXI
request
1 frame
Framing error,
ERI request
H8/338 U.M. '92
Fig. 9-8
RXI interrupt handler
reads data in RDR and
clears RDRF to “0”
208
(4) Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID.
A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the
receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending
cycles from data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to “1.” Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to “0.”
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
“1.”
After receiving data with the multiprocessor bit set to “1,” the receiving processor with an ID
matching the received data continues to receive further incoming data. Multiple processors can
send and receive data in this way.
Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected.
For details see table 9-7.
Figure 9-9. Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Transmitting
processor
Receiving
processor A
Serial communication line
Receiving
processor B Receiving
processor C Receiving
processor D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial data H'01 H'AA
(MPB = 1) (MPB = 0)
ID-sending cycle:
receiving processor address Data-sending cycle:
data sent to receiving
processor specified by ID
H8/338 U.M. '92
Fig. 9-9
MPB: multiprocessor bit
209
• Transmitting Multiprocessor Serial Data: See figures 9-5 and 9-6.
• Receiving Multiprocessor Serial Data: Follow the procedure below for receiving
multiprocessor serial data.
Figure 9-10. Sample Flowchart for Receiving Multiprocessor Serial Data
Start receiving
Set MPIE bit to “1” in SCR
Read RDRF bit in SSR
RDRF = “1”?
Read receive data from RDR
Own ID?
Read ORER and FER
bits in SSR
FER
ORER = “1”?
Read RDRF bit in SSR
∨
RDRF = “1”?
Read ORER and FER
bits in SSR
Read receive data from RDR
FER +
ORER = “1”?
Finished
receiving?
Clear RE to “0” in SCR
End
Error handling FER = “1”?
Clear error flags
Return
Break?
Clear RE bit to
“0” in SCR
End
1
2
3
4
No
Yes
No
Yes
Yes
No
No
Yes
Yes
No No
Yes
5
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
2. ID receive cycle: Set the MPIE bit in the serial control register
(SCR) to “1.”
3. SCI status check and ID check: read the serial status register
(SSR), check that RDRF is set to “1,” then read receive data
from the receive data register (RDR) and compare with the
processor’s own ID. Transition of the RDRF bit from “0” to
“1” can be reported by an RXI interrupt. If the ID does not match
the receive data, set MPIE to “1” again and clear RDRF to “0.”
If the ID matches the receive data, clear RDRF to “0.”
4. SCI status check and data receiving: read SSR, check that
RDRF is set to “1,” then read data from the receive data register
(RDR) and write “0” in the RDRF bit. Transition of the RDRF bit
from “0” to “1” can be reported by an RXI interrupt.
3. Receive error handling and break detection: if a receive error
occurs, read the ORER and FER bits in SSR to identify the error.
After executing the necessary error handling, clear both ORER
and FER to “0.” Receiving cannot resume while ORER or FER
remains set to “1.” When a framing error occurs, the RxD pin
can be read to detect the break state.
Yes
No
Yes
No
H8/338 U.M. '92
Fig. 9-10
Initialize
Start error handling
210
Figure 9-11 shows an example of SCI receive operation using a multiprocessor format.
Figure 9-11. Example of SCI Receive Operation
(Eight-Bit Data with Multiprocessor Bit and One Stop Bit)
“1” Start
bit
“0” D0 D1 D7 “1”
Stop
bit
“1”
Data (ID1) MPB Start
bit
“0” D0 D1 D7 “0”
Stop
bit
“1”
Data (Data1) MPB “1”
Mark (idle)
state
MPIE
RDRF
H8/338 U.M. '92
Fig. 9-11
RDR value ID1
RXI request,
MPIE = “0” RXI handler reads
RDR data and clears
RDRF to “0”
Not own ID, so
MPIE is set to
“1” again
No RXI request,
RDR not updated
(Multiprocessor interrupt)
(a) Own ID does not match data
“1” Start
bit
“0” D0 D1 D7 “1”
Stop
bit
“1”
Data (ID2) MPB Start
bit
“0” D0 D1 D7 “0”
Stop
bit
“1”
Data (Data2) MPB “1”
Mark (idle)
state
MPIE
RDRF
RDR value ID2
RXI request,
MPIE = “0” RXI handler reads
RDR data and clears
RDRF to “0”
Own ID, so receiving
continues, with data
received at each RXI
MPIE set to
“1” again
(Multiprocessor interrupt)
(b) Own ID matches data
ID1 Data 2
211
9.3.3 Synchronous Mode
(1) Overview: In clocked synchronous mode, the SCI transmits and receives data in
synchronization with clock pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex
communication is possible. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 9-12 shows the general format in clocked synchronous serial communication.
Figure 9-12. Data Format in Clocked Synchronous Communication
In clocked synchronous serial communication, each data bit is sent on the communication line from
one falling edge of the serial clock to the next. Data are received in synchronization with the rising
edge of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB.
Serial clock
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
LSB MSB
Don’t care Don’t care
H8/338 U.M. '92
Fig. 9-12
One unit (character or frame) of serial data
* *
Note: High except in continuous transmitting or receiving*
212
• Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor
bit can be added.
• Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register
(SCR). See table 9-6.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains at the high level.
(2) Transmitting and Receiving Data
• SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See
figure 9-4. When switching from asynchronous mode to clocked synchronous mode, check that the
ORER, FER, and PER bits are cleared to “0.” Transmitting and receiving cannot begin if ORER,
FER, or PER is set to “1.”
213
• Transmitting Serial Data: Follow the procedure below for transmitting serial data.
Figure 9-13. Sample Flowchart for Serial Transmitting
Start transmitting
Read TDRE bit in SSR
TDRE = “1”?
Write transmit data in
TDR and clear TDRE bit to
“0” in SSR
End of
transmission?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function of the TxD pin is
selected automatically.
(a)
(b)
To continue transmitting serial data: read the TDRE bit to check
whether it is safe to write; if TDRE = “1,” write data in TDR, then
clear TDRE to “0.”
To end serial transmission: end of transmission can be confirmed
by checking transition of the TEND bit from “0” to “1.” This can be
reported by a TEI interrupt.
H8/338 U.M. '92
Fig. 9-13
Read TEND bit in SSR
TEND = “1”? No
Yes
SCI status check and transmit data write: read the serial status
register (SSR), check that the TDRE bit is “1,” then write transmit
data in the transmit data register (TDR) and clear TDRE to “0.”
Transition of the TDRE bit from “0” to “1” can be reported by a
TXI interrupt.
1.
3.
2.
Initialize
Clear TE bit to “0” in SCR
Serial transmission
214
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to “1,” the SCI requests
a TXI interrupt (TDR-empty interrupt) at this time.
If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of
the TDRE bit to “0.” If an external clock source is selected, the SCI outputs data in
synchronization with the input clock.
Data are output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is “0,” the SCI loads
data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is “1,” the
SCI sets the TEND bit in SSR to “1,” transmits the MSB, then holds the output in the MSB
state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to “1,” a TEI interrupt (TSR-
empty interrupt) is requested at this time.
4. After the end of serial transmission, the SCK pin is held at the high level.
215
Figure 9-14 shows an example of SCI transmit operation.
Figure 9-14. Example of SCI Transmit Operation
Serial clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
H8/338 U.M. '92
Fig. 9-14
TXI
request
TDRE
TEND
TXI interrupt
handler writes
data in TDR and
clears TDRE to “0”
TXI
request TEI
request
1 frame
216
• Receiving Serial Data: Follow the procedure below for receiving serial data. When switching
from asynchronous mode to clocked synchronous mode, be sure to check that PER and FER are
cleared to “0.” If PER or FER is set to “1” the RDRF bit will not be set and both transmitting and
receiving will be disabled.
Figure 9-15. Sample Flowchart for Serial Receiving
Start receiving
Read RDRF bit in SSR
RDRF = “1”?
Read receive data
from RDR, and clear
RDRF bit to “0” in SSR
ORER = “1”?
Read ORER in SSR
Finished
receiving?
Clear RE to “0” in SCR
End
Error handling
1
2
3
No
Yes
Yes
No
No
Yes
4
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
3. To continue receiving serial data: read RDR and clear RDRF to
“0” before the MSB (bit 7) of the current frame is received.
4. Receive error handling: if a receive error occurs, read the ORER
bit in SSR then, after executing the necessary error handling,
clear ORER to “0.” Neither transmitting nor receiving can
resume while ORER remains set to “1.” When clock output
mode is selected, receiving can be halted temporarily by
receiving one dummy byte and causing an overrun error.
When preparations to receive the next data are completed, clear
the ORER bit to “0.” This causes receiving to resume, so
H8/338 U.M. '92
Fig. 9-15
Clear ORER to “0” in SSR
Return
Overrun error handling
2. SCI status check and receive data read: read the serial status
register (SSR), check that RDRF is set to “1,” then read receive
data from the receive data register (RDR) and clear RDRF to “0.”
Transition of the RDRF bit from “0” to “1” can be reported by an
RXI interrupt.
return to the step marked 2 in the flowchart.
Start error handling
Initialize
217
In receiving, the SCI operates as follows.
1. If an external clock is selected, data are input in synchronization with the input clock. If clock
output is selected, as soon as the RE bit is set to “1” the SCI begins outputting the serial clock
and inputting data. If clock output is stopped because the ORER bit is set to “1,” output of the
serial clock and input of data resume as soon as the ORER bit is cleared to “0.”
2. Receive data are shifted into RSR in order from LSB to MSB.
After receiving the data, the SCI checks that RDRF is “0” so that receive data can be loaded
from RSR into RDR. If this check passes, the SCI sets RDRF to “1” and stores the received
data in RDR. If the check does not pass (receive error), the SCI operates as indicated in
table 9-8.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF
bit is not set to “1.” Be sure to clear the error flag.
3. After setting RDRF to “1,” if the RIE bit (receive-end interrupt enable) is set to “1” in SCR, the
SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to “1” and the RIE bit in
SCR is set to “1,” the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to “0” or the
ORER bit is set to “1.” To prevent clock count errors, it is safest to receive one dummy byte
and generate an overrun error.
218
Figure 9-16 shows an example of SCI receive operation.
Figure 9-16. Example of SCI Receive Operation
Serial clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
H8/338 U.M. '92
Fig. 9-16
RXI
request
RDRF
ORER
RXI interrupt
handler reads
data in RDR and
clears RDRF to “0”
RXI
request Overrun error,
ERI request
1 frame
219
• Transmitting and Receiving Serial Data Simultaneously: Follow the procedure below for
transmitting and receiving serial data simultaneously. If clock output mode is selected, output of
the serial clock begins simultaneously with serial transmission.
Figure 9-17. Sample Flowchart for Serial Transmitting and Receiving
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear
both TE and RE to “0,” then set both TE and RE to “1.”
Start
Read TDRE bit in SSR
TDRE = “1”?
Write transmit data
in TDR and clear TDRE
bit to “0” in SSR
ORER = “1”?
Read RDRF bit in SSR
End of
transmitting and receiv-
ing?
Clear TE and RE bits
to “0” in SCR
End
Error handling
1
2
3
No
Yes
Yes
No
No
Yes
5
1. SCI initialization: the transmit data output function of the TxD pin
and receive data input function of the RxD pin are selected,
enabling simultaneous transmitting and receiving.
4. To continue transmitting and receiving serial data: read RDR
and clear RDRF to “0” before the MSB (bit 7) of the current
frame is received. Also read the TDRE bit and check that it is
set to "1," indicating that it is safe to write; then write data
in TDR and clear TDRE to “0” before the MSB (bit 7) of the
current frame is transmitted.
H8/338 U.M. '92
Fig. 9-17
2. SCI status check and transmit data write: read the serial status
register (SSR), check that the TDRE bit is “1,” then write transmit
data in the transmit data register (TDR) and clear TDRE to “0.”
Transition of the TDRE bit from “0” to “1” can be reported by a
TXI interrupt.
RDRF = “1”?
Read receive data
from RDR and clear
RDRF bit to “0” in SSR
Read ORER bit in SSR
4
No
Yes
3. SCI status check and receive data read: read the serial status
register (SSR), check that the RDRF bit is “1,” then read receive
data from the receive data register (RDR) and clear RDRF to “0.”
Transition of the RDRF bit from “0” to “1” can be reported by an
RXI interrupt.
5. Receive error handling: if a receive error occurs, read the ORER
bit in SSR then, after executing the necessary error handling,
clear ORER to “0.” Neither transmitting nor receiving can resume
while ORER remains set to “1.”
Initialize
220
9.4 Interrupts
The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 9-9 indicates the
source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE,
RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each
interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources:
overrun error, framing error, and parity error.
The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates
that the SCI has stopped transmitting data.
Table 9-9. SCI Interrupt Sources
Interrupt Description Priority
ERI Receive-error interrupt (ORER, FER, or PER) High
RXI Receive-end interrupt (RDRF)
TXI TDR-empty interrupt (TDRE)
TEI TSR-empty interrupt (TEND) Low
9.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is “0,” before the old TDR contents
have been moved into the TSR, the old byte will be lost. Software should check that the TDRE bit
is set to “1” before writing to the TDR.
221
(2) Multiple Receive Errors: Table 9-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
Table 9-10. SSR Bit States and Data Transfer when Multiple Receive Errors Occur
SSR bits RSR →
Receive error RDRF ORER FER PER RDR*2
Overrun error 1*1 100No
Framing error 0 0 1 0 Yes
Parity error 0 0 0 1 Yes
Overrun and framing errors 1*1 110No
Overrun and parity errors 1*1 101No
Framing and parity errors 0 0 1 1 Yes
Overrun, framing, and parity errors 1*1 111No
Notes: *1 Set to “1” before the overrun error occurs.
*2 Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
(3) Line Break Detection: When the RxD pin receives a continuous stream of 0’s in asynchronous
mode (line-break state), a framing error occurs because the SCI detects a “0” stop bit. The value
H'00 is transferred from the RSR to the RDR. Software can detect the line-break state as a framing
error accompanied by H'00 data in the RDR.
The SCI continues to receive data, so if the FER bit is cleared to “0” another framing error will
occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by
the SCI in asynchronous mode runs at 16 times the baud rate. The falling edge of the start bit is
detected by sampling the RxD input on the falling edge of this clock. After the start bit is detected,
each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is
sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 9-18.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data
can theoretically be received with distortion up to the margin given by equation (2). This is a
theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
222
Figure 9-18. Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%] (1)
M: Receive margin
N: Ratio of basic clock to baud rate (N=16)
D: Duty factor of clock—ratio of High pulse width to Low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F = 0
M = (0.5 –1/2 × 16) × 100 [%] = 46.875% (2)
1
2
4
0
5
6
7
8
9
3
2
1
2
3
4
5
6
7
8
9
1
1
1
1
2
1
3
1
4
1
5
1
6
1
0
1
3
1
4
1
5
1
6
1
2
1
0
1
1
3
4
5
Basic clock
Sync sampling
Data sampling
D0
D1
Receive data
Start bit
–7.5 pulses
+7.5 pulses
Figure 9-18
223
Section 10. A/D Converter
10.1 Overview
The H8/338 Series includes an analog-to-digital converter module with eight input channels. A/D
conversion is performed by the successive approximations method with 8-bit resolution.
10.1.1 Features
The features of the on-chip A/D module are:
• 8-bit resolution
• Eight analog input channels
• Rapid conversion
Conversion time is 12.2µs per channel (minimum) with a 10MHz system clock
• Single and scan modes
— Single mode: A/D conversion is performed once.
— Scan mode: A/D conversion is performed in a repeated cycle on one to four channels.
• Four 8-bit data registers
These registers store A/D conversion results for up to four channels.
• Sample-and-hold function
• External triggering can be selected
• A CPU interrupt (ADI) can be requested at the completion of each A/D conversion cycle.
225
10.1.2 Block Diagram
Figure 10-1. Block Diagram of A/D Converter
Module data bus
Internal
data bus
Successive approximations register
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
Analog
multi-
plexer
+
–
Comparator
Sample and
hold circuit
Interrupt signal
Ø/8
Ø/16
Bus interface
ADTRG
ADI
8 Bit
D/A
Control circuit
AN0
AN2
AN1
AN3
AN4
AN5
AN6
AN7
AV
CC
AV
SS
Figure 10-1
ADCR: A/D Control Register (8 bits)
ADCSR: A/D Control/Status Register (8 bits)
ADDRA: A/D Data Register A (8 bits)
ADDRB: A/D Data Register B (8 bits)
ADDRC: A/D Data Register C (8 bits)
ADDRD: A/D Data Register D (8 bits)
226
10.1.3 Input Pins
Table 10-1 lists the input pins used by the A/D converter module.
The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN0to
AN3) and analog inputs 4 to 7 (AN4to AN7), respectively.
Table 10-1. A/D Input Pins
Name Abbreviation I/O Function
Analog supply voltage AVCC Input Power supply and reference voltage for the
analog circuits.
Analog ground AVSS Input Ground and reference voltage for the
analog circuits.
Analog input 0 AN0Input
Analog input 1 AN1Input Analog input pins, group 0
Analog input 2 AN2Input
Analog input 3 AN3Input
Analog input 4 AN4Input
Analog input 5 AN5Input Analog input pins, group 1
Analog input 6 AN6Input
Analog input 7 AN7Input
A/D external trigger ADTRG Input External trigger for starting A/D conversion
10.1.4 Register Configuration
Table 10-2 lists the registers of the A/D converter module.
Table 10-2. A/D Registers
Name Abbreviation R/W Initial value Address
A/D data register A ADDRA R H'00 H'FFE0
A/D data register B ADDRB R H'00 H'FFE2
A/D data register C ADDRC R H'00 H'FFE4
A/D data register D ADDRD R H'00 H'FFE6
A/D control/status register ADCSR R/(W)* H'00 H'FFE8
A/D control register ADCR R/W H'7E H'FFEA
Note: * Software can write a “0” to clear bit 7, but cannot write a “1” in this bit.
227
10.2 Register Descriptions
10.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE6
Bit 76543210
ADDRn
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results
of A/D conversion. Each data register is assigned to two analog input channels as indicated in
table 10-3.
The A/D data registers are always readable by the CPU.
The A/D data registers are initialized to H'00 at a reset and in the standby modes.
Table 10-3. Assignment of Data Registers to Analog Input Channels
Analog input channel
Group 0 Group 1 A/D data register
AN0AN4ADDRA
AN1AN5ADDRB
AN2AN6ADDRC
AN3AN7ADDRD
10.2.2 A/D Control/Status Register (ADCSR)—H'FFE8
Bit 76543210
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W
Note: * Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
228
The ADCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF Description
0 To clear ADF, the CPU must read ADF after (Initial value)
it has been set to “1,” then write a “0” in this bit.
1 This bit is set to 1 at the following times:
(1) Single mode: when one A/D conversion is completed.
(2) Scan mode: when inputs on all selected channels have been
converted.
Bit 6—A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt (ADI)
when A/D conversion is completed.
Bit 6
ADIE Description
0 The A/D interrupt request (ADI) is disabled. (Initial value)
1 The A/D interrupt request (ADI) is enabled.
Bit 5—A/D Start (ADST): The A/D converter operates while this bit is set to “1.” This bit can be
set to “1” by the external trigger signal ADTRG.
Bit 5
ADST Description
0 A/D conversion is halted. (Initial value)
1 (1) Single mode: One A/D conversion is performed. The ADST bit is
automatically cleared to “0” at the end of the conversion.
(2) Scan mode: A/D conversion starts and continues cyclically on the
selected channels until the ADST bit is cleared to “0” by software (or
a reset, or by entry to a standby mode).
229
Bit 4—Scan Mode (SCAN): This bit selects the scan mode or single mode of operation.
See section 10.3, “Operation” for descriptions of these modes.
The mode should be changed only when the ADST bit is cleared to “0.”
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode
Bit 3—Clock Select (CKS): This bit controls the A/D conversion time.
The conversion time should be changed only when the ADST bit is cleared to “0.”
Bit 3
CKS Description
0 Conversion time = 242 states (max) (Initial value)
1 Conversion time = 122 states (max)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select
one or more analog input channels.
The channel selection should be changed only when the ADST bit is cleared to “0.”
Group select Channel select Selected channels
CH2 CH1 CH0 Single mode Scan mode
0 0 0 AN0(Initial value) AN0
0 1 AN1AN0, AN1
1 0 AN2AN0to AN2
1 1 AN3AN0to AN3
1 0 0 AN4AN4
0 1 AN5AN4, AN5
1 0 AN6AN4to AN6
1 1 AN7AN4to AN7
230
10.2.3 A/D Control Register (ADCR)—H'FFEA
Bit 76543210
TRGE — — — — — — CHS
Initial value 0 1 1 1 1 1 1 0
Read/Write R/W — — — — — — R/W
The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the
A/D external trigger signal.
The ADCR is initialized to H'7E at a reset and in the standby modes.
Bit 7—Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal to set
the ADST bit and start A/D conversion.
Bit 7
TRGE Description
0 A/D external trigger is disabled. ADTRG does not set (Initial value)
the ADST bit.
1 A/D external trigger is enabled. ADTRG sets the ADST bit.
(The ADST bit can also be set by software.)
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as “1.”
Bit 0—Channel Set Select (CHS): This bit is reserved. It does not affect any operation in the
H8/338 Series.
231
10.3 Operation
The A/D converter performs 8 successive approximations to obtain a result ranging from H'00
(corresponding to AVSS) to H'FF (corresponding to AVCC).
The A/D converter module can be programmed to operate in single mode or scan mode as
explained below.
10.3.1 Single Mode (SCAN = 0)
The single mode is suitable for obtaining a single data value from a single channel. A/D
conversion starts when the ADST bit is set to “1,” either by software or by a High-to-Low
transition of the
ADTRG
signal (if enabled). During the conversion process the ADST bit remains
set to “1.” When conversion is completed, the ADST bit is automatically cleared to “0.”
When the conversion is completed, the ADF bit is set to “1.” If the interrupt enable bit (ADIE) is
also set to “1,” an A/D conversion end interrupt (ADI) is requested, so that the converted data can
be processed by an interrupt-handling routine. The ADF bit is cleared when software reads the
A/D control/status register (ADCSR), then writes a “0” in this bit.
Before selecting the single mode, clock, and analog input channel, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
when the ADST bit is set to “1” again. The same instruction can be used to alter the mode and
channel selection and set ADST to “1.”
232
The following example explains the A/D conversion process in single mode when channel 1 (AN1)
is selected and the external trigger is disabled. Figure 10-2 shows the corresponding timing chart.
(1) Software clears the ADST bit to “0,” then selects the single mode (SCAN = “0”) and channel 1
(CH2 to CH0 = “001”), enables the A/D interrupt request (ADIE = “1”), and sets the ADST bit
to “1” to start A/D conversion.
Coding Example: (when using the slow clock, CKS = “0”)
BCLR #5, @H'FFE8 ;Clear ADST
MOV.B #H'7F, ROL
MOV.B ROL, @H'FFEA ;Disable external trigger
MOV.B #H'61, ROL
MOV.B ROL, @H'FFE8 ;Select mode and channel and set ADST to “1”
Value set in ADCSR:
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
01100001
(2) The A/D converter converts the voltage level at the AN1input pin to a digital value. At the end
of the conversion process the A/D converter transfers the result to register ADDRB, sets the
ADF bit to “1,” clears the ADST bit to “0,” and halts.
(3) ADF = “1” and ADIE = “1,” so an A/D interrupt is requested.
(4) The user-coded A/D interrupt-handling routine is started.
(5) The interrupt-handling routine reads the ADCSR value, then writes a “0” in the ADF bit to
clear this bit to “0.”
(6) The interrupt-handling routine reads and processes the A/D conversion result (ADDRB).
(7) The routine ends.
Steps (2) to (7) can now be repeated by setting the ADST bit to “1” again.
233
Note: * indicates execution of a software instruction
Waiting A/D conver-
sion
➀
Waiting
A/D conver-
sion ➁
Waiting
Waiting
Waiting
Waiting
Set*
➝
Clear*
➝
A/D conversion starts
➝
Set*
➝
➝
➀ ➁
Read result Read result
A/D conversion result A/D conversion result
Set*
➝
Clear*
➝
➝
ADST
ADF
Channel 0 (AN 0)
Channel 1 (AN 1)
Channel 2 (AN 2)
Channel 3 (AN 3)
ADDRA
ADDRB
ADDRC
ADDRD
Interrupt (ADI)
ADIE
Figure 10-3
Figure 10-2. A/D Operation in Single Mode (when Channel 1 is Selected)
234
10.3.2 Scan Mode (SCAN = 1)
The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit
is set to “1,” either by software or by a High-to-Low transition of the ADTRG signal (if enabled),
A/D conversion starts from the first channel selected by the CH bits. When CH2 = “0” the first
channel is AN0. When CH2 = “1” the first channel is AN4.
If the scan group includes more than one channel (i.e., if bit CH1 or CH0 is set), conversion of the
next channel (AN1or AN5) begins as soon as conversion of the first channel ends.
Conversion of the selected channels continues cyclically until the ADST bit is cleared to “0.” The
conversion results are placed in the data registers corresponding to the selected channels. The A/D
data registers are readable by the CPU.
Before selecting the scan mode, clock, and analog input channels, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
from the first selected channel when the ADST bit is set to “1” again. The same instruction can be
used to alter the mode and channel selection and set ADST to “1.”
The following example explains the A/D conversion process when three channels in group 0 are
selected (AN0, AN1, and AN2) and the external trigger is disabled. Figure 10-3 shows the
corresponding timing chart.
(1) Software clears the ADST bit to “0,” then selects the scan mode (SCAN = “1”), scan group 0
(CH2 = “0”), and analog input channels AN0to AN2(CH1 = “1” and CH0 = “0”) and sets the
ADST bit to “1” to start A/D conversion.
Coding Example: (with slow clock and ADI interrupt enabled)
BCLR #5, @H'FFE8 ;Clear ADST
MOV.B #H'7F, ROL
MOV.B ROL, @H'FFEA ;Disable external trigger
MOV.B #H'72, ROL
MOV.B ROL, @H'FFE8 ;Select mode and channels and set ADST to “1”
Value set in ADCSR
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
01110010
235
(2) The A/D converter converts the voltage level at the AN0input pin to a digital value, and
transfers the result to register ADDRA.
(3) Next the A/D converter converts AN1and transfers the result to ADDRB. Then it converts
AN2and transfers the result to ADDRC.
(4) After all selected channels (AN0to AN2) have been converted, the AD converter sets the ADF
bit to “1.” If the ADIE bit is set to “1,” an A/D interrupt (ADI) is requested. Then the A/D
converter begins converting AN0again.
(5) Steps (2) to (4) are repeated cyclically as long as the ADST bit remains set to “1.”
To stop the A/D converter, software must clear the ADST bit to “0.”
Regardless of which channel is being converted when the ADST bit is cleared to “0,” when the
ADST bit is set to “1” again, conversion begins from the the first selected channel (AN0).
236
ADST
ADF
Channel 0 (AN 0)
Channel 1 (AN 1)
Channel 2 (AN 2)
Channel 3 (AN 3)
ADDRA
ADDRB
ADDRC
ADDRD
Continuous A/D conversion
Set Clear
Clear
A/D conversion
time
Waiting A/D conver-
sion➀Waiting A/D conver-
sion➃Waiting
Waiting A/D conver-
sion ➁Waiting A/D conver-
sion Waiting
Waiting A/D conver-
sion ➂Waiting
Waiting
Transfer
A/D conver-
sion result➀A/D conversion result➃
A/D conversion result
A/D conversion result ➂
➁
➝
➝
➝
➄
*1
➝
Figure 10-4
*1
*1
*2
Notes: *1 indicates execution of a software instruction
*2 Data undergoing conversion when ADST bit is cleared are ignored.
Figure 10-3. A/D Operation in Scan Mode (when Channels 0 to 2 are Selected)
237
10.3.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time tDafter the ADST bit is set to “1.” The sampling process lasts for a time tSPL. The actual A/D
conversion begins after sampling is completed. Figure 10-4 shows the timing of these steps.
Table 10-4 (a) lists the conversion times for the single mode. Table 10-4 (b) lists the conversion
times for the scan mode.
The total conversion time (tCONV) includes tDand tSPL. The purpose of tDis to synchronize the
ADCSR write time with the A/D conversion process, so the length of tDis variable. The total
conversion time therefore varies within the minimum to maximum ranges indicated in table 10-4
(a) and (b).
In the scan mode, the ranges given in table 10-4 (b) apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = “0”) or 128 states
(when CKS = “1”).
Figure 10-4. A/D Conversion Timing
Ø
Internal address bus
Write signal
Input sampling timing
ADF
t
D
t
SPL
(1)
(2)
t
CONV
Figure 10-4
(1):
(2):
tD:
tSPL:
tCONV:
ADCSR write cycle
ADCSR address
Synchronization delay
Input sampling time
Total A/D conversion time
238
Table 10-4 (a). A/D Conversion Time (Single Mode)
CKS = “0” CKS = “1”
Item Symbol Min Typ Max Min Typ Max
Synchronization delay tD18 — 33 10 — 17
Input sampling time tSPL — 63 — — 31 —
Total A/D conversion time tCONV 227 — 242 115 — 122
Table 10-4 (b). A/D Conversion Time (Scan Mode)
CKS = “0” CKS = “1”
Item Symbol Min Typ Max Min Typ Max
Synchronization delay tD18 — 33 10 — 17
Input sampling time tSPL — 63 — — 31 —
Total A/D conversion time tCONV 259 — 274 131 — 138
Note: Values in the tables above are numbers of states.
10.3.4 External Trigger Input Timing
A/D conversion can be started by external trigger input at the ADTRG pin. This input is enabled or
disabled by the TRGE bit in the A/D control register (ADCR). If the TRGE bit is set to “1,” when
a falling edge of ADTRG is detected the ADST bit is set to “1” and A/D conversion begins.
Subsequent operation in both single and scan modes is the same as when the ADST bit is set to “1”
by software.
Figure 10-5 shows the trigger timing.
239
Figure 10-5. External Trigger Input Timing
10.4 Interrupts
The A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/D
conversion.
The ADI interrupt request can be enabled or disabled by the ADIE bit in the A/D control/status
register (ADCSR).
Ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Fig. 10-5
240
Section 11. D/A Converter
11.1 Overview
The H8/338 Series has an on-chip D/A converter module with two channels.
11.1.1 Features
Features of the D/A converter module are listed below.
• Eight-bit resolution
• Two-channel output
• Maximum conversion time: 10µs (with 30pF load capacitance)
• Output voltage: 0V to AVCC
11.1.2 Block Diagram
Figure 11-1 shows a block diagram of the D/A converter.
Figure 11-1. D/A Converter Block Diagram
Bus interface
Module data bus Internal data bus
8-bit D/A
DADR0
DADR1
DACR
Control
circuit
AV
DA
DA
AV
CC
0
1
SS
DACR:
DADR0:
DADR1:
H8/337 U.M. '91
Figure 11-1
D/A control register
D/A data register 0
D/A data register 1
241
11.1.3 Input and Output Pins
Table 11-1 lists the input and output pins used by the D/A converter module.
Table 11-1. Input and Output Pins of D/A Converter Module
Name Abbreviation I/O Function
Analog supply voltage AVCC Input Power supply and reference voltage for analog
circuits
Analog ground AVSS Input Ground and reference voltage for analog circuits
Analog output 0 DA0Output Analog output channel 0
Analog output 1 DA1Output Analog output channel 1
11.1.4 Register Configuration
Table 11-2 lists the three registers of the D/A converter module.
Table 11-2. D/A Converter Registers
Name Abbreviation R/W Initial value Address
D/A data register 0 DADR0 R/W H'00 H'FFA8
D/A data register 1 DADR1 R/W H'00 H'FFA9
D/A control register DACR R/W H'1F H'FFAA
242
11.2 Register Descriptions
11.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) H'FFA8, H'FFA9
Bit 76543210
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable and writable registers that
store data to be converted. When analog output is enabled, the value in the D/A data register is
converted and output continuously at the analog output pin.
The D/A data registers are initialized to H'00 at a reset and in the standby modes.
11.2.2 D/A Control Register (DACR) H'FFAA
Bit 76543210
DAOE1 DAOE0 DAE — — — — —
Initial value 0 0 0 1 1 1 1 1
Read/Write R/W R/W R/W — — — — —
The D/A control register is an 8-bit readable and writable register that controls the operation of the
D/A converter module.
The D/A control register is initialized to H'1F at a reset and in the standby modes.
Bit 7—D/A Output Enable 1 (DAOE1): Controls analog output from the D/A converter.
Bit 7
DAOE1 Description
0 Analog output at DA1is disabled.
1 D/A conversion is enabled on channel 1. Analog output is enabled at DA1.
243
Bit 6—D/A Output Enable 0 (DAOE0): Controls analog output from the D/A converter.
Bit 6
DAOE0 Description
0 Analog output at DA0is disabled.
1 D/A conversion is enabled on channel 0. Analog output is enabled at DA0.
Bit 5—D/A Enable (DAE): Controls analog output from the D/A converter, in combination with
bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when
DAE = 0. Channels 0 and 1 are controlled together when DAE = 1.
Whether or not to output the converted results is always controlled independently by DAOE0 and
DAOE1.
Bit 7 Bit 6 Bit 5
DAOE1 DAOE0 DAE D/A conversion
0 0 — Disabled on channels 0 and 1.
0 1 0 Enabled on channel 0.
Disabled on channel 1.
0 1 1 Enabled on channels 0 and 1.
1 0 0 Disabled on channel 0.
Enabled on channel 1.
1 0 1 Enabled on channels 0 and 1.
1 1 — Enabled on channels 0 and 1.
When the DAE bit is set to “1,” analog power supply current drain is the same as during A/D and
D/A conversion, even if the DAOE0 and DAOE1 bits in DACR and the ADST bit in ADSCR are
cleared to “0.”
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as “1.”
244
11.3 Operation
The D/A converter module has two built-in D/A converter circuits that can operate independently.
D/A conversion is performed continuously whenever enabled by the D/A control register. When a
new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The
converted result is output by setting the DAOE0 or DAOE1 bit to “1.”
An example of conversion on channel 0 is given next. Figure 11-2 shows the timing.
(1) Software writes the data to be converted in DADR0.
(2) D/A conversion begins when the DAOE0 bit in DACR is set to “1.” After a conversion delay,
analog output appears at the DA0 pin. The output value is AVCC
×(DADR0 value)/256.
This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.
(3) If a new value is written in DADR0, conversion begins immediately. Output of the converted
result begins after the conversion delay time.
(4) When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
Figure 11-2. D/A Conversion (Example)
DADR0
write cycle DACR
write cycle DADR0
write cycle DACR
write cycle
Address
Ø
DADR0
DAOE0
DA0
Conversion data ➀Conversion data ➁
High-impedance state
Conversion result ➀Conversion result ➁
tDCONVtDCONV
t :D/A conversion timeDCONV
H8/337 U.M. '91
Fig. 11-2
245
Section 12. RAM
12.1 Overview
The H8/338 includes 2k bytes of on-chip static RAM. The H8/337 and H8/336 have 1k byte. The
RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip
RAM are performed in two states, enabling rapid data transfer and instruction execution.
The on-chip RAM is assigned to addresses H'F780 to H'FF7F in the address space of the H8/338,
and addresses H'FB80 to H'FF7F in the address space of the H8/337 and H8/336. The RAME bit in
the system control register (SYSCR) can enable or disable the on-chip RAM, permitting these
addresses to be allocated to external memory instead, if so desired.
12.2 Block Diagram
Figure 12-1 is a block diagram of the on-chip RAM.
Figure 12-1. Block Diagram of On-Chip RAM (H8/338)
H'FF7E
Internal data bus (lower 8 bits)
Internal data bus (upper 8 bits)
H'FF7F
H'F782
H'F780
H'F783
H'F781
Even address
Odd address
On-chip RAM
247
12.3 RAM Enable Bit (RAME) in System Control Register (SYSCR)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control
register (SYSCR).
Bit 76543210
SSBY STS2 STS1 STS0 — NMIEG DPME RAME
Initial value 0 0 0 0 1 0 0 1
Read/Write R/W R/W R/W R/W — R/W R/W R/W
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See
section 2.2, “System Control Register,” for the other bits.
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized to “1” on the rising edge of the
RES
signal, so a reset enables the on-
chip RAM. The RAME bit is not initialized in the software standby mode.
Bit 7
RAME Description
0 On-chip RAM is disabled.
1 On-chip RAM is enabled. (Initial value)
12.4 Operation
12.4.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to “1,” accesses to addresses H'F780 to H'FF7F in the H8/338 and addresses
H'FB80 to H'FF7F in the H8/337 and H8/336 are directed to the on-chip RAM. If the RAME bit is
cleared to “0,” accesses to these addresses are directed to the external data bus.
12.4.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to “1,” accesses to addresses H'F780 to H'FF7F in the H8/338 and addresses
H'FB80 to H'FF7F in the H8/337 and H8/336 are directed to the on-chip RAM.
If the RAME bit is cleared to “0,” the on-chip RAM data cannot be accessed. Attempted write
access has no effect. Attempted read access always results in H'FF data being read.
248
Section 13. ROM
13.1 Overview
The H8/338 includes 48k bytes of high-speed, on-chip ROM. The H8/337 has 32k bytes. The
H8/336 has 24k bytes. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte
data and word data are accessed in two states, enabling rapid data transfer and instruction fetching.
The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is
determined by the inputs at the mode pins (MD1and MD0). See table 13-1.
Table 13-1. On-Chip ROM Usage in Each MCU Mode
Mode pins
Mode MD1MD0On-chip ROM
Mode 1 (expanded mode) 0 1 Disabled (external addresses)
Mode 2 (expanded mode) 1 0 Enabled
Mode 3 (single-chip mode) 1 1 Enabled
The H8/338 and H8/337 are available with electrically programmable ROM (PROM), or with
masked ROM. The PROM version has a PROM mode in which the chip can be programmed with
a standard PROM writer.
249
13.1.1 Block Diagram
Figure 13-1 is a block diagram of the on-chip ROM.
Figure 13-1. Block Diagram of On-Chip ROM (H8/338)
13.2 PROM Mode (H8/338, H8/337)
13.2.1 PROM Mode Setup
In the PROM mode of the PROM version of the H8/338 and H8/337, the usual microcomputer
functions are halted to allow the on-chip PROM to be programmed. The programming method is
the same as for the HN27C101.
To select the PROM mode, apply the signal inputs listed in table 13-2.
Table 13-2. Selection of PROM Mode
Pin Input
Mode pin MD1Low
Mode pin MD0Low
STBY pin Low
Pins P63and P64High
H'0002
H'0000
Internal data bus (lower 8 bits)
Internal data bus (upper 8 bits)
H'0003
H'0001
H'BFFF
H'BFFE
On-chip ROM
Even addresses
Odd addresses
250
13.2.2 Socket Adapter Pin Assignments and Memory Map
The H8/338 and H8/337 can be programmed with a general-purpose PROM writer by using a
socket adapter to change the pin-out to 32 pins. There are different socket adapters for different
packages as listed in table 13-3. The same socket adapters can be used for both the H8/338 and
H8/337. Figure 13-2 shows the socket adapter pin assignments.
Table 13-3. Socket Adapters
Package Socket adapter
84-pin PLCC HS338ESC02H
84-pin windowed LCC HS338ESG02H
80-pin QFP HS338ESH02H
The PROM size is 48k bytes for the H8/338 and 32k bytes for the H8/337. Figures 13-3 and 13-4
show memory maps of the H8/338 and H8/337 in PROM mode. H'FF data should be specified for
unused address areas in the on-chip PROM.
When programming with a PROM writer, limit the program address range to H'0000 to H'BFFF for
the H8/338 and H'0000 to H'7FFF for the H8/337. Specify H'FF data for addresses H'C000 and
above (H8/338) or H'8000 and above (H8/337). If these addresses are programmed by mistake, it
may become impossible to program or verify the PROM data. The same problem may occur if an
attempt is made to program the chip in page programming mode. Particular care is required with a
plastic package, since the programmed data cannot be erased.
251
Figure 13-2. Socket Adapter Pin Assignments
FP-80A
1
6
65
66
67
68
69
70
71
72
64
63
62
61
60
59
58
57
55
54
53
52
51
50
49
48
20
19
18
24
25
29
8
47
5
4
7
38
12
56
73
—
—
—
—
CG-84,
CP-84 Pin
RES
NMI
P3
P3
P3
P3
P3
P3
P3
P3
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
P9
P9
P9
P6
P6
AV
V
V
MD
MD
STBY
AV
V
V
V
V
V
V
V
12
17
79
80
81
82
83
84
1
3
78
77
76
75
74
73
72
71
69
68
67
66
65
63
62
61
32
31
30
36
37
42
19
60
16
15
18
51
2
4
23
24
41
64
70
Pin
V
EA
EO
EO
EO
EO
EO
EO
EO
EO
EA
EA
EA
EA
EA
EA
EA
EA
EA
OE
EA
EA
EA
EA
EA
CE
EA
EA
PGM
V
V
HN27C101
(32 pins)
1
26
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
2
3
31
32
16
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
CC
CC
CC
0
1
SS
SS
SS
SS
SS
SS
SS
SS
9
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
10
11
12
13
14
16
15
PP
CC
H8/337, H8/338 EPROM Socket
Note: All pins not listed in this figure should be left open.
V :
EO to EO :
EA to EA :
OE:
CE:
PGM:
PP
07
016
Program voltage (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program enable
H8/337 U.M. '91
Fig. 13-2
SS
252
Figure 13-3. H8/338 Memory Map in PROM Mode
Figure 13-4. H8/337 Memory Map in PROM Mode
H'BFFF
H'BFFF
Undetermined
output*
If this address area is read in PROM mode,
the output data are undetermined.
H'1FFFF
Address in PROM mode
Address in MCU mode
H'0000
H'0000
On-chip
PROM
Note: *
Fig. 13-3
H'7FFF
H'7FFF
Undetermined
output*
If this address area is read in PROM mode,
the output data are undetermined.
H'1FFFF
Address in PROM mode
Address in MCU mode
H'0000
H'0000
On-chip
PROM
Note: *
Fig. 13-4
253
13.3 Programming
The write, verify, and other sub-modes of the PROM mode are selected as shown in table 13-4.
Table 13-4. Selection of Sub-Modes in PROM Mode
Sub-Mode CE OE PGM VPP VCC EO7to EO0EA16 to EA0
Write Low High Low VPP VCC Data input Address input
Verify Low Low High VPP VCC Data output Address input
Programming Low Low Low VPP VCC High impedance Address input
inhibited Low High High
High Low Low
High High High
Note: The VPP and VCC pins must be held at the VPP and VCC voltage levels.
The H8/338 or H8/337 PROM has the same standard read/write specifications as the HN27C101
EPROM. Page programming is not supported, however, so do not select page programming mode.
PROM writers that provide only page programming cannot be used. When selecting a PROM
writer, check that it supports the byte-at-a-time high-speed programming mode. Be sure to set the
address range to H'0000 to H'BFFF for the H8/338, and to H'0000 to H'7FFF for the H8/337.
13.3.1 Writing and Verifying
An efficient, high-speed programming procedure can be used to write and verify PROM data. This
procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing
data reliability. It leaves the data H'FF written in unused addresses.
254
Figure 13-5 shows the basic high-speed programming flowchart.
Tables 13-5 and 13-6 list the electrical characteristics of the chip in the PROM mode. Figure 13-6
shows a write/verify timing chart.
Figure 13-5. High-Speed Programming Flowchart
Yes
No
Yes
No
Yes
n < 25?
Error
No
Yes
Address + 1
→
Address
No
Figure 13-5
START
Address = 0
n = 0
Set read mode
VCC = 5.0V ±0.25V, VPP = VCC
END
All addresses read?
n + 1
→
n
Last address?
Program tPW = 0.2 ms ±5%
Program tOPW = 0.2n ms
Verify OK?
Set program/verify mode
VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V
255
Table 13-5. DC Characteristics
(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V, Ta = 25˚C ±5˚C)
Measurement
Item Symbol Min Typ Max Unit conditions
Input High voltage EO7– EO0, VIH 2.4 — VCC + 0.3 V
A16 – A0,
OE, CE, PGM
Input Low voltage EO7– EO0, VIL –0.3 — 0.8 V
A16 – A0,
OE, CE, PGM
Output High voltage EO7– EO0VOH 2.4 — — V IOH = –200µA
Output Low voltage EO7– EO0VOL — — 0.45 V IOL = 1.6mA
Input leakage EO7– EO0, |ILI| — — 2 µA Vin = 5.25V/
current EA16 – EA0, 0.5V
OE, CE, PGM
VCC current ICC — — 40 mA
VPP current IPP — — 40 mA
Table 13-6. AC Characteristics
(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25˚C ±5˚C)
Measurement
Item Symbol Min Typ Max Unit conditions
Address setup time tAS 2 — — µs See figure 13-6*
OE setup time tOES 2 — — µs
Data setup time tDS 2 — — µs
Address hold time tAH 0 — — µs
Data hold time tDH 2 — — µs
Data output disable time tDF — — 130 ns
Vpp setup time tVPS 2 — — µs
Program pulse width tPW 0.19 0.20 0.21 ms
Note: * Input pulse level: 0.8V to 2.2V
Input rise/fall time ≤20ns
Timing reference levels: input—1.0V, 2.0V; output—0.8V, 2.0V
256
Table 13-6. AC Characteristics (cont.)
(when VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25˚C ±5˚C)
Measurement
Item Symbol Min Typ Max Unit conditions
OE pulse width for tOPW 0.19 — 5.25 ms See figure 13-6*
overwrite-programming
VCC setup time tVCS 2 — — µs
CE setup time tCES 2 — — µs
Data output delay time tOE 0 — 150 ns
Note: * Input pulse level: 0.8V to 2.2V
Input rise/fall time ≤20ns
Timing reference levels: input—1.0V, 2.0V; output—0.8V, 2.0V
Figure 13-6. PROM Write/Verify Timing
OE
PGM
Write
Verify
Address
Data
Input data
Output data
tVPS
tDS
tDH
tAS
tAH
tDF
VPP
VPP
VCC
VCC + 1
tVCS
tPW
tOES
tOE
VCC
Figure 13-6
CE
tCES
VCC
tOPW
257
13.3.2 Notes on Writing
(1) Write with the specified voltages and timing. The programming voltage (VPP) is 12.5V.
Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be
particularly careful about the PROM writer’s overshoot characteristics.
If the PROM writer is set to HN27C101 specifications, VPP will be 12.5V.
(2) Before writing data, check that the socket adapter and chip are correctly mounted in the
PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM writer,
socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while writing. Touching either of these can cause
contact faults and write errors.
(4) Page programming is not supported. Do not select page programming mode.
(5) The H8/338 PROM size is 48K bytes. The H8/337 PROM size is 32K bytes. Set the
address range to H'0000 to H'BFFF for the H8/338, and to H'0000 to H'7FFF for the H8/337.
When programming, specify H'FF data for unused address areas (H'C000 to H'1FFFF in the
H8/338, H'8000 to H'1FFFF in the H8/337).
13.3.3 Reliability of Written Data
An effective way to assure the data holding characteristics of the programmed chips is to bake them
at 150˚C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 13-7 shows the recommended screening procedure.
258
Figure 13-7. Recommended Screening Procedure
If a series of write errors occurs while the same PROM writer is in use, stop programming and
check the PROM writer and socket adapter for defects, using a microcomputer chip with a
windowed package and on-chip EPROM.
Please inform Hitachi of any abnormal conditions noted during programming or in screening of
program data after high-temperature baking.
13.3.4 Erasing of Data
The windowed package enables data to be erased by illuminating the window with ultraviolet light.
Table 13-7 lists the erasing conditions.
Table 13-7. Erasing Conditions
Item Value
Ultraviolet wavelength 253.7 nm
Minimum illumination 15W·s/cm2
The conditions in table 13-7 can be satisfied by placing a 12000µW/cm2ultraviolet lamp 2 or 3
centimeters directly above the chip and leaving it on for about 20 minutes.
Write and verify program
Read and check program
VCC = 5V
Install
Note: * Baking time should be measured from the point when the baking oven reaches 150°C.
Bake with power off
150° ± 10°C, 48 Hr
+ 8 Hr *
– 0 Hr
Fig. 11-7
259
13.4 Handling of Windowed Packages
(1) Glass Erasing Window: Rubbing the glass erasing window of a windowed package with a
plastic material or touching it with an electrically charged object can create a static charge on the
window surface which may cause the chip to malfunction.
If the erasing window becomes charged, the charge can be neutralized by a short exposure to
ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored
in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward.
Accumulation of static charge on the window surface can be prevented by the following
precautions:
①When handling the package, ground yourself. Don’t wear gloves. Avoid other possible
sources of static charge.
②Avoid friction between the glass window and plastic or other materials that tend to accumulate
static charge.
③Be careful when using cooling sprays, since they may have a slight ion content.
④Cover the window with an ultraviolet-shield label, preferably a label including a conductive
material. Besides protecting the PROM contents from ultraviolet light, the label protects the
chip by distributing static charge uniformly.
(2) Handling after Programming: Fluorescent light and sunlight contain small amounts of
ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. In
addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip
malfunction. It is recommended that after programming the chip, you cover the erasing window
with a light-proof label (such as an ultraviolet-shield label).
(3) Note on 84-Pin LCC Package: A socket should always be used when the 84-pin LCC
package is mounted on a printed-circuit board. Table 13-8 lists the recommended socket.
Table 13-8. Recommended Socket for Mounting 84-Pin LCC Package
Manufacturer Code
Sumitomo 3-M 284-1273-00-1102J
260
Section 14. Power-Down State
14.1 Overview
The H8/338 Series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 14-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 14-1. Power-Down State
Entering CPU Sup. I/O Exiting
Mode procedure Clock CPU Reg’s. Mod. RAM ports methods
Sleep Execute Run Halt Held Run Held Held • Interrupt
mode SLEEP • RES
instruction • STBY
Soft- Set SSBY bit Halt Halt Held Halt Held Held • NMI
ware in SYSCR to and • IRQ0– IRQ2
standby “1,” then initial- • RES
mode execute SLEEP ized • STBY
instruction
Hard- Set STBY Halt Halt Not Halt Held High • STBY High,
ware pin to Low held and impe- then RES
standby level initialized dance Low
→ High
mode state
Notes: 1. SYSCR: System control register
2. SSBY: Software standby bit
261
14.2 System Control Register: Power-Down Control Bits
Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically,
they concern the software standby mode.
Table 14-2 lists the attributes of the system control register.
Table 14-2. System Control Register
Name Abbreviation R/W Initial value Address
System control register SYSCR R/W H'09 H'FFC4
Bit 76543210
SSBY STS2 STS1 STS0 — NMIEG DPME RAME
Initial value 0 0 0 0 1 0 0 1
Read/Write R/W R/W R/W R/W — R/W R/W R/W
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to “1.”
To clear this bit, software must write a “0.”
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to the sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to the software
standby mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip
supporting modules.
262
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Settling time = 8192 states (Initial value)
0 0 1 Settling time = 16384 states
0 1 0 Settling time = 32768 states
0 1 1 Settling time = 65536 states
1 — — Settling time = 131072 states
When the on-chip clock pulse generator is used, the STS bits should be set to allow a settling time
of at least 10ms. Table 14-3 lists the settling times selected by these bits at several clock
frequencies and indicates the recommended settings.
When the chip is externally clocked, the STS bits can be set to any value. The minimum value
(STS2 = STS1 = STS0 = “0”) is recommended.
Table 14-3. Times Set by Standby Timer Select Bits (Unit: ms)
Settling
time System clock frequency (MHz)
STS2 STS1 STS0 (states) 10 8 6 4 2 1 0.5
0 0 0 8192 0.8 1.0 1.3 2.0 4.1 8.2 16.4
0 0 1 16384 1.6 2.0 2.7 4.1 8.2 16.4 32.8
0 1 0 32768 3.3 4.1 5.5 8.2 16.4 32.8 65.5
0 1 1 65536 6.6 8.2 10.9 16.4 32.8 65.5 131.1
1 — — 131072 13.1 16.4 21.8 32.8 65.5 131.1 262.1
Notes: 1. All times are in milliseconds.
2. Recommended values are printed in boldface.
263
14.3 Sleep Mode
The sleep mode provides an effective way to conserve power while the CPU is waiting for an
external interrupt or an interrupt from an on-chip supporting module.
14.3.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to “0,” execution of the SLEEP
instruction causes a transition from the program execution state to the sleep mode. After executing
the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged.
The on-chip supporting modules continue to operate normally.
14.3.2 Exit from Sleep Mode
The chip wakes up from the sleep mode when it receives an internal or external interrupt request, or
a Low input at the RES or STBY pin.
(1) Wake-Up by Interrupt: An interrupt releases the sleep mode and starts the CPU’s interrupt-
handling sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable
bit in the module’s control register, the interrupt cannot be requested, so it cannot wake the chip up.
Similarly, the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask) bit in
the CCR (condition code register) is set when the SLEEP instruction is executed.
(2) Wake-Up by RES pin: When the RES pin goes Low, the chip exits from the sleep mode to
the reset state.
(3) Wake-Up by STBY pin: When the STBY pin goes Low, the chip exits from the sleep mode to
the hardware standby mode.
264
14.4 Software Standby Mode
In the software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. Power consumption is reduced to
an extremely low level. The on-chip supporting modules and their registers are reset to their initial
states, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents
of the CPU registers and on-chip RAM remain unchanged.
14.4.1 Transition to Software Standby Mode
To enter the software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to “1,” then execute the SLEEP instruction.
14.4.2 Exit from Software Standby Mode
The chip can be brought out of the software standby mode by an input at one of six pins: NMI,
IRQ0, IRQ1, IRQ2, RES, or STBY.
(1) Recovery by External Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2request signal is
received, the clock oscillator begins operating. After the waiting time set in the system control
register (bits STS2 to STS0), clock pulses are supplied to the CPU and on-chip supporting modules.
The CPU executes the interrupt-handling sequence for the requested interrupt, then returns to the
instruction after the SLEEP instruction. The SSBY bit is not cleared.
See section 14.2, “System Control Register: Power-Down Control Bits,” for information about the
STS bits.
Interrupts IRQ3to IRQ7should be disabled before entry to the software standby mode. Clear
IRQ3E to IRQ7E to “0” in the interrupt enable register (IER).
(2) Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts and clock
pulses are supplied to the entire chip. Next, when the RES pin goes High, the CPU begins
executing the reset sequence. The SSBY bit is cleared to “0.”
The RES pin must be held Low long enough for the clock to stabilize.
(3) Recovery by STBY Pin: When the STBY pin goes Low, the chip exits from the software
standby mode to the hardware standby mode.
265
14.4.3 Sample Application of Software Standby Mode
In this example the chip enters the software standby mode when NMI goes Low and exits when
NMI goes High, as shown in figure 14-1.
The NMI edge bit (NMIEG) in the system control register is originally cleared to “0,” selecting the
falling edge. When NMI goes Low, the NMI interrupt handling routine sets NMIEG to “1,” sets
SSBY to “1” (selecting the rising edge), then executes the SLEEP instruction. The chip enters the
software standby mode. It recovers from the software standby mode on the next rising edge of
NMI.
Figure 14-1. NMI Timing in Software Standby Mode
14.4.4 Application Note
The I/O ports retain their current states in the software standby mode. If a port is in the High
output state, the current dissipation caused by the High output current is not reduced.
Clock
generator
NMI
SSBY
Ø
NMIEG
Settling time
NMI interrupt handler
NMIEG = “1”
SSBY = “1”
Software standby mode
(power-down state)
NMI interrupt handler
SLEEP
Figure 14-1
266
14.5 Hardware Standby Mode
14.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin
goes Low.
The hardware standby mode reduces power consumption drastically by halting the CPU, stopping
all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance
state. The registers of the on-chip supporting modules are reset to their initial values. Only the on-
chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained (at
least 2V).
Notes: 1. The RAME bit in the system control register should be cleared to “0” before the STBY
pin goes Low, to disable the on-chip RAM during the hardware standby mode.
2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby
mode. Be particularly careful not to let both mode pins go Low in hardware standby
mode, since that places the chip in PROM mode and increases current dissipation.
14.5.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs at both the STBY and RES pins.
When the STBY pin goes High, the clock oscillator begins running. The RES pin should be Low at
this time and should be held Low long enough for the clock to stabilize. When the RES pin
changes from Low to High, the reset sequence is executed and the chip returns to the program
execution state.
267
14.5.3 Timing Relationships
Figure 14-2 shows the timing relationships in the hardware standby mode.
In the sequence shown, first RES goes Low, then STBY goes Low, at which point the chip enters
the hardware standby mode. To recover, first STBY goes High, then after the clock settling time,
RES goes High.
Figure 14-2. Hardware Standby Mode Timing
Clock pulse
generator
RES
STBY
Clock settling
time
Restart
Figure 14-2
268
Section 15. Clock Pulse Generator
15.1 Overview
The H8/338 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a
system (Ø) clock divider, and a prescaler. The prescaler generates clock signals for the on-chip
supporting modules.
15.1.1 Block Diagram
Figure 15-1. Block Diagram of Clock Pulse Generator
15.2 Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit
generates a clock signal for the system clock divider. Alternatively, an external clock signal can be
applied to the EXTAL pin.
(1) Connecting an External Crystal
①Circuit Configuration: An external crystal can be connected as in the example in figure 15-2.
An AT-cut parallel resonating crystal should be used.
XTAL
EXTAL
Ø/2 to Ø/4096
Prescaler
÷ 2
Divider
Ø
CPG
Figure 15-1
Oscillator
circuit
269
Figure 15-2. Connection of Crystal Oscillator (Example)
②Crystal Oscillator: The external crystal should have the characteristics listed in table 15-1.
Table 15-1. External Crystal Parameters
Frequency (MHz) 2 4 8 12 16 20
Rs max (Ω) 500 120 60 40 30 20
C0(pF) 7 pF max
Figure 15-3. Equivalent Circuit of External Crystal
③Note on Board Design: When an external crystal is connected, other signal lines should be
kept away from the crystal circuit to prevent induction from interfering with correct oscillation.
See figure 15-4. The crystal and its load capacitors should be placed as close as possible to the
XTAL and EXTAL pins.
EXTAL
XTAL
CL1
CL1 = CL2 = 10 to 22pF
CL2
CL
C0
XTAL
EXTAL
L
RS
AT-cut parallel resonating crystal
Figure 15-3
270
Figure 15-4. Notes on Board Design around External Crystal
(2) Input of External Clock Signal
①Circuit Configuration: An external clock signal can be input as shown in the examples in
figure 15-5. In example (b) in figure 15-5, the external clock signal should be kept high during
standby.
Figure 15-5. External Clock Input (Example)
Figure 15-5
EXTAL
XTAL
External clock input
74HC04
(b)
EXTAL
XTAL
External clock input
Open
(a)
Not allowed
Signal A
Signal B
H8/337
XTAL
EXTAL
CL1
CL2
Figure 15-4
(Example of H8/337)
271
②External Clock Input
Frequency Double the system clock (Ø) frequency
Duty factor 45% to 55%
15.3 System Clock Divider
The system clock divider divides the crystal oscillator or external clock frequency by 2 to create the
system clock (Ø).
272
Section 16. Electrical Specifications
16.1 Absolute Maximum Ratings
Table 16-1 lists the absolute maximum ratings.
Table 16-1. Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +13.5 V
Input voltage Ports 1 – 6, 8, 9 Vin –0.3 to VCC + 0.3 V
Port 7 Vin –0.3 to AVCC + 0.3 V
Analog supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC + 0.3 V
Operating temperature Topr Regular specifications: –20 to +75 ˚C
Wide-range specifications: – 40 to +85 ˚C
Storage temperature Tstg –55 to +125 ˚C
Note: Exceeding the absolute maximum ratings shown in table 16-1 can permanently destroy
the chip.
16.2 Electrical Characteristics
16.2.1 DC Characteristics
Table 16-2 lists the DC characteristics of the 5V version. Table 16-3 lists the DC characteristics of
the 3V version. Table 16-4 gives the allowable current output values of the 5V version.
Table 16-5 gives the allowable current output values of the 3V version.
273
Table 16-2. DC Characteristics (5V Version)
Conditions: VCC = 5.0V ±10%, AVCC = 5.0V ±10%*, VSS = AVSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement
Item Symbol Min Typ Max Unit conditions
Schmitt trigger P67– P62, P60, VT-1.0 – – V
input voltage P86 – P80, VT+– – VCC
×0.7 V
(1) P97, P94– P90VT+–VT-0.4 – – V
Input High voltage
RES, STBY, NMI
VIH VCC – 0.7 – VCC + 0.3 V
(2) MD1, MD0
EXTAL
P77– P702.0 – AVCC + 0.3 V
Input High voltage Input pins VIH 2.0 – VCC + 0.3 V
other than (1)
and (2)
Input Low voltage RES, STBY VIL –0.3 – 0.5 V
(3) MD1, MD0
Input Low voltage Input pins VIL –0.3 – 0.8 V
other than (1)
and (3) above
Output High All output pins VOH VCC – 0.5 – – V IOH = –200µA
voltage 3.5 – – V IOH = –1.0mA
Output Low All output pins VOL – – 0.4 V IOL = 1.6mA
voltage Ports 1 and 2 – – 1.0 V IOL = 10.0mA
Input leakage RES |Iin| – – 10.0 µA Vin = 0.5V to
current STBY, NMI, – – 1.0 µA VCC – 0.5V
MD1, MD0
P77– P70– – 1.0 µA Vin = 0.5V to
AVCC – 0.5V
Leakage current Ports 1, 2, 3 |ITSI| – – 1.0 µA Vin = 0.5V to
in 3-state (off state) 4, 5, 6, 8, 9 VCC – 0.5V
Input pull-up Ports 1, 2, 3 -Ip 30 – 250 µA Vin = 0V
MOS current
Note: * Connect AVCC to the power supply (VCC) even when the A/D and D/A converters are
not used.
274
Table 16-2. DC Characteristics (5V Version) (cont.)
Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular specifications)
Ta = –40 to 85˚C (wide-range specifications)
Measurement
Item Symbol Min Typ Max Unit conditions
Input capacitance RES (VPP) Cin – – 60 pF Vin = 0V
NMI – – 30 pF f = 1MHz
All input pins – – 15 pF Ta = 25˚C
except RES
and NMI
Current Normal ICC – 12 25 mA f = 6MHz
dissipation*1 operation – 16 30 mA f = 8MHz
– 20 40 mA f = 10MHz
Sleep mode – 8 15 mA f = 6MHz
– 10 20 mA f = 8MHz
– 12 25 mA f = 10MHz
Standby modes*2 – 0.01 5.0 µA
Analog supply During A/D or AICC – 2.0 5.0 mA
current D/A conversion
Waiting – 0.01 5.0 µA
RAM standby VRAM 2.0 – – V
voltage
Notes: *1 Current dissipation values assume that VIH min = VCC – 0.5V, VIL max = 0.5V, all output
pins are in the no-load state, and all input pull-up transistors are off.
*2 For these values it is assumed that VRAM ≤VCC < 4.5V and VIH min = VCC ×0.9,
VIL max = 0.3V.
275
Table 16-3. DC Characteristics (3V Version)
Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta = –20 to 70˚C
Measurement
Item Symbol Min Typ Max Unit conditions
Schmitt P67– P62, P60, VT–VCC ×0.15 – – V
trigger input P86– P80, VT+– – VCC ×0.7 V
voltage*2 P97, P94– P90VT+–VT–0.2 – – V
(1)
Input High RES, STBY VIH VCC ×0.9 – VCC + 0.3 V
voltage*2 MD1, MD0
(2) EXTAL, NMI
P77– P70VCC ×0.7 – AVCC + 0.3 V
Input pins VCC ×0.7 – VCC + 0.3 V
other than (1)
and (2) above
Input Low RES, STBY VIL –0.3 – VCC ×0.1 V
voltage*2 MD1, MD0
(3) Input pins –0.3 – VCC ×0.15 V
other than (1)
and (3) above
Output High All output pins VOH VCC – 0.4 – – V IOH = –200µA
voltage VCC – 0.9 – – V IOH = –1.0mA
Output Low All output pins VOL – – 0.4 V IOL = 0.8mA
voltage Ports 1 and 2 – – 0.4 V IOL = 1.6mA
Input RES |Iin| – – 10.0 µA Vin = 0.5 to
leakage STBY, NMI, – – 1.0 µA VCC – 0.5V
current MD1, MD0
P77– P70– – 1.0 µA Vin = 0.5 to
AVCC – 0.5V
Leakage Ports 1, 2, 3 |ITSI| – – 1.0 µA Vin = 0.5 to
current in 4, 5, 6, 8, 9 VCC – 0.5V
3-state
(off state)
Input Ports 1, 2, 3 –Ip3 – 120 µA Vin = 5.0V
pull-up MOS
current
Notes: *1 Connect AVCC to the power supply (VCC) even when the A/D and D/A converters are
not used.
*2 In the range 3.3V < VCC < 4.5V, for the input levels of VIH and VT+, apply the higher of
the values given for the 5V and 3V versions. For VIL and VT–, apply the lower of the
values given for the 5V and 3V versions.
276
Table 16-3. DC Characteristics (3V Version) (cont.)
Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%*1, VSS = AVSS = 0V, Ta = –20 to 70˚C
Measurement
Item Symbol Min Typ Max Unit conditions
Input RES Cin – – 60 pF Vin = 0V
capacitance NMI – – 30 pF f = 1MHz
All input pins – – 15 pF Ta = 25˚C
except RES
and NMI
Current Normal ICC – 6 – mA f = 3MHz
dissipation*1 operation – 10 20 mA f = 5MHz
Sleep mode – 4 – mA f = 3MHz
– 6 12 mA f = 5MHz
Standby modes*2 – 0.01 5.0 µA
Analog During A/D or AICC – 2.0 5.0 mA
supply D/A conversion
current Waiting – 0.01 5.0 µA
RAM backup voltage VRAM 2.0 – – V
(in standby modes)
Notes: *1 Current dissipation values assume that VIH min = VCC – 0.5V, VIL max = 0.5V, all output
pins are in the no-load state, and all input pull-up transistors are off.
*2 For these values it is assumed that VRAM ≤VCC < 2.7V and VIH min = VCC ×0.9,
VIL max = 0.3V.
277
Table 16-4. Allowable Output Current Values (5V Version)
Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular specifications)
Ta = –40 to 85˚C (wide-range specifications)
Item Symbol Min Typ Max Unit
Allowable output Low Ports 1 and 2 IOL – – 10 mA
current (per pin) Other output pins – – 2.0 mA
Allowable output Low Ports 1 and 2, total ΣIOL – – 80 mA
current (total) Total of all output – – 120 mA
Allowable output High All output pins –IOH – – 2.0 mA
current (per pin)
Allowable output High Total of all output Σ–IOH – – 40 mA
current (total)
Table 16-5. Allowable Output Current Values (3V Version)
Conditions: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C
Item Symbol Min Typ Max Unit
Allowable output Low Ports 1 and 2 IOL – – 2 mA
current (per pin) Other output pins – – 1 mA
Allowable output Low Ports 1 and 2, total ΣIOL – – 40 mA
current (total) Total of all output – – 60 mA
Allowable output High All output pins –IOH – – 2 mA
current (per pin)
Allowable output High Total of all output Σ–IOH – – 30 mA
current (total)
Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current
values in tables 16-4 and 16-5. In particular, when driving a Darlington transistor pair or
LED directly, be sure to insert a current-limiting resistor in the output path. See figures 16-1
and 16-2.
278
Figure 16-1. Example of Circuit for Driving a Darlington Pair (5V Version)
Figure 16-2. Example of Circuit for Driving an LED (5V Version)
16.2.2 AC Characteristics
The AC characteristics are listed in three tables. Bus timing parameters are given in
table 16-6, control signal timing parameters in table 16-7, and timing parameters of the on-chip
supporting modules in table 16-8.
H8/338
Port
2 kΩ
Darlington
pair
Fig. 16-1
Vcc
600 Ω
LED
Port 1 or 2
H8/338
Fig. 16-2
279
Table 16-6. Bus Timing
Condition A: VCC = 5.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz Measurement
Item Symbol Min Max Min Max Min Max Min Max Unit conditions
Clock cycle time tcyc 200 2000 166.7 2000 125 2000 100 2000 ns Fig. 16-4
Clock pulse width Low tCL 70 – 65 – 45 – 35 – ns Fig. 16-4
Clock pulse width High tCH 70 – 65 – 45 – 35 – ns Fig. 16-4
Clock rise time tCr – 25 – 15 – 15 – 15 ns Fig. 16-4
Clock fall time tCf – 25 – 15 – 15 – 15 ns Fig. 16-4
Address delay time tAD – 90 – 70 – 60 – 50 ns Fig. 16-4
Address hold time tAH 30 – 30 – 25 – 20 – ns Fig. 16-4
Address strobe delay time tASD – 80 – 70 – 60 – 40 ns Fig. 16-4
Write strobe delay time tWSD – 80 – 70 – 60 – 50 ns Fig. 16-4
Strobe delay time tSD – 90 – 70 – 60 – 50 ns Fig. 16-4
Write strobe pulse width* tWSW 200 – 200 – 150 – 120 – ns Fig. 16-4
Address setup time 1* tAS1 25 – 25 – 20 – 15 – ns Fig. 16-4
Address setup time 2* tAS2 105 – 105 – 80 – 65 – ns Fig. 16-4
Read data setup time tRDS 90 – 70 – 50 – 35 – ns Fig. 16-4
Read data hold time* tRDH 0 – 0 – 0 – 0 – ns Fig. 16-4
Read data access time* tACC – 300 – 270 – 210 – 170 ns Fig. 16-4
Write data delay time tWDD – 125 – 85 – 75 – 75 ns Fig. 16-4
Write data setup time tWDS 10 – 20 – 10 – 5 – ns Fig. 16-4
Write data hold time tWDH 30 – 30 – 25 – 20 – ns Fig. 16-4
Wait setup time tWTS 60 – 40 – 40 – 40 – ns Fig. 16-5
Wait hold time tWTH 20 – 10 – 10 – 10 – ns Fig. 16-5
Note: * Values at maximum operating frequency
280
Table 16-7. Control Signal Timing
Condition A: VCC = 5.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz Measurement
Item Symbol Min Max Min Max Min Max Min Max Unit conditions
RES setup time tRESS 300 – 200 – 200 – 200 – ns Fig. 16-6
RES pulse width tRESW 10 – 10 – 10 – 10 – tcyc Fig. 16-6
NMI setup time tNMIS 300 – 150 – 150 – 150 – ns Fig. 16-7
(NMI, IRQ0to IRQ7)
NMI hold time tNMIH 10 – 10 – 10 – 10 – ns Fig. 16-7
(NMI, IRQ0to IRQ7)
Interrupt pulse width tNMIW 300 – 200 – 200 – 200 – ns Fig. 16-7
for recovery from soft-
ware standby mode
(NMI, IRQ0to IRQ2)
Crystal oscillator settling tOSC1 20 – 20 – 20 – 20 – ms Fig. 16-8
time (reset)
Crystal oscillator settling tOSC2 10 – 10 – 10 – 10 – ms Fig. 16-9
time (software standby)
281
Table 16-8. Timing Conditions of On-Chip Supporting Modules
Condition A: VCC = 5.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, VSS = 0V, Ø = 0.5MHz to maximum operating frequency,
Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz Measurement
Item Symbol Min Max Min Max Min Max Min Max Unit conditions
FRT Timer output delay time tFTOD – 150 – 100 – 100 – 100 ns Fig. 16-10
Timer input setup time tFTIS 80 – 50 – 50 – 50 – ns Fig. 16-10
Timer clock input tFTCS 80 – 50 – 50 – 50 – ns Fig. 16-11
setup time
Timer clockpulse width tFTCWH 1.5 – 1.5 – 1.5 – 1.5 – tcyc Fig. 16-11
tFTCWL
TMR Timer output delay time tTMOD – 150 – 100 – 100 – 100 ns Fig. 16-12
Timer reset input tTMRS 80 – 50 – 50 – 50 – ns Fig. 16-14
setup time
Timer clock input tTMCS 80 – 50 – 50 – 50 – ns Fig. 16-13
setup time
Timer clock pulse width tTMCWH 1.5 – 1.5 – 1.5 – 1.5 – tcyc Fig. 16-13
(single edge)
Timer clock pulse width tTMCWL 2.5 – 2.5 – 2.5 – 2.5 – tcyc Fig. 16-13
(both edges)
PWM Timer output delay time tPWOD – 150 – 100 – 100 – 100 ns Fig. 16-15
SCI Input clock (Async) tscyc 4–4–4–4–tcyc Fig. 16-16
cycle (Sync) tscyc 6–6–6–6–tcyc Fig. 16-16
Transmit data delay tTXD – 200 – 100 – 100 – 100 ns Fig. 16-16
time (Sync)
Receive data setup time tRXS 150 – 100 – 100 – 100 – ns Fig. 16-16
(Sync)
Receive data hold time tRXH 150 – 100 – 100 – 100 – ns Fig. 16-16
(Sync)
Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tscyc Fig. 16-17
Ports Output data delay time tPWD – 150 – 100 – 100 – 100 ns Fig. 16-18
Input data setup time tPRS 80 – 50 – 50 – 50 – ns Fig. 16-18
Input data hold time tPRH 80 – 50 – 50 – 50 – ns Fig. 16-18
282
• Measurement Conditions for AC Characteristics
Figure 16-3. Output Load Circuit
16.2.3 A/D Converter Characteristics
Table 16-9 lists the characteristics of the on-chip A/D converter.
Table 16-9. A/D Converter Characteristics
Condition A: VCC = 5.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ø = 0.5MHz to maximum
operating frequency, Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ø = 0.5MHz to
maximum operating frequency, Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz
Item Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 8 8 8 8 8 8 8 8 8 8 8 8 Bits
Conversion time (single mode)* — — 24.4 — — 20.4 — — 15.25 — — 12.2 µs
Analog input capacitance — — 20 — — 20 — — 20 — — 20 pF
Allowable signal source — — 10 — — 10 — — 10 — — 10 kΩ
impedance
Nonlinearity error — — ±1 — — ±1 — — ±1 — — ±1 LSB
Offset error — — ±1 — — ±1 — — ±1 — — ±1 LSB
Full-scale error — — ±1 — — ±1 — — ±1 — — ±1 LSB
Quantizing error — — ±0.5 — — ±0.5 — — ±0.5 — — ±0.5 LSB
Absolute accuracy — — ±1.5 — — ±1.5 — — ±1.5 — — ±1.5 LSB
Note: * Values at maximum operating frequency
Fig. 16-3
5 V
LSI
output pin
Input/output timing reference levels
Low:
High:
0.8 V
2.0 V
90 pF: Ports 1 – 4, 6, 9
30 pF: Ports 5, 8
2.4 kΩ
12 kΩ
C =
RL =
RH =
C
RL
RH
283
16.2.4 D/A Converter Characteristics
Table 16-10 lists the characteristics of the on-chip D/A converter.
Table 16-10. D/A Converter Characteristics
Condition A: VCC = 5.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ø = 0.5MHz to maximum
operating frequency, Ta = –20 to 75˚C (regular specifications),
Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 3.0V ±10%, AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ø = 0.5MHz to maximum
operating frequency, Ta = –20 to 75˚C
Condition B Condition A
5MHz 6MHz 8MHz 10MHz Measurement
Item Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit conditions
Resolution 8 8 8 8 8 8 8 8 8 8 8 8 Bits
Conversion time — — 10.0 — — 10.0 — — 10.0 — — 10.0 µs 30pF load
capacitance
Absolute accuracy — ±1 ±1.5 — ±1 ±1.5 — ±1 ±1.5 — ±1 ±1.5 LSB 2MΩload
resistance
— — ±1 — — ±1 — — ±1 — — ±1 LSB 4MΩload
resistance
16.3 MCU Operational Timing
This section provides the following timing charts:
16.3.1 Bus Timing Figures 16-4 to 16-5
16.3.2 Control Signal Timing Figures 16-6 to 16-9
16.3.3 16-Bit Free-Running Timer Timing Figures 16-10 to 16-11
16.3.4 8-Bit Timer Timing Figures 16-12 to 16-14
16.3.5 PWM Timer Timing Figure 16-15
16.3.6 SCI Timing Figures 16-16 to 16-17
16.3.7 I/O Port Timing Figure 16-18
284
16.3.1 Bus Timing
(1) Basic Bus Cycle (without Wait States) in Expanded Modes
Figure 16-4. Basic Bus Cycle (without Wait States) in Expanded Modes
T
T
1
t
cyc
2
T
3
t
CH
t
CL
t
AD
t
Cr
t
ASD
t
ACC
t
RDS
t
WSD
t
AS2
t
WDD
t
WDS
t
WDH
t
AH
t
WSW
t
RDH
t
AH
t
SD
Ø
A15 to A 0
WR
D7 to D 0
(Read)
D7 to D 0
(Write)
AS, RD
t
Cf
t
ASI
t
SD
Fig. 16-4
285
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
Figure 16-5. Basic Bus Cycle (with 1 Wait State) in Expanded Modes
16.3.2 Control Signal Timing
(1) Reset Input Timing
Figure 16-6. Reset Input Timing
Ø
AS, RD
WR
WAIT
D7to D0
(Read)
A15 to A0
D7to D0
(Write)
T
1
T
2
T
W
T
3
t
WTS
t
WTH
t
WTS
t
WTH
Fig. 17-5
Ø
RES
t
RESS
t
RESS
t
RESW
Fig. 17-7
286
(2) Interrupt Input Timing
Figure 16-7. Interrupt Input Timing
Ø
IRQL (Level)
NMI
IRQi
t
t
t
NMI
IRQE (Edge)
NMIS
NMIS
NMIH
t
NMIW
Note: i = 0 to 7; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed
Fig. 16-7
287
(3) Clock Settling Timing
Ø
VCC
RES
STBY tOSC1 tOSC1
Figure 16-8. Clock Settling Timing
288
(4) Clock Settling Timing for Recovery from Software Standby Mode
Figure 16-9. Clock Settling Timing for Recovery from Software Standby Mode
16.3.3 16-Bit Free-Running Timer Timing
(1) Free-Running Timer Input/Output Timing
Figure 16-10. Free-Running Timer Input/Output Timing
OSC2
Ø
NMI
IRQi
(i = 0, 1, 2)
t
Fig. 17-10
Ø
Compare-match
FTIA, FTIB,
FTIC, FTID
FTOA , FTOB
Free-running
timer counter
t
FTOD
t
FTIS
289
(2) External Clock Input Timing for Free-Running Timer
Figure 16-11. External Clock Input Timing for Free-Running Timer
16.3.4 8-Bit Timer Timing
(1) 8-Bit Timer Output Timing
Figure 16-12. 8-Bit Timer Output Timing
(2) 8-Bit Timer Clock Input Timing
Figure 16-13. 8-Bit Timer Clock Input Timing
Ø
FTCI
t
FTCS
t
FTCWL
t
FTCWH
Ø
Timer
counter
Compare-match
TMO0,
TMO1
t
TMOD
Fig. 16-12
Ø
t
TMCS
t
TMCS
t
TMCWL
t
TMCWH
TMCI0,
TMCI1
Fig. 16-13
290
(3) 8-Bit Timer Reset Input Timing
Figure 16-14. 8-Bit Timer Reset Input Timing
16.3.5 Pulse Width Modulation Timer Timing
Figure 16-15. PWM Timer Output Timing
16.3.6 Serial Communication Interface Timing
(1) SCI Input/Output Timing
Figure 16-16. SCI Input/Output Timing (Synchronous Mode)
N
H'00
Ø
Timer
counter
t
TMRS
TMRI0,
TMRI1
Fig. 16-14
Compare-match
t
PWOD
Ø
Timer
counter
PW0, PW1
Fig. 16-15
t
Scyc
t
TXD
t
RXS
t
RXH
Serial clock
(SCK)
Transmit
data
(TxD)
Receive
data
(RxD)
Fig. 17-17
291
(2) SCI Input Clock Timing
Figure 16-17. SCI Input Clock Timing
16.3.7 I/O Port Timing
Figure 16-18. I/O Port Input/Output Timing
tSCKW
tScyc
SCK0, SCK1
Fig. 16-17
Note: * Except P96 and P7 7to P70
Port read/write cycle
T1
T2
T3
t
PRS
t
PRH
t
PWD
Port 1
to
Port 9
(Input)
Port 1*
to
Port 9
(Output)
Ø
Fig. 16-18
292
Appendix A. CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16 General register (destination) (8 or 16 bits)
Rs8/16 General register (source) (8 or 16 bits)
Rn8/16 General register (8 or 16 bits)
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#xx:3/8/16 Immediate data (3, 8, or 16 bits)
d:8/16 Displacement (8 or 16 bits)
@aa:8/16 Absolute address (8 or 16 bits)
+ Addition
– Subtraction
×Multiplication
÷ Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Move
— Not
Condition Code Notation
↕Modified according to the instruction result
* Undetermined (unpredictable)
0 Always cleared to “0”
— Not affected by the instruction result
293
294
MOV.B #xx:8,Rd B #xx:8 → Rd8 2 – – ◊ ◊ 0 – 2
MOV.B Rs,Rd B Rs8 → Rd8 2 – – ◊ ◊ 0 – 2
MOV.B @Rs,Rd B @Rs16 → Rd8 2 – – ◊ ◊ 0 – 4
MOV.B @(d:16,Rs),Rd B @(d:16,Rs16)→ Rd8 4 – – ◊ ◊ 0 – 6
MOV.B @Rs+,Rd B @Rs16 → Rd8 2 – – ◊ ◊ 0 – 6
Rs16+1 → Rs16
MOV.B @aa:8,Rd B @aa:8 → Rd8 2 – – ◊ ◊ 0 – 4
MOV.B @aa:16,Rd B @aa:16 → Rd8 4 – – ◊ ◊ 0 – 6
MOV.B Rs,@Rd B Rs8 → @Rd16 2 – – ◊ ◊ 0 – 4
MOV.B Rs,@(d:16,Rd) B Rs8 → @(d:16,Rd16) 4 – – ◊ ◊ 0 – 6
MOV.B Rs,@–Rd B Rd16–1 → Rd16 2 – – ◊ ◊ 0 – 6
Rs8 → @Rd16
MOV.B Rs,@aa:8 B Rs8 → @aa:8 2 – – ◊ ◊ 0 – 4
MOV.B Rs,@aa:16 B Rs8 → @aa:16 4 – – ◊ ◊ 0 – 6
MOV.W #xx:16,Rd W #xx:16 → Rd 4 – – ◊ ◊ 0 – 4
MOV.W Rs,Rd W Rs16 → Rd16 2 – – ◊ ◊ 0 – 2
MOV.W @Rs,Rd W @Rs16 → Rd16 2 – – ◊ ◊ 0 – 4
MOV.W @(d:16,Rs),Rd W @(d:16,Rs16) → Rd16 4 – – ◊ ◊ 0 – 6
MOV.W @Rs+,Rd W @Rs16 → Rd16 2 – – ◊ ◊ 0 – 6
Rs16+2 → Rs16
MOV.W @aa:16,Rd W @aa:16 → Rd16 4 – – ◊ ◊ 0 – 6
MOV.W Rs,@Rd W Rs16 → @Rd16 2 – – ◊ ◊ 0 – 4
MOV.W Rs,@(d:16,Rd) W Rs16 → @(d:16,Rd16) 4 – – ◊ ◊ 0 – 6
MOV.W Rs,@–Rd W Rd16–2 → Rd16 2 – – ◊ ◊ 0 – 6
Rs16 → @Rd16
MOV.W Rs, @aa:16 W Rs16 → @aa:16 4 – – ◊ ◊ 0 – 6
POP Rd W @SP → Rd16 2 – – ◊ ◊ 0 – 6
SP+2 → SP
PUSH Rs W SP–2 → SP 2 – – ◊ ◊ 0 – 6
Rs16 → @SP
MOVFPE @aa:16,Rd B Not supported
MOVTPE Rs,@aa:16 B Not supported
EEPMOV – if R4L≠0 then 4 – – – – – – √
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next
Appendix A. Instruction Set List
I H N Z V C
Mnemonic Operation Condition code
Addressing mode/
instruction length
Operand size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@-Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
No. of states*
295
ADD.B #xx:8,Rd B Rd8+#xx:8 → Rd8 2 – ◊ ◊ ◊ ◊ ◊ 2
ADD.B Rs,Rd B Rd8+Rs8 → Rd8 2 – ◊ ◊ ◊ ◊ ◊ 2
ADD.W Rs,Rd W Rd16+Rs16 → Rd16 2 – ➀◊ ◊ ◊ ◊ 2
ADDX.B #xx:8,Rd B Rd8+#xx:8 +C → Rd8 2 – ◊ ◊ ➁◊ ◊ 2
ADDX.B Rs,Rd B Rd8+Rs8 +C → Rd8 2 – ◊ ◊ ➁◊ ◊ 2
ADDS.W #1,Rd W Rd16+1 → Rd16 2 – – – – – – 2
ADDS.W #2,Rd W Rd16+2 → Rd16 2 – – – – – – 2
INC.B Rd B Rd8+1 → Rd8 2 – – ◊◊◊– 2
DAA.B Rd B Rd8 decimal adjust → Rd8 2 – * ◊ ◊ *➂2
SUB.B Rs,Rd B Rd8–Rs8 → Rd8 2 – ◊ ◊ ◊ ◊ ◊ 2
SUB.W Rs,Rd W Rd16–Rs16 → Rd16 2 – ➀◊ ◊ ◊ ◊ 2
SUBX.B #xx:8,Rd B Rd8–#xx:8 –C → Rd8 2 – ◊ ◊ ➁◊ ◊ 2
SUBX.B Rs,Rd B Rd8–Rs8 –C → Rd8 2 – ◊ ◊ ➁◊ ◊ 2
SUBS.W #1,Rd W Rd16–1 → Rd16 2 – – – – – – 2
SUBS.W #2,Rd W Rd16–2 → Rd16 2 – – – – – – 2
DEC.B Rd B Rd8–1 → Rd8 2 – – ◊◊◊– 2
DAS.B Rd B Rd8 decimal adjust → Rd8 2 – * ◊ ◊ * – 2
NEG.B Rd B 0–Rd → Rd 2 – ◊ ◊ ◊ ◊ ◊ 2
CMP.B #xx:8,Rd B Rd8–#xx:8 2 – ◊ ◊ ◊ ◊ ◊ 2
CMP.B Rs,Rd B Rd8–Rs8 2 – ◊ ◊ ◊ ◊ ◊ 2
CMP.W Rs,Rd W Rd16–Rs16 2 – ➀◊ ◊ ◊ ◊ 2
MULXU.B Rs,Rd B Rd8×Rs8 → Rd16 2 – – – – – – 14
DIVXU.B Rs,Rd B Rd16÷Rs8 → Rd16 2 – – ≈ ∆ – – 14
(RdH:remainder, RdL:quotient)
AND.B #xx:8,Rd B Rd8∧#xx:8 → Rd8 2 – – ◊ ◊ 0 – 2
AND.B Rs,Rd B Rd8∧Rs8 → Rd8 2 – – ◊ ◊ 0 – 2
OR.B #xx:8,Rd B Rd8∨#xx:8 → Rd8 2 – – ◊ ◊ 0 – 2
OR.B Rs,Rd B Rd8∨Rs8 → Rd8 2 – – ◊ ◊ 0 – 2
XOR.B #xx:8,Rd B Rd8⊕#xx:8 → Rd8 2 – – ◊ ◊ 0 – 2
XOR.B Rs,Rd B Rd8⊕Rs8 → Rd8 2 – – ◊ ◊ 0 – 2
NOT.B Rd B Rd → Rd 2 – – ◊ ◊ 0 – 2
I H N Z V C
Addressing mode/
instruction length
Appendix A. Instruction Set List (cont.)
Mnemonic Operation Condition code
Operand size
No. of states*
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@-Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
296
C
SHAL.B Rd B 2 – – ◊ ◊ ◊ ◊ 2
SHAR.B Rd B 2 – – ◊ ◊ 0◊2
SHLL.B Rd B 2 – – ◊ ◊ 0◊2
SHLR.B Rd B 2 – – 0 ◊0◊2
ROTXL.B Rd B 2 – – ◊ ◊ 0◊2
ROTXR.B Rd B 2 – – ◊ ◊ 0◊2
ROTL.B Rd B 2 – – ◊ ◊ 0◊2
ROTR.B Rd B 2 – – ◊ ◊ 0◊2
BSET #xx:3,Rd B (#xx:3 of Rd8) ← 1 2 – – – – – – 2
BSET #xx:3,@Rd B (#xx:3 of @Rd16) ← 1 4 – – – – – – 8
BSET #xx:3,@aa:8 B (#xx:3 of @aa:8) ← 1 4 – – – – – – 8
BSET Rn,Rd B (Rn8 of Rd8) ← 1 2 – – – – – – 2
BSET Rn,@Rd B (Rn8 of @Rd16) ← 1 4 – – – – – – 8
BSET Rn,@aa:8 B (Rn8 of @aa:8) ← 1 4 – – – – – – 8
BCLR #xx:3,Rd B (#xx:3 of Rd8) ← 0 2 – – – – – – 2
BCLR #xx:3,@Rd B (#xx:3 of @Rd16) ← 0 4 – – – – – – 8
BCLR #xx:3,@aa:8 B (#xx:3 of @aa:8) ← 0 4 – – – – – – 8
BCLR Rn,Rd B (Rn8 of Rd8) ← 0 2 – – – – – – 2
BCLR Rn,@Rd B (Rn8 of @Rd16) ← 0 4 – – – – – – 8
BCLR Rn,@aa:8 B (Rn8 of @aa:8) ← 0 4 – – – – – – 8
BNOT #xx:3,Rd B (#xx:3 of Rd8) ← (#xx:3 of Rd8) 2 – – – – – – 2
BNOT #xx:3,@Rd B (#xx:3 of @Rd16) ← (#xx:3 of @Rd16) 4 – – – – – – 8
BNOT #xx:3,@aa:8 B (#xx:3 of @aa:8) ← (#xx:3 of @aa:8) 4 – – – – – – 8
C0
I H N Z V C
0C
0C
C
0C
0C
C
b0b7
b0b7
b0b7
b0b7
b0b7
b0b7
b0b7
b0b7
Addressing mode/
instruction length
Mnemonic Operation Condition code
Appendix A. Instruction Set List (cont.)
#xx:8/16
Operand size
Rn
@Rn
@(d:16, Rn)
@-Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
No. of states*
297
BNOT Rn,Rd B (Rn8 of Rd8) ← (Rn8 of Rd8) 2 – – – – – – 2
BNOT Rn,@Rd B (Rn8 of @Rd16) ← (Rn8 of @Rd16) 4 – – – – – – 8
BNOT Rn,@aa:8 B (Rn8 of @aa:8) ← (Rn8 of @aa:8) 4 – – – – – – 8
BTST #xx:3,Rd B (#xx:3 of Rd8) → Z 2 – – – ◊––2
BTST #xx:3,@Rd B (#xx:3 of @Rd16) → Z 4 – – – ◊––6
BTST #xx:3,@aa:8 B (#xx:3 of @aa:8) → Z 4 – – – ◊––6
BTST Rn,Rd B (Rn8 of Rd8) → Z 2 – – – ◊––2
BTST Rn,@Rd B (Rn8 of @Rd16) → Z 4 – – – ◊––6
BTST Rn,@aa:8 B (Rn8 of @aa:8) → Z 4 – – – ◊––6
BLD #xx:3,Rd B (#xx:3 of Rd8) → C 2 – – – – – ◊2
BLD #xx:3,@Rd B (#xx:3 of @Rd16) → C 4 – – – – – ◊6
BLD #xx:3,@aa:8 B (#xx:3 of @aa:8) → C 4 – – – – – ◊6
BILD #xx:3,Rd B (#xx:3 of Rd8) → C 2 – – – – – ◊2
BILD #xx:3,@Rd B (#xx:3 of @Rd16) → C 4 – – – – – ◊6
BILD #xx:3,@aa:8 B (#xx:3 of @aa:8) → C 4 – – – – – ◊6
BST #xx:3,Rd B C → (#xx:3 of Rd8) 2 – – – – – – 2
BST #xx:3,@Rd B C → (#xx:3 of @Rd16) 4 – – – – – – 8
BST #xx:3,@aa:8 B C → (#xx:3 of @aa:8) 4 – – – – – – 8
BIST #xx:3,Rd B C → (#xx:3 of Rd8) 2 – – – – – – 2
BIST #xx:3,@Rd B C → (#xx:3 of @Rd16) 4 – – – – – – 8
BIST #xx:3,@aa:8 B C → (#xx:3 of @aa:8) 4 – – – – – – 8
BAND #xx:3,Rd B C∧(#xx:3 of Rd8) → C 2 – – – – – ◊2
BAND #xx:3,@Rd B C∧(#xx:3 of @Rd16) → C 4 – – – – – ◊6
BAND #xx:3,@aa:8 B C∧(#xx:3 of @aa:8) → C 4 – – – – – ◊6
BIAND #xx:3,Rd B C∧(#xx:3 of Rd8) → C 2 – – – – – ◊2
BIAND #xx:3,@Rd B C∧(#xx:3 of @Rd16) → C 4 – – – – – ◊6
BIAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) → C 4 – – – – – ◊6
BOR #xx:3,Rd B C∨(#xx:3 of Rd8) → C 2 – – – – – ◊2
BOR #xx:3,@Rd B C∨(#xx:3 of @Rd16) → C 4 – – – – – ◊6
BOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) → C 4 – – – – – ◊6
BIOR #xx:3, Rd B C∨(#xx:3 of Rd8) → C 2 – – – – – ◊2
Addressing mode/
instruction length
Mnemonic Operation Condition code
I H N Z V C
Appendix A. Instruction Set List (cont.)
Operand size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@-Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
No. of states*
298
BIOR #xx:3,@Rd B C∨(#xx:3 of @Rd16) → C 4 – – – – – ◊6
BIOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) → C 4 – – – – – ◊6
BXOR #xx:3,Rd B C⊕(#xx:3 of Rd8) → C 2 – – – – – ◊2
BXOR #xx:3,@Rd B C⊕(#xx:3 of @Rd16) → C 4 – – – – – ◊6
BXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C 4 – – – – – ◊6
BIXOR #xx:3,Rd B C⊕(#xx:3 of Rd8) → C 2 – – – – – ◊2
BIXOR #xx:3,@Rd B C⊕(#xx:3 of @Rd16) → C 4 – – – – – ◊6
BIXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C 4 – – – – – ◊6
BRA d:8 (BT d:8) – PC ← PC+d:8 2 – – – – – – 4
BRN d:8 (BF d:8) – PC ← PC+2 2 – – – – – – 4
BHI d:8 – if condition C ∨ Z = 0 2 – – – – – – 4
BLS d:8 – is true then C ∨ Z = 1 2 – – – – – – 4
BCC d:8 (BHS d:8) – PC ← PC+d:8 C = 0 2 – – – – – – 4
BCS d:8 (BLO d:8) – else next; C = 1 2 – – – – – – 4
BNE d:8 – Z = 0 2 – – – – – – 4
BEQ d:8 – Z = 1 2 – – – – – – 4
BVC d:8 – V = 0 2 – – – – – – 4
BVS d:8 – V = 1 2 – – – – – – 4
BPL d:8 – N = 0 2 – – – – – – 4
BMI d:8 – N = 1 2 – – – – – – 4
BGE d:8 – N⊕V = 0 2 – – – – – – 4
BLT d:8 – N⊕V = 1 2 – – – – – – 4
BGT d:8 – Z ∨ (N⊕V) = 0 2 – – – – – – 4
BLE d:8 – Z ∨ (N⊕V) = 1 2 – – – – – – 4
JMP @Rn – PC ← Rn16 2 – – – – – – 4
JMP @aa:16 – PC ← aa:16 4 – – – – – – 6
JMP @@aa:8 – PC ← @aa:8 2 – – – – – – 8
BSR d:8 – SP–2 → SP 2 – – – – – – 6
PC → @SP
PC ← PC+d:8
I H N Z V C
Addressing mode/
instruction length
Mnemonic Operation Condition code
Branching
condition
Appendix A. Instruction Set List (cont.)
Operand size
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@-Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
No. of states*
299
JSR @Rn – SP–2 → SP 2 – – – – – – 6
PC → @SP
PC ← Rn16
JSR @aa:16 – SP–2 → SP 4 – – – – – – 8
PC → @SP
PC ← aa:16
JSR @@aa:8 SP–2 → SP 2 – – – – – – 8
PC → @SP
PC ← @aa:8
RTS – PC ← @SP 2 – – – – – – 8
SP+2 → SP
RTE – CCR ← @SP 2 ◊ ◊ ◊ ◊ ◊ ◊ 10
SP+2 → SP
PC ← @SP
SP+2 → SP
SLEEP – Transit to sleep mode. 2 – – – – – – 2
LDC #xx:8,CCR B #xx:8 → CCR 2 ◊ ◊ ◊ ◊ ◊ ◊ 2
LDC Rs,CCR B Rs8 → CCR 2 ◊ ◊ ◊ ◊ ◊ ◊ 2
STC CCR,Rd B CCR → Rd8 2 – – – – – – 2
ANDC #xx:8,CCR B CCR∧#xx:8 → CCR 2 ◊ ◊ ◊ ◊ ◊ ◊ 2
ORC #xx:8,CCR B CCR∨#xx:8 → CCR 2 ◊ ◊ ◊ ◊ ◊ ◊ 2
XORC #xx:8,CCR B CCR⊕#xx:8 → CCR 2 ◊ ◊ ◊ ◊ ◊ ◊ 2
NOP – PC ← PC+2 2 – – – – – – 2
Notes: The number of states is the number of states required for execution when the instruction and its
operands are located in on-chip memory.
①Set to “1” when there is a carry or borrow from bit 11; otherwise cleared to “0.”
≠If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to “0.”
③Set to “1” if decimal adjustment produces a carry; otherwise cleared to “0.”
④The number of states required for execution is 4n+8 (n = value of R4L)
∞These instructions are not supported by the H8/338 Series.
±Set to “1” if the divisor is negative; otherwise cleared to “0.”
≤Cleared to “0” if the divisor is not zero; undetermined when the divisor is zero.
I H N Z V C
Addressing mode/
instruction length
Mnemonic Operation Condition code
Appendix A. Instruction Set List (cont.)
Operand size
@-Rn/@Rn+
@aa:8/16
#xx:8/16
Rn
@Rn
@(d:16, Rn)
@(d:8, PC)
@@aa
Implied
No. of states*
A.2 Operation Code Map
Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15
to 8 of the first instruction word).
Some pairs of instructions have identical first bytes. These instructions are differentiated by the
first bit of the second byte (bit 7 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is “0.”
Instruction when first bit of byte 2 (bit 7 of first instruction word) is “1.”
300
Table A-2. Operation Code Map
Notes: *1 The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word).
The PUSH and POP instructions are identical in machine language to MOV instructions.
*2 The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
HI
LO
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
SLEEP
STC
LDC
ORC
XORC
ANDC
LDC
ADD
INC
ADDS
MOV
ADDX
DAA
SHLL
SHAL
SHLR
SHAR
ROTXL
ROTL
ROTXR
ROTR
NOT
NEG
OR
XOR
AND
SUB
DEC
SUBS
CMP
SUBX
DAS
MOV
BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEQ
BVS
BPL
BMI
BLT
BGT
BLE
MULXU
DIVXU
RTS
BSR
RTE
JMP
JSR
BVC
BGE
BSET
BNOT
BCLR
BTST
MOV
MOV
EEPMOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
BXOR
BIXOR
BAND
BIAND
BOR
BIOR
BLD
BILD
BST
BIST
Bit manipulation instruction
*1
*2
*2
*2
*2
301
A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I
×SI+ J ×SJ+ K ×SK+ L ×SL+ M ×SM+ N ×SN
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2, J = K = M = N= 0
From table A-3: SI= 8, SL= 3
Number of states required for execution: 2 ×8 + 2 ×3 =22
2. JSR @@30
From table A-4: I = 2, J = K = 1, L = M = N = 0
From table A-3: SI= SJ= SK= 8
Number of states required for execution: 2 ×8 + 1 ×8 + 1 ×8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution status Access location
(instruction cycle) On-chip memory On-chip reg. field External memory
Instruction fetch SI
Branch address read SJ6 6 + 2m
Stack operation SK2
Byte data access SL3 3 + m
Word data access SM6 6 + 2m
Internal operation SN1
Notes: m: Number of wait states inserted in access to external device.
302
Table A-4. Number of Cycles in Each Instruction
Instruction Branch Stack Byte data Word data Internal
fetch addr. read operation access access operation
Instruction Mnemonic I J K L M N
ADD ADD.B #xx:8, Rd 1
ADD.B Rs, Rd 1
ADD.W Rs, Rd 1
ADDS ADDS.W #1/2, Rd 1
ADDX ADDX.B #xx:8, Rd 1
ADDX.B Rs, Rd 1
AND AND.B #xx:8, Rd 1
AND.B Rs, Rd 1
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd 1
BAND #xx:3, @Rd 2 1
BAND #xx:3, @aa:8 2 1
Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
BMI d:8 2
BGE d:8 2
BLT d:8 2
BGT d:8 2
BLE d:8 2
BCLR BCLR #xx:3, Rd 1
BCLR #xx:3, @Rd 2 2
BCLR #xx:3, @aa:8 2 2
BCLR Rn, Rd 1
BCLR Rn, @Rd 2 2
BCLR Rn, @aa:8 2 2
Note: All values left blank are zero.
303
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch Stack Byte data Word data Internal
fetch addr. read operation access access operation
Instruction Mnemonic I J K L M N
BIAND BIAND #xx:3, Rd 1
BIAND #xx:3, @Rd 2 1
BIAND #xx:3, @aa:8 2 1
BILD BILD #xx:3, Rd 1
BILD #xx:3, @Rd 2 1
BILD #xx:3, @aa:8 2 1
BIOR BIOR #xx:3, Rd 1
BIOR #xx:3, @Rd 2 1
BIOR #xx:3, @aa:8 2 1
BIST BIST #xx:3, Rd 1
BIST #xx:3, @Rd 2 2
BIST #xx:3, @aa:8 2 2
BIXOR BIXOR #xx:3, Rd 1
BIXOR #xx:3, @Rd 2 1
BIXOR #xx:3, @aa:8 2 1
BLD BLD #xx:3, Rd 1
BLD #xx:3, @Rd 2 1
BLD #xx:3, @aa:8 2 1
BNOT BNOT #xx:3, Rd 1
BNOT #xx:3, @Rd 2 2
BNOT #xx:3, @aa:8 2 2
BNOT Rn, Rd 1
BNOT Rn, @Rd 2 2
BNOT Rn, @aa:8 2 2
BOR BOR #xx:3, Rd 1
BOR #xx:3, @Rd 2 1
BOR #xx:3, @aa:8 2 1
BSET BSET #xx:3, Rd 1
BSET #xx:3, @Rd 2 2
BSET #xx:3, @aa:8 2 2
BSET Rn, Rd 1
BSET Rn, @Rd 2 2
BSET Rn, @aa:8 2 2
Note: All values left blank are zero.
304
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch Stack Byte data Word data Internal
fetch addr. read operation access access operation
Instruction Mnemonic I J K L M N
BSR BSR d:8 2 1
BST BST #xx:3, Rd 1
BST #xx:3, @Rd 2 2
BST #xx:3, @aa:8 2 2
BTST BTST #xx:3, Rd 1
BTST #xx:3, @Rd 2 1
BTST #xx:3, @aa:8 2 1
BTST Rn, Rd 1
BTST Rn, @Rd 2 1
BTST Rn, @aa:8 2 1
BXOR BXOR #xx:3, Rd 1
BXOR #xx:3, @Rd 2 1
BXOR #xx:3, @aa:8 2 1
CMP CMP.B #xx:8, Rd 1
CMP.B Rs, Rd 1
CMP.W Rs, Rd 1
DAA DAA.B Rd 1
DAS DAS.B Rd 1
DEC DEC.B Rd 1
DIVXU DIVXU.B Rs, Rd 1 12
EEPMOV EEPMOV 2 2n+2* 1
INC INC.B Rd 1
JMP JMP @Rn 2
JMP @aa:16 2 2
JMP @@aa:8 2 1 2
JSR JSR @Rn 2 1
JSR @aa:16 2 1 2
JSR @@aa:8 2 1 1
LDC LDC #xx:8, CCR 1
LDC Rs, CCR 1
MOV MOV.B #xx:8, Rd 1
MOV.B Rs, Rd 1
MOV.B @Rs, Rd 1 1
MOV.B @(d:16,Rs), Rd 2 1
Notes: All values left blank are zero.
* n: Initial value in R4L. Source and destination are accessed n + 1 times each.
305
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch Stack Byte data Word data Internal
fetch addr. read operation access access operation
Instruction Mnemonic I J K L M N
MOV MOV.B @Rs+, Rd 1 1 2
MOV.B @aa:8, Rd 1 1
MOV.B @aa:16, Rd 2 1
MOV.B Rs, @Rd 1 1
MOV.B Rs, @(d:16, Rd) 2 1
MOV.B Rs, @–Rd 1 1 2
MOV.B Rs, @aa:8 1 1
MOV.B Rs, @aa:16 2 1
MOV.W #xx:16, Rd 2
MOV.W Rs, Rd 1
MOV.W @Rs, Rd 1 1
MOV.W @(d:16, Rs), Rd 2 1
MOV.W @Rs+, Rd 1 1 2
MOV.W @aa:16, Rd 2 1
MOV.W Rs, @Rd 1 1
MOV.W Rs, @(d:16, Rd) 2 1
MOV.W Rs, @–Rd 1 1 2
MOV.W Rs, @aa:16 2 1
MOVFPE MOVFPE @aa:16, Rd Not supported
MOVTPE MOVTPE.Rs, @aa:16 Not supported
MULXU MULXU.Rs, Rd 1 12
NEG NEG.B Rd 1
NOP NOP 1
NOT NOT.B Rd 1
OR OR.B #xx:8, Rd 1
OR.B Rs, Rd 1
ORC ORC #xx:8, CCR 1
POP POP Rd 1 1 2
PUSH PUSH Rs 1 1 2
ROTL ROTL.B Rd 1
ROTR ROTR.B Rd 1
ROTXL ROTXL.B Rd 1
ROTXR ROTXR.B Rd 1
RTE RTE 2 2 2
RTS RTS 2 1 2
Note: All values left blank are zero. 306
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch Stack Byte data Word data Internal
fetch addr. read operation access access operation
Instruction Mnemonic I J K L M N
SHAL SHAL.B Rd 1
SHAR SHAR.B Rd 1
SHLL SHLL.B Rd 1
SHLR SHLR.B Rd 1
SLEEP SLEEP 1
STC STC CCR, Rd 1
SUB SUB.B Rs, Rd 1
SUB.W Rs, Rd 1
SUBS SUBS.W #1/2, Rd 1
SUBX SUBX.B #xx:8, Rd 1
SUBX.B Rs, Rd 1
XOR XOR.B #xx:8, Rd 1
XOR.B Rs, Rd 1
XORC XORC #xx:8, CCR 1
Note: All values left blank are zero.
307
Appendix B. Register Field
B.1 Register Addresses and Bit Names
Addr.
(last Register Bit names
byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'80 External
H'81 addresses
H'82 (in
H'83 expanded
H'84 modes)
H'85
H'86
H'87
H'88 SMR C/A CHR PE O/E STOP MP CKS1 CKS0 SCI1
H'89 BRR
H'8A SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'8B TDR
H'8C SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'8D RDR
H'8E
H'8F
H'90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — FRT
H'91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'92 FRC (H)
H'93 FRC (L)
H'94 OCRA (H)
OCRB (H)
H'95 OCRA (L)
OCRB (L)
H'96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
H'97 TOCR — — — OCRS OEA OEB OLVLA OLVLB
H'98 ICRA (H)
H'99 ICRA (L)
H'9A ICRB (H)
H'9B ICRB (L)
H'9C ICRC (H)
H'9D ICRC (L)
H'9E ICRD (H)
H'9F ICRD (L) (Continued on next page)
Notes: FRT: Free-Running Timer
SCI1: Serial Communication Interface 1
308
(Continued from previous page)
Addr.
(last Register Bit names
byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'A0 TCR OE OS — — — CKS2 CKS1 CKS0 PWM0
H'A1 DTR
H'A2 TCNT
H'A3 — — — — — — — — —
H'A4 TCR OE OS — — — CKS2 CKS1 CKS0 PWM1
H'A5 DTR
H'A6 TCNT
H'A7 — — — — — — — — —
H'A8 DADR0 D/A
H'A9 DADR1
H'AA DACR DAOE1 DAOE0 DAE — — — — —
H'AB — — — — — — — — —
H'AC P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1
H'AD P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2
H'AE P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3
H'AF — — — — — — — — — —
H'B0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDRP11DDR P10DDR Port 1
H'B1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDRP21DDR P20DDR Port 2
H'B2 P1DR P17P16P15P14P13P12P11P10Port 1
H'B3 P2DR P27P26P25P24P23P22P21P20Port 2
H'B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDRP31DDR P30DDR Port 3
H'B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDRP41DDR P40DDR Port 4
H'B6 P3DR P37P36P35P34P33P32P31P30Port 3
H'B7 P4DR P47P46P45P44P43P42P41P40Port 4
H'B8 P5DDR — — — — — P52DDRP51DDR P50DDR Port 5
H'B9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDRP61DDR P60DDR Port 6
H'BA P5DR — — — — — P52P51P50Port 5
H'BB P6DR P67P66P65P64P63P62P61P60Port 6
H'BC — — — — — — — — — —
H'BD P8DDR — P86DDR P85DDR P84DDR P83DDR P82DDRP81DDR P80DDR Port 8
H'BE P7DR P77P76P75P74P73P72P71P70Port 7
H'BF P8DR — P86P85P84P83P82P81P80Port 8
(Continued on next page)
Notes: PWM0: Pulse-Width Modulation timer channel 0
PWM1: Pulse-Width Modulation timer channel 1
D/A: D/A converter
309
(Continued from preceding page)
Addr.
(last Register Bit names
byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'C0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDRP91DDR P90DDR Port 9
H'C1 P9DR P97P96P95P94P93P92P91P90
H'C2 — — — — — — — — —
H'C3 STCR — — — — — MPE ICKS1 ICKS0
H'C4 SYSCR SSBY STS2 STS1 STS0 — NMIEG DPME RAME System
H'C5 MDCR — — — — — — MDS1 MDS0 control
H'C6 ISCR IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
H'C7 IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
H'C8 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR0
H'C9 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'CA TCORA
H'CB TCORB
H'CC TCNT
H'CD — — — — — — — — —
H'CE — — — — — — — — —
H'CF — — — — — — — — —
H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR1
H'D1 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'D2 TCORA
H'D3 TCORB
H'D4 TCNT
H'D5 — — — — — — — — —
H'D6 — — — — — — — — —
H'D7 — — — — — — — — —
H'D8 SMR C/A CHR PE O/E STOP MP CKS1 CKS0 SCI0
H'D9 BRR
H'DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'DB TDR
H'DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'DD RDR
H'DE — — — — — — — — —
H'DF — — — — — — — — —
(Continued on next page)
Notes: TMR0: 8-Bit Timer channel 0
TMR1: 8-Bit Timer channel 1
SCI0: Serial Communication Interface 0
310
(Continued from preceding page)
Addr.
(last Register Bit names
byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'E0 ADDRA A/D
H'E1 — — — — — — — — —
H'E2 ADDRB
H'E3 — — — — — — — — —
H'E4 ADDRC
H'E5 — — — — — — — — —
H'E6 ADDRD
H'E7 — — — — — — — — —
H'E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'E9 — — — — — — — — —
H'EA ADCR TRGE — — — — — — CHS
H'EB — — — — — — — — —
H'EC — — — — — — — — — —
H'ED — — — — — — — — —
H'EE — — — — — — — — —
H'EF — — — — — — — — —
H'F0 — — — — — — — — — —
H'F1 — — — — — — — — —
H'F2 — — — — — — — — —
H'F3 — — — — — — — — —
H'F4 — — — — — — — — —
H'F5 — — — — — — — — —
H'F6 — — — — — — — — —
H'F7 — — — — — — — — —
H'F8 — — — — — — — — —
H'F9 — — — — — — — — —
H'FA — — — — — — — — —
H'FB — — — — — — — — —
H'FC — — — — — — — — —
H'FD — — — — — — — — —
H'FE — — — — — — — — —
H'FF — — — — — — — — —
Note: A/D: Analog-to-Digital converter
311
B.2 Register Descriptions
H161 H8/337 H.M '91
B.2 Register Description
7
ICIAE
0
R/W
Bit
Initial value
Read/Write
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
R/W
Overflow Interrupt Enable
Overflow interrupt request is enabled.
Overflow interrupt request is disabled.
1
0
Output Compare Interrupt B Enable
Output compare interrupt request B is enabled.
Output compare interrupt request B is disabled.
1
0
Output Compare Interrupt A Enable
Output compare interrupt request A is enabled.
Output compare interrupt request A is disabled.
1
0
Input Capture Interrupt D Enable
Input capture interrupt request D is enabled.
Input capture interrupt request D is disabled.
1
0
3
OCIAE
0
R/W
2
OCIBE
0
R/W
1
OVIE
0
R/W
0
—
1
—
TIER—Timer Interrupt Enable Register H'FF90 FRT
Bit No.
Initial value
Type of access permitted
R
W
R/W
Abbreviation of
register name
Register name Address onto which
register is mapped
Name of on-chip
supporting module
Bit names (abbreviations).
Bits marked “—”
are reserved.
Full name of bit
Description of bit function
Read only
Write only
Read or write
312
SMR—Serial Mode Register H'FF88 SCI1
Bit 7 6 5 4 3 2 1 0
C/A CHR PE O/E STOP MP CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Select
0 0 Ø clock
0 1 Ø/4 clock
1 0 Ø/16 clock
1 1 Ø/64 clock
Multiprocessor Mode
0 Multiprocessor function disabled
1 Multiprocessor format selected
Stop Bit Length
0 One stop bit
1 Two stop bits
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
0 Transmit: No parity bit added.
Receive: Parity bit not checked.
1 Transmit: Parity bit added.
Receive: Parity bit checked.
Character Length
0 8-Bit data length
1 7-Bit data length
Communication Mode
0 Asynchronous
1 Synchronous
313
BRR—Bit Rate Register H'FF89 SCI1
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Constant that determines the bit rate
314
SCR—Serial Control Register H'FF8A SCI1
Bit 7 6 5 4 3 2 1 0
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Enable 0
0 Asynchronous serial clock not output
1 Asynchronous serial clock output at SCK pin
Clock Enable 1
0 Internal clock
1 External clock
Transmit End Interrupt Enable
0 TSR-empty interrupt request is disabled.
1 TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0 Multiprocessor receive interrupt function is disabled.
1 Multiprocessor receive interrupt function is enabled.
Receive Enable
0 Receive disabled
1 Receive enabled
Transmit Enable
0 Transmit disabled
1 Transmit enabled
Receive Interrupt Enable
0 Receive interrupt and receive error interrupt requests are disabled.
1 Receive interrupt and receive error interrupt requests are enabled.
Transmit Interrupt Enable
0 TDR-empty interrupt request is disabled.
1 TDR-empty interrupt request is enabled.
315
TDR—Transmit Data Register H'FF8B SCI1
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Transmit data
316
SSR—Serial Status Register H'FF8C SCI1
Bit 7 6 5 4 3 2 1 0
TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value 1 0 0 0 0 1 0 0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W
Multiprocessor Bit Transfer
0 Multiprocessor bit = “0” in transmit data.
1 Multiprocessor bit = “1” in transmit data.
Multiprocessor Bit
0 Multiprocessor bit = “0” in receive data.
1 Multiprocessor bit = “1” in receive data.
Transmit End
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1 Set to “1” when TE = “0,” or when TDRE = “1” at the end of
character transmission.
Parity Error
0 Cleared when CPU reads PER = “1,” then writes “0” in PER.
1 Set when a parity error occurs (parity of receive data does not match
parity selected by O/E bit in SMR).
Framing Error
0 Cleared when CPU reads FER = “1,” then writes “0” in FER.
1 Set when a framing error occurs (stop bit is “0”).
Overrun Error
0 Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely received while
RDRF bit is set to “1”).
Receive Data Register Full
0 Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
1 Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = “0.”
Note: * Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these
bits.
317
RDR—Receive Data Register H'FF8D SCI1
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Receive data
318
TIER—Timer Interrupt Enable Register H'FF90 FRT
Bit 7 6 5 4 3 2 1 0
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE —
Initial value 0 0 0 0 0 0 0 1
Read/Write R/W R/W R/W R/W R/W R/W R/W —
Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0 Output compare interrupt request B is disabled.
1 Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0 Output compare interrupt request A is disabled.
1 Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0 Input capture interrupt request D is disabled.
1 Input capture interrupt request D is enabled.
Input Capture Interrupt C Enable
0 Input capture interrupt request C is disabled.
1 Input capture interrupt request C is enabled.
Input Capture Interrupt B Enable
0 Input capture interrupt request B is disabled.
1 Input capture interrupt request B is enabled.
Input Capture Interrupt A Enable
0 Input capture interrupt request A is disabled.
1 Input capture interrupt request A is enabled.
319
TCSR—Timer Control/Status Register H'FF91 FRT
Bit 7 6 5 4 3 2 1 0
ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
Initial value 0 0 0 0 0 0 0 0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W
Counter Clear A
0 FRC count is not cleared.
1 FRC count is cleared by compare-match A.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when FRC changes from H'FFFF to H'0000.
Output Compare Flag B
0 Cleared when CPU reads OCFB = “1”, then writes “0” in OCFB.
1 Set when FRC = OCRB.
Output Compare Flag A
0 Cleared when CPU reads OCFA = “1”, then writes “0” in OCFA.
1 Set when FRC = OCRA.
Input Capture Flag D
0 Cleared when CPU reads ICFD = “1”, then writes “0” in ICFD.
1 Set by FTID input.
Input Capture Flag C
0 Cleared when CPU reads ICFC = “1”, then writes “0” in ICFC.
1 Set by FTIC input.
Input Capture Flag B
0 Cleared when CPU reads ICFB = “1”, then writes “0” in ICFB.
1 Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0 Cleared when CPU reads ICFA = “1”, then writes “0” in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
Note: * Software can write a “0” in bits 7 to 1 to clear the flags, but cannot write a “1” in these
bits.
320
FRC (H and L)—Free-Running Counter H'FF92, H'FF93 FRT
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Count value
OCRA (H and L)—Output Compare Register A H'FF94, H'FF95 FRT
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Continually compared with FRC. OCFA is set to “1” when OCRA = FRC.
OCRB (H and L)—Output Compare Register B H'FF94, H'FF95 FRT
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Continually compared with FRC. OCFB is set to “1” when OCRB = FRC.
321
TCR—Timer Control Register H'FF96 FRT
Bit 7 6 5 4 3 2 1 0
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Select
0 0 Internal clock source: Ø/2
0 1 Internal clock source: Ø/8
1 0 Internal clock source: Ø/32
1 1 External clock source: counted on rising edge
Buffer Enable B
0 ICRD is used for input capture D.
1 ICRD is buffer register for input capture B.
Buffer Enable A
0 ICRC is used for input capture C.
1 ICRC is buffer register for input capture A.
Input Edge Select D
0 Falling edge of FTID is valid.
1 Rising edge of FTID is valid.
Input Edge Select C
0 Falling edge of FTIC is valid.
1 Rising edge of FTIC is valid.
Input Edge Select B
0 Falling edge of FTIB is valid.
1 Rising edge of FTIB is valid.
Input Edge Select A
0 Falling edge of FTIA is valid.
1 Rising edge of FTIA is valid.
322
TOCR—Timer Output Compare Control Register H'FF97 FRT
Bit 7 6 5 4 3 2 1 0
— — — OCRS OEA OEB OLVLA OLVLB
Initial value 1 1 1 0 0 0 0 0
Read/Write — — — R/W R/W R/W R/W R/W
Output Level B
0 Compare-match B causes “0” output.
1 Compare-match B causes “1” output.
Output Level A
0 Compare-match A causes “0” output.
1 Compare-match A causes “1” output.
Output Enable B
0 Output compare B output is disabled.
1 Output compare B output is enabled.
Output Enable A
0 Output compare A output is disabled.
1 Output compare A output is enabled.
Output Compare Register Select
0 The CPU can access OCRA.
1 The CPU can access OCRB.
ICRA (H and L)—Input Capture Register A H'FF98, H'FF99 FRT
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Contains FRC count captured on FTIA input.
323
ICRB (H and L)—Input Capture Register B H'FF9A, H'FF9B FRT
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Contains FRC count captured on FTIB input.
ICRC (H and L)—Input Capture Register C H'FF9C, H'FF9D FRT
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
ICRD (H and L)—Input Capture Register D H'FF9E, H'FF9F FRT
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Contains FRC count captured on FTID input, or old ICRB value in buffer mode.
324
TCR—Timer Control Register H'FFA0 PWM0
Bit 7 6 5 4 3 2 1 0
OE OS — — — CKS2 CKS1 CKS0
Initial value 0 0 1 1 1 0 0 0
Read/Write R/W R/W — — — R/W R/W R/W
Clock Select (Values When Ø = 10MHz)
Internal Reso- PWM PWM
clock Freq. lution period frequency
0 0 0 Ø/2 200ns 50µs 20kHz
0 0 1 Ø/8 800ns 200µs 5kHz
0 1 0 Ø/32 3.2µs 800µs 1.25kHz
0 1 1 Ø/128 12.8µs 3.2ms 312.5Hz
1 0 0 Ø/256 25.6µs 6.4ms 156.3Hz
1 0 1 Ø/1024 102.4µs 25.6ms 39.1Hz
1 1 0 Ø/2048 204.8µs 51.2ms 19.5Hz
1 1 1 Ø/4096 409.6µs 102.4ms 9.8Hz
Output Select
0 Positive logic
1 Negative logic
Output Enable
0 PWM output disabled; TCNT cleared to H'00 and stops.
1 PWM output enabled; TCNT runs.
DTR—Duty Register H'FFA1 PWM0
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Pulse duty cycle
325
TCNT—Timer Counter H'FFA2 PWM0
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Count value (runs from H'00 to H'F9, then repeats from H'00)
TCR—Timer Control Register H'FFA4 PWM1
Bit 7 6 5 4 3 2 1 0
OE OS — — — CKS2 CKS1 CKS0
Initial value 0 0 1 1 1 0 0 0
Read/Write R/W R/W — — — R/W R/W R/W
Note: Bit functions are the same as for PWM0.
DTR—Duty Register H'FFA5 PWM1
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for PWM0.
326
TCNT—Timer Counter H'FFA6 PWM1
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for PWM0.
DADR0—D/A Data Register 0 H'FFA8 D/A
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Data to be converted
DADR1—D/A Data Register 1 H'FFA9 D/A
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Data to be converted
327
DACR—D/A Control Register H'FFAA D/A
Bit 7 6 5 4 3 2 1 0
DAOE1 DAOE0 DAE — — — — —
Initial value 0 0 0 1 1 1 1 1
Read/Write R/W R/W R/W — — — — —
DAOE1 DAOE0 DAE D/A Analog Output
0 0 0 Channels 0 and 1 disabled.
0 1 0 Channel 0 disabled, channel 1 enabled.
0 1 1 Channels 0 and 1 enabled.
1 0 0 Channel 0 enabled, channel 1 disabled.
1 0 1 Channels 0 and 1 enabled.
1 1 — Channels 0 and 1 enabled.
P1PCR—Port 1 Input Pull-Up Control Register H'FFAC Port 1
Bit 7 6 5 4 3 2 1 0
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Port 1 Input Pull-Up Control
0 Input pull-up transistor is off.
1 Input pull-up transistor is on.
328
P2PCR—Port 2 Input Pull-Up Control Register H'FFAD Port 2
Bit 7 6 5 4 3 2 1 0
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Port 2 Input Pull-Up Control
0 Input pull-up transistor is off.
1 Input pull-up transistor is on.
P3PCR—Port 3 Input Pull-Up Control Register H'FFAE Port 3
Bit 7 6 5 4 3 2 1 0
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Port 3 Input Pull-Up Control
0 Input pull-up transistor is off.
1 Input pull-up transistor is on.
329
P1DDR—Port 1 Data Direction Register H'FFB0 Port 1
Bit 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value 1 1 1 1 1 1 1 1
Read/Write — — — — — — — —
Modes 2 and 3
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Port 1 Input/Output Control
0 Input port
1 Output port
P1DR—Port 1 Data Register H'FFB2 Port 1
Bit 7 6 5 4 3 2 1 0
P17P16P15P14P13P12P11P10
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
330
P2DDR—Port 2 Data Direction Register H'FFB1 Port 2
Bit 7 6 5 4 3 2 1 0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Mode 1
Initial value 1 1 1 1 1 1 1 1
Read/Write — — — — — — — —
Modes 2 and 3
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Port 2 Input/Output Control
0 Input port
1 Output port
P2DR—Port 2 Data Register H'FFB3 Port 2
Bit 7 6 5 4 3 2 1 0
P27P26P25P24P23P22P21P20
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P3DDR—Port 3 Data Direction Register H'FFB4 Port 3
Bit 7 6 5 4 3 2 1 0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Port 3 Input/Output Control
0 Input port
1 Output port
331
P3DR—Port 3 Data Register H'FFB6 Port 3
Bit 7 6 5 4 3 2 1 0
P37P36P35P34P33P32P31P30
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P4DDR—Port 4 Data Direction Register H'FFB5 Port 4
Bit 7 6 5 4 3 2 1 0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Port 4 Input/Output Control
0 Input port
1 Output port
P4DR—Port 4 Data Register H'FFB7 Port 4
Bit 7 6 5 4 3 2 1 0
P47P46P45P44P43P42P41P40
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P5DDR—Port 5 Data Direction Register H'FFB8 Port 5
Bit 7 6 5 4 3 2 1 0
— — — — — P52DDR P51DDR P50DDR
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — W W W
Port 5 Input/Output Control
0 Input port
1 Output port
332
P5DR—Port 5 Data Register H'FFBA Port 5
Bit 7 6 5 4 3 2 1 0
— — — — — P52P51P50
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — R/W R/W R/W
P6DDR—Port 6 Data Direction Register H'FFB9 Port 6
Bit 7 6 5 4 3 2 1 0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Port 6 Input/Output Control
0 Input port
1 Output port
P6DR—Port 6 Data Register H'FFBB Port 6
Bit 7 6 5 4 3 2 1 0
P67P66P65P64P63P62P61P60
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
P7DR—Port 7 Data Register H'FFBE Port 7
Bit 7 6 5 4 3 2 1 0
P77P76P75P74P73P72P71P70
Initial value * * * * * * * *
Read/Write R R R R R R R R
Note: * Depends on the levels of pins P77to P70.
333
P8DDR—Port 8 Data Direction Register H'FFBD Port 8
Bit 7 6 5 4 3 2 1 0
— P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Initial value 1 0 0 0 0 0 0 0
Read/Write — W W W W W W W
Port 8 Input/Output Control
0 Input port
1 Output port
P8DR—Port 8 Data Register H'FFBF Port 8
Bit 7 6 5 4 3 2 1 0
— P86P85P84P83P82P81P80
Initial value 1 0 0 0 0 0 0 0
Read/Write — R/W R/W R/W R/W R/W R/W R/W
P9DDR—Port 9 Data Direction Register H'FFC0 Port 9
Bit 7 6 5 4 3 2 1 0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Modes 1 and 2
Initial value 0 1 0 0 0 0 0 0
Read/Write W — W W W W W W
Mode 3
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
Port 9 Input/Output Control
0 Input port
1 Output port
334
P9DR—Port 9 Data Register H'FFC1 Port 9
Bit 7 6 5 4 3 2 1 0
P97P96P95P94P93P92P91P90
Initial value 0 * 0 0 0 0 0 0
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Note: * Depends on the level of pin P96.
STCR—Serial/Timer Control Register H'FFC3 TMR0/1
Bit 7 6 5 4 3 2 1 0
— — — — — MPE ICKS1 ICKS0
Initial value 1 1 1 1 1 0 0 0
Read/Write — — — — — R/W R/W R/W
Multiprocessor Enable
0 Multiprocessor communication function is disabled.
1 Multiprocessor communication function is enabled.
Internal Clock Source Select
See TCR under TMR0 and TMR1.
335
SYSCR—System Control Register H'FFC4 System Control
Bit 7 6 5 4 3 2 1 0
SSBY STS2 STS1 STS0 — NMIEG DPME RAME
Initial value 0 0 0 0 1 0 0 1
Read/Write R/W R/W R/W R/W — R/W R/W* R/W
RAM Enable
0 On-chip RAM is disabled.
1 On-chip RAM is enabled.
Dual-Port RAM Enable
Not supported. (Do not set to “1.”)
NMI Edge
0 Falling edge of NMI is detected.
1 Rising edge of NMI is detected.
Standby Timer Select
0 0 0 Clock settling time = 8192 states
0 0 1 Clock settling time = 16384 states
0 1 0 Clock settling time = 32768 states
0 1 1 Clock settling time = 65536 states
1 – – Clock settling time = 131072 states
Software Standby
0 SLEEP instruction causes transition to sleep mode.
1 SLEEP instruction causes transition to software standby mode.
Note: * Do not set DPME to 1.
336
MDCR—Mode Control Register H'FFC5 System Control
Bit 7 6 5 4 3 2 1 0
— — — — — — MDS1 MDS0
Initial value 1 1 1 0 0 1 * *
Read/Write — — — — — — R R
Mode Select Bits
Value at mode pins.
Note: * Determined by inputs at pins MD1and MD0.
ISCR—IRQ Sense Control Register H'FFC6 System Control
Bit 7 6 5 4 3 2 1 0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
IRQ0 to IRQ7Sense Control
0 IRQiis level-sensed (active Low).
1 IRQiis edge-sensed (falling edge).
IER—IRQ Enable Register H'FFC7 System Control
Bit 7 6 5 4 3 2 1 0
IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
IRQ0 to IRQ7Enable
0 IRQiis disabled.
1 IRQiis enabled.
337
TCR—Timer Control Register H'FFC8 TMR0
Bit 7 6 5 4 3 2 1 0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Select
TCR STCR
CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 — — Timer stopped
0 0 1 — 0 Ø/8 internal clock, falling edge
0 0 1 — 1 Ø/2 internal clock, falling edge
0 1 0 — 0 Ø/64 internal clock, falling edge
0 1 0 — 1 Ø/32 internal clock, falling edge
0 1 1 — 0 Ø/1024 internal clock, falling edge
0 1 1 — 1 Ø/256 internal clock, falling edge
1 0 0 — — Timer stopped
1 0 1 — — External clock, rising edge
1 1 0 — — External clock, falling edge
1 1 1 — — External clock, rising and falling
edges
Counter Clear
0 0 Counter is not cleared.
0 1 Cleared by compare-match A.
1 0 Cleared by compare-match B.
1 1 Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Compare-Match Interrupt Enable A
0 Compare-match A interrupt request is disabled.
1 Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0 Compare-match B interrupt request is disabled.
1 Compare-match B interrupt request is enabled.
338
TCSR—Timer Control/Status Register H'FFC9 TMR0
Bit 7 6 5 4 3 2 1 0
CMFB CMFA OVF — OS3*2 OS2*2 OS1*2 OS0*2
Initial value 0 0 0 1 0 0 0 0
Read/Write R/(W)*1 R/(W)*1 R/(W)*1 — R/W R/W R/W R/W
Output Select
0 0 No change on compare-match A.
0 1 Output “0” on compare-match A.
1 0 Output “1” on compare-match A.
1 1 Invert (toggle) output on compare-match A.
Output Select
0 0 No change on compare-match B.
0 1 Output “0” on compare-match B.
1 0 Output “1” on compare-match B.
1 1 Invert (toggle) output on compare-match B.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when TCNT changes from H'FF to H'00.
Compare-Match Flag A
0 Cleared when CPU reads CMFA = “1,” then writes “0” in CMFA.
1 Set when TCNT = TCORA.
Compare-Match Flag B
0 Cleared from when CPU reads CMFB = “1,” then writes “0” in CMFB.
1 Set when TCNT = TCORB.
Notes: *1 Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these
bits.
*2 When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
339
TCORA—Time Constant Register A H'FFCA TMR0
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The CMFA bit is set to “1” when TCORA = TCNT.
TCORB—Time Constant Register B H'FFCB TMR0
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
The CMFB bit is set to “1” when TCORB = TCNT.
TCNT—Timer Counter H'FFCC TMR0
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Count value
340
TCR—Timer Conrol Register H'FFD0 TMR1
Bit 7 6 5 4 3 2 1 0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Select
TCR STCR
CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 — — Timer stopped
0 0 1 0 — Ø/8 internal clock, falling edge
0 0 1 1 — Ø/2 internal clock, falling edge
0 1 0 0 — Ø/64 internal clock, falling edge
0 1 0 1 — Ø/128 internal clock, falling edge
0 1 1 0 — Ø/1024 internal clock, falling edge
0 1 1 1 — Ø/2048 internal clock, falling edge
1 0 0 — — Timer stopped
1 0 1 — — External clock, rising edge
1 1 0 — — External clock, falling edge
1 1 1 — — External clock, rising and falling
edges
Counter Clear
0 0 Counter is not cleared.
0 1 Cleared by compare-match A.
1 0 Cleared by compare-match B.
1 1 Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Compare-Match Interrupt Enable A
0 Compare-match A interrupt request is disabled.
1 Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0 Compare-match B interrupt request is disabled.
1 Compare-match B interrupt request is enabled.
341
TCSR—Timer Control/Status Register H'FFD1 TMR1
Bit 7 6 5 4 3 2 1 0
CMFB CMFA OVF — OS3*2 OS2*2 OS1*2 OS0*2
Initial value 0 0 0 1 0 0 0 0
Read/Write R/(W)*1 R/(W)*1 R/(W)*1 — R/W R/W R/W R/W
Note: Bit functions are the same as for TMR0.
*1 Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these
bits.
*2 When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
TCORA—Time Constant Register A H'FFD2 TMR1
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for TMR0.
TCORB—Time Constant Register B H'FFD3 TMR1
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for TMR0.
TCNT—Timer Counter H'FFD4 TMR1
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for TMR0.
342
SMR—Serial Mode Register H'FFD8 SCI0
Bit 7 6 5 4 3 2 1 0
C/A CHR PE O/E STOP MP CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Select
0 0 Ø clock
0 1 Ø/4 clock
1 0 Ø/16 clock
1 1 Ø/64 clock
Multiprocessor Mode
0 Multiprocessor function disabled
1 Multiprocessor format selected
Stop Bit Length
0 One stop bit
1 Two stop bits
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
0 Transmit: No parity bit added.
Receive: Parity bit not checked.
1 Transmit: Parity bit added.
Receive: Parity bit checked.
Character Length
0 8-Bit data length
1 7-Bit data length
Communication Mode
0 Asynchronous
1 Synchronous
Note: Bit functions are the same as for SCI1.
343
BRR—Bit Rate Register H'FFD9 SCI0
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Constant that determines the bit rate
Note: Bit functions are the same as for SCI1.
344
SCR—Serial Control Register H'FFDA SCI0
Bit 7 6 5 4 3 2 1 0
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Clock Enable 0
0 Asynchronous serial clock not output
1 Asynchronous serial clock output at SCK pin
Clock Enable 1
0 Internal clock
1 External clock
Transmit End Interrupt Enable
0 TSR-empty interrupt request is disabled.
1 TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0 Multiprocessor receive interrupt function is disabled.
1 Multiprocessor receive interrupt function is enabled.
Receive Enable
0 Receive disabled
1 Receive enabled
Transmit Enable
0 Transmit disabled
1 Transmit enabled
Receive Interrupt Enable
0 Receive interrupt and receive error interrupt requests are disabled.
1 Receive interrupt and receive error interrupt requests are enabled.
Transmit Interrupt Enable
0 TDR-empty interrupt request is disabled.
1 TDR-empty interrupt request is enabled.
Note: Bit functions are the same as for SCI1.
345
TDR—Transmit Data Register H’FFDB SCI0
Bit 7 6 5 4 3 2 1 0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Transmit data
Note: Bit functions are the same as for SCI1.
346
SSR—Serial Status Register H'FFDC SCI0
Bit 7 6 5 4 3 2 1 0
TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value 1 0 0 0 0 1 0 0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W
Multiprocessor Bit Transfer
0 Multiprocessor bit = “0” in transmit data.
1 Multiprocessor bit = “1” in transmit data.
Multiprocessor Bit
0 Multiprocessor bit = “0” in receive data.
1 Multiprocessor bit = “1” in receive data.
Transmit End
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1 Set to “1” when TE = “0,” or when TDRE = “1” at the end of
character transmission.
Parity Error
0 Cleared when CPU reads PER = “1,” then writes “0” in PER.
1 Set when a parity error occurs (parity of receive data does not match
parity selected by O/E bit in SMR).
Framing Error
0 Cleared when CPU reads FER = “1,” then writes “0” in FER.
1 Set when a framing error occurs (stop bit is “0”).
Overrun Error
0 Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely received while
RDRF bit is set to “1”).
Receive Data Register Full
0 Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
1 Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = “0.”
Note: * Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these bits.
Bit functions are the same as for SCI1.
347
RDR—Receive Data Register H'FFDD SCI0
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Receive data
Note: Bit functions are the same as for SCI1.
ADDRn—A/D Data Register n (n = A, B, C, D) H'FFE0, H'FFE2, A/D
H'FFE4, H'FFE6
Bit 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
A/D conversion result
348
ADCSR—A/D Control/Status Register H'FFE8 A/D
Bit 7 6 5 4 3 2 1 0
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W
Channel Select
CH2 CH1 CH0 Single mode Scan mode
0 0 0 AN0AN0
0 1 AN1AN0, AN1
1 0 AN2AN0to AN2
1 1 AN3AN0to AN3
1 0 0 AN4AN4
0 1 AN5AN4, AN5
1 0 AN6AN4to AN6
1 1 AN7AN4to AN7
Clock Select
0 Conversion time = 242 states (max)
1 Conversion time = 122 states (max)
Scan Mode
0 Single mode
1 Scan mode
A/D Start
0 A/D conversion is halted.
1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to “0.”
2. Scan mode: A/D conversion starts and continues cyclically on all selected channels until “0”
is written in this bit.
A/D Interrupt Enable
0 The A/D interrupt request (ADI) is disabled.
1 The A/D interrupt request (ADI) is enabled.
A/D End Flag
0 Cleared from “1” to “0” when CPU reads ADF = “1,” then writes “0” in ADF.
1 Set to “1” at the following times:
1. Single mode: at the completion of A/D conversion
2. Scan mode: when all selected channels have been converted.
Note: * Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
349
ADCR—A/D Control Register H'FFEA A/D
Bit 7 6 5 4 3 2 1 0
TRGE — — — — — — CHS
Initial value 0 1 1 1 1 1 1 0
Read/Write R/W — — — — — — R/W
Reserved bit.
Trigger Enable
0 ADTRG is disabled.
1 ADTRG is enabled. A/D conversion can be started by external trigger,
or by software.
350
Appendix C. Pin States
C.1 Pin States in Each Mode
Table C-1. Pin States
Pin MCU Hardware Software Sleep Normal
name mode Reset standby standby mode operation
P17– P101 Low 3-State Low Prev. state A7– A0
A7– A02 3-State Low if (Addr. Addr. output
DDR = 1, output pins: or input port
Prev. state last address
if DDR = 0 accessed)
3 Prev. state I/O port
P27– P201 Low 3-State Low Prev. state A15 – A8
A15 – A82 3-State Low if (Addr. Addr. output
DDR = 1, output pins: or input port
Prev. state last address
if DDR = 0 accessed)
3 Prev. state I/O port
P37– P301 3-State 3-State 3-state 3-State D7– D0
D7– D02
3 Prev. state Prev. state I/O port
P47– P401 3-State 3-State Prev. state* Prev. state I/O port
2
3
P52– P501 3-State 3-State Prev. state* Prev. state I/O port
2
3
Notes: 1. 3-State: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may
also be used by the on-chip supporting modules.
See section 5, “I/O Ports,” for further information.
* On-chip supporting modules are initialized, so these pins revert to I/O ports according
to the DDR and DR bits.
351
Table C-1. Pin States (cont.)
Pin MCU Hardware Software Sleep Normal
name mode Reset standby standby mode operation
P67– P601 3-State 3-State Prev. state* Prev. state I/O port
2
3
P77– P701 3-State 3-State 3-State 3-State Input port
2
3
P86– P801 3-State 3-State Prev. state* Prev. state I/O port
2
3
P97/WAIT 1 3-State 3-State 3-State 3-State WAIT
2
3 Prev. state Prev. state I/O port
P96/Ø 1 Clock 3-State High Clock Clock
2 output output output
3 3-State High if Clock output Clock output
DDR = 1, if DDR = 1, if DDR = 1,
3-state if 3-state if input port if
DDR = 0 DDR = 0 DDR = 0
P95– P93, 1 High 3-State High High AS, WR,
AS, WR, RD 2 RD
3 3-State Prev. state Prev. state I/O port
P92– P901 3-State 3-State Prev. state Prev. state I/O port
2
3
Notes: 1. 3-State: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS
pull-up on if PCR = 1). Output ports hold their previous output level.
3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may
also be used by the on-chip supporting modules.
See section 5, “I/O Ports,” for further information.
* On-chip supporting modules are initialized, so these pins revert to I/O ports according
to the DDR and DR bits.
352
Appendix D. Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents when the RAME bit in SYSCR is cleared to 0, drive the RES signal
low 10 system clock cycles before the STBY signal goes low, as shown below. RES must
remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
(2) When the RAME bit in SYSCR is set to “1” or when it is not necessary to retain RAM
contents, RES does not have to be driven low as in (1).
Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
t 10 t
1≥cyc t 0 ns
2≥
STBY
RES
t 100 ns
≥tOSC
353
Appendix E. Package Dimensions
Figure E-1 shows the dimensions of the CG-84 package. Figure E-2 shows the dimensions of the
CP-84 package. Figure E-3 shows the dimensions of the FP-80A package.
Unit: mm
Figure E-1. Package Dimensions (CG-84)
Unit: mm
Figure E-2. Package Dimensions (CP-84)
29.21 ± 0.38
2.16 1.27
12 32
11 33
1
84
75 53
74 54
1.27
0.635 4.03 Max
φd
1.27
0.42 ± 0.10
29.28
28.20 ± 0.50
28.20 ± 0.50
4.40 ± 0.20
2.55 ± 0.15
0.10
30.23 ± 0.12
53
33
54
74
75
84
1
11
12 32
30.23 ± 0.12
0.75
Unit: mm
Figure E-3. Package Dimensions (FP-80A)
60
0 – 5 °
0.10
0.12 M
17.2 ± 0.3
41
61
80 120
40
21
17.2 ±0.3
0.30 ±0.10
0.65
3.05 Max
0.10
1.60
0.80 ± 0.30
14.0
2.70 +0.20
–0.16
0.17 +0.08
–0.05
