CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs Translates any single-ended input signal to 3.3 V LVDS levels with resistor bias on INx# input 30-ps maximum output-to-output skew 480-ps maximum propagation delay 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) Up to 1.5-GHz operation Output enable and synchronous clock enable functions 20-pin TSSOP 2.5-V or 3.3-V operating voltage [1] Commercial and industrial operating temperature range The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between two separate differential (LVPECL, LVDS, HCSL, or CML) input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz. Logic Block Diagram Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation Document Number: 001-56312 Rev. *I * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised February 1, 2013 CY2DL1504 Contents Pinouts ..............................................................................3 Pin Definitions ..................................................................3 Absolute Maximum Ratings ............................................4 Operating Conditions .......................................................4 DC Electrical Specifications ............................................5 AC Electrical Specifications ............................................6 Switching Waveforms ......................................................8 Application Information .................................................10 Ordering Information ......................................................11 Ordering Code Definitions .........................................11 Document Number: 001-56312 Rev. *I Package Diagram ............................................................12 Acronyms ........................................................................13 Document Conventions .................................................13 Units of Measure .......................................................13 Document History Page .................................................14 Sales, Solutions, and Legal Information ......................16 Worldwide Sales and Design Support .......................16 Products ....................................................................16 PSoC Solutions .........................................................16 Page 2 of 16 CY2DL1504 Pinouts Figure 1. 20-pin TSSOP pinout Pin Definitions Pin No. Pin Name Pin Type 1,9,13 VSS Power Description 2 CLK_EN Input Synchronous clock enable. LVCMOS/LVTTL; When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high 3 IN_SEL Input Input clock select pin. LVCMOS/LVTTL; When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active 4 IN0 Input Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL = Low 5 IN0# Input Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active when IN_SEL = Low Ground 6 IN1 Input Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL = High 7 IN1# Input Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active when IN_SEL = High 8 OE Input Output enable. LVCMOS/LVTTL; When OE = Low, Q(0:3) and Q(0:3)# outputs are disabled (see IOZ) 10,18 VDD Power Power supply 11,14,16,19 Q(0:3)# Output LVDS complementary output clocks 12,15,17,20 Q(0:3) Output LVDS output clocks Document Number: 001-56312 Rev. *I Page 3 of 16 CY2DL1504 Absolute Maximum Ratings Parameter Description Condition Min Max Unit VDD Supply voltage Nonfunctional -0.5 4.6 V VIN[2] Input voltage, relative to VSS Nonfunctional -0.5 Lesser of 4.0 or VDD + 0.4 V VOUT[2] DC output or I/O voltage, relative Nonfunctional to VSS -0.5 Lesser of 4.0 or VDD + 0.4 V TS Storage temperature -55 150 C ESDHBM Electrostatic discharge (ESD) JEDEC STD 22-A114-B protection (Human body model) 2000 - V LU Latch up UL-94 Flammability rating MSL Moisture sensitivity level Nonfunctional Meets or exceeds JEDEC Spec JESD78B IC latch up test At 1/8 in. V-0 3 Operating Conditions Parameter VDD Description Supply voltage Min Max Unit 2.5-V supply Condition 2.375 2.625 V 3.3-V supply 3.135 3.465 V 0 70 C TA Ambient operating temperature Commercial Industrial -40 85 C tPU Power ramp time Power-up time for VDD to reach minimum specified voltage. (Power ramp must be monotonic) 0.05 500 ms Note 2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Document Number: 001-56312 Rev. *I Page 4 of 16 CY2DL1504 DC Electrical Specifications (VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter Description Min Max Unit - 61 mA Input high voltage, differential input clocks, IN0, IN0#, IN1, and IN1# - VDD + 0.3 V VIL1 Input low voltage, differential input clocks, IN0, IN0#, IN1, and IN1# -0.3 - V VIH2 Input high voltage, CLK_EN, IN_SEL, and OE VDD = 3.3 V 2.0 VDD + 0.3 V VIL2 Input low voltage, CLK_EN, IN_SEL, and OE VDD = 3.3 V -0.3 0.8 V VIH3 Input high voltage, CLK_EN, IN_SEL, and OE VDD = 2.5 V 1.7 VDD + 0.3 V VIL3 Input low voltage, CLK_EN, IN_SEL, and OE VDD = 2.5 V -0.3 0.7 V LVDS input differential amplitude See Figure 3 on page 8 0.4 0.8 V LVPECL/CML/HCSL input differential amplitude See Figure 3 on page 8 0.4 1.0 V Input common mode voltage See Figure 3 on page 8 0.2 VDD - 0.2 V - 150 A IDD Operating supply current VIH1 VID_LVDS[5] VID_LVPECL VICM IIH [5] Input high current, All inputs Condition All LVDS outputs terminated with a load of 100 [3, 4] Input = VDD VSS[6] IIL Input low current, All inputs VPP LVDS differential output voltage VDD = 3.3 V or 2.5 V, peak to Peak, Single-ended RTERM = 100 between Q and Q# pairs [3, 7] LVDS differential output common VDD = 3.3 V or 2.5 V, mode voltage RTERM = 100 between Q and Q# pairs [3, 7] VOCM Input = [6] -150 - A 250 470 mV 1.125 1.375 V - 50 mV -15 15 A VOCM Change in VOCM between complementary output states VDD = 3.3 V or 2.5 V, RTERM = 100 between Q and Q# pairs [3, 7] IOZ Output leakage current OE = VSS, VOUT = 0.75 V-1.75 V RP Internal pull-up/pull-down CLK_EN has pull-up only resistance, LVCMOS logic inputs IN_SEL has pull-down only OE has pull-up only 60 165 k CIN Input capacitance - 3 pF Measured at 10 MHz; per pin Notes 3. Refer to Figure 2 on page 8. 4. IDD includes current that is dissipated externally in the output termination resistors. 5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 6. Positive current flows into the input pin, negative current flows out of the input pin. 7. Refer to Figure 4 on page 8. Document Number: 001-56312 Rev. *I Page 5 of 16 CY2DL1504 AC Electrical Specifications (VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter FIN FOUT Description Input frequency Output frequency Min Typ Max Unit Differential Input Condition DC - 1.5 GHz Single ended input [8] DC - 250 MHz FOUT = FIN,Differential Input DC - 1.5 GHz FOUT = FIN, Single ended input [8] DC - 250 MHz tPD[9] Propagation delay differential input pair to differential output pair Input rise/fall time < 1.5 ns (20% to 80%) - - 480 ps tODC[10] Output duty cycle Diff input at 50% duty cycle Frequency range up to 1 GHz 48 - 52 % 50% duty cycle at input, Frequency range up to 250MHz, Single ended input [8] 45 - 55 % tSK1[11] Output-to-output skew Any output to any output, with same load conditions at DUT - - 30 ps tSK1 D[11] Device-to-device output skew Any output to any output between two or more devices. Devices must have the same input and have the same output load. - - 150 ps PNADD Additive RMS phase noise 156.25 MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV or Input Swing = 3.0 V[8] Offset = 1 kHz - - -120 dBc/ Hz Offset = 10 kHz - - -135 dBc/ Hz Offset = 100 kHz - - -135 dBc/ Hz Offset = 1 MHz - - -150 dBc/ Hz Offset = 10 MHz - - -154 dBc/ Hz Offset = 20 MHz - - -155 dBc/ Hz Notes 8. Refer to Application Information on page 10. 9. Refer to Figure 5 on page 8. 10. Refer to Figure 6 on page 8. 11. Refer to Figure 7 on page 9. Document Number: 001-56312 Rev. *I Page 6 of 16 CY2DL1504 AC Electrical Specifications (continued) (VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter tJIT[12] Description Additive RMS phase jitter (Random) Min Typ Max Unit 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV Condition - - 0.11 ps 156.25 MHz Sinewave, 12 kHz to 20 MHz offset, input rise/fall time < 150 ps (20% to 80%), Input Swing = 3.0 V [13] - - 0.11 ps tR, tF[14] Output rise/fall time, single-ended 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) Measured at 1 GHz. - - 300 ps tSOD Time from clock edge to outputs disabled Synchronous clock enable (CLK_EN) switched low - - 700 ps tSOE Time from clock edge to outputs enabled Synchronous clock enable (CLK_EN) switched high - - 700 ps Notes 12. Refer to Figure 8 on page 9. 13. Refer to Application Information on page 10. 14. Refer to Figure 9 on page 9. Document Number: 001-56312 Rev. *I Page 7 of 16 CY2DL1504 Switching Waveforms Figure 2. LVDS Output Termination Figure 3. Input Differential and Common Mode Voltages Figure 4. Output Differential and Common Mode Voltages Figure 5. Input to Any Output Pair Propagation Delay Figure 6. Output Duty Cycle Document Number: 001-56312 Rev. *I Page 8 of 16 CY2DL1504 Switching Waveforms (continued) Figure 7. Output-to-output and Device-to-device Skew Figure 8. RMS Phase Jitter Figure 9. Output Rise/Fall Time Document Number: 001-56312 Rev. *I Page 9 of 16 CY2DL1504 Switching Waveforms (continued) Figure 10. Synchronous Clock Enable Timing Application Information Figure 11 shows the schematic which can be used to give single ended CMOS input to the CY2DL1504. CY2DL1504 can be used with a single ended CMOS input by biasing the Complementary Input Clock (INx#). "True" input pins (INx) of differential input pair can be fed with a single ended CMOS input signal. The "complementary" input pin (INx#) of the same differential input pair can be biased with Vref. The reference voltage Vref = VDD/2 is generated by the bias resistors R1, R2 and capacitor C0. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the Vref in the center of the input voltage swing. For example, if the input clock swing is 2.5 V and VDD = 3.3 V, Vref should be 1.25 V and R2/R1 = 0.609. Figure 11. Single ended CMOS input given to the CY2DL1504 Document Number: 001-56312 Rev. *I Page 10 of 16 CY2DL1504 Ordering Information Part Number Type Production Flow Pb-free CY2DL1504ZXC 20-pin TSSOP Commercial, 0 C to 70 C CY2DL1504ZXCT 20-pin TSSOP Commercial, 0 C to 70 C CY2DL1504ZXI 20-pin TSSOP Industrial, -40 C to 85 C CY2DL1504ZXIT 20-pin TSSOP Industrial, -40 C to 85 C Ordering Code Definitions CY 2DL15 04 Z X X X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: Z = 20-pin TSSOP Number of differential output pairs: 4 Base part number Company ID: CY = Cypress Document Number: 001-56312 Rev. *I Page 11 of 16 CY2DL1504 Package Diagram Figure 12. 20-pin TSSOP (4.40 mm Body) Z20.173/ZZ20.173 Package Outline, 51-85118 51-85118 *D Document Number: 001-56312 Rev. *I Page 12 of 16 CY2DL1504 Acronyms Acronym Document Conventions Description Units of Measure ESD electrostatic discharge HBM human body model C degree Celsius HCSL high-speed current steering logic dBc decibels relative to the carrier JEDEC joint electron devices engineering council GHz gigahertz LVDS low-voltage differential signal Hz hertz LVCMOS low-voltage complementary metal oxide semiconductor k kilohm MHz megahertz A microampere F microfarad s microsecond mA milliampere ms millisecond mV millivolt ns nanosecond ohm LVPECL low-voltage positive emitter-coupled logic LVTTL low-voltage transistor-transistor logic OE output enable RMS root mean square TSSOP thin shrunk small outline package Document Number: 001-56312 Rev. *I Symbol Unit of Measure pF picofarad ps picosecond V volt W watt Page 13 of 16 CY2DL1504 Document History Page Document Title: CY2DL1504, 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ECN Orig. of Change Submission Date ** 2782891 CXQ 10/09/09 *A 2838613 CXQ 01/05/2010 Changed status from "ADVANCE" to "PRELIMINARY". Changed from 0.34 ps to 0.25 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added tPU spec to the Operating Conditions table on page 3. Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA to 61 mA. Removed VOD and VOD specs from the DC Electrical Specs table on page 4. Changed IOZ in the DC Electrical Specs table on page 4 from min of -10 uA to -15 uA and from max of 10 uA to 15 uA. Added RP spec in the DC Electrical Specs table on page 4. Min = 60 k, Max = 140 k. Added a measurement definition for CIN in the DC Electrical Specs table on page 4. Added VPP and VPP specs to the AC Electrical Specs table on page 5. VPP min = 250 mV and max = 470 mV; VPP max = 50 mV. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 5 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs table on page 5. Added condition to tR and tF specs in the AC Electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 4, 5, 6, 7 and 9, to be consistent with EROS. Updated Figure 4 with definition for VPP and VPP. *B 3010332 CXQ 08/18/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added "Functional equivalent to ICS8543i" to the "Features" section. Changed pin 13 in Figure 1 and Table 1 from VDD to VSS. Changed pin 8 description in Table 1 from "high impedance" to "disabled". Added note 6 to describe IIH and IIL specs. Removed reference to data distribution from "Functional Description". Changed RP for diff inputs from 100 k to 150 k in the Logic Block Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the DC Electrical Specs table. Split VID into separate specs in DC Electrical Specs table: 0.4 V min and 0.8 V max for LVDS, 0.4 V min and 1.0 V max for LVPECL. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added "Frequency range up to 1 GHz" condition to tODC spec. Changed tOD in the AC Electrical Specs table from 3 ns max to 5 ns max. Added Acronyms and Ordering Code Definition. Document Number: 001-56312 Rev. *I Description of Change New Datasheet. Page 14 of 16 CY2DL1504 Document History Page (continued) Document Title: CY2DL1504, 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ECN Orig. of Change Submission Date Description of Change *C 3090644 CXQ 11/19/2010 Changed VIN and VOUT specs from 4.0V to "lesser of 4.0 or VDD + 0.4" Removed 200mA min LU spec, replaced with "Meets or exceeds JEDEC Spec JESD78B IC Latchup Test" Added "VOUT = 0.75V - 1.75V" to IOZ comments. Moved VPP from AC spec table to DC spec table, removed VPP. Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to "Measured at 10 MHz". Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets. Added "Measured at 1 GHz" to tR, tF spec condition. Removed specs tS, tH, tOD, and tOE from AC spec table. Removed VPP reference from Figure 4. *D 3135189 CXQ 01/12/2011 Removed "Preliminary" status heading. Removed "Functional equivalent" bullet on page 1. Added "(see IOZ)" note to pin 8 description in Pin Definitions. Fixed typo and removed resistors from INX/INX# in Logic Block Diagram. Added Figure 10 to describe TSOE and TSOD. *E 3090938 CXQ 02/25/11 *F 3208968 CXQ 03/29/2011 Changed RP max from 140 k to 165 k and updated RP in Logic Block Diagram. *G 3308039 CXQ 07/11/2011 Updated supported differential input clock types to include CML in Features, Functional Description, Pin Definitions, and DC specs table sections. *H 3395868 PURU 10/05/11 Updated supported differential input clock types to include HCSL in Features, Pinouts, and DC Electrical Specifications table. Changed Min value of VICM. *I 3892255 PURU 02/01/2013 Updated Features (Added "Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input"). Post to external web. Updated AC Electrical Specifications: Added Note 8 and Note 13. Added FIN parameter values for "Single Ended Input" condition (Minimum value = DC, Maximum value = 250 MHz). Added FOUT parameter values for "Single Ended Input" condition (Minimum value = DC, Maximum value = 250 MHz). Added tODC parameter values for "Single Ended Input" condition (Minimum value = 45%, Maximum value = 55%). Updated Description of PNADD parameter (Replaced "Additive RMS phase noise, 156.25-MHz input, Rise/fall time < 150 ps (20% to 80%), VID > 400 mV" with "Additive RMS phase noise, 156.25-MHz input, Rise/fall time < 150 ps (20% to 80%), VID > 400 mV or Input Swing = 3.0 V[8]"). Added tJIT parameter values for the Condition "156.25 MHz Sinewave, 12 kHz to 20 MHz offset, input rise/fall time < 150 ps (20% to 80%), Input Swing = 3.0 V [13]" (Maximum value = 0.11 ps). Added Application Information. Updated in new template. Document Number: 001-56312 Rev. *I Page 15 of 16 CY2DL1504 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. 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Document Number: 001-56312 Rev. *I Revised February 1, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16