LT1054/LT1054L
1
1954lfg
BLOCK DIAGRAM
FEATURES DESCRIPTION
Switched-Capacitor Voltage
Converter with Regulator
The LT
®
1054 is a monolithic, bipolar, switched-capacitor
voltage converter and regulator. The LT1054 provides
higher output current than previously available converters
with significantly lower voltage losses. An adaptive switch
driver scheme optimizes efficiency over a wide range of
output currents. Total voltage loss at 100mA output current
is typically 1.1V. This holds true over the full supply voltage
range of 3.5V to 15V. Quiescent current is typically 2.5mA.
The LT1054 also provides regulation, a feature not previ-
ously available in switched-capacitor voltage converters. By
adding an external resistive divider a regulated output can
be obtained. This output will be regulated against changes
in both input voltage and output current. The LT1054 can
also be shut down by grounding the feedback pin. Supply
current in shutdown is less than 100µA.
The internal oscillator of the LT1054 runs at a nominal
frequency of 25kHz. The oscillator pin can be used to ad-
just the switching frequency or to externally synchronize
the LT1054.
The LT1054 is pin compatible with previous converters
such the LTC1044/ICL7660.
LT1054/LT1054 Voltage Loss
APPLICATIONS
■Output Current: 100mA (LT1054)
125mA (LT1054L)
■ Reference and Error Amplifier for Regulation
■ Low Loss: 1.1V at 100mA
■ Operating Range: 3.5V to 15V (LT1054)
3.5V to 7V (LT1054L)
■ External Shutdown
■ External Oscillator Synchronization
■ Can Be Paralleled
■ Pin Compatible with the LTC
®
1044/ICL7660
■ Available in SW16 and SO-8 Packages
■ Voltage Inverter
■ Voltage Regulator
■ Negative Voltage Doubler
■ Positive Voltage Doubler
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
REFERENCE
OSC
DRIVE DRIVE
DRIVE
DRIVE
OSC
CAP–
GND
CAP+
FEEDBACK/
SHUTDOWN
–
+
R
R
*EXTERNAL CAPACITORS
2.5V
6
1
4
3
–VOUT
LT1054 • BD
5
2
8
7
Q
Q
V
REF
CIN*
VIN
COUT*
+
+
OUTPUT CURRENT (mA)
0
VOLTAGE LOSS (V)
1
2
50
1054 TA01•
025 75 100 125
TJ = 125°C
TJ = 25°C
TJ = –55°C
LT1054
LT1054L
3.5V ≤ VIN ≤ 15V (LT1054)
3.5V ≤ VIN ≤ 7V (LT1054L)
CIN = COUT = 100µF
INDICATES GUARANTEED
TEST POINT
LT1054/LT1054L
2
1054lfg
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 2)
LT1054 .................................................................16V
LT1054L .................................................................7V
Input Voltage
Pin 1 ................................................. 0V ≤ VPIN1 ≤ V+
Pin 3 (S Package) ............................. 0V ≤ VPIN3 ≤ V+
Pin 7 .............................................. 0V ≤ VPIN7 ≤ VREF
Pin 13 (S Package) ...................... 0V ≤ VPIN13 ≤ VREF
Operating Junction Temperature Range
LT1054C/LT1054LC .............................. 0°C to 100°C
LT1054I ............................................. –40°C to 100°C
LT1054M ............................................ –55°C to 125°C
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
FB/SHDN
CAP+
GND
CAP–
V+
OSC
VREF
VOUT
N8 PACKAGE
8-LEAD PLASTIC DIP
J8 PACKAGE
8-LEAD CERAMIC DIP
TJMAX = 125°C, θJA = 130°C/W
1
2
3
4
8
7
6
5
TOP VIEW
V+
OSC
VREF
VOUT
FB/SHDN
CAP+
GND
CAP–
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 120°C/W
SEE REGULATION AND CAPACITOR SELECTION SECTIONS
IN THE APPLICATIONS INFORMATION FOR IMPORTANT
INFORMATION ON THE S8 DEVICE
1
2
3
4
5
6
7
8
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC SO
16
15
14
13
12
11
10
9
NC
NC
FB/SHDN
CAP+
GND
CAP–
NC
NC
NC
NC
V+
OSC
VREF
VOUT
NC
NC
TJMAX = 125°C, θJA = 150°C/W
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1054CN8#PBF LT1054CN8#TRPBF LT1054CN8 8-Lead Plastic DIP 0°C to 100°C
LT1054IN8#PBF LT1054IN8#TRPBF LT1054IN8 8-Lead Plastic DIP –40°C to 100°C
LT1054MJ8#PBF LT1054MJ8#TRPBF LT1054MJ8 8-Lead Ceramic DIP –55°C to 125°C
LT1054CS8#PBF LT1054CS8#TRPBF 1054 8-Lead Plastic SO 0°C to 100°C
LT1054LCS8#PBF LT1054LCS8#TRPBF 1054L 8-Lead Plastic SO 0°C to 100°C
LT1054IS8#PBF LT1054IS8#TRPBF 1054I 8-Lead Plastic SO –40°C to 100°C
LT1054CSW#PBF LT1054CSW#TRPBF LT1054CSW 16-Lead Plastic SO 0°C to 100°C
LT1054ISW#PBF LT1054ISW#TRPBF LT1054ISW 16-Lead Plastic SO –40°C to 100°C
LT1054CJ8#PBF OBSOLETE PART LT1054CJ8#TRPBF LT1054CJ8 8-Lead Ceramic DIP 0°C to 100°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Maximum Junction Temperature (Note 3)
LT1054C/LT1054LC ......................................... 125°C
LT1054I ............................................................. 125°C
LT1054M ........................................................... 150°C
Storage Temperature Range
J8, N8 and S8 Packages .................... –55°C to 150°C
S Package ......................................... – 65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
LT1054/LT1054L
3
1954lfg
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The absolute maximum supply voltage rating of 16V is for
unregulated circuits using LT1054. For regulation mode circuits using
LT1054 with VOUT ≤ 15V at Pin 5 (Pin 11 on S package), this rating may be
increased to 20V. The absolute maximum supply voltage for LT1054L is 7V.
Note 3: The devices are guaranteed by design to be functional up to the
absolute maximum junction temperature.
Note 4: For voltage loss tests, the device is connected as a voltage inverter,
with pins 1, 6, and 7 (3, 12, and 13 S package) unconnected. The voltage
losses may be higher in other configurations.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 7)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Current ILOAD = 0mA LT1054: VIN = 3.5V
VIN = 15V
l
l
2.5
3.0
4.0
5.0
mA
mA
LT1054L: VIN = 3.5V
VIN = 7V
l
l
2.5
3.0
4.0
5.0
mA
mA
Supply Voltage Range LT1054
LT1054L
l
l
3.5
3.5
15
7
V
V
Voltage Loss (VIN – |VOUT|) CIN = COUT = 100µF Tantalum (Note 4)
IOUT = 10mA
IOUT = 100mA
IOUT = 125mA (LT1054L)
l
l
l
0.35
1.10
1.35
0.55
1.60
1.75
V
V
V
Output Resistance ∆IOUT = 10mA to 100mA (Note 5) l10 15 Ω
Oscillator Frequency LT1054: 3.5V ≤ VIN ≤ 15V
LT1054L: 3.5V ≤ VIN ≤ 7V
l
l
15
15
25
25
40
35
kHz
kHz
Reference Voltage IREF = 60µA, TJ = 25°C
l
2.35
2.25
2.50 2.65
2.75
V
V
Regulated Voltage VIN = 7V, TJ = 25°C, RL = 500Ω (Note 6) –4.70 –5.00 –5.20 V
Line Regulation LT1054: 7V ≤ VIN ≤ 12V, RL = 500Ω (Note 6) l5 25 mV
Load Regulation VIN = 7V, 100Ω ≤ 500Ω (Note 6) l10 50 mV
Maximum Switch Current 300 mA
Supply Current in Shutdown VPIN1 = 0V l100 200 µA
Note 5: Output resistance is defined as the slope of the curve, (∆VOUT vs
∆IOUT), for output currents of 10mA to 100mA. This represents the linear
portion of the curve. The incremental slope of the curve will be higher at
currents <10mA due to the characteristics of the switch transistors.
Note 6: All regulation specifications are for a device connected as a
positive-to-negative converter/regulator with R1 = 20k, R2 = 102.5k,
C1 = 0.002µF, (C1 = 0.05µF S package) CIN = 10µF tantalum, COUT = 100µF
tantalum.
Note 7: The S8 package uses a different die than the H, J8, N8 and S
packages. The S8 device will meet all the existing data sheet parameters.
See Regulation and Capacitor Selection in the Applications Information
section for differences in application requirements.
LT1054/LT1054L
4
1054lfg
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current in Shutdown Average Input Current Output Voltage Loss
Output Voltage Loss Output Voltage Loss
Shutdown Threshold Supply Current Oscillator Frequency
TEMPERATURE (°C)
–50
SHUTDOWN THRESHOLD (V)
0.4
0.5
0.6
25 75
LT1054 • TPC01
0.3
0.2
–25 0 50 100 125
0.1
0
VPIN1
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (mA)
1
2
3
4
5
IL = 0
510 15
LT1054 • TPC02
TEMPERATURE (°C)
–50–70
15
FREQUENCY (kHz)
25
35
050 75
LT1054 • TPC03
–25 25 100 125
VIN = 15V
VIN = 3.5V
INPUT VOLTAGE (V)
0
0
QUIESCENT CURRENT (µA)
20
40
60
80
120
510 15
LT1054 • TPC04
100
VPIN1 = 0V
OUTPUT CURRENT (mA)
0
0
AVERAGE INPUT CURRENT (mA)
20
60
80
100
140
LT1050 • TPC05
40
120
40 100
20 60 80
INPUT CAPACITANCE (µF)
0
0
VOLTAGE LOSS (V)
0.2
0.6
0.8
1.0
1.4
10 50 70
LT1054 • TPC06
0.4
1.2
40 90 100
20 30 60 80
INVERTER CONFIGURATION
COUT = 100µF TANTALUM
fOSC = 25kHz
IOUT = 100mA
IOUT = 50mA
IOUT = 10mA
OSCILLATOR FREQUENCY (kHz)
1
0
VOLTAGE LOSS (V)
1
2
10 100
LT1054 • TPC07
INVERTER CONFIGURATION
CIN = 10µF TANTALUM
COUT = 100µF TANTALUM
IOUT = 100mA
IOUT = 50mA
IOUT = 10mA
OSCILLATOR FREQUENCY (kHz)
1
0
VOLTAGE LOSS (V)
1
2
10 100
LT1054 • TPC08
INVERTER CONFIGURATION
CIN = 100µF TANTALUM
COUT = 100µF TANTALUM
IOUT = 100mA
IOUT = 50mA
IOUT = 10mA
LT1054/LT1054L
5
1954lfg
TYPICAL PERFORMANCE CHARACTERISTICS
Regulated Output Voltage
Reference Voltage Temperature
Coefficient
TEMPERATURE (°C)
–50
–12.6
–12.4
–12.0
–11.8
–11.6
–5.0
050 75
LT1054 • TPC09
–12.2
–4.9
–4.8
–5.1
–25 25 100 125
TEMPERATURE (°C)
–50
–100
REFERENCE VOLTAGE CHANGE (mV)
–80
–40
–20
0
100
40
050 75
LT1054 • TPC10
–60
60
80
20
–25 25 100 125
VREF AT 0 = 2.500V
PIN FUNCTIONS
FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has
two functions. Pulling Pin 1 below the shutdown threshold
(≈0.45V) puts the device into shutdown. In shutdown the
reference/regulator is turned off and switching stops. The
switches are set such that both CIN and COUT are discharged
through the output load. Quiescent current in shutdown
drops to approximately 100µA (see Typical Performance
Characteristics). Any open-collector gate can be used to
put the LT1054 into shutdown. For normal (unregulated)
operation the device will start back up when the external
gate is shut off. In LT1054 circuits that use the regulation
feature, the external resistor divider can provide enough
pull-down to keep the device in shutdown until the output
capacitor (COUT) has fully discharged. For most applica-
tions where the LT1054 would be run intermittently, this
does not present a problem because the discharge time
of the output capacitor will be short compared to the off-
time of the device. In applications where the device has
to start up before the output capacitor (COUT) has fully
discharged, a restart pulse must be applied to Pin 1 of
the LT1054. Using the circuit of Figure 5, the restart signal
can be either a pulse (tp > 100µs) or a logic high. Diode
coupling the restart signal into Pin 1 will allow the output
voltage to come up and regulate without overshoot. The
resistor divider R3/R4 in Figure 5 should be chosen to
provide a signal level at pin 1 of 0.7V to 1.1V.
Pin 1 is also the inverting input of the LT1054’s error
amplifier and as such can be used to obtain a regulated
output voltage.
CAP+/CAP – (Pin 2/Pin 4): Pin 2, the positive side of the
input capacitor (CIN), is alternately driven between V+
and ground. When driven to V+, Pin 2 sources current
from V+. When driven to ground Pin 2 sinks current to
ground. Pin 4, the negative side of the input capacitor, is
driven alternately between ground and VOUT. When driven
to ground, Pin 4 sinks current to ground. When driven to
VOUT Pin 4 sources current from COUT. In all cases current
flow in the switches is unidirectional as should be expected
using bipolar switches.
VOUT (Pin 5): In addition to being the output pin this pin
is also tied to the substrate of the device. Special care
must be taken in LT1054 circuits to avoid pulling this
pin positive with respect to any of the other pins. Pulling
Pin5 positive with respect to Pin 3 (GND) will forward
bias the substrate diode which will prevent the device from
starting. This condition can occur when the output load
driven by the LT1054 is referred to its positive supply (or
to some other positive voltage). Note that most op amps
present just such a load since their supply currents flow
from their V+ terminals to their V– terminals. To prevent
start-up problems with this type of load an external
LT1054/LT1054L
6
1054lfg
transistor must be added as shown in Figure 1. This will
prevent VOUT (Pin 5) from being pulled above the ground
pin (Pin 3) during start-up. Any small, general purpose
transistor such as 2N2222 or 2N2219 can be used. RX
should be chosen to provide enough base drive to the
external transistor so that it is saturated under nominal
output voltage and maximum output current conditions.
In some cases an N-channel enhancement mode MOSFET
can be used in place of the transistor.
RX≤VOUT
( )
β
IOUT
OSC (Pin 7): Oscillator Pin. This pin can be used to raise
or lower the oscillator frequency or to synchronize the
device to an external clock. Internally Pin 7 is connected
to the oscillator timing capacitor (Ct ≈ 150pF) which is
alternately charged and discharged by current sources of
±7µA so that the duty cycle is ≈50%. The LT1054 oscillator
is designed to run in the frequency band where switch-
ing losses are minimized. However the frequency can be
raised, lowered, or synchronized to an external system
clock if necessary.
The frequency can be lowered by adding an external
capacitor (C1, Figure 2) from Pin 7 to ground. This will
increase the charge and discharge times which lowers the
oscillator frequency. The frequency can be increased by
adding an external capacitor (C2, Figure 2, in the range
of 5pF to 20pF) from Pin 2 to Pin 7. This capacitor will
couple charge into CT at the switch transitions, which will
shorten the charge and discharge time, raising the oscil-
lator frequency. Synchronization can be accomplished
by adding an external resistive pull-up from Pin 7 to the
reference pin (Pin 6). A 20k pull-up is recommended. An
open collector gate or an NPN transistor can then be used
to drive the oscillator pin at the external clock frequency
as shown in
Figure 2. Pulling up Pin 7 to an external volt-
age is not recommended. For circuits that require both
frequency synchronization and regulation, an external
reference can be used as the reference point for the top
of the R1/R2 divider allowing Pin 6 to be used as a pull-
up point for Pin 7.
–
+
LOAD
CIN
COUT
LT1054 • F01
IL
V+
RX
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
IQ
IOUT
+
+
VREF (Pin 6): Reference Output. This pin provides a 2.5V
reference point for use in LT1054-based regulator circuits.
The temperature coefficient of the reference voltage has
been adjusted so that the temperature coefficient of the
regulated output voltage is close to zero. This requires the
reference output to have a positive temperature coefficient
as can be seen in the typical performance curves. This
nonzero drift is necessary to offset a drift term inherent
in the internal reference divider and comparator network
tied to the feedback pin. The overall result of these drift
terms is a regulated output which has a slight positive
temperature coefficient at output voltages below 5V and a
slight negative TC at output voltages above 5V. Reference
output current should be limited, for regulator feedback
networks, to approximately 60µA. The reference pin will
draw ≈100µA when shorted to ground and will not af-
fect the internal reference/regulator, so that this pin can
also be used as a pull-up for LT1054 circuits that require
synchronization.
Figure 1
Figure 2
VIN
COUT
CIN
C2
C1
LT1054 • F02
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
+
+
V+ (Pin 8): Input Supply. The LT1054 alternately charges
CIN to the input voltage when CIN is switched in parallel
with the input supply and then transfers charge to COUT
when CIN is switched in parallel with COUT. Switching oc-
curs at the oscillator frequency. During the time that CIN
PIN FUNCTIONS
LT1054/LT1054L
7
1954lfg
PIN FUNCTIONS
is charging, the peak supply current will be approximately
equal to 2.2 times the output current. During the time that
CIN is delivering charge to COUT the supply current drops
to approximately 0.2 times the output current. An input
supply bypass capacitor will supply part of the peak input
current drawn by the LT1054 and average out the current
drawn from the supply. A minimum input supply bypass
capacitor of 2µF, preferably tantalum or some other low ESR
type is recommended. A larger capacitor may be desirable
in some cases, for example, when the actual input supply
is connected to the LT1054 through long leads, or when
the pulse current drawn by the LT1054 might affect other
circuitry through supply coupling.
APPLICATIONS INFORMATION
Theory of Operation
To understand the theory of operation of the LT1054, a re-
view of a basic switched-capacitor building block is helpful.
In Figure 3 when the switch is in the left position, capaci-
tor C1 will charge to voltage V1. The total charge on C1
will be q1 = C1V1. The switch then moves to the right,
discharging C1 to voltage V2. After this discharge time
the charge on C1 is q2 = C1V2. Note that charge has been
transferred from the source V1 to the output V2. The
amount of charge transferred is:
∆q = q1 – q2 = C1(V1 – V2)
If the switch is cycled f times per second, the charge
transfer per unit time (i.e., current) is:
I = (f)(∆q) = (f)[C1(V1 – V2)]
To obtain an equivalent resistance for the switched-
capacitor network we can rewrite this equation in terms
of voltage and impedance equivalence:
I=V1– V2
1/ fC1 =V1– V2
REQUIV
A new variable REQUIV is defined such that REQUIV = 1/fC1.
Thus the equivalent circuit for the switched-capacitor
network is as shown in Figure 4. The LT1054 has the same
switching action as the basic switched-capacitor building
block. Even though this simplification doesn’t include finite
switch on-resistance and output voltage ripple, it provides
an intuitive feel for how the device works.
These simplified circuits explain voltage loss as a function
of frequency (see Typical Performance Characteristics).
As frequency is decreased, the output impedance will
eventually be dominated by the 1/fC1 term and voltage
losses will rise.
Note that losses also rise as frequency increases. This is
caused by internal switching losses which occur due to
some finite charge being lost on each switching cycle. This
charge loss per-unit-cycle, when multiplied by the switching
frequency, becomes a current loss. At high frequency this
loss becomes significant and voltage losses again rise.
The oscillator of the LT1054 is designed to run in the
frequency band where voltage losses are at a minimum.
Regulation
T
he error amplifier of the LT1054 servos the drive to the
PNP switch to control the voltage across the input capaci-
tor (CIN) which in turn will determine the output voltage.
Using the reference and error amplifier of the LT1054,
an external resistive divider is all that is needed to set
the regulated output voltage. Figure 5 shows the basic
regulator configuration and the formula for calculating
the appropriate resistor values. R1 should be chosen to
f
C1 C2 RL
V2
LT1054 • F03
V1
Figure 3. Switched-Capacitor Building Block
Figure 3. Switched-Capacitor Equivalent Circuit
C2 RL
R
EQUIV
REQUIV =
V2
LT1054 • F04
V1
1
fC1
LT1054/LT1054L
8
1054lfg
APPLICATIONS INFORMATION
R4
RESTART SHUTDOWN C1
R2
CIN
10µF
TANTALUM
COUT
100µF
TANTALUM
VOUT
LT1054 • F05
VIN
R1
2.2µF
R3
R2
R1 = ≈+ 1
WHERE VREF = 2.5V NOMINAL
*CHOOSE THE CLOSEST 1% VALUE
FOR EXAMPLE: TO GET VOUT = –5V REFERRED TO THE GROUND
PIN OF THE LT1054, CHOOSE R1 = 20k, THEN
|VOUT|
)
)
VREF
2– 40mV
R2 = 20k = 102.6k*
+ 1
|–5V|
)
)
2.5V
2– 40mV
)
)
+ 1
|VOUT|
1.21V
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
+
+
+
be 20k or greater because the reference output current
is limited to ≈100µA. R2 should be chosen to be in the
range of 100k to 300k. For optimum results the ratio of
CIN/COUT is recommended to be 1/10. C1, required for
good load regulation at light load currents, should be
0.002µF for all output voltages.
A new die layout was required to fit into the physical
dimensions of the S8 package. Although the new die
of the LT1054CS8 will meet all the specifications of the
existing LT1054 data sheet, subtle differences in the
layout of the new die require consideration in some ap-
plication circuits. In regulating mode circuits using the
1054CS8 the nominal values of the capacitors, CIN and
COUT, must be approximately equal for proper operation
at elevated junction temperatures. This is different from
the earlier part. Mismatches within normal production
tolerances for the capacitors are acceptable. Making the
nominal capacitor values equal will ensure proper opera-
tion at elevated junction temperatures at the cost of a
small degradation in the transient response of regulator
circuits. For unregulated circuits the values of CIN and
COUT are normally equal for all packages. For S8 applica-
tions assistance in unusual applications circuits, please
consult the factory.
It can be seen from the circuit block diagram that the
maximum regulated output voltage is limited by the supply
voltage. For the basic configuration, |VOUT| referred to the
ground pin of the LT1054 must be less than the total of the
supply voltage minus the voltage loss due to the switches.
The voltage loss versus output current due to the switches
can be found in Typical Performance Characteristics. Other
configurations such as the negative doubler can provide
higher output voltages at reduced output currents (see
Typical Applications).
Capacitor Selection
For unregulated circuits the nominal values of CIN and COUT
should be equal. For regulated circuits see the section on
Regulation. While the exact values of CIN and COUT are
noncritical, good quality, low ESR capacitors such as solid
tantalum are necessary to minimize voltage losses at high
currents. For CIN the effect of the ESR of the capacitor will
be multiplied by four due to the fact that switch currents
are approximately two times higher than output current and
losses will occur on both the charge and discharge cycle.
This means that using a capacitor with 1Ω of ESR for CIN
will have the same effect as increasing the output imped-
ance of the LT1054 by 4Ω. This represents a significant
increase in the voltage losses. For COUT the affect of ESR is
less dramatic. COUT is alternately charged and discharged
at a current approximately equal to the output current and
the ESR of the capacitor will cause a step function to oc-
cur in the output ripple at the switch transitions. This step
function will degrade the output regulation for changes
in output load current and should be avoided. Realizing
that large value tantalum capacitors can be expensive, a
technique that can be used is to parallel a smaller tantalum
capacitor with a large aluminum electrolytic capacitor to
gain both low ESR and reasonable cost. Where physical
size is a concern some of the newer chip type surface
mount tantalum capacitors can be used. These capacitors
are normally rated at working voltages in the 10V to 20V
range and exhibit very low ESR (in the range of 0.1Ω).
Output Ripple
The peak-to-peak output ripple is determined by the value
of the output capacitor and the output current. Peak-to-
peak output ripple may be approximated by the formula:
dV =IOUT
2fCOUT
Figure 5
LT1054/LT1054L
9
1954lfg
APPLICATIONS INFORMATION
where dV = peak-to-peak ripple and f = oscillator frequency.
For output capacitors with significant ESR a second term
must be added to account for the voltage step at the switch
transitions. This step is approximately equal to:
(2IOUT)(ESR of COUT)
Power Dissipation
The power dissipation of any LT1054 circuit must be
limited such that the junction temperature of the device
does not exceed the maximum junction temperature rat-
ings. The total power dissipation must be calculated from
two components, the power loss due to voltage drops
in the switches and the power loss due to drive current
losses. The total power dissipated by the LT1054 can be
calculated from:
P ≈ (VIN – |VOUT|)(IOUT) + (VIN)(IOUT)(0.2)
where both VIN and VOUT are referred to the ground pin
(Pin3) of the LT1054. For LT1054 regulator circuits, the
power dissipation will be equivalent to that of a linear
regulator. Due to the limited power handling capability of
the LT1054 packages, the user will have to limit output
current requirements or take steps to dissipate some power
external to the LT1054 for large input/output differentials.
This can be accomplished by placing a resistor in series
with CIN as shown in Figure 6. A portion of the input
voltage will then be dropped across this resistor without
affecting the output regulation. Because switch current is
approximately 2.2 times the output current and the resistor
will cause a voltage drop when CIN is both charging and
discharging, the resistor should be chosen as:
RX = VX/(4.4 IOUT)
where:
VX ≈ VIN – [(LT1054 Voltage Loss)(1.3) + |VOUT|]
and IOUT = maximum required output current. The factor
of 1.3 will allow some operating margin for the LT1054.
For example: assume a 12V to –5V converter at 100mA
output current. First calculate the power dissipation without
an external resistor:
P = (12V – |–5V|)(100mA) + (12V)(100mA)(0.2)
P = 700mW + 240mW = 940mW
At θJA of 130°C/W for a commercial plastic device this
would cause a junction temperature rise of 122°C so that
the device would exceed the maximum junction tempera-
ture at an ambient temperature of 25°C. Now calculate the
power dissipation with an external resistor (RX). First find
how much voltage can be dropped across RX. The maxi-
mum voltage loss of the LT1054 in the standard regulator
configuration at 100mA output current is 1.6V, so:
VX = 12V – [(1.6V)(1.3) + |–5V|] = 4.9V and
RX = 4.9V/(4.4)(100mA) = 11Ω
This resistor will reduce the power dissipated by the
LT1054 by (4.9V)(100mA) = 490mW. The total power dis-
sipated by the LT1054 would then be (940mW – 490mW)
= 450mW. The junction temperature rise would now be
only 58°C. Although commercial devices are guaranteed
to be functional up to a junction temperature of 125°C, the
specifications are only guaranteed up to a junction tem-
perature of 100°C, so ideally you should limit the junction
temperature to 100°C. For the above example this would
mean limiting the ambient temperature to 42°C. Other
steps can be taken to allow higher ambient temperatures.
The thermal resistance numbers for the LT1054 packages
represent worst-case numbers with no heat sinking and
still air. Small clip-on type heat sinks can be used to lower
the thermal resistance of the LT1054 package. In some
systems there may be some available airflow which will
help to lower the thermal resistance. Wide PC board traces
from the LT1054 leads can also help to remove heat from
the device. This is especially true for plastic packages.
C1
R2
CIN
COUT
VOUT
LT1054 • F06
VIN
R1
RX
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
+
+
Figure 6
LT1054/LT1054L
10
1054lfg
TYPICAL APPLICATIONS
Basic Voltage Inverter
Negative Voltage Doubler
Basic Voltage Inverter/Regulator
Positive Doubler
100µF
VIN
–VOUT
LT1054 • TAO2
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
2µF
100µF
+
+
+
0.002µF
R2
10µF
100µF
REFER TO FIGURE 5
2µF
VOUT
LT1054 • TA03
VIN
R1
R2
R1 = =+ 1
|VOUT|
)
)
VREF
2– 40mV
)
)
+ 1 ,
|VOUT|
1.21V
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
+
+
+
2µF 100µF
VIN = –3.5V TO –15V
VOUT = 2VIN + (LT1054 VOLTAGE LOSS) + (QX SATURATION VOLTAGE)
*SEE FIGURE 3
VIN
VIN
VOUT
LT1054 • TAO4
RX*
+
–
100µF
+
+
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
QX*
1N4001
VIN = 3.5V TO 15V
VOUT ≈ 2VIN – (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
V
IN
3.5V TO 15V
LT1054 • TAO5
1N4001
VOUT
50mA
+
–100µF 2µF
10µF
++ +
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
100mA Regulating Negative Doubler
1N4002
HP5082-2810
V
IN
3.5 TO 15V
20k
1N4002
0.002µF
LT1054 • TAO6
2.2µF
R1
40k
VOUT
SET
PIN 2
LT1054 #1
–VOUT
IOUT ≅ 100mA MAX
R2
500k
1N4002
1N4002
1N4002
, REFER TO FIGURE 5
VIN = 3.5 TO 15V
VOUT MAX ≈ –2VIN + [1054 VOLTAGE LOSS + 2(VDIODE)]
R2
R1 = =+ 1
|VOUT|
)
)
VREF
2– 40mV
)
)
+ 1
|VOUT|
1.21V
10µF 10µF
100µF
+
+
+
10µF
+
10µF
10µF
+
+
+
10µF
+
LT1054 #1
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
LT1054 #2
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
LT1054/LT1054L
11
1954lfg
TYPICAL APPLICATIONS
5V to ±12V Converter
Bipolar Supply Doubler
Strain Gauge Bridge Signal Conditioner
VIN
3.5V TO 15V
–VOUT
LT1054 • TAO7
+VOUT
+
–
+
–
= 1N4001
VIN = 3.5V TO 15V
+VOUT ≈ 2VIN – (VL + 2VDIODE)
–VOUT ≈ –2VIN + (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
100µF 10µF
10µF
10µF
100µF
100µF
++
+
+
+
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
20k
1N9141N914
V
IN
= 5V
TO PIN 4
LT1054 #1
VOUT ≈ –12V
IOUT = 25mA
VOUT ≈ 12V
IOUT = 25mA
LT1054 • TAO8
1k
2N2219
10µF
100µF
10µF
10µF
100µF
5µF
100µF
5µF
+
+
+
+
+
+
+
+
LT1054 #2
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
LT1054 #1
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
1µF
5V
1
2
3
8
200k
3k
100µF
TANTALUM
LT1054 • TAO9
0.022µF
–
+
2N2222 A = 125 FOR 0V TO 3V OUT FROM FULL-SCALE
BRIDGE OUTPUT OF 24mV
100k
100k
10k
ZERO
TRIM
5k
GAIN
TRIM
10k
10k
5V
40Ω
301k 1M
A1
1/2 LT1013
5k 6
5
4
7
10k
2N2907
INPUT TTL
OR CMOS
LOW FOR ON
350Ω
–
+
A2
1/2 LT1013
10µF
+
+
10µF
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
LT1054/LT1054L
12
1054lfg
TYPICAL APPLICATIONS
3.5V to 5V Regulator
Regulating 200mA, 12V to –5V Converter
Digitally Programmable Negative Supply
5µF
100µF
20k 1N914
R1
20k
1N914
VIN = 3.5V TO 5.5V
VOUT = 5V
IOUT(MAX) = 50mA
1N914
1N5817
V
IN
3.5V TO 5.5V
LT1054 • TA10
LTC1044
1
2
3
4
8
7
6
5
1µF
1µF
0.002µF R2
125k 3k
1N914
R2
125k
2N2219
VOUT = 5V
+
–
10µF
+
+
+
+
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
0.002µF
HP5082-2810
VOUT = –5V
IOUT = 0mA to 200mA
12V
R1
39.2k
R2
200k
20k
10Ω
1/2W
LT1054 • TA11
10Ω
1/2W
10µF
5µF
200µF
10µF
+
+
+
+
LT1054 #1
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
LT1054 #2
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
REFER TO FIGURE 5
R2
R1 = =+ 1
|VOUT|
)
)
VREF
2– 40mV
)
)
+ 1 ,
|VOUT|
1.21V
20k
VOUT = –VIN (PROGRAMMED)
20k
15V
LT1004-2.5
2.5V
LT1054 • TA12
AD558
16
11
14
DIGITAL
INPUT
13 12
10µF
5µF
+
100µF
+
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
LT1054/LT1054L
13
1954lfg
PACKAGE DESCRIPTION
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0 – 15
.005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
1 2 34
8 7 6 5
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 .005
(3.302 0.127)
.020
(0.508)
MIN
.018 .003
(0.457 0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
1 2 34
87 65
.255 .015*
(6.477 0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
LT1054/LT1054L
14
1054lfg
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S16 (WIDE) 0502
NOTE 3
.398 – .413
(10.109 – 10.490)
NOTE 4
16 15 14 13 12 11 10 9
1
N
2 3 4567 8
N/2
.394 – .419
(10.007 – 10.643)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0 – 8 TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.005
(0.127)
RAD MIN
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
¥ 45∞
.010 – .029
(0.254 – 0.737)
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.420
MIN
.325 .005
RECOMMENDED SOLDER PAD LAYOUT
.045 .005
N
1 2 3 N/2
.050 BSC
.030 .005
TYP
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
LT1054/LT1054L
15
1954lfg
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
F 12/10 The LTC1054MJ8 is now available. Changes reflected throughout the data sheet 1 to 16
G 6/11 Correct error to part number from LTC7660 to ICL7660 1
(Revision history begins at Rev F)
LT1054/LT1054L
16
1054lfg
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0611 REV G • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATIONS
Negative Doubler with Regulator
Positive Doubler with Regulation
0.03µF
V
IN
= 5V
50k
1N5817
1N5817
LT1054 • TA13
–
+
10k
10k
10k
5.5k
2.5k
0.1µF
5V
LT1006
100µF
VOUT
8V
50mA
2µF
10µF
+
+
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
2µF
VIN
3.5V TO 15V
100µF R2
1M
1N4001 1N4001
LT1054 • TA14
100µF
0.002µF
–V
OUT
VIN = 3.5V TO 15V
VOUT(MAX) ≈ –2VIN + (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
, REFER TO FIGURE 5
R2
R1 = =+ 1
|VOUT|
)
)
VREF
2– 40mV
)
)
+ 1
|VOUT|
1.21V
10µF
+
+
+
+
10µF
+
LT1054
FB/SHDN
CAP+
GND
CAP –
V+
OSC
VREF
VOUT
R1, 20k
PART NUMBER DESCRIPTION COMMENTS
LT C
®
1144 Switched-Capacitor Wide Input Range Voltage Converter with
Shutdown
Wide Input Voltage Range: 2V to 18V, ISD < 8µA, SO8
LTC1514/LTC1515 Step-Up/Step-Down Switched-Capacitor DC/DC Converters VIN: 2V to 10V, VOUT: 3.3V to 5V, IQ = 60µA, SO8
LT1611 150mA Output, 1.4mHz Micropower Inverting Switching Regulator VIN: 0.9V to 10V, VOUT: ±34V ThinSOT™
LT1614 250mA Output, 600kHz Micropower Inverting Switching Regulator VIN: 0.9V to 6V, VOUT: ±30V, IQ = 1mA, MS8, SO8
LTC1911 250mA, 1.5MHz Inductorless Step-Down DC/DC Converter VIN: 2.7V to 5.5V, VOUT: 1.5V/1.8V, IQ = 180µA, MS8
LTC3250/LTC3250-1.2/
LTC3250-1.5
Inductorless Step-Down DC/DC Converter VIN: 3.1V to 5.5V, VOUT: 1.2V, 1.5V, IQ = 35µA, ThinSOT
LTC3251 500mA Spread Spectrum Inductorless Step-Down DC/DC Converter VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, 1.2V, 1.5V, IQ = 9µA,
MS10E
LTC3252 Dual 250mA, Spread Spectrum Inductorless Step-Down
DC/DC Converter
VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, IQ = 50µA, DFN12
THE TYPICAL APPLICATIONS CIRCUITS WERE VERIFIED USING THE STANDARD LT1054. FOR S8 APPLICATIONS
ASSISTANCE IN ANY OF THE UNUSUAL APPLICATIONS CIRCUITS PLEASE CONSULT THE FACTORY