3 MHz, 600 mA, Low Quiescent Current
Buck with 300 mA LDO Regulator
ADP2140
Rev. 0
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FEATURES
Input voltage range: 2.3 V to 5.5 V
LDO input (VIN2) 1.65 V to 5.5 V
Buck output voltage range: 1.0 V to 3.3 V
LDO output voltage range: 0.8 V to 3.3 V
Buck output current: 600 mA
LDO output current: 300 mA
LDO quiescent current: 22 μA with zero load
Buck quiescent current: 20 μA in PSM mode
Low shutdown current: <0.3 μA
Low LDO dropout 110 mV @ 300 mA load
High LDO PSRR
65 dB @ 10 kHz at VOUT2 = 1.2 V
55 dB @ 100 kHz at VOUT2 = 1.2 V
Low noise LDO: 40 μV rms at VOUT2 = 1.2 V
Initial accuracy: ±1%
Current-limit and thermal overload protection
Power-good indicator
Optional enable sequencing
10-lead 0.75 mm × 3 mm × 3 mm LFCSP package
APPLICATIONS
Mobile phones
Personal media players
Digital camera and audio devices
Portable and battery-powered equipment
GENERAL DESCRIPTION
The ADP2140 includes a high efficiency, low quiescent 600 mA
stepdown dc-to-dc converter and a 300 mA LDO packaged in a
small 10-lead 3 mm × 3 mm LFCSP. The total solution requires
only four tiny external components.
The buck regulator uses a proprietary high speed current-mode,
constant frequency, pulse-width modulation (PWM) control
scheme for excellent stability and transient response. To ensure
the longest battery life in portable applications, the ADP2140 has
a power saving variable frequency mode to reduce switching fre-
quency under light loads.
The LDO is a low quiescent current, low dropout linear regulator
designed to operate in a split supply mode with VIN2 as low as
1.65 V. The low input voltage minimum allows the LDO to be
powered from the output of the buck regulator increasing effi-
ciency and reducing power dissipation. The ADP2140 runs from
input voltages of 2.3 V to 5.5 V allowing single Li+/Li− polymer
TYPICAL APPLICATION CIRCUITS
VIN1 PGND
PG SW
EN1 AGND
EN2
PG
EN1
EN2 FB
VOUT2
10
9
8
7
6
VIN2
1
2
3
4
5
ADP2140
100k
+
C
IN
10µF
+
C
OUT2
1µF
+C
OUT
10µF
V
IN1
= 3.6
V
V
OUT2
= 1. 8V
1µH V
OUT
= 1.2V
07932-001
Figure 1. ADP2140 with LDO Connected to VIN1
VIN1 PGND
PG SW
EN1 AGND
EN2
PG
EN1
EN2 FB
VOUT2
10
9
8
7
6
VIN2
1
2
3
4
5
ADP2140
100k
+
C
IN
10µF
+
C
OUT2
1µF
+C
OUT
10µF
V
IN1
= 3.3
V
V
OUT2
= 1. 2V
1µH V
OUT
= 1.8V
07932-002
Figure 2. ADP2140 with LDO Connected to Buck Output
cell, multiple alkaline/NiMH cell, PCMCIA, and other standard
power sources.
ADP2140 includes a power-good pin, soft start, and internal
compensation. Numerous power sequencing options are user-
selectable through two enable inputs. In autosequencing mode,
the highest voltage output enables on the rising edge of EN1.
During logic controlled shutdown, the input disconnects from
the output and draws less than 300 nA from the input source.
Other key features include: undervoltage lockout to prevent deep
battery discharge, soft start to prevent input current overshoot
at startup, and both short-circuit protection and thermal overload
protection circuits to prevent damage in adverse conditions.
When the ADP2140 is used with two 0603 capacitors, one 0402
capacitor, one 0402 resistor, and one 0805 chip inductor, the total
solution size is approximately 90 mm2 resulting in the smallest foot-
print solution to meet a variety of portable applications.
ADP2140
Rev. 0 | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuits ............................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Recommended Specifications: Capacitors and Inductor ........ 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Buck Output .................................................................................. 7
LDO Output ................................................................................ 14
Theory of Operation ...................................................................... 19
Buck Section ................................................................................ 19
Control Scheme .......................................................................... 19
PWM Operation ......................................................................... 19
PSM Operation ........................................................................... 19
Pulse Skipping Threshold .......................................................... 19
Selected Features ............................................................................. 20
Short-Circuit Protection ............................................................ 20
Undervoltage Lockout ............................................................... 20
Thermal Protection .................................................................... 20
Soft Start ...................................................................................... 20
Current Limit .............................................................................. 20
Power-Good Pin ......................................................................... 20
LDO Section ............................................................................... 20
Applications Information .............................................................. 21
Power Sequencing ...................................................................... 21
Power-Good Function ............................................................... 24
External Component Selection ................................................ 24
Selecting the Inductor ................................................................ 24
Output Capacitor ........................................................................ 24
Input Capacitor ........................................................................... 24
Efficiency ..................................................................................... 25
Recommended Buck External Components .......................... 25
LDO Capacitor Selection .......................................................... 26
LDO as a Postregulator to Reduce Buck Output Noise ........ 26
Thermal Considerations ................................................................ 28
PCB Layout Considerations ...................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
6/10—Revision 0: Initial Version
ADP2140
Rev. 0 | Page 3 of 32
SPECIFICATIONS
VIN1 = 3.6 V, VIN2 = VOUT2 + 0.3 V or 1.65 V, whichever is greater; 5 V EN1 = EN2 = VIN1; IOUT = 200 mA, IOUT2 = 10 mA, CIN = 10 F,
COUT = 10 µF, COUT2 = 1 µF, LOUT = 1 H; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
BUCK SECTION
Input Voltage Range VIN1 2.3 5.5 V
Buck Output Accuracy VOUT I
OUT = 10 mA −1.5 +1.5 %
V
IN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V, IOUT = 1 mA to 600 mA −2.5 +2.5 %
Transient Load Regulation VTR-LOAD V
OUT = 1.8 V
Load = 50 mA to 250 mA, rise/fall time = 200 ns 75 mV
Load = 200 mA to 600 mA, rise/fall time = 200 ns 75 mV
Transient Line Regulation VTR-LINE Line transient = 4 V to 5 V, 4 s rise time
V
OUT = 1.0 V 40 mV
V
OUT = 1.8 V 25 mV
V
OUT = 3.3 V 25 mV
PWM To PSM Threshold VIN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V 100 mA
Output Current IOUT 600 mA
Current Limit ILIM V
IN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V 1100 1300 mA
Switch On Resistance
PFET RPFET V
IN1 = 2.3 V to 5.5 V 250 mΩ
NFET RNFET V
IN1 = 2.3 V to 5.5 V 250 mΩ
Switch Leakage Current ILEAK-SW EN1 = GND, VIN1 = 5.5 V, and SW = 0 V −1 A
Quiescent Current IQ No load, device not switching 20 30 A
Minimum On Time ON-TIMEMIN 70 ns
Oscillator Frequency FREQ 2.55 3.0 3.15 MHz
Frequency Foldback Threshold VFOLD Output voltage where fSW ≤ 50% of nominal frequency 50 %
Start-Up Time1 t
START-UP V
OUT = 1.8 V, 600 mA load 70 µs
Soft Start Time2 SSTIME V
OUT = 1.8 V, 600 mA load 150 s
LDO SECTION
Input Voltage Range VIN2 1.65 5.5 V
LDO Output Accuracy VOUT2 I
OUT2 = 10 mA, TJ = 25°C −1 +1 %
1 mA < IOUT2 < 300 mA, VIN2 = (VOUT2 + 0.3 V) to 5.5 V, TJ
= 25°C
−1.5 +1.5 %
1 mA < IOUT2 < 300 mA, VIN2 = (VOUT2 + 0.3 V) to 5.5 V −3 +3 %
Line Regulation
V
OUT2
/V
IN2
VIN2 = (VOUT2 + 0.3 V) to 5.5 V, IOUT2 = 10 mA −0.05 +0.05 %/V
Load Regulation3
V
OUT2
/I
OUT2
IOUT2 = 1 mA to 300 mA 0.001 0.005 %/mA
Dropout Voltage4 V
DROPOUT I
OUT2 = 10 mA, VOUT2 = 1.8 V 4 7 mV
I
OUT2 = 300 mA, VOUT2 = 1.8 V 110 200 mV
Ground Current IAGND No load, buck disabled 22 35 A
I
OUT2 = 10 mA 65 90 A
I
OUT2 = 300 mA 150 220 A
Power Supply Rejection Ratio PSRR VIN2 = VOUT2 + 1 V, VIN1 = 5 V, IOUT2 = 10 mA
PSRR on VIN2 10 kHz, VOUT2 = 1.2 V, 1.8 V, 3.3 V 65 dB
100 kHz, VOUT2 = 3.3 V 53 dB
100 kHz, VOUT2 = 1.8 V 54 dB
100 kHz, VOUT2 = 1.2 V 55 dB
ADP2140
Rev. 0 | Page 4 of 32
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Output Noise OUTNOISE V
IN2 = VIN1 = 5 V, IOUT2 = 10 mA
10 Hz to 100 kHz, VOUT2 = 0.8 V 29 µV rms
10 Hz to 100 kHz, VOUT2 = 1.2 V 40 µV rms
10 Hz to 100 kHz, VOUT2 = 1.8 V 50 µV rms
10 Hz to 100 kHz, VOUT2 = 2.5 V 66 µV rms
10 Hz to 100 kHz, VOUT2 = 3.3 V 88 µV rms
Current Limit ILIM T
J = 25°C 360 500 760 mA
Input Leakage Current ILEAK-LDO EN2 = GND, VIN2 = 5.5 V and VOUT2 = 0 V 1 A
Start-Up Time1 t
START-UP V
OUT2 = 3.3 V, 300 mA load 70 µs
Soft Start Time2 SSTIME V
OUT2 = 3.3 V, 300 mA load 130 s
ADDITIONAL FUNCTIONS
Undervoltage Lockout UVLO
Input Voltage Rising UVLORISE 2.23 2.3 V
Input Voltage Falling UVLOFALL 2.05 2.16 V
EN Input
EN1, EN2 Input Logic High VIH 2.3 V VIN1 ≤ 5.5 V 1.0 V
EN1, EN2 Input Logic Low VIL 2.3 V VIN1 ≤ 5.5 V 0.27 V
EN1, EN2 Input Leakage IEN-LKG EN1, EN2 = VIN1 or GND 0.05 µA
EN1, EN2 = VIN1 or GND 1 µA
Shutdown Current ISHUT V
IN1 = 5.5 V, EN1, EN2 = GND, TJ = −40°C to +85°C 0.3 1.2 A
Thermal Shutdown
Threshold TSSD T
J rising 150 °C
Hysteresis TSSD-HYS 20 °C
Power Good
Rising Threshold PGRISE 92 %VOUT
Falling Threshold PGFALL 86 %VOUT
Power-Good Hysteresis PGHYS 6 %VOUT
Output Low VOL I
SINK = 4 mA 0.2 V
Leakage Current IOH Power-good pin pull-up voltage = 5.5 V 1 A
Buck to LDO Delay tDELAY PWM mode only 5 ms
Power-Good Delay tRESET PWM mode only 5 ms
1 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 10% of the VOUTx nominal value.
2 Soft start time is defined as the time between VOUTx being at 10% to VOUTx being at 90% of the VOUTx nominal value.
3 Based on an endpoint calculation using 1 mA and 300 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
RECOMMENDED SPECIFICATIONS: CAPACITORS AND INDUCTOR
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 TA = −40°C to +125°C
Buck CMIN 7.5 10 µF
LDO CMIN 0.7 1.0 µF
CAPACITOR ESR TA = −40°C to +125°C
Buck RESR 0.001 0.01
LDO RESR 0.001 1
MINIMUM INDUCTOR INDMIN 0.7 1 H
1 The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.
ADP2140
Rev. 0 | Page 5 of 32
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN1, VIN2 to PGND, AGND −0.3 V to +6.5 V
VOUT2 to PGND, AGND −0.3 V to VIN2
SW to PGND, AGND −0.3 V to VIN1
FB to PGND, AGND −0.3 V to +6.5 V
PG to PGND, AGND −0.3 V to +6.5 V
EN1, EN2 to PGND, AGND −0.3 V to +6.5 V
Storage Temperature Range −65°C to +150°C
Operating Ambient Temperature Range −40°C to +85°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in com-
bination. The ADP2140 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
packageJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. Refer to JESD 51-7 for detailed information on the board
construction.
For more information, see AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path, as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) using the
formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Ψ
JB Unit
10-Lead 3 mm × 3 mm LFCSP 35.3 16.9 °C/W
ESD CAUTION
ADP2140
Rev. 0 | Page 6 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN1
PG
EN1
EN2
VOUT2
10
9
8
7
6
PGND
SW
AGND
FB
VIN2
1
2
3
4
5
ADP2140
TOP VIEW
(No t to Scale )
NOTES
1. THE EXPO SED PAD ON THE BOT TOM OF THE L FCSP P ACKAG E ENHANCES
THERM AL PERFO RMANCE AND IS ELECT RICALLY CO NNECTED TO GROUND
INSIDE T HE PACKAGE . IT I S RE COMME NDE D T HAT T HE EXPO S ED PAD BE
CONNECTED T O T HE GRO UND PLANE O N THE CI RCUIT BOARD.
07932-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin Mnemonic Description
1 PGND Power Ground.
2 SW Connection from Power MOSFETs to Inductor.
3 AGND Analog Ground.
4 FB Feedback from Buck Output.
5 VIN2 LDO Input Voltage.
6 VOUT2 LDO Output Voltage.
7 EN2 Logic 1 to Enable LDO or No Connect for Autosequencing.
8 EN1 Logic 1 to Enable Buck or Initiate Sequencing. This is a dual function pin and the state of EN2 determines
which function is operational.
9 PG Power Good. Open-drain output. PG is held low until both output voltages (which includes the external
inductor and capacitor sensed by the FB pin) rise above 92% of nominal value. PG is held high until both
outputs fall below 85% of nominal value.
10 VIN1 Analog Power Input.
EP Exposed Pad. The exposed pad on the bottom of the LFCSP package enhances thermal performance and is
electrically connected to ground inside the package. It is recommended that the exposed pad be connected
to the ground plane on the circuit board.
ADP2140
Rev. 0 | Page 7 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
BUCK OUTPUT
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
30
0
5
10
15
20
25
2.3 2.8 3.3 3.8 4.3 4.8 5.3
QUI E S CE NT CURRENT A)
INPUT VOLTAGE (V)
–40°C
–5°C
+25°C
+85°C
+125°C
07932-004
Figure 4. Quiescent Supply Current vs. Input Voltage, Different Temperatures
3.1
2.5
2.6
2.7
2.8
2.9
3.0
2.3 2.8 3.3 3.8 4.3 4.8 5.3
FREQUENCY ( M Hz )
INPUT VOLTAGE (V)
–40°C
–5°C
+25°C
+85°C
+125°C
07932-005
Figure 5. Switching Frequency vs. Input Voltage, Different Temperatures
3.10
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
–60 –40 –20 0 20 40 60 80 100 120 140
FREQUENCY ( M Hz )
TEMPERAT URE ( °C)
5.5V
4.6V
3.1V
2.3V
07932-006
Figure 6. Switching Frequency vs. Temperature, Different Input Voltages
1.82
1.76
1.77
1.78
1.79
1.80
1.81
–40 1258525–5
OUTPUT VOLTAGE (V)
JUNCTI ON TE M P ERATURE ( °C)
LO AD CURRE NT = 1mA
LO AD CURRE NT = 10mA
LO AD CURRE NT = 50mA
LO AD CURRE NT = 100mA
LO AD CURRE NT = 300mA
LO AD CURRE NT = 600mA
07932-007
Figure 7. Output Voltage vs. Temperature, VIN1 = 2.3 V, Different Loads
1200
700
750
800
850
900
950
1000
1050
1100
1150
–60 –40 –20 0 20 40 60 80 100 120 140
CURRENT L IMIT ( mA)
JUNCTI ON T EMPERAT URE ( °C)
2.3V
3.0V
4.0V
5.0V
5.5V
07932-008
Figure 8. Current Limit vs. Temperature, Different Input Voltages
140
0
20
40
60
80
100
120
3.50 5.505.255.004.754.504.254.003.75
CURRENT ( mA)
INPUT VOLTAGE (V)
–40°C
–5°C
+25°C
+85°C
+125°C
07932-009
Figure 9. PSM to PWM Mode Transition vs. Input Voltage, Different
Temperatures
ADP2140
Rev. 0 | Page 8 of 32
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
1.82
1.81
1.80
1.79
1.78
1.77
1.762.3 5.55.14.74.33.93.53.12.7
OUTPUT VOLTAGE (V)
INPUT V O LTAG E ( V)
LO AD CURRENT = 1mA
LO AD CURRENT = 10mA
LO AD CURRENT = 50mA
LO AD CURRE NT = 100mA
LO AD CURRE NT = 300mA
LO AD CURRE NT = 600mA
07932-010
Figure 10. Line Regulation, VOUT = 1.8 V, Different Loads
1.82
1.81
1.80
1.79
1.78
1.77
1.76 1 10 100 1000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
07932-011
Figure 11. Load Regulation, VOUT = 1.8 V, VIN1 = 2.3 V
1.22
1.21
1.20
1.19
1.18
1.17 1 10 100 1000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
07932-012
Figure 12. Load Regulation, VOUT = 1.2 V, VIN1 = 2.3 V
3.350
3.325
3.300
3.275
3.250 1 10 100 1000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
07932-013
Figure 13. Load Regulation, VOUT = 3.3 V
100
90
80
70
60
50
40
30
20
10
01 10 100 1000
EFFICIENCY (%)
LO AD CURRENT (mA)
2.5V
3.0V
4.0V
5.0V
5.5V
07932-014
Figure 14. Efficiency vs. Load Current, VOUT = 1.8 V, Different Input Voltages
100
90
80
70
60
50
40
30
20
10
01 10 100 1000
EFFICIENCY (%)
LO AD CURRENT (mA)
–40°C
–5°C
+25°C
+85°C
+125°C
07932-015
Figure 15. Efficiency vs. Load Current, VOUT = 1.8 V, Different Temperatures
ADP2140
Rev. 0 | Page 9 of 32
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 μF, TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
01 10 100 1000
EFFICIENCY (%)
LO AD CURRENT (mA)
2.5V
3.0V
4.0V
5.0V
5.5V
07932-016
Figure 16. Efficiency vs. Load Current, VOUT = 1.2 V, Different Input Voltages
100
90
80
70
60
50
40
30
20
10
01 10 100 1000
EFFICIENCY (%)
LO AD CURRENT (mA)
–40°C
–5°C
+25°C
+85°C
+125°C
07932-017
Figure 17. Efficiency vs. Load Current, VOUT = 1.2 V, Different Temperatures
CH1 1.00V CH2 50.0mV M20.0µs A CH1 4.68V
T 11.60%CH3 5.00V
1
2
3
T
INPUT VOLTAGE
OUTPUT VOLTAGE
SW ITCH NO DE
07932-020
Figure 18. Line Transient, VOUT = 1.8 V, Power Save Mode, 50 mA,
VIN1 = 4 V to 5 V, 4 μs Rise Time
100
90
80
70
60
50
40
30
20
10
01 10 100 1000
EFFICIENCY (%)
LO AD CURRENT (mA)
–40°C
–5°C
+25°C
+85°C
+125°C
07932-019
Figure 19. Efficiency vs. Load Current, VOUT = 3.3 V, Different Temperatures
100
90
80
70
60
50
40
30
20
10
01 10 100 1000
EFFICIENCY (%)
LO AD CURRENT (mA)
4.0V
5.0V
5.5V
07932-018
Figure 20. Efficiency vs. Load Current, VOUT = 3.3 V, Different Input Voltages
CH1 1.00V CH2 20.0mV M20.0µs A CH1 4.68V
T 11.60%CH3 5.00V
1
2
3
T
INPUT VOLTAGE
OUTPUT VOLTAGE
SW ITCH NO DE
07932-021
Figure 21. Line Transient, VOUT = 1.8 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V,
4 μs Rise Time
ADP2140
Rev. 0 | Page 10 of 32
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
CH1 1.00V CH2 50.0mV M20.0µs A CH1 4.68V
T 11.60%CH3 5.00V
1
2
3
T
INPUT VOLTAGE
OUTPUT VOLTAGE
SW ITCH NO DE
07932-022
Figure 22. Line Transient, VOUT = 1.2 V, PSM Mode, 50 mA, VIN1 = 4 V to 5 V,
4 s Rise Time
CH1 1.00V CH2 20.0mV M20.0µs A CH1 4.32V
T 10.80%CH3 5.00V
1
2
3
T
INPUT VOLTAGE
OUTPUT VOLTAGE
SW ITCH NO DE
07932-023
Figure 23. Line Transient, VOUT = 1.2 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V,
4 s Rise Time
CH1 1.00V CH2 50.0mV M20.0µs A CH1 4.68V
T 11.60%CH3 5.00V
1
2
3
T
INPUT VOLTAGE
OUTPUT VOLTAGE
SW ITCH NO DE
07932-024
Figure 24. Line Transient, VOUT = 3.3 V, PSM Mode, 50 mA, VIN1 = 4 V to 5 V,
4 s Rise Time
CH1 1.00V CH2 20.0mV M20.0µs A CH1 4.68V
T 11.60%CH3 5.00V
1
2
3
T
INPUT VOLTAGE
OUTPUT VOLTAGE
SW ITCH NO DE
07932-025
Figure 25. Line Transient, VOUT = 3.3 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V,
4 s Rise Time
CH1 200mA CH2 50.0mV M20.0µ s A CH1 288mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUTPUT VOLTAGE
SW ITCH NO DE
07932-026
Figure 26. Load Transient, VOUT = 1.8 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
CH1 100mA CH2 50.0mV M20.0µ s A CH1 136mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD OUTP UT
OUTPUT VOLTAGE
SW ITCH NO DE
07932-027
Figure 27. Load Transient, VOUT = 1.8 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
ADP2140
Rev. 0 | Page 11 of 32
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
CH1 50.0mA CH2 50.0mV M20.0µ s A CH1 51. 0mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUTPUT VOLTAGE
SW ITCH NO DE
07932-028
Figure 28. Load Transient, VOUT = 1.8 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
CH1 200mA CH2 100 .0mV M 20.0µs A CH1 292mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUTPUT VOLTAGE
SW ITCH NO DE
07932-029
Figure 29. Load Transient, VOUT = 3.3 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
CH1 100mA CH2 100 .0mV M 20.0µs A CH1 80. 0 mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUTPUT VOLTAGE
SW ITCH NO DE
07932-030
Figure 30. Load Transient, VOUT = 3.3 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
CH1 50.0mA CH2 100. 0mV M20. s A CH1 50.0mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
07932-031
Figure 31. Load Transient, VOUT = 3.3 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
CH1 200.0mA CH2 50.0mV M20.0µ s A CH1 376mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
07932-032
Figure 32. Load Transient, VOUT = 1.2 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
CH1 100.0mA CH2 50.0mV M20.0µ s A CH1 154mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
07932-033
Figure 33. Load Transient, VOUT = 1.2 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
ADP2140
Rev. 0 | Page 12 of 32
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
CH1 50.0mA CH2 50.0mV M20.0µ s A CH1 48. 0mA
T 10.40%CH3 5.00V
1
2
3
T
LO AD CURRENT
OUTPUT VOLTAGE
SW ITCH NO DE
07932-034
Figure 34. Load Transient, VOUT = 1.2 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
CH1 500mA CH2 1.00V
CH4 5.00V M 1 00µs A CH4 2.70V
T 10.40%CH3 5.00V
1
2
3
4
T
INDUCTOR CURRENT
OUTPUT VOLTAGE
SW ITCH NO DE
ENABLE 1
07932-035
Figure 35. Startup, VOUT = 1.8 V, 10 mA
CH1 500mA CH2 1.00V
CH4 5.00V M 4 0.0µs A CH4 2.70V
T 10.40%CH3 5.00V
1
2
3
4
T
INDUCTOR CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
ENABLE 1
07932-036
Figure 36. Startup, VOUT = 1.8 V, 600 mA
CH1 500mA CH2 2.00V
CH4 5.00V M 4 0.0µs A CH4 2.70V
T 10.40%CH3 5.00V
1
2
3
4
T
INDUCTOR CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
ENABLE 1
07932-037
Figure 37. Startup, VOUT = 3.3 V, 10 mA
CH1 500mA CH2 2.00V
CH4 5.00V M 4 0.0µs A CH4 2.70V
T 10.40%CH3 5.00V
1
2
3
4
T
INDUCTOR CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
ENABLE 1
07932-100
Figure 38. Startup, VOUT = 3.3 V, 600 mA
CH1 200mA CH2 1.00V
CH4 5.00V M 1 00µs A CH4 2.30V
T 10.40%CH3 5.00V
1
2
3
4
T
INDUCTOR CURRENT
OUT P UT VO LTAGE
SW ITCH NO DE
ENABLE 1
07932-039
Figure 39. Startup, VOUT = 1.2 V, 10 mA
ADP2140
Rev. 0 | Page 13 of 32
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 µF, TA = 25°C, unless otherwise noted.
CH1 500mA CH2 1.00V
CH4 5.00V M 4 0.0µs A CH4 2.30V
T 10.00%CH3 5.00V
1
2
3
4
T
OUTPUT VOLTAGE
SW IT C H NODE
INDUCT OR CURRENT
ENABLE 1
07932-040
Figure 40. Startup, VOUT = 1.2 V, 600 mA
CH1 1.00V CH2 1.00V
CH4 5.00V M 2 .00ms A CH4 2.30V
T 10.00%CH3 5.00V
1
2
3
4
T
LDO OUTPUT
PG SIGNAL
BUCK OUT P UT
ENABLE 1
07932-041
Figure 41. Startup, Autosequence Mode, VOUT = 1.8 V, VOUT2 = 1.2 V
ADP2140
Rev. 0 | Page 14 of 32
LDO OUTPUT
VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 µF, TA = 25°C, unless otherwise noted.
1.83
1.77
1.78
1.79
1.80
1.81
1.82
–40 1258525–5
OUTPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
LO AD CURRE NT = 1