12-Bit, 5MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●HIGH SFDR: 82dB at NYQUIST
●HIGH SNR: 69dB
●LOW POWER: 115mW
●LOW DLE: 0.25LSB
●FLEXIBLE INPUT RANGE
●OVER-RANGE INDICATOR
APPLICATIONS
●IF AND BASEBAND DIGITIZATION
●CCD IMAGING SCANNERS
●TEST INSTRUMENTATION
DESCRIPTION
The ADS803 is a high-speed, high dynamic range, 12-bit
pipelined Analog-to-Digital (A/D) converter. This converter
includes a high-bandwidth track-and-hold that gives excel-
lent spurious performance up to and beyond the Nyquist rate.
This high-bandwidth, linear track-and-hold minimizes har-
monics and has low jitter, leading to excellent SNR perfor-
mance. The ADS803 is also pin-compatible with the 10MHz
ADS804 and the 20MHz ADS805.
The ADS803 provides an internal reference and can be
programmed for a 2Vp-p input range for the best spurious
performance and ease of driving. Alternatively, the 5Vp-p input
range can be used for the lowest input referred noise of
0.09LSBs rms giving superior imaging performance. There is
also a capability to set the input range in between the 2Vp-p
and 5Vp-p input ranges or to use an external reference. The
ADS803 also provides an over-range indicator flag to indicate
an input range that exceeds the full-scale input range of the
converter. This flag can be used to reduce the gain of the front-
end gain-ranging circuitry.
The ADS803 employs digital error-correction techniques to
provide excellent differential linearity for demanding imaging
applications. Its low distortion and high SNR give the extra
margin needed for communications, medical imaging, video,
and test instrumentation applications. The ADS803 is avail-
able in an SSOP-28 package.
12-Bit
Pipelined
ADC
Reference and
Mode Select
Reference Ladder
and Driver
Timing Circuitry
Error
Correction
Logic
3-State
Outputs
T & H D0
D11
•
•
•
CLK
+V
S
ADS803
VDRV
OE
SEL REFBV
REF
REFT
INV
IN
IN
CM OVR
ADS803
SBAS074B – JANUARY 1997 – REVISED SEPTEMBER 2002
www.ti.com
Copyright © 1997, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADS803E
ADS803
2SBAS074B
www.ti.com
+VS....................................................................................................... +6V
Analog Input........................................................... (–0.3V) to (+VS +0.3V)
Logic Input ............................................................. (–0.3V) to (+VS +0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature..................................................................... +150°C
ABSOLUTE MAXIMUM RATINGS(1)
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.
ADS803E
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 12 Tested Bits
SPECIFIED TEMPERATURE RANGE –40 +85 °C
CONVERSION CHARACTERISTICS
Sample Rate 10k 5M Samples/s
Data Latency 6 Clk Cycles
ANALOG INPUT
Single-Ended Input Range 1.5 3.5 V
Standard Optional Single-Ended Input Range 0 5 V
Common-Mode Voltage 2.5 V
Standard Optional Common-Mode Voltage 1V
Input Capacitance 20 pF
Track-Mode Input Bandwidth –3dBFS Input 270 MHz
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 500kHz ±0.25 ±0.75 LSB
No Missing Codes Tested
Spurious-Free Dynamic Range(1)
f = 2.48MHz (–1dB input) 74 82 dBFS(2)
2-Tone Intermodulation Distortion(3) 74 dBc
f = 1.8M and 1.9M (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 2.48MHz (–1dB input) 66.5 69 dB
Signal-to-(Noise + Distortion) (SINAD)
f = 2.48MHz (–1dB input) 65 68 dB
Effective Number of Bits at 2.48MHz(4) 11 Bits
Input Referred Noise 0V to 5V Input 0.09 LSBs rms
1.5V to 3.5V Input 0.23 LSBs rms
Integral Nonlinearity Error
f = 500kHz ±1±2 LSB
Aperture Delay Time 1ns
Aperture Jitter 4 ps r ms
Over-Voltage Recovery Time 1.5 • FS Input 2 ns
Full-Scale Step Acquisition Time 50 ns
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY
ADS803E SSOP-28 DB –40°C to +85°C ADS803E ADS803E Rails, 48
" """"ADS803E/1K Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ADS803 3
SBAS074B www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 5MHz, unless otherwise specified.
ADS803E
PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS
Logic Family CMOS Compatible
Convert Command Start Conversion Rising Edge of Convert Clock
High Level Input Current (VIN = 5V)(5) 100 µA
Low Level Input Current (VIN = 0V) ±10 µA
High Level Input Voltage +3.5 V
Low Level Input Voltage +1.0 V
Input Capacitance 5pF
DIGITAL OUTPUTS
Logic Family CMOS/TTL Compatible V
Logic Coding Straight Offset Binary
Low Output Voltage (IOL = 50µA) 0.1 V
Low Output Voltage (IOL = 1.6mA) 0.4 V
High Output Voltage (IOH = 50µA) +4.5 V
High Output Voltage (IOH = 0.5mA) +2.4 V
3-State Enable Time
OE
= L 20 40 ns
3-State Disable Time
OE
= H 2 10 ns
Output Capacitance 5pF
ACCURACY (5Vp-p Input Range) fS = 2.5MHz
Zero Error (Referred to –FS) At 25°C 0.2 ±1.5 %FS
Zero Error Drift (Referred to –FS) ±5 ppm/°C
Gain Error(6) At 25°C±2.0 %FS
Gain Error Drift(6) ±15 ppm/°C
Gain Error(7) At 25°C±1.5
%FS
Gain Error Drift(7) ±15 ppm/°C
Power-Supply Rejection of Gain ∆VS = ±5% 60 82 dB
Reference Input Resistance 1.6 kΩ
Internal Voltage Reference Tolerance (V
REF
= 2.5V)
At 25°C±35 mV
Internal Voltage Reference Tolerance (V
REF
= 1.0V)
At 25°C±14 mV
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VSOperating +4.7 +5.0 5.3 V
Supply Current: +ISOperating 23 27 mA
Power Dissipation Operating 115 135 mW
Thermal Resistance,
θ
JA
SSOP-28 50 °C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full-scale. (3) 2-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective
number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) Internal 50kΩ pull-down resistor. (6) Includes internal reference. (7) Excludes internal reference.
ADS803
4SBAS074B
www.ti.com
PIN CONFIGURATION
PIN DESIGNATOR DESCRIPTION
1 OVR Over-Range Indicator
2 B1 Data Bit 1 (MSB)
3 B2 Data Bit 2
4 B3 Data Bit 3
5 B4 Data Bit 4
6 B5 Data Bit 5
7 B6 Data Bit 6
8 B7 Data Bit 7
9 B8 Data Bit 8
10 B9 Data Bit 9
11 B10 Data Bit 10
12 B11 Data Bit 11
13 B12 Data Bit 12 (LSB)
14 CLK Convert Clock Input
15 OE Output Enable
16 +VS+5V Supply
17 GND Ground
18 SEL Input Range Select
19 VREF Reference Voltage Select
20 REFB Bottom Reference
21 CM Common-Mode Voltage
22 REFT Top Reference
23 IN Complementary Analog Input
24 GND Analog Ground
25 IN Analog Input (+)
26 GND Analog Ground
27 +VS+5V Supply
28 VDRV Output Driver Voltage
PIN DESCRIPTIONS
Top View SSOP
6 Clock Cycles
Data Invalid
tDtLtH
tCONV
N – 6N – 5N – 4N – 3N – 2N – 1 N N + 1
Data Out
Clock
Analog In N
t2
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7
t1
TIMING DIAGRAM
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tCONV Convert Clock Period 200 1 • 105(ns) ns
tLClock Pulse LOW 96 99 ns
tHClock Pulse HIGH 96 99 ns
tDAperture Delay 3 ns
t1Data Hold Time, CL = 0pF 3.9 ns
t2New Data Delay Time, CL = 15pF max 12 ns
OVR
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
CLK
VDRV
+V
S
GND
IN
GND
IN
REFT
CM
REFB
VREF
SEL
GND
+V
S
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS803
ADS803 5
SBAS074B www.ti.com
TYPICAL CHARACTERISTICS
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, and single-ended input and sampling rate = 5MHz, unless otherwise specified.
SPECTRAL PERFORMANCE
Frequency (MHz)
Amplitude (dB)
0 0.5 1.0 1.5 2.0 2.5
0
–20
–40
–60
–80
–100
–120
f
IN
= 500kHz
SPECTRAL PERFORMANCE
Frequency (MHz)
Amplitude (dB)
0 0.5 1.0 1.5 2.0 2.5
0
–20
–40
–60
–80
–100
–120
f
IN
= 2.48MHz
FREQUENCY SPECTRUM
Frequency (MHz)
Magnitude (dBFSR)
0 0.5 1.0 1.5 2.0 2.5
0
–20
–40
–60
–80
–100
–120
f1 = 1.8MHz at –7dB
f2 = 1.9MHz at –7dB
IMD (3) = –74dBc
DIFFERENTIAL LINEARITY ERROR
Output Code
DLE (LSB)
0 1024 2048 3072 4096
1.0
0.5
0
–0.5
–1.0
f
IN
= 500kHz
INTEGRAL LINEARITY ERROR
Output Code
ILE (LSB)
0 1024 2048 3072 4096
4.0
2.0
0
–2.0
–4.0
f
IN
= 500kHz
100
80
60
40
20
0
SWEPT POWER SFDR
SFDR (dBFS, dBc)
–60 –50 –40 –30 –20 –10 0
Input Amplitude (dBFS)
dBFS
dBc
fIN = 2.48MHz
ADS803
6SBAS074B
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TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, and single-ended input and sampling rate = 5MHz, unless otherwise specified.
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
SFDR, SNR (dBFS)
85
80
75
70
65
600.1 1
Frequency (MHz) 10
SFDR
SNR
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
(Differential Input, V
IN
= 5Vp-p)
SFDR, SNR (dBFS)
85
80
75
70
65
600.1 1
Frequency (MHz) 10
SFDR
SNR
0.40
0.30
0.20
0.10
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
DLE (LSB)
–50 –25 0 25 50 75 100
Temperature (°C)
f
IN
= 500kHz
f
IN
= 2.48MHz
85
80
75
70
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
SFDR (dBFS)
–50 –25 0 25 50 10075
Temperature (°C)
f
IN
= 500kHz
f
IN
= 2.48MHz
72
70
68
66
64
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE
SINAD, SNR (dBFS)
–50 –25 0 25 50 75 100
Temperature (°C)
fIN = 2.48MHz fIN = 2.48MHz
fIN = 500kHz
fIN = 500kHz
SNR
SINAD
117
116
115
114
POWER DISSIPATION vs TEMPERATURE
Power (mW)
–50 –25 0 25 50 10075
Temperature (°C)
ADS803 7
SBAS074B www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, and single-ended input and sampling rate = 5MHz, unless otherwise specified.
800k
600k
400k
200k
0
OUTPUT NOISE HISTOGRAM
(DC Input, V
IN
= 2Vp-p)
Counts
N – 2N – 1 N N + 1 N + 2
Code
800k
600k
400k
200k
0
OUTPUT NOISE HISTOGRAM
(DC Input, VIN = 5Vp-p Range)
Counts
N – 2N – 1 N N + 1 N + 2
Code
APPLICATION INFORMATION
DRIVING THE ANALOG INPUT
The ADS803 allows its analog inputs to be driven either
single-ended or differentially. The focus of the following
discussion is on the single-ended configuration. Typically, its
implementation is easier to achieve and the rated specifica-
tions for the ADS803 are characterized using the single-
ended mode of operation.
AC-COUPLED INPUT CONFIGURATION
Given in Figure 1 is the circuit example of the most common
interface configuration for the ADS803. With the VREF pin
connected to the SEL pin, the full-scale input range is defined
to be 2Vp-p. This signal is ac-coupled in single-ended form
to the ADS803 using the low-distortion voltage-feedback
amplifier OPA642. As is generally necessary for single-
supply components, operating the ADS803 with a full-scale
input signal swing requires a level-shift of the amplifier’s
zero-centered analog signal to comply with the A/D converter’s
input range requirements. Using a DC blocking capacitor
between the output of the driving amplifier and the converter’s
input, a simple level-shifting scheme can be implemented. In
this configuration, the top and bottom references (REFT and
REFB) provide an output voltage of +3V and +2V, respec-
tively. Here, two resistor pairs (2 • 2kΩ) are used to create a
common-mode voltage of approximately +2.5V to bias the
inputs of the ADS803 (IN,
IN
) to the required DC voltage.
FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal
Top and Bottom Reference.
OPA642
VIN
+VIN 0V
–VIN RF
402Ω
RG
402Ω
ADS803
RS
24.9Ω2kΩ2kΩ
2kΩ
2kΩ
100pF
0.1µF
0.1µF2Vp-p IN
IN
(+2V)
REFB (+1V)
VREF SEL
REFT
(+3V)
+5V –5V
+2.5VDC
ADS803
8SBAS074B
www.ti.com
FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-Level Shift.
An advantage of ac-coupling is that the driving amplifier still
operates with a ground-based signal swing. This will keep the
distortion performance at its optimum since the signal swing
stays within the linear region of the op amp and sufficient
headroom to the supply rails can be maintained. Consider
using the inverting gain configuration to eliminate CMR in-
duced errors of the amplifier. The addition of a small series
resistor (R
S
) between the output of the op amp and the input
of the ADS803 will be beneficial in almost all interface configu-
rations. This will decouple the op amp’s output from the
capacitive load and avoid gain peaking, which can result in
increased noise. For best spurious and distortion performance,
the resistor value should be kept below 50Ω. Furthermore, the
series resistor together with the 100pF capacitor, establish a
passive low-pass filter, limiting the bandwidth for the wideband
noise thus help improving the SNR performance.
DC-COUPLED WITHOUT LEVEL SHIFT
In some applications the analog input signal may already be
biased at a level which complies with the selected input
range and reference level of the ADS803. In this case, it is
only necessary to provide an adequately low source imped-
ance to the selected input, IN or
IN
. Always consider wideband
op amps, since their output impedance will stay low over a
wide range of frequencies. For those applications requiring
the driving amplifier to provide a signal amplification (with a
gain ≥ 3), consider using the decompensated voltage-feed-
back op amp OPA643.
DC-COUPLED WITH LEVEL SHIFT
Several applications may require that the bandwidth of the
signal path includes DC, in which case the signal has to be
DC-coupled to the A/D converter. In order to accomplish
this, the interface circuit has to provide a DC-level shift. The
circuit presented in Figure 2 employs an op amp, A1, to sum
the ground centered input signal with a required DC offset.
OPA691
V
IN
+V
S
2Vp-p
0
+1V
–1V
R
F
R
IN
NOTE: R
F
= R
IN
, G = –1
+V
S
ADS803
R
S
24.9Ω
2kΩ
100pF
10µF
++2.5V
R
2
R
1
2kΩ
IN
IN
REFB (+1V)
V
REF
SEL
REFT
0.1µF
0.1µF
The ADS803 typically operates with a +2.5V common-mode
voltage, which is established at the center tap of the ladder
and connected to the
IN
input of the converter. Amplifier A1
operates in inverting configuration. Here, resistors R1 and
R2 set the DC bias level for A1. Due to the op amp’s noise
gain of +2V/V (assuming RF = RIN), the DC offset voltage
applied to its noninverting input has to be divided down to
+1.25V, resulting in a DC output voltage of +2.5V.
DC voltage differences between the IN and
IN
inputs of the
ADS803 will effectively produce an offset, which can be
corrected for by adjusting the values of resistors R1 and R2.
The bias current of the op amp may also result in an
undesired offset. The selection criteria of the appropriate op
amp should include the input bias current, output voltage
swing, distortion, and noise specification. Note that in this
example the overall signal phase is inverted. To re-estab-
lish the original signal polarity it is always possible to
interchange the IN and
IN
connections.
SINGLE-ENDED-TO-DIFFERENTIAL
CONFIGURATION (TRANSFORMER COUPLED)
In order to select the best suited interface circuit for the
ADS803, the performance requirements must be known. If
an ac-coupled input is needed for a particular application, the
next step is to determine the method of applying the signal;
either single-ended or differentially. The differential input
configuration may provide a noticeable advantage of achiev-
ing good SFDR performance based on the fact that in the
differential mode, the signal swing can be reduced to half of
the swing required for single-ended drive. Secondly, by
driving the ADS803 differentially, the even-order harmonics
will be reduced. See Figure 3 for the schematic of the
suggested transformer coupled interface circuit. The resistor
across the secondary side (RT) should be set to get an input
impedance match (e.g., RT = n2 • RG).
ADS803 9
SBAS074B www.ti.com
V
IN
IN
IN CM
22Ω
22Ω
100pF
R
T
100pF
+4.7µF0.1µF
ADS803
1:n
0.1µF
R
G
REFERENCE OPERATION
Integrated into the ADS803 is a bandgap reference circuit
including logic that provides either a +1V or +2.5V reference
output by simply selecting the corresponding pin-strap con-
figuration. Different reference voltages can be generated by
the use of two external resistors, which will set a different
gain for the internal reference buffer. For more design flexibil-
ity, the internal reference can be shut off and an external
reference voltage used. Table I provides an overview of the
possible reference options and pin configurations.
FIGURE 3. Transformer-Coupled Input
INPUT
FULL-SCALE REQUIRED
MODE RANGE VREF CONNECT TO
Internal 2Vp-p +1V SEL VREF
Internal 5Vp-p +2.5V SEL GND
Internal 2V ≤ FSR < 5V 1V < VREF < 2.5V R1VREF and SEL
FSR = 2 x VREF VREF = 1 + (R1/R2)R
2SEL and GND
External 1V < FSR < 5V 0.5V < VREF < 2.5V SEL +VS
VREF Ext. VREF
TABLE I. Selected Reference Configuration Examples.
A simple model of the internal reference circuit is shown in
Figure 4. The internal blocks are a 1V-bandgap voltage
reference, buffer, the resistive reference ladder, and the
drivers for the top and bottom reference that supply the
necessary current to the internal nodes. As shown, the
output of the buffer appears at the VREF pin. The full-scale
input span of the ADS803 is determined by the voltage at
VREF, according to Equation 1:
Full-Scale Input Span = 2 • VREF (1)
Note that the current drive capability of this amplifier is limited to
approximately 1mA and should not be used to drive low loads.
The programmable reference circuit is controlled by the voltage
applied to the select pin (SEL). Refer to Table I for an overview.
FIGURE 4. Equivalent Reference Circuit.
800Ω
800Ω
REFB
CM
Reference
Driver
Bandgap
and Logic
REFT
VREF
SEL
1VDC
Resistor Network
and Switches
Disable
Switch
to A/D
to A/D
ADS803
ADS803
10 SBAS074B
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3.5V
1.5V IN
IN
+1V
SELV
REF
+2.5V ext.
ADS803
V
IN
VIN
5V
0V IN
IN
+2.5V
SELVREF
ADS803
FIGURE 8. Internal Reference with 1.5V to 3.5V Input Range.
FIGURE 9. Internal Reference with 1V to 4V Input Range.
FIGURE 7. Internal Reference with 0V to 5V Input Range.
The top reference (REFT) and the bottom reference (REFB)
are brought out mainly for external bypassing. For proper
operation with all reference configurations, it is necessary to
provide solid bypassing to the reference pins in order to keep
the clock feedthrough to a minimum. Figure 5 shows the
recommended decoupling network.
4V
1V IN
IN SELV
REF
+2.5V ext.
V
REF
= 1V
1 + R
1
R
2
FSR = 2 • V
REF
ADS803
R
1
5kΩ
+1.5V R
2
10kΩ
FIGURE 5. Recommended Reference Bypassing Scheme.
ADS803
CMREFB
0.1µF
0.1µF
V
REF
0.1µF10µF
+
0.1µF
REFT
0.1µF
10µF
+
FIGURE 6. Alternative Circuit to Generate CM Voltage.
IN
IN
REFT
R1
CMV
R2
0.1µF
0.1µF
ADS803
REFB
In addition, the common-mode voltage (CMV) may be used as
a reference level to provide the appropriate offset for the driving
circuitry. However, care must be taken not to appreciably load
this node, which is not buffered and has a high impedance. An
alternate method of generating a common-mode voltage is
given in Figure 6. Here, two external precision resistors (toler-
ance 1% or better) are located between the top and bottom
reference pins. The common-mode level will appear at the
midpoint. The output buffers of the top and bottom reference
are designed to supply approximately 2mA of output current.
SELECTING THE INPUT RANGE AND REFERENCE
Figures 7 through 9 show a selection of circuits for the most
common input ranges when using the internal reference of
the ADS803. All examples are for single-ended inputs and
operate with a nominal common-mode voltage of +2.5V.
EXTERNAL REFERENCE OPERATION
Depending on the application requirements, it might be
advantageous to operate the ADS803 with an external refer-
ence. This may improve the DC accuracy if the external
ADS803 11
SBAS074B www.ti.com
FIGURE 10. External Reference, Input Range 0.5V to 4.5V
(4Vp-p), with +2.5V Common-Mode Voltage.
reference circuitry is superior in its drift and accuracy. To use
the ADS803 with an external reference, the user must
disable the internal reference, as shown in Figure 10. By
connecting the SEL pin to +VS, the internal logic will shut
down the internal reference. At the same time, the output of
the internal reference buffer is disconnected from the VREF
pin, which must now be driven with the external reference.
Note that a similar bypassing scheme should be maintained
as described for the internal reference operation.
Therefore, this edge should have the lowest possible jitter.
The jitter noise contribution to total SNR is given by the
following equation. If this value is near your system require-
ments, input clock jitter must be reduced.
JitterSNR rms signal to rmsnoise=ƒ
20 1
2
log πIN A
t
where: ƒIN is Input Signal Frequency
t
A
is rms Clock Jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
a 50% duty cycle (tH = tL), along with fast rise and fall times
of 2ns or less.
DIGITAL OUTPUTS
The digital outputs of the ADS803 are designed to be
compatible with both high speed TTL and CMOS logic
families. The driver stage for the digital outputs is supplied
through a separate supply pin, VDRV, which is not con-
nected to the analog supply pins. By adjusting the voltage on
VDRV, the digital output levels will vary respectively. There-
fore, it is possible to operate the ADS803 on a +5V analog
supply while interfacing the digital outputs to 3V logic.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Larger capacitive loads
demand higher charging currents as the outputs are chang-
ing. Those high current surges can feed back to the analog
portion of the ADS803 and influence the performance. If
necessary, external buffers or latches may be used, which
provide the added benefit of isolating the ADS803 from any
digital noise activities on the bus coupling back high-fre-
quency noise. In addition, resistors in series with each data
line may help maintain the ac performance of the ADS803.
Their use depends on the capacitive loading seen by the
converter. Values in the range of 100Ω to 200Ω will limit the
instantaneous current the output stage has to provide for
recharging the parasitic capacitances as the output levels
change from LOW to HIGH or HIGH to LOW.
4.5V
0.5V IN
IN
+2.5V ext.
SEL
V
REF
1.24kΩ
4.99kΩ
0.1µF
10µF
REF1004
+2.5V +
ADS803
+5V
V
IN
+2V
DC
DIGITAL INPUTS AND OUTPUTS
Over-Range (OVR)
One feature of the ADS803 is its ‘Over-Range’ (OVR) digital
output. This pin can be used to monitor any out-of-range
condition, which occurs every time the applied analog input
voltage exceeds the input range (set by VREF). The OVR
output is LOW when the input voltage is within the defined
input range. It becomes HIGH when the input voltage is
beyond the input range. This is the case when the input
voltage is either below the bottom reference voltage or above
the top reference voltage. OVR will remain active until the
analog input returns to its normal signal range and another
conversion is completed. Using the MSB and its complement
in conjunction with OVR, a simple clue logic can be built that
detects the over-range and under-range conditions, as shown
in Figure 11. It should be noted that OVR is a digital output
that is updated along with the bit information corresponding
to the particular sampling incidence of the analog signal.
Therefore, the OVR data is subject to the same pipeline
delay (latency) as the digital data.
CLOCK INPUT REQUIREMENTS
Clock jitter is critical to the SNR performance of high-speed,
high-resolution A/D converters. It leads to aperture jitter (tA)
which adds noise to the signal being converted. The ADS803
samples the input signal on the rising edge of the CLK input.
OVR
MSB
Under = H
Over = H
FIGURE 11. External Logic for Decoding Under- and Over-
Range Conditions.
ADS803
12 SBAS074B
www.ti.com
FIGURE 12. Recommended Bypassing for Analog Supply Pins.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high-
frequency designs. Multi-layer PC boards are recommended
for best performance, since they offer distinct advantages
like minimizing ground impedance, separation of signal lay-
ers by ground layers, etc. It is recommended that the analog
and digital ground pins of the ADS803 be joined together at
the IC and be connected only to the analog ground of the
system.
The ADS803 has analog and digital supply pins, however,
the converter should be treated as an analog component and
all supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise that would otherwise be
coupled into the converter and degrade the achievable per-
formance.
Due to the pipeline architecture, the converter also generates
high-frequency current transients and noise that are fed back
into the supply and reference lines. This requires that the
supply and reference pins be sufficiently bypassed. Figure
12 shows the recommended decoupling scheme for the
+V
S
27 26
GND
ADS803
+
0.1µF 0.1µF
+V
S
16 17
GND
2.2µF
VDRV
28
0.1µF
+5V/+3V
+5V
analog supplies. In most cases, 0.1µF ceramic chip capaci-
tors are adequate to keep the impedance low over a wide
frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they should
be located as close to the supply pins as possible. In
addition, a larger size bipolar capacitor (1µF to 22µF) should
be placed on the PC board in close proximity to the converter
circuit.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS803E ACTIVE SSOP DB 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS803E/1K ACTIVE SSOP DB 28 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS803E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS803EG4 ACTIVE SSOP DB 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS803U OBSOLETE SOIC DW 28 TBD Call TI Call TI
ADS803U/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS803E/1K SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS803E/1K SSOP DB 28 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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