Data Sheet September 2007 TruePHY TM ET1011C Gigabit Ethernet Transceiver Features n n n n 10Base-T, 100Base-TX, and 1000Base-T gigabit Ethernet transceiver: -- 0.13 m process -- 128-pin TQFP and 84-pin MLCC: o RGMII, GMII, MII, RTBI, and TBI interfaces to MAC or switch -- 68-pin MLCC: o RGMII and RTBI interfaces to MAC or switch Low power consumption: -- Typical power less than 750 mW in 1000Base-T mode -- Advanced power management -- ACPI compliant wake-on-LAN support Oversampling architecture to improve signal integrity and SNR Optimized, extended performance echo and NEXT filters n All-digital baseline wander correction n Digital PGA control n On-chip diagnostic support n Automatic speed negotiation n Automatic speed downshift n n n n Single supply 3.3 V or 2.5 V operation: -- On-chip regulator controllers -- 3.3 V or 2.5 V digital I/O -- 3.3 V tolerant I/O pins (MDC, MDIO, COMA, RESET_N, and JTAG pins) -- 1.0 V or 1.1 V core power supplies -- 1.8 V or 2.5 V for transformer center tap JTAG ET1011C is a pin-compatible replacement for the ET1011 device Commercial- and industrial-temperature versions available Introduction The LSI ET1011C is a Gigabit Ethernet transceiver fabricated on a single CMOS chip. Packaged in either an 128pin TQFP, an 84-pin MLCC, or a 68-pin MLCC, the ET1011C is built on 0.13 m technology for low power consumption and application in server and desktop NIC cards. It features single power supply operation using on-chip regulator controllers. The 10/100/ 1000Base-T device is fully compliant with IEEE(R) 802.3, 802.3u, and 802.3ab standards. The ET1011C uses an oversampling architecture to gather more signal energy from the communication channel than possible with traditional architectures. The additional signal energy or analog complexity transfers into the digital domain. The result is an analog front end that delivers robust operation, reduced cost, and lower power consumption than traditional architectures. Using oversampling has allowed for the implementation of a fractionally spaced equalizer, which provides better equalization and has greater immunity to timing jitter, resulting in better signal-to-noise ratio (SNR) and thus improved BER. In addition, advanced timing algorithms are used to enable operation over a wider range of cabling plants. TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Table of Contents Contents Page Features................................................................................. 1 Introduction .......................................................................... 1 Functional Description ......................................................... 5 Oversampling Architecture............................................... 5 Automatic Speed Downshift ............................................. 5 Transmit Functions ........................................................... 6 Receive Functions............................................................. 6 Autonegotiation ................................................................ 7 Carrier Sense (128-Pin TQFP and 84-Pin MLCC Only) ..................................................... 7 Link Monitor..................................................................... 8 LEDs ................................................................................. 8 Regulator Control ............................................................. 8 Resetting the ET1011C ..................................................... 8 Loopback Mode ................................................................ 9 Digital Loopback .............................................................. 9 Analog Loopback............................................................ 10 Low-Power Modes.......................................................... 11 Pin Information................................................................... 12 Pin Diagram, 128-Pin TQFP .......................................... 12 Pin Diagram, 84-Pin MLCC ........................................... 13 Pin Diagram, 68-Pin MLCC .......................................... 14 Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC....................................................... 15 MAC Interface ................................................................ 22 Management Interface .................................................... 27 Configuration Interface................................................... 29 LEDs Interface ................................................................ 31 Media-Dependent Interface: Transformer Interface ................................................. 32 Clocking and Reset ......................................................... 33 JTAG............................................................................... 34 Regulator Control ........................................................... 34 Power, Ground, and No Connect .................................... 35 Cable Diagnostics............................................................... 36 Register Description ........................................................... 37 Register Address Map..................................................... 37 Register Functions/Settings ............................................ 38 Electrical Specifications ..................................................... 62 Absolute Maximum Ratings ........................................... 62 Recommended Operating Conditions ............................. 62 Device Electrical Characteristics .................................... 63 Timing Specification .......................................................... 67 GMII 1000Base-T Transmit Timing (128-Pin TQFP and 84-Pin MLCC Only)................... 67 GMII 1000Base-T Receive Timing (128-Pin TQFP and 84-Pin MLCC Only)................... 68 RGMII 1000Base-T Transmit Timing ............................ 69 RGMII 1000Base-T Receive Timing ............................. 71 MII 100Base-TX Transmit Timing................................. 73 MII 100Base-TX Receive Timing ................................. 74 MII 10Base-T Transmit Timing ..................................... 75 2 Contents Page MII 10Base-T Receive Timing........................................76 Serial Management Interface Timing..............................77 Reset Timing ...................................................................78 Clock Timing...................................................................79 JTAG Timing ..................................................................80 Package Diagram, 128-Pin TQFP ......................................81 Package Diagram, 84-Pin MLCC ......................................82 Package Diagram, 68-Pin MLCC ......................................83 Ordering Information .........................................................84 Table Page Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC........................................... 15 Table 2. Multiplexed Signals on the ET1011C .................. 20 Table 3. GMII Signal Description (1000Base-T Mode) (128-pin TQFP and 84-pin MLCC only) ........................................ 22 Table 4. RGMII Signal Description (1000Base-T Mode)........................................ 23 Table 5. MII Interface (100Base-TX and 10Base-T) (128-Pin TQFP and 84-Pin MLCC Only) ....................................... 24 Table 6. Ten-Bit Interface (1000Base-T) (128-Pin TQFP and 84-Pin MLCC Only)....... 25 Table 7. RTBI Signal Description (1000Base-T Mode) ....................................... 26 Table 8. Management Frame Structure .............................. 27 Table 9. Management Interface.......................................... 28 Table 10. Configuration Signals......................................... 29 Table 11. LED ................................................................... 31 Table 12. Transformer Interface Signals ............................ 32 Table 13. Clocking and Reset ............................................ 33 Table 14. JTAG Test Interface............................................ 34 Table 15. Regulator Control Interface................................ 34 Table 16. Supply Voltage Combinations............................ 35 Table 17. Power, Ground, and No Connect........................ 35 Table 18. Cable Diagnostic Functions ............................... 36 Table 19. Register Address Map ........................................ 37 Table 20. Register Type Definition .................................... 37 Table 21. Control Register--Address 0 ............................. 38 Table 22. Status Register--Address 1................................ 39 Table 23. PHY Identifier Register 1--Address 2 ...............40 Table 24. PHY Identifier Register 2--Address 3 ...............40 Table 25. Autonegotiation Advertisement Register-- Address 4 .........................................................41 Table 26. Autonegotiation Link Partner Ability Register--Address 5 ....................................... 42 Table 27. Autonegotiation Expansion Register --Address 6 .................................................... 43 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Table of Contents (continued) Table Page Table 28. Autonegotiation Next Page Transmit Register--Address 7........................................43 Table 29. Link Partner Next Page Register -- Address 8 .........................................................44 Table 30. 1000 Base-T Control Register-- Address 9 .........................................................45 Table 31. 1000Base-T Status Register-- Address 10 .......................................................46 Table 32. Reserved Registers--Addresses 11--14 ............47 Table 33. Extended Status Register--Address 15 ..............47 Table 34. Reserved Registers--Addresses 16--17 ............47 Table 35. PHY Control Register 2--Address 18................48 Table 36. MDI/MDI-X Configuration ................................49 Table 37. MDI/MDI-X Pin Mapping..................................49 Table 38. Loopback Control Register--Address 19...........50 Table 39. Loopback Bit (0.14) and Cable Diagnostic Mode Bit (23.13) Settings for Loopback Mode...............................................50 Table 40. RX Error Counter Register--Address 20 ...........51 Table 41. Management Interface (MI) Control Register--Address 21......................................51 Table 42. PHY Configuration Register--Address 22.........52 Table 43. PHY Control Register--Address 23...................53 Table 44. Interrupt Mask Register--Address 24 ................54 Table 45. Interrupt Status Register--Address 25 ...............55 Table 46. PHY Status Register--Address 26 .....................56 Table 47. LED Control Register 1--Address 27 ................57 Table 48. LED Control Register 2--Address 28 ................58 Table 49. LED Control Register 3--Address 29 ................58 Table 50. Diagnostics Control Register (TDR Mode)--Address 30 ..............................59 Table 51. Diagnostics Status Register (TDR Mode)--Address 31 ..............................60 Table 52. Diagnostics Control Register (Link Analysis Mode)--Address 30 ...............61 Table 53. MDI/MDI-X Configuration for 1000Base-T with C and D Swapped/Not Swapped .............61 Table 54. Absolute Maximum Ratings ...............................62 Table 55. ET1011C Recommended Operating Conditions.......................................62 Table 56. Device Characteristics--3.3 V Digital I/O Supply (DVDDIO)........................63 LSI Corporation Table Page Table 57. Device Characteristics--2.5 V Digital I/O Supply (DVDDIO) ....................... 63 Table 58. ET1011C Current Consumption 1000Base-T ..................................................... 64 Table 59. ET1011C Current Consumption 100Base-TX .................................................... 64 Table 60. ET1011C Current Consumption 10Base-T ......................................................... 64 Table 61. ET1011C Current Consumption 10Base-T Idle.................................................. 65 Table 62. ET1011C Current Consumption Hardware Powerdown..................................... 65 Table 63. ET1011C Current Consumption Low Power Energy Detect (LPED) ................ 65 Table 64. ET1011C Current Consumption Standby Powerdown ....................................... 66 Table 65. ET1011C Current Consumption Software Powerdown ...................................... 66 Table 66. GMII 1000Base-T Transmit Timing .................. 67 Table 67. GMII 1000Base-T Receive Timing.................... 68 Table 68. RGMII 1000Base-T Transmit Timing................ 69 Table 69. RGMII 1000Base-T Transmit Timing................ 70 Table 70. RGMII 1000Base-T Receive Timing ................. 71 Table 71. RGMII 1000Base-T Receive Timing ................. 72 Table 72. MII 100Base-TX Transmit Timing .................... 73 Table 73. MII 100Base-TX Receive Timing...................... 74 Table 74. MII 10Base-T Transmit Timing ......................... 75 Table 75. MII 10Base-T Receive Timing........................... 76 Table 76. Serial Management Interface Timing ................. 77 Table 77. Reset Timing ...................................................... 78 Table 78. Clock Timing...................................................... 79 Table 79. JTAG Timing ...................................................... 80 Table 80. Ordering Information ......................................... 84 3 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Table of Contents Figure Contents Page Figure 1. ET1011C Block Diagram...................................... 5 Figure 2. Loopback Functionality ........................................ 9 Figure 3. Digital Loopback................................................... 9 Figure 4. Replica and Line Driver Analog Loopback ........ 10 Figure 5. External Cable Loopback.................................... 10 Figure 6. Pin Diagram for ET1011C in 128-Pin TQFP Package (Top View).............. 12 Figure 7. Pin Diagram for ET1011C in 84-Pin MLCC Package (Top View) .............. 13 Figure 8. Pin Diagram for ET1011C in 68-Pin MLCC Package (Top View) .............. 14 Figure 9. ET1011C Gigabit Ethernet Card Block Diagram .............................................. 21 Figure 10. GMII MAC-PHY Signals ................................. 22 Figure 11. RGMII MAC-PHY Signals............................... 23 Figure 12. MII Signals........................................................ 24 Figure 13. Ten-Bit Interface ............................................... 25 Figure 14. Reduced Ten-Bit Interface ................................ 26 Figure 15. GMII 1000Base-T Transmit Timing ................. 67 Figure 16. GMII 1000Base-T Receive Timing .................. 68 4 Figure Contents (continued) Page Figure 17. RGMII 1000Base-T Transmit Timing-- Trace Delay....................................................69 Figure 18. RGMII 1000Base-T Transmit Timing-- Internal Delay ................................................70 Figure 19. RGMII 1000Base-T Receive Timing-- Trace Delay....................................................71 Figure 20. RGMII 1000Base-T Receive Timing-- Internal Delay ................................................72 Figure 21. MII 100Base-TX Transmit Timing....................73 Figure 22. MII 100Base-TX Receive Timing .....................74 Figure 23. MII 10Base-T Transmit Timing ........................75 Figure 24. MII 10Base-T Receive Timing ..........................76 Figure 25. Serial Management Interface Timing ................77 Figure 26. Reset Timing......................................................78 Figure 27. Clock Timing .....................................................79 Figure 28. JTAG Timing .....................................................80 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description The LSI ET1011C is a Gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four UTP pairs of category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using five-level pulse-amplitude modulation (PAM). Figure 1 is a block diagram of its basic configuration. GTX_CLK TX_CLK TXD[7:0] TX_ER TX_EN RX_CLK RXD[7:0] RX_ER RX_DV COL CRS PMA D PMA C PMA B PMA A NEXT Cancellers RGMII Echo Canceller PHYAD[4:0] MDC MDIO MDINT_N DAC Hybrid GMII MII FFE BLW Correction Gain Control PCS ADC TBI LEDS/ Config Management Interface Bias Timing Control AutoNegotiation TRD[0-3] PGA RTBI Trellis Decoder LEDS Config Transmit Shaping Clock Generator JTAG/ Test 10BASE-T Clock MI Registers Reset RSET TCK TRST_N TMS TDI TDO SYS_CLK XTAL_1 XTAL_2 RESET_N Figure 1. ET1011C Block Diagram Oversampling Architecture Automatic Speed Downshift The ET1011C architecture uses oversampling techniques to sample at two times the symbol rate. A fractionally spaced feed forward equalizer (FFE) adapts to remove intersymbol interference (ISI) and to shape the spectrum of the received signal to maximize the (SNR) at the trellis decoder input. The FFE equalizes the channel to a fixed target response. Oversampling enables the use of a fractionally spaced equalizer (FSE) structure for the FFE, resulting in symbol rate clocking for both the FFE and the rest of the receiver. This provides robust operation and substantial power savings. Automatic speed downshift is an enhanced feature of autonegotiation that allows the ET1011C to: n n n Fallback in speed, based on cabling conditions or link partner abilities. Operate over CAT-3 cabling (in 10Base-T mode). Operate over two-pair CAT-5 cabling (in 100Base-TX mode). For speed fallback, the ET1011C first tries to autonegotiate by advertising 1000Base-T capability. After a number of failed attempts to bring up the link, the ET1011C falls back to advertising 100Base-TX and restarts the autonegotiation process. This process continues through all speeds down to 10Base-T. At this point, there are no lower speeds to try and so the host enables all technologies and starts again. PHY configuration register, address 22, bits 11 and 10 enable automatic speed downshift and specifies if fallback to 10Base-T is allowed. PHY control register, address 23, bits 11 and 12 specify the number of failed attempts before downshift (programmable to 1, 2, 3, or 4 attempts). LSI Corporation 5 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Hybrid Transmit Functions The hybrid subtracts the transmitted signal from the input signal allowing full-duplex operation on each of the twistedpair cables. 1000Base-T Encoder In 1000Base-T mode, the ET1011C translates 8-bit data from the MAC interfaces into a code group of four quinary symbols that are then transmitted by the PMA as 4D fivelevel PAM signals over the four pairs of CAT-5 cable. 100Base-TX Encoder In 100Base-TX mode, 4-bit data from the media independent interface (MII) is 4B/5B encoded to output 5-bit serial data at 125 MHz. The bit stream is sent to a scrambler, and then encoded to a three-level MLT3 sequence that is then transmitted by the PMA. 10Base-T Encoder In 10Base-T mode, the ET1011C transmits and receives Manchester-encoded data. Receive Functions Decoder 1000Base-T In 1000Base-T mode, the PMA recovers the 4D PAM signals after compensating for the cabling conditions. The resulting code group is decoded to 8-bit data. Data stream delimiters are translated appropriately, and the data is output to the receive data pins of the MAC interfaces. The GMII receive error signal is asserted when invalid code groups are detected in the data stream. Decoder 100Base-TX In 100Base-TX mode, the PMA recovers the three-level MLT3 sequence that is descrambled and 5B/4B decoded to 4-bit data. This is output to the MII receive data pins after data stream delimiters have been translated appropriately. The MII receive error signal is asserted when invalid code groups are detected in the data stream. Decoder 10Base-T Programmable Gain Amplifier (PGA) The PGA operates on the received signal in the analog domain prior to the analog-to-digital converter (ADC). The gain control module monitors the signal at the output of the ADC in the digital domain to control the PGA. It implements a gain that maximizes the signal at the ADC while ensuring that no hard clipping occurs. Clock Generator A clock generator circuit uses the 25 MHz input clock signal and a phase-locked loop (PLL) circuit to generate all the required internal analog and digital clocks. A 125 MHz system clock is also generated and is available as an output clock. Analog-to-Digital Converter The ADC operates at 250 MHz oversampling at twice the symbol rate in 1000Base-T and 100Base-TX. This enables innovative timing recovery and fractional skew correction and has allowed transfer of analog complexity to the digital domain. Timing Recovery/Generation The timing recovery and generator block creates transmit and receive clocks for all modes of operation. In transmit mode, the 10Base-T and 100Base-TX modes use the 25 MHz clock input. While in receive mode, the input clock is locked to the receive data stream. 1000Base-T is implemented using a master-slave timing scheme, where the master transmit and receive are locked to the 25 MHz clock input, and the slave acquires timing information from the receive data stream. Timing recovery is accomplished by first acquiring lock on one channel and then making use of the constant phase relationship between channels to lock on the other pairs, resulting in a simplified PLL architecture. Timing shifts due to changing environmental conditions are tracked by the ET1011C. In 10Base-T mode, the ET1011C decodes the Manchesterencoded received signal. 6 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Autonegotiation Adaptive Fractionally Spaced Equalizer Autonegotiation is implemented in accordance with IEEE 802.3. The device supports 10Base-T, 100Base-TX, and 1000Base-T and can autonegotiate between them in either half- or full-duplex mode. It can also parallel detect 10BaseT or 100Base-TX. If autonegotiation is disabled, a 10Base-T or 100Base-TX link can be manually selected via the IEEE MII registers. The ET1011C's unique oversampling architecture employs an FSE in place of the traditional FFE structure. This results in robust equalization of the communications channel, which translates to superior bit error rate (BER) performance over the widest variety of worst-case cabling scenarios. The alldigital equalizer automatically adapts to changing conditions. Echo and Crosstalk Cancellers Since the four twisted pairs are bundled together and not insulated from each other in Gigabit Ethernet, each of the transmitted signals is coupled onto the three other cables and is seen at the receiver as near-end crosstalk (NEXT). A hybrid circuit is used to transmit and receive simultaneously on each pair. If the transmitter is not perfectly matched to the line, a signal component will be reflected back as an echo. Reflections can also occur at other connectors or cable imperfections. The ET1011C cancels echo and NEXT by subtracting an estimate of these signals from the equalizer output. Baseline Wander Correction A known issue for 1000Base-T and 100Base-TX is that the transformer attenuates at low frequencies. As a result, when a large number of symbols of the same sign are transmitted consecutively, the signal at the receiver gradually dies away. This effect is called baseline wander. By employing a circuit that continuously monitors and compensates for this effect, the probability of encountering a receive symbol error is reduced. Pair Skew Correction In Gigabit Ethernet, pair skew (timing differences between pairs of cable) can result from differences in length or manufacturing variations between the four individual twisted-pair cables. The ET1011C automatically corrects for both integer and fractional symbol timing differences between pairs. Automatic MDI Crossover During autonegotiation, the ET1011C automatically detects and sets the required MDI configuration so that the remote transmitter is connected to the local receiver and vice versa. This eliminates the need for crossover cables or crosswired (MDIX) ports. If the remote device also implements automatic MDI crossover, and/or the crossover is implemented in the cable, the crossover algorithm ensures that only one element implements the required crossover. Polarity Inversion Correction In addition to automatic MDI crossover that is necessary for autonegotiation, 10Base-T, and 100Base-TX operation, the ET1011C automatically corrects crossover of the additional two pairs used in 1000Base-T. Polarity inversion on all pairs is also corrected. Both of these effects may arise if the cabling has been incorrectly wired. Carrier Sense (128-Pin TQFP and 84-Pin MLCC Only) The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011C whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15. LSI Corporation 7 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Link Monitor LEDs 1000Base-T Four status LEDs are provided. These can be used to indicate speed of operation, duplex mode, link status, etc. There is a very high degree of programmability allowed. Hence, the LEDs can be programmed to different status functions from their default value, or they can be controlled directly from the MII register interface. The LED signal pins can also be used for general-purpose I/O if not needed for LED indication. Once 1000Base-T is autonegotiated and the link is established, both link partners continuously monitor their local receiver status. If the master device determines a problem with its receiver, it signals the slave and both devices cease transmitting data but transmit IDLE. If the master retrains its receiver within 750 ms, then normal operation recommences. Otherwise, both devices restart autonegotiation. If the slave device determines a problem with its receiver, it ceases transmitting and expects the master to transmit the IDLE sequence. If the slave retrains its receiver within 350 ms, normal operation recommences when the master signals that its receiver is ready. If either receiver fails to reacquire, then autonegotiation is restarted. 100Base-TX In 100Base-TX mode, the ET1011C monitors the link and determines the link quality based on signal energy, mean square error and scrambler lock. If the link quality is deemed insufficient, transmit and receive data are disabled. If the link had been autonegotiated, then control is handed back to autonegotiation. If the link had been manually set, the 100Base-TX receiver is retrained, and the transmitter is set to transmit idle. Once the link quality has been recovered, data transmit and receive are enabled. 10Base-T In 10Base-T mode, the ET1011C monitors the link and determines the link quality based either on the presence of valid link pulses or valid 10Base-T packets. If the link is deemed to have failed and the link had been autonegotiated, then control is handed back to autonegotiation. If the link had been manually set, the ET1011C continues to try to reestablish the link. 8 Regulator Control The ET1011C has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or 2.5 V. The on-chip regulator control circuits provide output control voltages that can be used to control two external transistors and thus provide regulated 1.0 V and 2.5 V supplies. Resetting the ET1011C The ET1011C provides the ability to reset the device by hardware (pin RESET_N) or via software through the management interface. A hardware reset is accomplished by driving the active-low pin RESET_N to 0 volts for a minimum of 20 s. The configuration pins and the physical address configuration are read during a hardware reset. A hardware reset is required after powerup in order to ensure proper operation. A software reset is accomplished by setting bit 15 of the control register (MII register address 0, bit 15). The configuration pins and the physical address configuration are not read during software reset. LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Loopback Mode Enabling loopback mode allows in-circuit testing of the ET1011C's digital and analog data path. The ET1011C provides several options for loopback that test and verify various functional blocks within the PHY. These are digital loopback and analog loopback. Figure 2 is a block diagram that shows the PHY loopback functionality. All Digital Loopback G M I I MAC / Switch PHY Digital Replica Loopback Remote PHY PHY AFE MII Loopback Line Driver Loopback Figure 2. Loopback Functionality The loopback mode is selected by setting the respective bit in the PHY loopback control register, MII register address 19. The default loopback mode is digital MII loopback. Loopback is enabled by writing to the PHY control register, address 0, bit 14. Digital Loopback Digital loopback provides the ability to loop the transmitted data back to the receiver via the digital circuitry. The point at which the signal is looped back is selected using the loopback control register with the following options being provided: MII and all digital. Selecting the MII option gives a simple loopback with minimal latency where the data is looped back directly at the media-independent interface. This loopback is currently set as the default, but it should be noted that it only exercises a small percentage of the PHY circuitry. When the all-digital option is selected, the transmitted data is looped back at the interface between the digital and the analog circuitry, thereby exercising a high percentage of the digital logic. Figure 3 shows a block diagram of digital loopback. MAC / Switch G M I I PHY Digital PHY AFE Figure 3. Digital Loopback LSI Corporation 9 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Analog Loopback Analog loopback provides the ability to loop the transmitted signal back to the receiver within the AFE. The point at which the signal is looped back is selected using the loopback control register with the following options being provided: replica and line driver. Selecting the replica option causes the transmitted signal to be looped back through the replica generation circuitry of the onchip hybrid, thereby allowing most of the digital and analog circuitry to be exercised. This loopback mode may be used even when the device is connected to a network because nothing is transmitted to or received from the MDI in this case. Line driver loopback transmits data to and receives data from the MDI. However, in general, this loopback may not be used when the device is connected to a network because it could cause an unanticipated response from the link partner. Line driver loopback requires 100 terminations to be present on the line side of the transformer for each wire pair. For example, for wire pair A, connect a 100 resistor between the leads (pins 1 and 2) of a short cable plugged into the RJ45. This should also be done for wire pairs B, C, and D. Another way to accomplish this is to connect to a link partner with a short cable and powerdown the link partner. Figure 4 shows a block diagram of both replica and line driver loopbacks. REPLICA LOOPBACK MAC / Switch G M I I PHY Digital PHY AFE RJ-45 LINE DRIVER LOOPBACK Figure 4. Replica and Line Driver Analog Loopback External Cable Loopback External cable loopback loops GMII Tx to GMII Rx via complete digital and analog path and via an external cable. The external cable should have pair A (pins 1 and 2) looped to pair B (pins 3 and 6), and pair C (pins 4 and 5) looped to pair D (pins 7 and 8). This will test all the digital data paths and all the analog circuits. Figure 5 shows a block diagram of external cable loopback MAC / Switch G M I I PHY Digital PHY AFE RJ-45 Figure 5. External Cable Loopback 10 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Low-Power Modes Hardware Powerdown Mode In Hardware Powerdown, all PHY functions (analog and digital) are disabled. During Hardware Powerdown, SYS_CLK is not available and the MII registers are not accessible. This is the lowest power mode for the ET1011C. Hardware Powerdown is entered when the LPED_EN_N and SYS_CLK_EN_N pins are high (deasserted), and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). Low-Power Energy-Detect (LPED) Mode In LPED mode, the PHY is in a low power state but still monitors the cable (MDI interface) for energy. If energy is detected, the MDINT_N pin is asserted. During LPED mode, SYS_CLK is not available and the MII registers are not accessible. The host system monitors the MDINT_N pin and then places the PHY into a regular operating mode in response to the interrupt. LPED mode is entered when the LPED_EN_N pin is low (asserted), SYS_CLK_EN_N pin is high (deasserted), and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). At exit from Hardware Powerdown or LPED modes, the ET1011C does the following: n Initializes all analog circuits including the PLL. n Initializes all digital logic and state machines. n Reads and latches the PHY address pins. n Initializes all MII registers to their default values (H/W configuration pins are reread). This powerdown mode is a combination of Standby Powerdown mode and LPED mode. The PLL is running and the PHY monitors the cable (MDI interface) for energy. If energy is detected, the MDINT_N pin is asserted. During this mode, SYS_CLK is available and the MII registers are not accessible. The host system monitors the MDINT_N pin and then places the PHY into a regular operating mode in response to the interrupt. This mode is entered when the LPED_EN_N pin is low (asserted), SYS_CLK_EN_N pin is low (asserted), and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). At exit from Standby Powerdown or Standby Powerdown with LPED, the ET1011C does the following: n Initializes all analog circuits excluding the PLL. n Initializes all digital logic and state machines. n Reads and latches the PHY address pins. n Initializes all MII registers to their default values (H/W configuration pins are reread). Software Powerdown Mode Software powerdown is entered when bit 11 of the control register (MII register address 0, bit 11) is set. In software powerdown, all PHY functions except the serial management interface and clock circuitry are disabled. The MII registers can be read or written. If the system clock output is enabled (MII register address 22, bit 4), the 125 MHz system clock will still be available for use by the MAC on pin SYS_CLK. At exit from software powerdown, the ET1011C initializes all digital logic and state machines only. NOTE: The H/W configuration pins and the PHY address pins are not re-read and the MII registers are not reset to their default values. These operations are only done during reset or recovery from hardware powerdown. Standby Powerdown Mode Wake-On-LAN Powerdown Mode In Standby Powerdown, most PHY functions (analog and digital) are disabled but the PLL is still running. During Standby Powerdown, SYS_CLK is available and the MII registers are not accessible. Standby Powerdown mode is entered when the LPED_EN_N pin is high (deasserted), SYS_CLK_EN_N pin is low (asserted), and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). ACPI power consumption compliant Wake-On-LAN mode is implemented on the ET1011C by using the IEEE standard MII registers to put the PHY into 10Base-T or 100Base-TX modes. Clearing the advertisement of 1000Base-T (MII register address 9, bits 8, 9) and setting the desired 10Base-T and 100Base-TX advertisement (MII register address 4, bits 5--8) activates this feature. This must be followed by an autonegotiation restart via the control register (MII register address 0, bit 9). Standby Powerdown with Low-Power Energy-Detect (LPED) Mode LSI Corporation 11 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 LSI ET1011 ET1011C 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDD DVSS RXD[4] RXD[5] RXD[6] RXD[7] DVDDIO DVSS SYS_CLK DVSS VDD MDC MDIO MDINT_N DVDDIO PRES NC LED_LNK/PAUSE NC NC LED_1000/SPEED_1000 VDD DVSS CTRL_1V0 CTRL_2V5 VDD_REG DVSS NC NC NC NC PHYAD[0]/LED_TXRX PHYAD[1]/LED_100 PHYAD[2] PHYAD[3] PHYAD[4] NC NC TRD[0]+ AVSS TRD[0]- AVSS AVDDL NC TRD[1]+ AVSS TRD[1]- AVSS AVDDL AVSS AVDDH RSET AVDDL TRD[2]+ AVSS TRD[2]- AVSS AVDDL NC TRD[3]+ AVSS TRD[3]- AVSS AVDDL 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC DVSS TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] DVSS DVDDIO TCK VDD DVSS DVSS TRST_N TMS/SYS_CLK_EN_N TDI/LPED_EN_N TDO MAC_IF_SEL[0] MAC_IF_SEL[1] MAC_IF_SEL[2] AUTO_MDI_EN VDD DVSS NC COMA VDD DVSS AVDDL AVSS AVDDH CLK_IN/XTAL_1 XTAL_2 NC RESET_N NC NC NC NC 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 TXD[2] TXD[1] TXD[0] TX_EN/TXD[8]/TX_CTL TX_ER/TXD[9] DVSS NC GTX_CLK/PMA_TX_CLK/TXC NC DVDDIO TX_CLK DVSS CRS/COMMA COL/PMA_RX_CLK1 NC RX_CLK/PMA_RX_CLK[0]/RXC DVSS DVDDIO RX_ER/RXD[9] RX_DV/RXD[8]/RX_CTL RXD[0] RXD[1] RXD[2] RXD[3] NC DVSS Pin Diagram, 128-Pin TQFP Figure 6. Pin Diagram for ET1011C in 128-Pin TQFP Package (Top View) 12 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) RX_CLK/PMA_RX_CLK[0]/RXC DVDDIO RX_ER/RXD[9] RX_DV/RXD[8]/RX_CTL/RXD[4] RXD[0] RXD[1] RXD[2] RXD[3] DVDDIO 71 70 69 68 67 66 65 64 COL/PMA_RX_CLK[1] 73 72 TX_CLK CRS/COMMA 76 74 DVDDIO 77 75 TX_ER/TXD[9] GTX_CLK/PMA_TX_CLK/TXC 78 TXD[0] TXD[1] 81 TX_EN/TXD[8]/TX_CTL/TXD[4] TXD[2] 82 79 TXD[3] 83 80 TXD[4] 84 Pin Diagram, 84-Pin MLCC TXD[5] 1 63 VDD TXD[6] 2 62 RXD[4] TXD[7] 3 61 RXD[5] DVDDIO 4 60 RXD[6] TCK 5 59 RXD[7] VDD 6 58 DVDDIO NC 7 57 SYS_CLK NC 8 56 VDD NC 9 55 MDC NC 10 54 MDIO NC 11 53 MDINT_N TRST_N 12 52 DVDDIO TMS/SYS_CLK_EN_N 13 51 PRES TDI/LPED_EN_N 14 50 LED_LNK/PAUSE TDO 15 49 LED_1000/SPEED_1000 MAC_IF_SEL[0] 16 48 VDD MAC_IF_SEL[1] 17 47 CTRL_1V0 MAC_IF_SEL[2] 18 46 CTRL_2V5 VDD 19 45 VDD_REG AVDDL 20 44 PHYAD[0] PHYAD[0]/LED_TXRX AVDDH 21 43 PHYAD[1] PHYAD[1]/LED_100 LSI ET1011C AGERE SYSTEMS ET1011 36 37 38 39 40 41 42 TRD[3]- AVDDL PHYAD[4] PHYAD[3] PHYAD[2] 35 TRD[2]- AVDDL 34 TRD[3]+ 33 AVDDL 29 TRD[1]- TRD[2]+ 28 TRD[1]+ 32 27 AVDDL RSET 26 TRD[0]- 31 25 TRD[0]+ 30 24 RESET_N AVDDL 23 XTAL_2 AVDDH 22 CLK_IN/XTAL_1 EXPOSED PAD (DVSS AND AVSS) Figure 7. Pin Diagram for ET1011C in 84-Pin MLCC Package (Top View) LSI Corporation 13 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) TXD[1] TXD[0] TX_CTL TXC DVDDIO TX_CLK RXC DVDDIO RX_CTL RXD[0] RXD[1] RXD[2] RXD[3] DVDDIO VDD 65 64 63 62 61 60 59 58 57 56 55 54 53 52 VDD TXD[2] 1 2 66 TXD[3] 68 DVDDIO TCK 67 Pin Diagram, 68-Pin MLCC 51 DVDDIO 50 SYS_CLK 3 49 VDD DVSS 4 48 MDC TRST_N 5 47 MDIO TMS/SYS_CLK_EN_N 6 46 MDINT_N TDI/LPED_EN_N 7 45 DVDDIO 44 PRES 43 LED_LNK/PAUSE * LSI ET1011C TDO 8 MAC_IF_SEL[0] 9 MAC_IF_SEL[1] 10 42 LED_1000/SPEED_1000 VDD 11 41 VDD COMA 12 40 CTRL_1V0 VDD 13 39 CTRL_2V5 AVDDL 14 38 VDD_REG AVDDH 15 37 PHYAD[0]/LED_TXRX CLK_IN/XTAL_1 16 36 PHYAD[1]/LED_100 XTAL_2 17 35 PHYAD[2] 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 RESET_N TRD[0]+ TRD[0]- AVDDL TRD[1]+ TRD[1]- AVDDL AVDDH RSET AVDDL TRD[2]+ TRD[2]- AVDDL TRD[3]+ TRD[3]- AVDDL PHYAD[3] EXPOSED PAD (DVSS AND AVSS) Figure 8. Pin Diagram for ET1011C in 68-Pin MLCC Package (Top View) 14 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC Name Description Pad Type Internal Pull-Up/ Pull-Down 3Analog State Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC MAC: GMII--Gigabit Media-Independent Interface (128-Pin TQFP and 84-Pin MLCC Only) GTX_CLK TX_ER TX_EN TXD[7:0] GMII transmit clock Transmit error Transmit enable Transmit data bits I I I I -- -- -- Pull-down -- -- -- -- -- -- -- -- RX_CLK RX_ER RX_DV RXD[7:0] Receive clock Receive error Receive data valid Receive data bits O O O O -- -- -- -- Z Z Z Z -- -- -- -- CRS COL Carrier sense Collision detect O O -- -- Z Z -- -- 121 124 125 7, 6, 5, 4, 3 128, 127, 126 113 110 109 97, 98, 99, 100, 105, 106, 107, 108 116 115 77 78 79 3, 2, 1, 84, 83, 82, 81, 80 72 70 69 59, 60, 61, 62, 65, 66, 67, 68 -- -- -- -- 74 73 -- -- 77 83, 82, 81, 80 63 68, 67, 66, 65 64 60 54, 55, 56, 57 58 -- -- -- -- MAC: RGMII--Reduced Gigabit Media-Independent Interface TXC TXD[3:0] RGMII transmit clock Transmit data bits I I -- Pull-down -- -- -- -- TX_CTL RXC RXD[3:0] Transmit control Receive clock Receive data bits I O O -- -- -- -- Z Z -- -- -- RX_CTL Receive control O -- Z -- 121 3, 128, 127, 126 125 113 105, 106, 107, 108 109 79 72 65, 66, 67, 68 69 MAC: MII--Media-Independent Interface (128-Pin TQFP and 84-Pin MLCC Only) TX_CLK TX_ER TX_EN TXD[3:0] MII transmit clock Transmit error Transmit enable Transmit data bits O I I I -- -- -- Pull-down Z -- -- -- -- -- -- -- RX_CLK RX_ER RX_DV RXD[3:0] Receive clock Receive error Receive data valid Receive data bits O O O O -- -- -- -- Z Z Z Z -- -- -- -- CRS COL Carrier sense Collision detect O O -- -- Z Z -- -- LSI Corporation 118 124 125 3, 128, 127, 126 113 110 109 105, 106, 107, 108 116 115 75 78 79 83, 82, 81, 80 -- -- -- -- 72 70 69 65, 66, 67, 68 -- -- -- -- 74 73 -- -- 15 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type Internal 3-State Analog Pull-Up/ Pull-Down Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC MAC: TBI--Ten-Bit Interface (128-Pin TQFP and 84-Pin MLCC Only) PMA_ TX_CLK TXD[9:0] TBI transmit clock Transmit data bits I I -- Pull-down on TXD[7:0] -- -- -- -- PMA_RX_CLK[0] TBI receive clock RXD[9:0] Receive data bits O O -- -- Z Z -- -- PMA_RX_ CLK[1] TBI receive clock COMMA Valid comma detect O O -- -- Z -- -- -- 121 77 124, 125, 7, 6, 78, 79, 3, 2, 5, 4, 3, 128, 1, 84, 127, 126 83, 82, 81, 80, 113 72 110, 109, 97, 70, 69, 59, 60, 61, 62, 98, 99, 100, 105, 106, 107, 65, 66, 67, 68, 108 115 73 116 74 -- -- -- -- -- -- MAC: RTBI--Reduced Ten-Bit Interface TXC TXD[3:0] RTBI transmit clock Transmit data bits I I -- Pull-down -- -- -- -- TX_CTL RXC RXD[3:0] Transmit control RTBI receive clock Receive data bits I O O -- -- -- -- Z Z -- -- -- RX_CTL Receive control O -- Z -- 121 3, 128, 127, 126 125 113 105, 106, 107, 108 109 77 83, 82, 81, 80, 79 72 65, 66, 67, 68 69 63 68, 67, 66, 65 64 60 54, 55, 56, 57 58 39 41 45 47 54 56 60 62 52 25 26 28 29 34 35 37 38 32 19 20 22 23 28 29 31 32 26 MDI: Transformer Interface TRD[0]+ TRD[0]- TRD[1]+ TRD[1]- TRD[2]+ TRD[2]- TRD[3]+ TRD[3]- RSET 16 Transmit and receive differential pair I/O -- -- A Transmit and receive differential pair I/O -- -- A Transmit and receive differential pair I/O -- -- A Transmit and receive differential pair I/O -- -- A Analog reference resistor I/O -- -- A LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type Internal Pull-Up/ Pull-Down 3-State Analog Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC 40, 41, 42, 43, 44 Management Interface PHYAD[4:0] PHY address 4--1 PHY address 0 MDC MDIO MDINT_N Management interface clock Management data I/O Management interface interrupt I, I, I, I/O I/O Pull-down -- -- Pull-up -- -- 67, 68, 69, 71, 70 I I/O O Pull-down Pull-up -- -- -- -- -- -- -- 91 90 89 55 54 53 34, 35, 36, 37 PHYAD [3:0] 48 47 46 Configuration1 SPEED_1000 PAUSE AUTO_MDI_EN MAC_IF_SEL[0] MAC_IF_SEL[1] MAC_IF_SEL[2] SYS_CLK_EN_N LPED_EN_N PRES 1000Base-T speed select Pause mode Auto-MDI detection enable MAC interface select 0 MAC interface select 1 MAC interface select 2 System clock enable Low power energy detection enable Precision resistor I I I I I I I I Pull-up Pull-down Pull-up Pull-down Pull-down Pull-down Pull-up Pull-up -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 82 85 21 18 19 20 15 16 49 50 -- 16 17 18 13 14 42 43 -- 9 10 -- 6 7 I -- -- A 87 51 44 1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configuration and later to select the polarity to drive the LEDs. LSI Corporation 17 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type Internal Pull-Up/ Pull-Down 3-State Analog Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC LED Interface LED_1000 LED_LNK LED_TXRX LED_100 1000Base-T LED Link established LED General-purpose LED General-purpose LED O O I/O I/O Pull-up Pull-down Pull-up Pull-down -- -- -- -- -- -- -- -- 82 85 71 70 49 50 44 43 42 43 37 36 -- -- -- -- -- -- -- -- -- -- 10 14 15 16 17 5 12 13 14 15 2 5 6 7 8 A A A -- -- -- 31 31 32 94 34 25 22 22 23 57 24 -- 16 16 17 50 18 12 A A 79 78 47 46 40 39 JTAG TCK TRST_N TMS TDI TDO Test clock Test reset Test mode select Test data input Test data output I I I I O Pull-up Pull-down Pull-up Pull-up Pull-up Clocking and Reset CLK_IN XTAL_1 XTAL_2 SYS_CLK RESET_N COMA Reference clock input Reference crystal input Reference crystal System clock Reset Hardware powerdown I/O I/O I/O O I I -- -- -- -- -- Pull-down -- -- -- -- -- -- Regulator Control CTRL_1V0 CTRL_2V5 Regulator control 1.0 V Regulator control 2.5 V O O -- -- -- -- 1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configuration and later to select the polarity to drive the LEDs. 18 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 84-Pin MLCC and 68-Pin MCCC (continued) Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type Internal Pull-Up/ Pull-Down 3-State Analog Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC 45 38 Power, Ground, and No Connect VDD_REG Regulator 2.5 V or 3.3 V supply Digital I/O 2.5 V or 3.3 V supply VDD -- -- -- 77 VDD -- -- -- 9, 88, 96, 111, 119 VDD Digital core 1.0 V supply VDD -- -- -- 11, 22, 26, 81, 92, 102 DVSS2 Digital ground VSS -- -- -- AVDDH AVDDL Analog power 2.5 V Analog power 1.0 V VDD VDD -- -- -- -- -- -- 2, 8, 12, 13, 23, 27, 76, 80, 93, 95, 101, 103, 112, 117, 123 30, 51 21, 31 28, 43, 49, 20, 27, 30, 53, 58, 64 33, 36, 39 AVSS2 Analog ground VSS -- -- -- NC Reserved--do not connect -- -- -- -- DVDDIO 29, 40, 42, 46, 48, 50, 55, 57, 61, 63 1, 24, 33, 35, 36, 37, 38, 44, 59, 65, 66, 72, 73, 74, 75, 104, 114, 120, 122 4, 52, 58, 1, 45, 51, 64, 71, 76 53, 59, 62 6, 19, 48, 3, 11, 13, 56, 63 41, 49, 52 -- 4 -- 7, 8, 9, 10, 11 15, 25 14, 21, 24, 27, 30, 33 -- -- 1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configuration and later to select the polarity to drive the LEDs. 2. All AVSS and DVSS pins share a common ground pin (pad) in the center of the device. LSI Corporation 19 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 2. Multiplexed Signals on the ET1011C Default Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Alternate COL 115 73 -- CRS 116 74 -- GTX_CLK 121 77 LED_LNK 85 50 -- -- 63 43 LED_1000 82 49 42 LED_TXRX 71 44 37 LED_100 70 43 36 RX_CLK 113 72 RX_ER 110 70 -- -- 60 -- RX_DV 109 69 TDI 16 14 -- -- 58 7 TMS 15 13 6 TX_ER 124 78 -- TX_EN 125 79 XTAL_1 31 22 -- -- 64 16 COL1, 6 PMA_RX_CLK[1]2 CRS1, 6 COMMA2 GTX_CLK1 PMA_TX_CLK2 TXC3, 4 LED_LNK PAUSE5 LED_1000 SPEED_10005 LED_TXRX PHYAD[0]5 LED_100 PHYAD[1]5 RX_CLK1, 6 PMA_RX_CLK[0]2 RXC3, 4 RX_ER1, 6 RXD[9]2 RX_DV1, 6 RXD[8]2 RX_CTL3, 4 TDI LPED_EN_N5 TMS SYS_CLK_EN_N5 TX_ER1, 6 TXD[9]2 TX_EN1, 6 TXD[8]2 TX_CTL3, 4 XTAL_1 CLK_IN 1. GMII signal. 2. TBI signal. 3. RGMII signal. 20 4. RTBI signal. 5. Reset/configuration signal. 6. MII signal. LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces The following hardware interfaces are included on the ET1011C Gigabit Ethernet transceiver: n MAC interfaces: -- GMII (128-pin TQFP/84-pin MLCC only) -- RGMII -- MII (128-pin TQFP/84-pin MLCC only) -- TBI (128-pin TQFP/84-pin MLCC only) -- RTBI n Configuration interface n LED interface n Clock and reset signals n JTAG interface n Media-dependent interface n Regulator control n Management interface n Power and ground signals Several of the pins of the MAC interface are multiplexed, but they are designed to be interchangeable so that the device can change the MAC interface once the transmission capabilities (1000Base-T, 100Base-TX, and 10Base-T) are established. The following diagram shows the various interfaces on each ET1011C and how they connect to the MAC and other support devices in a typical application. Agere Systems ET1011C ET1011 Gigabit Ethernet PHY GTX_CLK TX_CLK TXD[7:0] TX_ER TX_EN MAC RX_CLK RXD[7:0] RX_ER RX_DV COL CRS MAC_IF_SEL[2:0] PHYAD[4:0] MDC MDIO MDINT_N TCK TRST_N TMS TDI TDO LED_100 LED_TXRX LED_1000 LED_LNK ET1011 ET1011C TRD[0]+/TRD[1]+/TRD[2]+/TRD[3]+/RSET VDD_REG CTRL_2V5 CTRL_1V0 COMA RESET_N XTAL_1 XTAL_2 2.5V Power Plane 1.0V Power Plane Figure 9. ET1011C Gigabit Ethernet Card Block Diagram LSI Corporation 21 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) TX_ER GTX_CLK MAC Interface TXD[7:0] The ET1011C supports RGMII, GMII, MII, RTBI, and TBI interfaces to the MAC. The MAC interface mode is selected via the hardware configuration pins, MAC_IF_SEL[2:0]. Gigabit Media-Independent Interface (GMII) (128-Pin TQFP and 84-Pin MLCC Only) TX_EN RX_CLK MAC RX_ER PHY RX_DV RXD[7:0] The GMII is fully compliant with IEEE 802.3 clause 35. The GMII interface mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 000. CRS COL Figure 10. GMII MAC-PHY Signals Table 3. GMII Signal Description (1000Base-T Mode) (128-Pin TQFP and 84-Pin MLCC only) Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC GTX_CLK 121 77 TX_ER TX_EN 124 125 78 79 TXD[7:0] RX_CLK 7, 6, 5, 4, 3, 128, 127, 126 113 3, 2, 1, 84, 83, 82, 81, 80 72 RX_ER 110 70 RX_DV 109 69 RXD[7:0] 59, 60, 61, 62, 65, 66, 67, 68 CRS 97, 98, 99, 100, 105, 106, 107, 108 116 74 Carrier sense COL 115 73 Collision detect 22 Pin Description Functional Description Transmit clock The MAC drives this 125 MHz clock signal that is held low during autonegotiation or when operating in modes other than 1000Base-T. Transmit error The MAC drives this signal high to indicate a transmit coding error. Transmit The MAC drives this signal high to indicate that data is available on enable the transmit data bus. Transmit data The MAC transmits data synchronized with GTX_CLK to the bits 7--0 ET1011C for transmission on the media-dependent (transformer) interface. Receive clock The ET1011C generates a 125 MHz clock to synchronize receive data. Receive error The ET1011C drives RX_ER to indicate that an error was detected in the frame that was received and is being transmitted to the MAC. Receive data The ET1011C drives RX_DV to indicate that it is sending recovvalid ered and decoded data to the MAC. Receive data The ET1011C transmits data that is synchronized with RX_CLK to the MAC. The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011C whenever the receive medium is nonidle. In halfduplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15. In 10Base-T, 100Base-TX, and 1000Base-T half-duplex modes, COL is asserted when both transmit and receive media are nonidle. LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) TXC Reduced Gigabit Media-Independent Interface (RGMII) The RGMII interface is fully compliant with the RGMII Rev. 1.3 specification. The RGMII interface mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 100 or 110. (See Table 10 on page 30 for further information on MAC_IF_SEL pin operation.) TXD[3:0] TX_CTL MAC PHY RXC RXD[3:0] RX_CTL Figure 11. RGMII MAC-PHY Signals Table 4. RGMII Signal Description (1000Base-T Mode) Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Pin Description TXC 121 77 63 Transmit clock Functional Description The MAC drives this 125 MHz clock signal that is held low during autonegotiation. To obtain the 1 Gbit transmission rate, the MAC uses both the positive and negative clock transitions. TXD[3:0] 3, 128, 127, 83, 82, 68, 67, 66, Transmit data bits The MAC transmits data synchronized with TXC to 126 81, 80 65 the ET1011C for transmission on the media-dependent (transformer) interface. The MAC transmits bits 3:0 on a positive transition of TXC and bits 7:4 on a negative transition of TXC. TX_CTL 125 79 64 Transmit control The MAC transmits control signals across this line (TX_ER and TX_EN). The MAC transmits TX_EN1 on a positive transition of TXC and TX_EN and TX_ER1 on the negative transition of TXC. RXC 113 72 60 Receive clock The ET1011C generates a 125 MHz clock to synchronize receive data. To obtain the 1 gigabit transmission rate, the ET1011C uses both the positive and negative clock transitions. RXD[3:0] 105, 106, 65, 66, 67, 54, 55, 56, Receive data The ET1011C transmits data that is synchronized 107, 108 68 57 with RX_CLK to the MAC. The ET1011C transmits bits 3:0 on a positive transition of RXC and bits 7:4 on the negative transition of RXC. RX_CTL 109 69 58 Receive control The ET1011C transmits control signals across this line (RX_ER and RX_EN). The ET1011C transmits RX_DV1 on a positive transition of RXC and RX_EN1 and RX_ER1 on the negative transition of TXC. 1. Reference the GMII interface for description of the following parameters: TX_EN, TX_ER, RX_DV, RX_EN, and RX_ER. LSI Corporation 23 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Media-Independent Interface (128-Pin TQFP and 84-Pin MLCC Only) 25 MHz at the GTX_CLK pin. The ET1011C then uses a FIFO to resynchronize data presented synchronously with this reference clock. TX_CLK The MII is fully compliant with IEEE 802.3 clause 22. The MII interface mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 000. In 100Base-TX and 10Base-T mode, the RXD[7:4] pins are driven low by the ET1011C and the TXD[7:4] pins are ignored. They should not be left floating but should be set either high or low. In the MII interface mode, the GTX_CLK pin may be held low. An alternative to the standard MII is provided when operating in 10Base-T or 100Base-TX mode by setting hardware configuration pins MAC_IF_SEL[2:0] = 010. In this alternative interface, the MAC provides a reference clock at 2.5 MHz or TX_ER TX_EN TXD[3:0] RX_CLK MAC RX_ER PHY RX_DV RXD[3:0] CRS COL Figure 12. MII Signals Table 5. MII Interface (100Base-TX and 10Base-T) (128-Pin TQFP and 84-Pin MLCC Only) Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin Description TX_CLK 118 75 Transmit clock GTX_CLK TX_ER TX_EN TXD[3:0] RX_CLK RX_ER RX_DV RXD[3:0] CRS COL 24 Functional Description In 100Base-TX mode, the ET1011C generates 25 MHz reference clocks and in 10Base-T mode provides 2.5 MHz reference clocks. MAC_IF_SEL[2:0] = 000--this is default behavior. 121 77 Alternate In 100Base-TX mode, the MAC generates the 25 MHz reference clock and transmit clock in 10Base-T mode provides a 2.5 MHz reference clock. MAC_IF_SEL[2:0] = 010. 124 78 Transmit error The MAC drives this signal high to indicate a transmit coding error. 125 79 Transmit The MAC drives this signal high to indicate that data is available on the enable transmit data bus. 3, 128, 83, 82, 81, Transmit data The MAC transmits data synchronized with TX_CLK to the ET1011C for 127, 126 80 bits transmission on the media-dependent (transformer) interface. 113 72 Receive clock In 100Base-TX mode, the ET1011C generates 25 MHz reference clocks and in 10Base-T mode provides 2.5 MHz reference clocks. 110 70 Receive error The ET1011C drives RX_ER to indicate that an error was detected in the frame that was received and is being transmitted to the MAC. 109 69 Receive data The ET1011C drives RX_DV to indicate that it is sending recovered and valid decoded data to the MAC. 105, 106, 65, 66, 67, Receive data The ET1011C transmits data synchronized with RX_CLK to the MAC. 107, 108 68 bits 116 74 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011C whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15. 115 73 Collision In 10Base-T, 100Base-TX, and 1000Base-T half-duplex modes, COL is detect asserted when both transmit and receive media are nonidle. LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) PMA_TX_CLK Ten-Bit Interface (TBI) (128-Pin TQFP and 84-Pin MLCC Only) TXD[9] The TBI is fully compliant with IEEE 802.3 clause 36. It may be used as an alternative to the GMII in 1000Base-T mode. The TBI mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 001. TXD[8] TXD[7:0] GTX-CLK TX_ER TX_EN TXD[7:0] PMA_RX_CLK MAC RX_CLK RXD[9] RXD[8] RXD[7:0] PHY RX_ER RX_DV RXD[7:0] PMA_RX_CLK[1] COL COMMA CRS Figure 13. Ten-Bit Interface Table 6. Ten-Bit Interface (1000Base-T) (128-Pin TQFP and 84-Pin MLCC Only) Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin Description Functional Description PMA_TX _CLK 121 77 TBI transmit clock The MAC drives this 125 MHz clock signal and should be held low during autonegotiation or when operating in modes other than 1000Base-T. The MAC transmits data synchronized with PMA_TX_CLK to the ET1011C for transmission on the media-dependent (transformer) interface. 124, 125, 7, 78, 79, 3, 2, 6, 5, 4, 3, 1, 84, 83, 82, 81, 80 128, 127, 126 PMA_RX _CLK[0] 113 72 TXD[9:0] RXD[9:0] 110, 109, 97, 98, 99, 100, 105, 106, 107, 108 PMA_RX _CLK[1] 115 COMMA LSI Corporation 116 70, 69, 59, 60, 61, 62, 65, 66, 67, 68 73 74 Transmit data bits Receive clock The ET1011C generates a 62.5 MHz clock to synchronize receive data for the odd code group. This signal is 180 degrees out of phase from PMA_RX_CLK[1]. Receive data bits The ET1011C transmits data that is synchronized with PMA_ RX_CLK[0] to the MAC. Receive clock Comma signal The ET1011C generates a 62.5 MHz clock to synchronize receive data for the even code group. This signal is 180 degrees out of phase from PMA_RX_CLK[0]. This signal indicates that COMMA has been detected. 25 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) TXC Reduced Ten-Bit Interface (RTBI) TXD[3:0] TXD[4:0] The RTBI is fully compliant with RGMII rev 1.3 specification. The RTBI mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 101 or 111. (See Table 10 on page 30 for further information on MAC_IF_SEL pin operation.) TX_CTL MAC PHY RXC RXD[3:0] RXD[4:0] RX_CTL Figure 14. Reduced Ten-Bit Interface Table 7. RTBI Signal Description (1000Base-T Mode) Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Pin Description TXC 121 77 63 Transmit clock TXD[3:0] 3, 128, 127, 126 83, 82, 81, 80 68, 67, 66, 65 TX_CTL 125 79 64 RXC 113 72 60 RXD[3:0] RX_CTL 26 105, 106, 65, 66, 67, 107, 108 68 109 69 54, 55, 56, 57 58 Functional Description The MAC drives this 125 MHz clock signal that is held low during autonegotiation. Transmit data bits The MAC transmits data synchronized with TXC to the ET1011C for transmission on the media-dependent (transformer) interface. The MAC transmits bits 3:0 on a positive transition of TXC and bits 8:5 on a negative transition of TXC. Transmit control The MAC transmits bit 5 and bit 10 synchronized with TXC to the ET1011C for transmission on the mediadependent (transformer) interface. The MAC transmits bit 5 on a positive transition of TXC and bit 10 on the negative transition of TXC. Receive clock The ET1011C generates a 125 MHz clock to synchronize receive data. Receive data The ET1011C transmits data that is synchronized with RXC to the MAC. The ET1011C transmits bits 3:0 on a positive transition of RXC and bits 8:5 on the negative transition of RXC. Receive control The ET1011C transmits bit 5 and bit 10 synchronized with RXC to the MAC. The ET1011C transmits bit 5 on a positive transition of RXC and bit 10 on the negative transition of RXC. LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Management Interface Serial Management Interface The MII management interface (MI) provides a simple, two-wire serial interface between the MAC and the PHY to allow access to control and status information in the internal registers of the ET1011C. The interface is compliant with IEEE 802.3 clause 22 and is compatible with the clause 45.3, enabling the two systems to co-exist on the same MDIO bus. Management Frame Structure Frames transmitted on the MI have the following structure. Table 8. Management Frame Structure PRE Read Write n n n n n n n n 1. . . 1 1...1 ST 01 01 OP 10 01 PHYAD aaaaa aaaaa REGAD rrrrr rrrrr TA ZO 10 DATA d...d d...d IDLE Z Z PRE (preamble): At the beginning of each transaction, the MAC may send a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use to establish synchronization. The ET1011C supports MF preamble suppression, and thus the MAC may initiate management frames with the ST (start of frame) pattern. ST (start of frame): The start of frame is indicated by a <01> pattern. This pattern ensures transitions from the default logic one line state to zero and back to one. When a clause 45 start of frame <00> is received, the frame is ignored. OP (operation code): The operation code for a read transaction is <10>, while the operation code for a write transaction is <01>. PHYAD (PHY address): The PHY address is 5 bits. The first PHY address bit transmitted and received is the MSB of the address. Only the PHY that is addressed will respond to the MI operation. REGAD (register address): The register address is 5 bits. The first register address bit transmitted and received is the MSB of the address. TA (turnaround): The turnaround time is a 2-bit time spacing between the register address field and the data field of a management frame to avoid contention during a read transaction. For a read transaction, the PHY remains in a high-impedance state for the first bit time of the turnaround and drives a zero bit during the second bit time of the turnaround. During a write transaction, the PHY expects a one for the first bit time of the turnaround and a zero for the second bit time of the turnaround. DATA (data): The data field is 16 bits. The first data bit transmitted and received is the MSB of the register being addressed. IDLE (idle condition): The IDLE condition on MDIO is a high-impedance state, and the ET1011C internal pull-up resistor will pull the MDIO line to logic one. LSI Corporation 27 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Table 9. Management Interface Pin Name PHYAD [4:0] Pin # 128-Pin TQFP Pin # 84-Pin MLCC 67, 68, 69, 40, 41, 42, 70, 71 43, 44 91 55 48 MDIO 90 54 47 89 53 Functional Description 34, 35, PHY Address 36, 37 (PHYAD [3:0]) MDC MDINT_N Pin Description Pin # 68-Pin MLCC The physical address of the ET1011C is configured at reset by the current state of the PHYAD[4:0] pins. Once these pins have been latched in at reset, the ET1011C is accessible via the management interface at the configured address. The default address is set to 1 by internal pull-up/downs. These may be overridden by external pull-up/downs. The valid range is 0 to 311. Management The management data clock (MDC) is a reference for the Interface Clock data signal and is generated by the MAC. It can be turned off when the MI is not being used. This pin has an internal pulldown resistor. MDC is nominally 2.5 MHz, and can work up to a maximum of 12.5 MHz. Management The management data input/output (MDIO) is a bidirectional Data I/O data signal between the MAC and one or more PHYs. MDIO is a 3-state pin that allows either the MAC or the selected PHY to drive this signal. This pin has an internal pull-up resistor. An external pull-up resistor should also be used, the exact value depending on the number of PHYs sharing the MDIO signal. Data signals written by the MAC are sampled by the PHY synchronously with respect to the MDC. Data signals written by the PHY are generated synchronously with respect to the MDC. This pin requires an external pull-up (1 k to 10 k). Management This pin is active-low and indicates an unmasked manageInterface ment interrupt. This pin requires an external pull-up resistor (1 k to 4.7 k). Pin is open drain. Interrupt 46 1. PHYAD description applies to the 84-MLCC only. For the 68-MLCC, the valid range will be 0--15. Management Interrupt The ET1011C is capable of generating hardware interrupts on pin MDINT_N in response to a variety of user-selectable conditions. MDINT_N is an open-drain, active-low signal that can be wire-ORed with several other ET1011C devices. A single 2.2 k pull-up resistor is recommended for this wire-OR configuration. When an interrupt occurs, the system can poll the status of the interrupt status register on each device to determine the origin of the interrupt. There are nine conditions that can be selected to generate an interrupt: n n n Autonegotiation status change Autonegotiation page received FIFO overflow/underflow n n n Link status change CRC errors Full error counter n n n Local/remote rx status change Automatic speed downshift occurred MDIO synchronization lost The ET1011C is configured to generate an interrupt based on any of these conditions by use of the interrupt mask register (MII register 24). By setting the corresponding bit in the interrupt mask register for the desired condition, the ET1011C will generate the desired interrupt. The ET1011C can be polled on the status of an activated interrupt condition by accessing MII register interrupt status register (MII register 25). If this condition has occurred, the corresponding bit in the interrupt status register will be set. The interrupt status register is self-clearing on a read operation. 28 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Configuration Interface The hardware configuration pins listed in Table 10 initialize the ET1011C at power-on and reset. The configuration is latched during initialization and stored. These pins set the default value of their corresponding MII register bits. Some configuration inputs are shared with LED pins. The hardware configuration and LED pins are read on initial powerup of the ET1011C, during a hardware reset and during recovery from hardware powerdown. The logic value at the pin is sensed and latched. After RESET_N has been deasserted (raised high), the shared configuration pins become outputs that are used to drive LEDs. (For details on sharing LED and configuration pins, refer to the application note, TruePHY ET1011 Gigabit Ethernet PHY Design and Layout Guide.) Table 10. Configuration Signals Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Pin Description Functional Description SPEED_1000 82 49 42 Speed 1000 The SPEED_1000 configuration pin sets the default advertised speed. The deassertion of SPEED_1000 disables advertisement of the 1000Base-T to the remote end. The default is to advertise all three speeds. PAUSE 85 50 43 Pause This input sets the pause mode. If PAUSE is asserted, full-duplex pause and asymmetric pause operation are advertised. 0 = Don't advertise pause (default).1 = Advertise full-duplex pause and asymmetric pause. SYS_CLK_EN_N 15 13 6 SYS_CLK Enable Enables the system clock. If SYS_CLK_EN_N is asserted when RESET_N is low, SYS_CLK will be enabled and will continue to be generated while RESET_N is low. If SYS_CLK_EN_N is not asserted when RESET_N is low, then SYS_CLK is disabled. 0 = SYS_CLK enabled. 1 = SYS_CLK disabled (default). See Low Power Modes on page 11 for additional information. LPED_EN_N 16 14 7 Low Power Energy Detection Enable LPED_EN_N enables the low-power energydetect (LPED) mode when COMA is asserted. See Low Power Modes on page 11 for additional information. When the PHY is in LPED mode, it can wake the MAC/controller (instead of Magic Packet) by asserting the MDINT_N pin to indicate the presence of cable energy. 0 = Low-power energy-detect mode enable. 1 = Low-power energy-detect mode disabled (default). PRES LSI Corporation 87 51 44 Precision Resistor Connect a 1.0 k precision resistor to ground to set termination for all digital I/Os. 29 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Table 10. Configuration Signals (continued) Pin Name MAC_IF_ SEL[2:0] Pin # Pin # 128-Pin 84-Pin TQFP MLCC 20 18 19 17 18 16 Pin Pin # Description 68-Pin MLCC MAC Inter-- face Mode 10 9 (MAC_IF_ SEL[1:0] (See Note 1.) Functional Description This input selects the desired MAC interface mode. Configure the MAC during reset as follows: 000 = GMII/MII (84-Pin MLCC default). 001 = TBI. 010 = GMII/MII (clocked by GTX_CLK instead of TX_CLK). 011 = Reserved. 100 = RGMII/RMII (RXC DLL delay; 68-MLCC default)1. 101 = RTBI (RXC DLL delay)1. 110 = RGMII/RMII (RXC and TXC DLL delay)1. 111 = RTBI (RXC and TXC DLL delay)1. 1. In the 68-MLCC, MAC_IF_SEL 2 (= 1) will be set internally. Also, for all package types: -- MAC_IF_SEL pins = 100 will set MAC interface mode select bits in register 22.2:0 = 110; alternative RGMII TXC DLL Delay bit 23.6 = 1. -- MAC_IF_SEL pins = 101 will set MAC interface mode select bits in register 22.2:0 = 111; alternative RGMII TXC DLL Delay bit 23.6 = 1. -- MAC_IF_SEL pins = 110 will set MAC interface mode select bits in register 22.2:0 = 110; alternative RGMII TXC DLL Delay bit 23.6 = 0. -- MAC_IF_SEL pins = 111 will set MAC interface mode select bits in register 22.2:0 = 111; alternative RGMII TXC DLL Delay bit 23.6 = 0. 30 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) LEDs Interface The ET1011C is capable of sinking or sourcing current to drive LEDs. These LEDs are used to provide link status information to the user. The ET1011C is capable of automatically sensing the polarity of the LEDs. The device determines the active sense of the LED based upon the input that is latched during configuration. Thus, if logic 1 is read, the device will drive the pin to ground to activate the LED; otherwise, it will drive the pin to supply to activate the LED. The LEDs can be programmed to stretch out events to either 28, 60, or 100 ms. This makes very short events more visible to the user. All LEDs can be programmed to be on, off, or blink instead of the default status function. This is useful for alternative function indication under host processor control: for example, a system error during power-on self-check. All LEDs can be programmed to indicate one of thirteen different status functions instead of the default status function: n 1000Base-T n Transmit or receive activity n 100Base-TX n Full duplex n 10Base-T n Collision n 1000Base-T (on) and 100Base-TX (blink) n Link established (on) and activity (blink) n Link established n Link established (on) and receive activity (blink) n Transmit activity n Full duplex (on) and collision (blink) n Receive activity The LED drivers can be configured by use of LED control register 1, LED control register 2, and LED control register 3 (MII registers 27--29). Table 11. LED Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC LED_1000 82 49 42 1000Base-T LED LED_LNK 85 50 43 LED_TXRX LED_100 71 70 44 43 37 36 Link Established LED General-Purpose LEDs LSI Corporation Pin Description Functional Description This LED indicates that the device is operating in 1000Base-T mode. Setting can be overridden. This LED indicates that the link is established. Setting can be overridden. Set to be off by default. 31 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Media-Dependent Interface: Transformer Interface Table 12. Transformer Interface Signals Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC TRD[0]+ TRD[0]- 39 41 25 26 19 20 Pin Description Functional Description Transmit and Connect this signal pair through a transformer to the Receive Differen- media-dependent interface. tial Pair 0 In 1000Base-T mode, transmit and receive occur simultaneously at TRD[0]. In 10Base-T and 100Base-TX modes, TRD[0] are used to transmit when operating in the MDI configuration and to receive when operating in the MDI-X configuration. TRD[1]+ TRD[1]- 45 47 28 29 22 23 The PHY automatically determines the appropriate MDI/MDI-X configuration. Transmit/Receive Connect this signal pair through a transformer to the Differential Pair 1 media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[1]. In 10Base-T and 100Base-TX modes, TRD[1] are used to receive when operating in the MDI configuration and to transmit when operating in the MDI-X configuration. TRD[2]+ TRD[2]- 54 56 34 35 28 29 The PHY automatically determines the appropriate MDI/MDI-X configuration. Transmit/Receive Connect this signal pair through a transformer to the Differential Pair 2 media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[2]. TRD[3]+ TRD[3]- 60 62 37 38 31 32 In 10Base-T and 100Base-TX modes, TRD[2] are unused. Transmit/Receive Connect this signal pair through a transformer to the Differential Pair 3 media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[3]. RSET 52 32 26 In 10Base-T and 100Base-TX modes, TRD[3] are unused. Analog Reference RSET sets an absolute value reference current for the Resistor transmitter. Connect this signal to analog ground through a precision 6.34 k 1% resistor. 32 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Clocking and Reset Table 13. Clocking and Reset Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC CLK_IN 31 22 16 XTAL_1 31 22 16 XTAL_2 32 23 17 SYS_CLK 94 57 50 RESET_N 34 24 18 Pin Description Reference Clock Input Reference Crystal Input Reference Crystal Input System Clock Reset Functional Description Connect this signal to a 25 MHz clock input (CLK_IN will only accept a 2.5V signal) or a 25 MHz 50 ppm tolerance crystal (XTAL_1). Connect this signal to a 25 MHz 50 ppm tolerance crystal. Float this signal if an external clock is used (CLK_IN). Use this signal to supply a 125 MHz clock to the MAC. By default, the SYS_CLK output is disabled. The SYS_CLK output can be enabled by asserting the SYS_CLK_EN_N pin or via the management interface. Drive RESET_N low for 20 s to initiate a hardware reset. The ET1011C completes all reset operations within 5 ms of this signal returning to a high state. The configuration pins and the physical address configuration are read during a hardware reset. COMA 25 -- 12 Hardware Powerdown See Low Power Modes on page 11 for additional information. Drive COMA high to initiate a hardware powerdown. The ET1011C completes all reset operations within 5 ms of this signal returning to a low state. All hardware functions are disabled during a hardware powerdown. The configuration pins and the physical address configuration are read during a hardware powerdown. See Low Power Modes on page 11 for additional information. LSI Corporation 33 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) JTAG The ET1011C has a standard IEEE 1149.1 JTAG test interface. The interface provides extensive test and diagnostics capability. It contains internal circuitry that allows the device to be controlled through the JTAG port to provide on-chip, in-circuit emulation. The JTAG interface is a bidirectional serial interface with its own reset strobe (TRST_N). The reset strobe can be used independently to reset the JTAG state machine but must be used during a power-on reset (see Reset Timing on page 78). Table 14. JTAG Test Interface Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Pin Description TDI 16 14 7 Test Data Input TDO 17 15 8 Test Data Output TCK 10 5 2 Test Clock TMS 15 13 6 TRST_N 14 12 5 Test Mode Select Test Reset (JTAG Reset) Functional Description This signal is the JTAG serial input. All instructions and scanned data are input using this pin. This pin has an internal pull-up resistor. This signal is the JTAG serial output. Scanned data and status bits are output using this pin. This pin has an internal pull-up resistor. This signal is the JTAG serial shift clock. It clocks all of the data that passes through the port on TDI and TDO. This pin has an internal pull-up resistor. This signal is the JTAG test mode control. This pin has an internal pull-up resistor. This signal is active-low and causes the JTAG TAP controller to enter the reset state. This pin has an internal pull-down resistor. Regulator Control The ET1011C has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or 2.5 V. The on-chip regulator control circuits provide output control voltages that can be used to control two external transistors and thus provide regulated 1.0 V and 2.5 V supplies. Table 15. Regulator Control Interface Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC CTRL_1V0 79 47 40 Regulator Control for 1.0 V This is the regulator output control voltage for the 1.0 V supply. It is used to control an external transistor and thus provide a regulated 1.0 V supply. CTRL_2V5 78 46 39 Regulator Control for 2.5 V This is the regulator output control voltage for the 2.5 V supply. It is used to control an external transistor and thus provide a regulated 2.5 V supply. 34 Pin Description Functional Description LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Regulator Control (continued) The ET1011C digital and analog core operates at 1.0 V. The analog I/O operates at 2.5 V. The digital I/O can operate at either 3.3 V or 2.5 V. The GMII interface operates at 3.3 V and the RGMII interface operates at 2.5 V. The on-chip regulator control allows the device to be operated from a wide variety of external supply combinations. When more than one external supply is available, one or both of the regulator control circuits may be left unused. Table 16 lists example combinations of available external supplies and shows how the on-chip regulator control may be used to provide the required supplies. Table 16. Supply Voltage Combinations Available External Supplies AVDDL DVDD AVDDH VDD_REG1 Description 3.3 V only 1.0 1.0 2.5 3.3 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 1.0 V and 2.5 V. 2.5 V only 1.0 1.0 2.5 2.5 Digital I/O is 2.5 V. Regulator control is used to provide 1.0 V. 3.3 V and 1.0 V 1.0 1.0 2.5 3.3 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 2.5 V. 2.5 V and 1.0 V 1.0 1.0 2.5 2.5 Digital I/O is 2.5 V. Regulator controls are not connected. 3.3 V and 2.5 V 1.0 1.0 2.5 3.3 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 1.0 V. 3.3 V, 2.5 V, and 1.0 V 1.0 1.0 2.5 3.3 or 2.5 Digital I/O can be either 3.3 V or 2.5 V. Regulator controls are not connected. 1. Even if the regulator controls are not connected, VDD_REG must be powered. Power, Ground, and No Connect Table 17. Power, Ground, and No Connect Pin Name Pin Description Functional Description VDD_REG VDD Regulator 2.5 V or 3.3 V supply. DVDDIO VDD Digital I/O 3.3 V or 2.5 V supply. DVDD VDD Digital core 1.0 V supply. DVSS VSS Digital ground1. AVDDH VDD Analog power 2.5 V. AVDDL VDD Analog power 1.0 V. AVSS VSS Analog ground1. NC No Connect Reserved--do not connect. 1. For 84-pin MLCC and 68-pin MLCC, all AVSS and DVSS pins share a common ground pin (exposed pad) in the center of the device. LSI Corporation 35 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Cable Diagnostics The ET1011C has on-chip cable diagnostics. The cable analysis uses two distinct methods for evaluating the cable: link analysis and time domain reflectometry (TDR) analysis. This analysis can be used to detect cable impairments that may be preventing a gigabit link or affecting performance. When there is a link active, the link analysis can detect cable length, link quality, pair skew, pair swaps (MDI/MDI-X configuration), and polarity reversal. When there is no link, TDR can detect cable faults (open circuit, short circuit), distance to the fault, pair fault is on, cable length, pair skew, and excessive crosstalk. Table 18 summarizes the specifications of the cable diagnostic functions. Table 18. Cable Diagnostic Functions Feature Detection of Cable Fault on Any Pair Detect Polarity Reversal Good Cable with Link Description 10 100 1000 Term Unterm Analysis Cable open -- -- -- 3 3 Cable short -- -- -- 3 3 Line Probing Indicate distance to fault -- -- -- 2 m 2 m Pair swaps 3 3 31 -- -- Link Analysis 3 -- -- Link Analysis 10 m -- -- Link Analysis -- Indicate length 2 3 -- -- 10 m 3 Good Cable Without Link Indicate length -- -- -- 5 m 2 m Line Probing Pair Skew with Link Detect excessive, >50 ns -- -- 3 -- -- Link Analysis Pair Skew Without Link Detect excessive, >50 ns -- -- -- 33 3 Line Probing Excessive Crosstalk Cable quality or split pairs -- -- -- 3 3 Line Probing 1. Pair swaps on C and D as well as pairs A and B are reported. 2. Polarity reversal in 100Base-TX is not detected because MLT-3 signaling is polarity insensitive. 3. If the magnitude of the peak reflection is greater than 15% of an open circuit. 36 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description Register Address Map Table 19. Register Address Map Address 0 1 2 3 4 5 6 7 8 9 10 11--14 15 16--17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Description Control register. Status register. PHY identifier register 1. PHY identifier register 2. Autonegotiation advertisement register. Autonegotiation link partner ability register. Autonegotiation expansion register. Autonegotiation next page transmit register. Link partner next page register. 1000Base-T control register. 1000Base-T status register. Reserved. Extended status register. Reserved. PHY control register 2. Loopback control register. RX error counter register. Management interface (MI) control register. PHY configuration register. PHY control register. Interrupt mask register. Interrupt status register. PHY status register. LED control register 1. LED control register 2. LED control register 3. Diagnostics control register. Diagnostics status register (TDR mode). Table 20. Register Type Definition Type Description LL LH R/W RO Latching low. Latching high. Read write. Register can be read or written. Read only. Register is read only. Writes to register are ignored. Self-clearing. Register is self-clearing; if a one is written, the register will automatically clear to zero after the function is completed. SC LSI Corporation 37 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings Table 21. Control Register--Address 0 Control Register Bit 15 14 13 12 11 10 9 8 7 6 5:0 Name Reset Description 1 = PHY reset. 0 = Normal operation. Loopback 1 = Enable loopback. 0 = Disable loopback. Speed Selection Bit 6,13. (LSB) 11 = Reserved. 10 = 1000 Mbits/s. 01 = 100 Mbits/s. 00 = 10 Mbits/s. Autonegotiation 1 = Enable autonegotiation process. Enable 0 = Disable autonegotiation process. Powerdown 1 = Powerdown. 0 = Normal operation. Isolate 1 = Isolate PHY from MII. 0 = Normal operation. Restart Autonegotia- 1 = Restart autonegotiation process. tion 0 = Normal operation. Duplex Mode 1 = Full duplex. 0 = Half duplex. Collision Test 1 = Enable collision test. 0 = Disable collision test. Speed Selection See bit 13. (MSB) Reserved -- Type Default Notes R/W SC R/W 0 1 0 2 R/W SPEED_1000 3 R/W 1 4 R/W 0 -- R/W 0 5 R/W SC R/W 0 -- 1 6 R/W 0 7 R/W See bit 13. 3 RO 0 -- 1. The reset bit is automatically cleared upon completion of the reset sequence. This bit is set to 1 during reset. 2. This is the master enable for digital and analog loopback as defined by the standard. The exact type of loopback is determined by the loopback control register (address 19). 3. The speed selection address 0 bits 13 and 6 may be used to configure the link manually. Setting these bits has no effect unless address 0 bit 12 is clear. 4. When this bit is cleared, the link configuration is determined manually. 5. Setting this bit isolates the PHY from the MII, GMII, or RGMII interfaces. 6. This bit may be used to configure the link manually. Setting this bit has no effect unless address 0 bit 12 is clear. 7. Enables IEEE 22.2.4.1.9 collision test. 38 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 22. Status Register--Address 1 Status Register Bit Name Description Type Default Notes 15 100Base-T4 0 = Not 100Base-T4 capable. RO 0 1 14 100Base-X Full Duplex 1 = 100Base-X full-duplex capable. 0 = Not 100Base-X full-duplex capable. RO 1 -- 13 100Base-X Half Duplex 1 = 100Base-X half-duplex capable. 0 = Not 100Base-X half-duplex capable. RO 1 -- 12 10Base-T Full Duplex 1 = 10Base-T full-duplex capable. 0 = Not 10Base-T full-duplex capable. RO 1 -- 11 10Base-T Half Duplex 1 = 10Base-T half-duplex capable. 0 = Not 10Base-T half-duplex capable. RO 1 -- 10 100Base-T2 Full Duplex 0 = Not 100Base-T2 full-duplex capable. RO 0 -- 9 100Base-T2 Half Duplex 0 = Not 100Base-T2 half-duplex capable. RO 0 -- 8 Extended Status 1 = Extended status information in register 0Fh. RO 1 -- 7 Reserved RO -- -- 6 MF Preamble Suppression 1 = Preamble suppressed management frames accepted. RO 1 -- 5 Autonegotiation Complete 1 = Autonegotiation process complete. 0 = Autonegotiation process not complete. RO 0 2 4 Remote Fault 1 = Remote fault detected. 0 = No remote fault detected. RO LH 0 3 3 Autonegotiation Ability 1 = Autonegotiation capable. 0 = Not autonegotiation capable. RO 1 -- 2 Link Status 1 = Link is up. 0 = Link is down. RO LL 0 4 1 Jabber Detect 1 = Jabber condition detected. 0 = No jabber condition detected. RO LH 0 -- 0 Extended Capability 1 = Extended register capabilities. RO 1 5 -- 1. The ET1011C does not support 100Base-T4 or 100Base-T2; therefore, these register bits will always be set to zero. 2. Upon completion of autonegotiation, this bit becomes set. 3. This bit indicates that a remote fault has been detected. Once set, it remains set until it is cleared by reading register 1 via the management interface or by PHY reset. 4. This bit indicates that a valid link has been established. Once cleared due to link failure, this bit will remain cleared until register 1 is read via the management interface. 5. Indicates that the PHY provides an extended set of capabilities that may be accessed through the extended register set. For a PHY that incorporates a GMII/RGMII, the extended register set consists of all management registers except registers 0, 1, and 15. LSI Corporation 39 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 23. PHY Identifier Register 1--Address 2 PHY Identifier Register 1 Bit 15:0 Name PHY Identifier Bits 3:18 Description Type Default Notes RO 0x0282 1 Type Default Notes Organizationally unique identifier (OUI), bits 19:24. RO 111100 1 Model number = 1. Revision number = 4. RO RO 000001 0100 -- -- Organizationally unique identifier (OUI), bits 3:18. Table 24. PHY Identifier Register 2--Address 3 PHY Identifier Register 2 Bit 15:10 9:4 3:0 Name PHY Identifier Bits 19:24 Model Number Revision Number Description 1. The LSI OUI is 00-05-3D. 40 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 25. Autonegotiation Advertisement Register--Address 4 Autonegotiation Advertisement Register 1 Bit Name Description Default Notes R/W 0 -- RO 0 -- R/W 0 -- RO 0 -- 15 Next Page 14 Reserved 13 Remote Fault 12 Reserved 11 Asymmetric Pause 1 = Advertise asymmetric pause ability. 0 = Advertise no asymmetric pause ability. R/W PAUSE 1 10 Pause Capable 1 = Capable of full-duplex pause operation. 0 = Not capable of pause operation. R/W PAUSE 1 9 100Base-T4 Capabil- 1 = 100Base-T4 capable. ity 0 = Not 100Base-T4 capable. R/W 0 2 8 100Base-TX FullDuplex Capable 1 = 100Base-TX full-duplex capable. 0 = Not 100Base-TX full-duplex capable. R/W 1 -- 7 100Base-TX HalfDuplex Capable 1 = 100Base-TX half-duplex capable. 0 = Not 100Base-TX half-duplex capable. R/W 1 -- 6 10Base-T FullDuplex Capable 1 = 10Base-T full-duplex capable. 0 = Not 10Base-T full-duplex capable. R/W 1 -- 5 10Base-T HalfDuplex Capable 1 = 10Base-T half-duplex capable. 0 = Not 10Base-T half-duplex capable. R/W 1 -- Selector Field 00001 = IEEE 802.3 CSMA/CD. R/W 00001 -- 4:0 1 = Advertise next page ability supported. 0 = Advertise next page ability not supported. Type -- 1 = Advertise remote fault detected. 0 = Advertise no remote fault detected. -- 1. Value read from PAUSE on reset. 2. The ET1011C does not support 100Base-T4, so the default value of this register bit is zero. Note: Any write to this register prior to the completion of autonegotiation is followed by a restart of autonegotiation. Also note that this register is not updated following autonegotiation. LSI Corporation 41 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 26. Autonegotiation Link Partner Ability Register--Address 5 Autonegotiation Link Partner Ability Register Bit 15 Next page 14 Acknowledge 13 Remote Fault 12 11 Reserved Asymmetric Pause 10 Pause Capable 9 100Base-T4 Capability 100Base-TX FullDuplex Capable 8 7 100Base-TX HalfDuplex Capable 6 10Base-T FullDuplex Capable 10Base-T HalfDuplex Capable Protocol Selector Field 5 4:0 42 Name Description Type Default Notes 1 = Link partner has next page ability. 0 = Link partner does not have next page ability. 1 = Link partner has received link code word. 0 = Link partner has not received link code word. 1 = Link partner has detected remote fault. 0 = Link partner has not detected remote fault. -- 1 = Link partner desired asymmetric pause. 0 = Link partner does not desire asymmetric pause. 1 = Link partner capable of full-duplex pause operation. 0 = Link partner is not capable of pause operation. 1 = Link partner is 100Base-T4 capable. 0 = Link partner is not 100Base-T4 capable. 1 = Link partner is 100Base-TX full-duplex capable. 0 = Link partner is not 100Base-TX full-duplex capable. 1 = Link partner is 100Base-TX half-duplex capable. 0 = Link partner is not 100Base-TX half-duplex capable. 1 = Link partner is 10Base-T full-duplex capable. 0 = Link partner is not 10Base-T full-duplex capable. 1 = Link partner is 10Base-T half-duplex capable. 0 = Link partner is not 10Base-T half-duplex capable. Link partner protocol selector field. RO 0 -- RO 0 -- RO 0 -- RO RO 0 0 -- -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 27. Autonegotiation Expansion Register--Address 6 Autonegotiation Expansion Register Bit Name 15:5 4 Reserved Parallel Detection Fault Link Partner Next Page Ability Next Page Capability Page Received 3 2 1 0 Link Partner Autonegotiation Ability Description Type Default Notes RO RO LH RO -- 0 -- -- 0 -- RO LH RO LH RO 1 -- 0 -- 0 -- Description Type Default Notes 1 = Additional next pages follow. 0 = Sending last next page. -- 1 = Formatted page. 0 = Unformatted page. 1 = Complies with message. 0 = Cannot comply with message. 1 = Previous value of transmitted link code word was logic zero. 0 = Previous value of transmitted link code word was logic one. Next page message code or unformatted data. R/W 0 -- RO R/W 0 1 -- -- R/W 0 -- RO 0 -- R/W 1 -- -- 1 = Parallel link fault detected. 0 = Parallel link fault not detected. 1 = Link partner has next page capability. 0 = Link partner does not have next page capability. 1 = Local device has next page capability. 0 = Local device does not have next page capability. 1 = New page has been received from link partner. 0 = New page has not been received. 1 = Link partner has autonegotiation capability. 0 = Link partner does not have autonegotiation capability. Table 28. Autonegotiation Next Page Transmit Register--Address 7 Autonegotiation Next Page Transmit Register Bit Name 15 Next Page 14 13 Reserved Message Page 12 Acknowledge 2 11 Toggle 10:0 Message/ Unformatted Code Field LSI Corporation 43 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 29. Link Partner Next Page Register--Address 8 Link Partner Next Page Register Bit 15 Next Page 14 Acknowledge 13 Message Page 12 Acknowledge 2 11 Toggle 10:0 44 Name Message/ Unformatted Code Field Description Type Default Notes 1 = Additional next pages follow. 0 = Sending last next page. 1 = Acknowledge. 0 = No acknowledge. 1 = Formatted page. 0 = Unformatted page. 1 = Complies with message. 0 = Cannot comply with message. 1 = Previous value of transmitted link code word was logic zero. 0 = Previous value of transmitted link code word was logic one. Next page message code or unformatted data. RO 0 -- RO 0 -- R/W 0 -- R/W 0 -- RO 0 -- R/W 0 -- LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 30. 1000 Base-T Control Register--Address 9 1000Base-T Control Register Bit 15:13 12 11 10 9 8 7:0 Name Test Mode Master/Slave Configuration Enable Master/Slave Configuration Value Port Type Description Type Default Notes 000 = Normal mode. 001 = Test mode 1--transmit waveform test. 010 = Test mode 2--master transmit jitter test. 011 = Test mode 3--slave transmit jitter test (slave mode). 100 = Test mode 4--transmit distortion test. 101, 110, 111 = Reserved. 1 = Enable master/slave configuration. 0 = Automatic master/slave configuration. R/W 000 -- R/W 0 -- 1 = Configure PHY as master. 0 = Configure PHY as slave. R/W 0 1 R/W 0 -- R/W SPEED_1000 2 R/W SPEED_1000 2 RO -- -- 1 = Prefer multiport device (master). 0 = Prefer single-port device (slave). Advertise 1 = Advertise 1000Base-T full-duplex capability. 1000Base-T Full- 0 = Advertise no 1000Base-T full-duplex capability. duplex Capability Advertise 1 = Advertise 1000Base-T half-duplex capability. 1000Base-T Half- 0 = Advertise no 1000Base-T half-duplex capability. duplex Capability Reserved -- 1. Setting this bit has no effect unless address 9, bit 12 is set. 2. Value read from SPEED_1000 pin at reset. Note: Logically, bits 12:8 can be regarded as an extension of the technology ability field of register 4. LSI Corporation 45 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 31. 1000Base-T Status Register--Address 10 1000Base-T Status Register Bit Name 15 Master/ Slave Configuration Fault Master/Slave Configuration Resolution Local Receiver Status Remote Receiver Status Link Partner 1000Base-T Fullduplex Capability Link Partner 1000Base-T Half-duplex Capability Reserved Idle Error Count 14 13 12 11 10 9:8 7:0 Description Type Default Notes RO, LH, SC RO 0 1 0 2 1 = Local receiver okay. 0 = Local receiver not okay. 1 = Remote receiver okay. 0 = Remote receiver not okay. 1 = Link partner is capable of 1000Base-T full duplex. 0 = Link partner not 1000Base-T full-duplex capable. RO 0 -- RO 0 -- RO 0 3 1 = Link partner is 1000Base-T half-duplex capable. 0 = Link partner not 1000Base-T half-duplex capable. RO 0 3 RO RO 0 -- 4 1 = Master/slave configuration fault detected. 0 = No master/slave configuration fault detected. 1 = Local PHY resolved to master. 0 = Local PHY resolved to slave. -- MSB of idle error count. 1. Once set, this bit remains set until cleared by the following actions: n Read of register 10 via the management interface. n Reset. n Completion of autonegotiation. n Enable of autonegotiation. 2. This bit is not valid when bit 15 is set. 3. Note that logically, bits 11:10 may be regarded as an extension of the technology ability field of register 5. 4. These bits contain a cumulative count of the errors detected when the receiver is receiving idles and both local and remote receiver status are OK. The count is held at 255 in the event of overflow and is reset to zero by reading register 10 via the management interface or by reset. 46 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description Register Functions/Settings (continued) Table 32. Reserved Registers--Addresses 11--14 Reserved Registers Bit 15:0 Name Description Type Default Notes -- -- -- -- Type Default Notes 0 = Not 1000Base-X full-duplex capable. RO 0 -- 0 = Not 1000Base-X half-duplex capable. RO 0 -- 1 = 1000Base-T full-duplex capable. 0 = Not 1000Base-T full-duplex capable. 1 = 1000Base-T half-duplex capable. 0 = Not 1000Base-T half-duplex capable. -- RO 1 1 RO 1 -- RO 0 -- Description Type Default Notes -- -- -- -- Reserved Table 33. Extended Status Register--Address 15 Extended Status Register Bit 15 14 13 12 11:0 Name 1000Base-X Fullduplex 1000Base-X Halfduplex 1000Base-T Fullduplex 1000Base-T Halfduplex Reserved Description 1. Value is a result of (SPEED_1000) pin at reset. Table 34. Reserved Registers--Addresses 16--17 Reserved Registers Bit 15:0 Name Reserved LSI Corporation 47 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 35. PHY Control Register 2--Address 18 PHY Control Register 2 Bit Name Description Type Default Notes 15 14 Reserved Count False Carrier Events -- R/W -- 0 -- 1 13 Count Symbol Errors Reserved Automatic MDI/MDI-X MDI/MDI-X Configuration Reserved Enable Diagnostics Reserved -- 1 = Rx error counter counts false carrier events. 0 = Rx error counter does not count false carrier events. 1 = Rx error counter counts symbol errors. 0 = Rx error counter counts CRC errors. -- 1 = Enable automatic MDI/MDI-X detection. 0 = Disable automatic MDI/MDI-X detection. 1 = Manual MDI-X configuration. 0 = Manual MDI configuration. -- 1 = Enable diagnostics. 0 = Disable diagnostics. -- R/W 0 1 -- R/W -- 1 -- -- R/W 0 -- R/W -- 0 See Table 36. -- 2 -- -- -- 12:11 10 9 8:3 2 1:0 1. Count symbol errors (18.13) and count false carrier events (18.14) control the type of errors that the Rx error counter (20.15:0) counts (settings are shown below). The default is to count CRC errors. Count False Carrier Events Count Symbol Errors Rx Error Counter 1 1 Counts symbol errors and false carrier events. 1 0 Counts CRC errors and false carrier events 0 1 Counts symbol errors. 0 0 Counts CRC errors. 2. This bit enables PHY diagnostics, which include IP phone detection and TDR cable diagnostics. It is not recommended to enable this bit in normal operation (when the link is active). This bit does not need to be set for link analysis cable diagnostics. 48 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Bit 9, PHY Control Register 2, manually sets the MDI/MDI-X configuration if automatic MDIX is disabled, as indicated below. Table 36. MDI/MDI-X Configuration Automatic MDI/MDI-X MDI/MDI-X Configuration 1 0 0 X 0 1 MDI/MDI-X Mode Automatic MDI/MDI-X detection. MDI configuration (NIC/DTE). MDI-X configuration (switch). The mapping of the transmitter and receiver to pins for MDI and MDI-X configuration for 10Base-T, 100Base-TX, and 1000Base-T is shown below. Note that even in manual MDI/MDI-X configuration, the PHY automatically detects and corrects for C and D pair swaps. Table 37. MDI/MDI-X Pin Mapping Pin MDI Pin Mapping MDI-X Pin Mapping 10Base-T 100Base-TX 1000Base-T 10Base-T 100Base-TX 1000Base-T TRD[0]+/- Transmit +/- Transmit +/- Transmit A+/- Receive B+/- Receive +/- Receive +/- Transmit B+/- Receive A+/- TRD[1]+/- Receive +/- Receive +/- Transmit B+/- Transmit +/- Receive A+/- Transmit +/- Transmit A+/- Receive B+/- TRD[2]+/- -- -- Transmit C+/- Receive D+/- -- -- Transmit D+/- Receive C+/- TRD[3]+/- -- -- Transmit D+/- Receive C+/- -- -- Transmit C+/- Receive D+/- LSI Corporation 49 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 38. Loopback Control Register--Address 19 Loopback Control Register Bit Name 15 MII Description 1 = MII loopback selected. 0 = MII loopback not selected. Default Notes R/W 1 -- -- -- -- 14:13 Reserved 12 All Digital 1 = All digital loopback selected. 0 = All digital loopback not selected. R/W 0 -- 11 Replica 1 = Replica loopback selected. 0 = Replica loopback not selected. R/W 0 1 10 Line Driver 1 = Line driver loopback selected. 0 = Line driver loopback not selected. R/W 0 -- 9:8 Reserved -- -- -- R/W 0 -- -- -- -- R/W 0 2 7 External Cable 6:1 0 -- Type -- 1 = External cable loopback enabled. 0 = External cable loopback disabled. Reserved Force Link Status -- 1 = Force link status okay in MII loopback. 2 = Force link status not okay in MII loopback. 1. Replica loopback is not available in 10Base-T. 2. This bit can be used to force link status okay during MII loopback. In MII loopback, the link status bit will not be set unless force link status is used. In all other loopback modes, the link status bit will be set when the link comes up. Loopback Mode Settings The following table shows how the loopback bit (0.14) and the cable diagnostic mode bit (23.13) should be set for each loopback mode. It also indicates whether the loopback mode sets the link status bit and when the PHY is ready to receive data. Table 39. Loopback Bit (0.14) and Cable Diagnostic Mode Bit (23.13) Settings for Loopback Mode 50 Loopback Bit 0.14 Loopback Required Bit 23.13 = 1 Cable Diagnostic Mode Required Bit 26.6 Link Status Set PHY Ready for Data MII Yes No 19.0 After a few ms All Digital Yes Yes Yes Link Status Replica Yes Yes Yes Link Status Line Driver Yes Yes Yes Link Status Ext Cable No Yes Yes Link Status LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 40. RX Error Counter Register--Address 20 RX Error Counter Register Bit 15:0 Name Rx Error Counter Description 16-bit Rx error counter. Type Default Notes RO, SC 0 Reference Register 18 (bits 13 and 14) for error type descriptions Type Default Notes -- R/W -- 1 -- -- -- R/W -- 1 -- -- Table 41. Management Interface (MI) Control Register--Address 21 Management Interface (MI) Control Register Bit 15:3 2 1 0 Name Description Reserved -- Ignore 10G Frames 1 = Management frames with ST = <00> are ignored. 0 = Management frames with ST = <00> are treated as wrong frames Reserved -- Preamble Suppres- 1 = MI preamble is ignored. sion Enable 0 = MI preamble is required. LSI Corporation 51 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 42. PHY Configuration Register--Address 22 PHY Configuration Register Bit 15 14 13:12 11:10 9 8 7 6 5 4 3 2:0 Name CRS Transmit Enable Description 1 = Enable CRS on transmit in half-duplex mode. 0 = Disable CRS on transmit. Reserved -- Transmit FIFO depth 00 = 8. (1000Base-T) 01 = 16. 10 = 24. 11 = 32. Automatic Speed 00 = Disable automatic speed downshift. Downshift Mode 10 = 100Base-TX downshift enabled. x1 = 100Base-TX and 10Base-T enabled. TBI Detect Select 1 = CRS pin outputs comma detect. 0 = CRS pin outputs link status detect TBI Rate Select 1 = Output 125 MHz clock on RX_CLK while COL is held low (full rate). 0 = Output even/odd clocks on RX_CLK/COL Alternate Next-Page 1 = Enables manual control of 1000Base-T next pages only. 0 = Normal operation of 1000Base-T next page exchange Group MDIO Mode 1 = Enable group MDIO mode. Enable 0 = Disable Group MDIO mode. Transmit Clock Enable 1 = Enable output of 1000Base-T transmit clock (TX_CLK pin). 0 = Disable output. System Clock Enable 1 = Enable output of 125 MHz reference clock (SYS_CLK pin). 0 = Disable output of 125 MHz reference clock. Reserved -- MAC Interface Mode 000 = GMII/MII. Select 001 = TBI. 010 = GMII/MII clocked by GTX_CLK instead of TX_CLK. 011 = Reserved. 100 = RGMII (trace delay). 101 = RTBI (trace delay). 110 = RGMII (DLL delay). 111 = RTBI (DLL delay). Type Default Notes R/W 0 -- -- R/W -- 01 -- -- R/W 11 1 R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W -- R/W SYS_CLK_EN_N -- See bit 23.6 (next page) and Note 1, Table 10, page 30. 2 -- 3 1. If automatic speed downshift is enabled and the PHY fails to autonegotiate at 1000Base-T, the PHY will fall back to attempt connection at 100Base-TX and, subsequently, 10Base-T. This cycle will repeat. If the link is broken at any speed, the PHY will restart this process by reattempting connection at the highest possible speed (e.g., 1000Base-T). 2. Value is read from inversion of SYS_CLK_EN_N at reset. 3. For the 68-pin MLCC, only RGMII and RTBI modes/options are supported. Register Description (continued) 52 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Functions/Settings (continued) Table 43. PHY Control Register--Address 23 PHY Control Register Bit 15 Name Description IP Phone Detected 14 13 12:11 10:7 6 5 1 = IP phone detected. 0 = IP phone not detected. IP Phone Detect 1 = Enable automatic IP phone detect. Enable 0 = Disable automatic IP phone detect. Cable Diagnostic 1 = Link analysis mode. Mode 0 = TDR mode. Automatic Speed 00 = 1. Downshift Attempts 01 = 2. Before Downshift 10 = 3. 11 = 4. Reserved -- Alternative RGMII 1 = TXC DLL delay in RGMII mode is opposite of RXC. TXC DLL Delay 0 = TXC DLL delay in RGMII mode is same as RXC. Jabber (10Base-T) SQE (10Base-T) TP_LOOPBACK (10Base-T) Preamble Generation Enable Reserved Force Interrupt 4 3 2 1 0 1 = Disable jabber. 0 = Normal operation. 1 = Enable heartbeat. 0 = Disable heartbeat. 1 = Disable TP loopback during half-duplex. 0 = Normal operation. 1 = Enable preamble generation for 10Base-T. 0 = Disable preamble generation for 10Base-T. -- 1 = Assert MDINT_N pin. 0 = Deassert MDINT_N pin. Type Default Notes RO 0 1 R/W, SC R/W 0 2 1 3 R/W 11 -- -- R/W -- 4 R/W -- See Note 1, Table 10, page 30. 0 R/W 0 -- R/W 1 -- R/W 1 -- -- R/W -- 0 -- -- -- 1. This bit is only valid when the PHY is in PHY standby mode (26.15 = 1) and after the IP phone detect enable bit (23.14) has been set and has self-cleared to indicate that the IP phone detection algorithm has completed. 2. Setting this bit enables the automatic IP phone detection algorithm and clears the IP phone detected bit (23.15). Diagnostics must be enabled (18.2 = 1), cable diagnostic TDR mode must be selected (23.13 = 0), and the PHY must be in PHY standby mode (26.15 = 1) to do IP phone detection. IP phone detect enable self-clears when the IP phone detection algorithm is complete, the result is then indicated in IP phone detected. 3. This bit sets the cable diagnostics mode. The default is link analysis mode wherein the PHY brings up a link with a remote partner. For analysis of cable faults, the PHY can be put in TDR mode. In TDR mode, the PHY will not respond to link pulses from a remote link partner and will not bring up a link. 4. This bit allows independent control over TXC and RXC DLL delay. Settings are shown below: RGMII Mode Delay Description 22.2:0 23.6 TXC RXC 10x 0 0 ns 0 ns 11x 0 2 ns 2 ns RGMII (TXC and RXC DLL delay). 10x 1 2 ns 0 ns RGMII (TXC DLL delay). 11x 1 0 ns 2 ns RGMII (RXC DLL delay). LSI Corporation RGMII (trace delay). 53 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 44. Interrupt Mask Register--Address 24 Interrupt Mask Register Bit 15:11 10 9 8 7 6 5 4 3 2 1 0 Name Description Type Default Notes -- -- -- -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- R/W 0 -- Reserved TDR/IP Phone 1 = Interrupt enabled. 0 = Interrupt disabled. MDIO Sync Lost 1 = Interrupt enabled. 0 = Interrupt disabled. Autonegotiation 1 = Interrupt enabled. Status Change 0 = Interrupt disabled. CRC Errors 1 = Interrupt enabled. 0 = Interrupt disabled. Next Page Received 1 = Interrupt enabled. 0 = Interrupt disabled. Error Counter Full 1 = Interrupt enabled. 0 = Interrupt disabled. FIFO Overflow/ 1 = Interrupt enabled. Underflow 0 = Interrupt disabled. Receive Status 1 = Interrupt enabled. Change 0 = Interrupt disabled. Link Status Change 1 = Interrupt enabled. 0 = Interrupt disabled. Automatic Speed 1 = Interrupt enabled. Downshift 0 = Interrupt disabled. MDINT_N Enable 1 = MDINT_N enabled1. 0 = MDINT_N disabled. 1. MDINT_N is asserted (active-low) if MII interrupt pending = 1. 54 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 45. Interrupt Status Register--Address 25 Interrupt Status Register Bit 15:11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved TDR/IP Phone Description Type Default Notes -- -- -- -- RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH RO, LH 0 -- 0 1 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 2 1 = Event has completed. 0 = Event has not completed. MDIO Sync Lost 1 = Event has occurred. 0 = Event has not occurred. Autonegotiation 1 = Event has occurred. Status Change 0 = Event has not occurred. CRC Errors 1 = Event has occurred. 0 = Event has not occurred. Next Page Received 1 = Event has occurred. 0 = Event has not occurred. Error Counter Full 1 = Event has occurred. 0 = Event has not occurred. FIFO Overflow/ 1 = Event has occurred. Underflow 0 = Event has not occurred. Receive Status 1 = Event has occurred. Change 0 = Event has not occurred. Link Status Change 1 = Event has occurred. 0 = Event has not occurred. Automatic Speed 1 = Event has occurred. Downshift 0 = Event has not occurred. MII Interrupt Pend- 1 = Interrupt pending. ing 0 = No interrupt pending. 1. If the management frame preamble is suppressed (MF preamble suppression, register 0, bit 6), it is possible for the PHY to lose synchronization if there is a glitch at the interface. The PHY can recover if a single frame with a preamble is sent to the PHY. The MDIO sync lost interrupt can be used to detect loss of synchronization and, thus, enable recovery. 2. An event has occurred and the corresponding interrupt mask bit is enabled (set = 1). LSI Corporation 55 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 46. PHY Status Register--Address 26 PHY Status Register Bit 15 14:13 12 Name PHY in Standby Mode Autonegotiation Fault Status 11 Autonegotiation Status MDI-X Status 10 Polarity Status 9:8 Speed Status 7 Duplex Status 6 Link Status 5 Transmit Status 4 Receive Status 3 Collision Status 2 Autonegotiation Enabled PAUSE Enabled 1 0 Asymmetric Direction Description Type Default Notes 1 = PHY in standby mode. 0 = PHY not in standby mode. 10 = Master/slave autonegotiation fault. 01 = Parallel detect autonegotiation fault. 00 = No autonegotiation fault. 1 = Autonegotiation is complete. 0 = Autonegotiation not complete. 1 = MDI-X configuration. 0 = MDI configuration. 1 = Polarity is normal (10Base-T only). 0 = Polarity is inverted (10Base-T only). 11 = Undetermined. 10 = 1000Base-T. 01 = 100Base-TX. 00 = 10Base-T. 1 = Full duplex. 0 = Half duplex. 1 = Link is up. 0 = Link is down. 1 = PHY is transmitting a packet. 0 = PHY is not transmitting a packet. 1 = PHY is receiving a packet. 0 = PHY is not receiving a packet. 1 = Collision is occurring. 0 = Collision not occurring. 1 = Both partners have autonegotiation enabled. 0 = Both partners do not have autonegotiation enabled. 1 = Link partner advertised PAUSE mode enabled. 0 = Link partner advertised PAUSE mode disabled. 1 = Link partner advertised direction is symmetric. 0 = Link partner advertised that direction is asymmetric. R0 0 1 RO 00 -- RO 0 -- RO 0 -- RO 1 -- RO 11 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- RO 0 -- 1. This bit indicates that the PHY is in standby mode and is ready to perform IP phone detection or TDR cable diagnostics. The PHY enters standby mode when cable diagnostic TDR mode is selected (23.13 = 0) and the link is dropped. A software reset (0.15) or software power down (0.11) can be used to force the link to drop. 56 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 47. LED Control Register 1--Address 27 LED Control Register 1 Bit Name Description Type Default Notes 15 Two-Color Mode LED_1000/LED_100 Two-Color Mode LED_LINK/LED_TXRX LED_TXRX Extended Modes LED_LINK Extended Modes LED_100 Extended Modes LED_1000 Extended Modes Reserved LED Blink Pattern Pause LED Pulse Duration 1 = Two-color mode for LED_1000 and LED_100. 0 = Normal mode for LED_1000 and LED_100. 1 = Two-color mode for LED_LINK and LED_TXRX. 0 = Normal mode for LED_LINK and LED_TXRX. 1 = Extended modes for LED_TXRX. 0 = Standard modes for LED_TXRX. 1 = Extended modes for LED_LINK. 0 = Standard modes for LED_LINK. 1 = Extended modes for LED_100. 0 = Standard modes for LED_100. 1 = Extended modes for LED_1000. 0 = Standard modes for LED_1000. -- LED blink pattern pause cycles. 00 = Stretch LED events to 28 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. -- 1 = Enable pulse stretching of LED functions: transmit activity, receive activity, and collision. 0 = Disable pulse stretching of LED functions: transmit activity, receive activity, and collision. R/W 0 1 R/W 0 1 R/W 0 2 R/W 0 2 R/W 0 2 R/W 0 2 -- R/W R/W -- 0x0 00 -- -- -- -- R/W -- 1 -- -- 14 13 12 11 10 9:8 7:4 3:2 1 0 Reserved Pulse Stretch 0 1. If two-color mode is enabled for pair LED_LINK and LED_TXRX, the signal output for LED_LINK is equal to (LED_LINK and LED_TXRX). For the case where LED_LINK and LED_TXRX are not mutually exclusive (e.g., duplex and collision), this mode can simplify the external circuitry because it ensures either LED_LINK or LED_TXRX is on, and not both at the same time. The same rule applies to pair LED_1000 and LED_100. 2. The LED function is programmed using this bit and register 28. LSI Corporation 57 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 48. LED Control Register 2--Address 28 LED Control Register 2 Bit Name 15:12 LED_TXRX 11:8 LED_LINK Description As per 11:8. Standard modes Type Default Notes RW R/W 1111 0100 -- -- RW R/W 1111 0000 -- -- Type Default Notes 0000 = 1000Base-T. 0001 = 100Base-TX. 0010 = 10Base-T. 0011 = 1000Base-T on, 100Base-TX blink. 0100 = Link established. 0101 = Transmit. 0110 = Receive. 0111 = Transmit or receive activity. 1000 = Full duplex. 1001 = Collision. 1010 = Link established (on) and activity (blink). 1011 = Link established (on) and receive (blink). 1100 = Full duplex (on) and collision (blink). 1101 = Blink. 1110 = On. 1111 = Off. Extended modes 7:4 3:0 LED_100 LED_1000 0000 = 10Base-T or 100Base-TX. 0001 = Reserved. 0010 = Reserved. 0011 = Reserved. 0100 = 1000Base-T (on) and activity (blink). 0101 = 10Base-T or 100Base-TX (on) and activity (blink). 011x = Reserved. As per 11:8. As per 11:8. Table 49. LED Control Register 3--Address 29 LED Control Register 3 Bit Name 15:14 LED Blink Pattern Address 13:8 LED Blink Pattern Frequency LED Blink Pattern 7:0 Description Select LED blink pattern register set. 00 = Select register set for LED_LINK. 01 = Select register set for LED_TXRX. 10 = Select register set for LED_1000. 11 = Select register set for LED_100. LED blink pattern clock frequency divide ratio. R/W 00 -- R/W 0x1f 1 LED blink pattern. R/W 0x55 1 1. The default pattern is a 512 ms blink. 58 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 50. Diagnostics Control Register (TDR Mode)--Address 30 Diagnostics Control Register (TDR Mode) Bit Name Description Type Default Notes 15:14 TDR Request 11 = Automatic TDR analysis in progress. 10 = Single-pair TDR analysis in progress. 01 = TDR analysis complete, results valid. 00 = TDR analysis complete, results invalid. R/W 00 1 13:12 TDR Tx Dim Transmit dimension for single-pair TDR analysis. 00 = TDR transmit on pair A. 01 = TDR transmit on pair B. 10 = TDR transmit on pair C. 11 = TDR transmit on pair D. R/W 00 2 11:10 TDR Rx Dim Receive dimension for single-pair TDR analysis. 00 = TDR receive on pair A. 01 = TDR receive on pair B. 10 = TDR receive on pair C. 11 = TDR receive on pair D. R/W 00 2 9:2 Distance to Fault Distance to open or short fault. R/W 0 3, 4 1:0 Reserved -- -- -- -- 1. Automatic TDR analysis is enabled by setting TDR request to {11}. All 10 combinations of pairs are analyzed in sequence, and the results are available in registers 30 and 31. TDR analysis for a single-pair combination can be enabled by setting TDR request to {10}. Diagnostics must be enabled (18.2 = 1), cable diagnostic TDR must be mode selected (23.13 = 0), and the PHY must be in PHY standby mode (26.15 = 1) to perform TDR operations. Bit 15 selfclears when the TDR operation is complete. When TDR is complete, bit 14 indicates whether the results are valid. 2. TDR transmit and receive dimensions are only valid for single-pair TDR analysis. They are ignored for automatic TDR analysis when all 10 pair combinations are analyzed. 3. This is the distance to an open, short, or strong impedance mismatch fault on the chosen pair for single-pair TDR analysis. For automatic TDR analysis, this returns the distance to the last open, short, or strong impedance mismatch fault found. The automatic algorithm searches for faults in the order of short between C and D, B and D, B and C, A and D, A and C, A and B; and faults on pair D, pair C, pair B, and pair A. If there is no fault, the result will be 0xff and should be ignored. 4. The 8-bit integer value can be linearly converted to distance in meters. The value 0x08 (or less) corresponds to a distance of 0 m, and the value 0xfe corresponds to a distance of 200 m (180 m for Cat-3 cable). The following equation can be used to convert the integer value to meters: distance (m) = 1.179 x (x - 8) x NVP Where, NVP = normalized velocity of propagation (typically 0.69 for CAT5, CAT5e, and CAT6; 0.62 for CAT3). For CAT5/5e/6 cable, a simple approximation (accurate to 0.1%) is (x - 8) x 13/16. LSI Corporation 59 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 51. Diagnostics Status Register (TDR Mode)--Address 31 Diagnostics Status Register (TDR Mode) Bit Name Description Type Default Notes 15:14 TDR Fault Type Pair A (or fault type for single pair combination) 11 = Short found on pair A. 10 = Open found on pair A. 01 = Strong impedance mismatch found on pair A. 00 = Good termination found on pair A. R/W 00 1 13:12 TDR Fault Type Pair B 11 = Short found on pair B. 10 = Open found on pair B. 01 = Strong impedance mismatch found on pair B. 00 = Good termination found on pair B. R/W 00 -- 11:10 TDR Fault Type Pair C 11 = Short found on pair C. 10 = Open found on pair C. 01 = Strong impedance mismatch found on pair C. 00 = Good termination found on pair C. R/W 00 -- 9:8 TDR Fault Type Pair D 11 = Short found on pair D. 10 = Open found on pair D. 01 = Strong impedance mismatch found on pair D. 00 = Good termination found on pair D. R/W 00 -- 7 Short Between Pairs A and B 1 = Short between pairs A and B. 0 = No short between pairs A and B. R/W 0 -- 6 Short Between Pairs A and C 1 = Short between pairs A and C. 0 = No short between pairs A and C. R/W 0 -- 5 Short Between Pairs A and D 1 = Short between pairs A and D. 0 = No short between pairs A and D. R/W 0 -- 4 Short Between Pairs B and C 1 = Short between pairs B and C. 0 = No short between pairs Band C. R/W 0 -- 3 Short Between Pairs B and D 1 = Short between pairs B and D. 0 = No short between pairs B and D. R/W 0 -- 2 Short Between Pairs C and D 1 = Short between pairs C and D. 0 = No short between pairs C and D. R/W 0 -- -- -- -- 1:0 Reserved -- 1. For automatic TDR analysis, this returns the fault type on pair A. For single-pair TDR analysis, this returns the fault type on the pair combination under test, i.e., as specified in the TDR Tx Dim and Rx Dim (30.13:12 and 30.11:10, respectively). 60 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 52. Diagnostics Control Register (Link Analysis Mode)--Address 30 Diagnostics Control Register (Link Analysis Mode) Bit Name Description Type Default Notes -- -- -- -- Pair Swap on Pairs C 1 = Pairs C and D are swapped (1000Base-T only). and D 0 = Pairs C and D are not swapped (1000Base-T only). R/W 0 See Table 53. Cable Length Cable length when link is active. R/W 0 1 4 Polarity on Pair D 1 = Polarity on pair D is normal (1000Base-T only). 0 = Polarity on pair D is inverted (1000Base-T only). R/W 0 -- 3 Polarity on Pair C 1 = Polarity on pair C is normal (1000Base-T only). 0 = Polarity on pair C is inverted (1000Base-T only). R/W 0 -- 2 Polarity on Pair B 1 = Polarity on pair B is normal (1000Base-T only). 0 = Polarity on pair B is inverted (1000Base-T only). R/W 0 -- 1 Polarity on Pair A 1 = Polarity on pair A is normal (1000Base-T only). 0 = Polarity on pair A is inverted (1000Base-T only). R/W 0 -- 0 Excessive Pair Skew 1 = Excessive pair skew (1000Base-T only). 0 = Not excessive pair skew (1000Base-T only). R/W 0 2 15:12 Reserved 11 10:5 1. This is the cable length estimate when the link is active (maximum of 155 m). The values of 0x00 to 0x1f correspond to 0 m--155 m in 5 m increments. The values of 0x20 to 0x3e are reserved for future use, e.g., cable lengths of 160 m--315 m. The result may be invalid for a 10Base-T link. If the result is invalid, a value of 0x3f is returned. 2. Excessive pair skew is detected by determining that the scrambler has not acquired. It is possible for other scrambler acquisition errors to be mistaken for excessive pair skew. The following table shows the mapping of the transmitter and receiver for MDI and MDI-X configuration for 1000Base-T when pairs C and D are not swapped and are swapped. Table 53. MDI/MDI-X Configuration for 1000Base-T with C and D Swapped/Not Swapped Pin Pair C and D Are Not Swapped Pair C and D Are Swapped MDI Configuration MDI-X Configuration MDI Configuration MDI-X Configuration TRD_[0:7]_[0]+/- Transmit A+/-Receive B+/- Transmit B+/- Receive A+/- Transmit A+/- Receive B+/- Transmit B+/- Receive A+/- TRD_[0:7]_[1]+/- Transmit B+/-Receive A+/- Transmit A+/- Receive B+/- Transmit B+/- Receive A+/- Transmit A+/- Receive B+/- TRD_[0:7]_[2]+/- Transmit C+/- Receive D+/- Transmit D+/- Receive C+/- Transmit C+/- Receive C+/- Transmit D+/- Receive D+/- TRD_[0:7]_[3]+/- Transmit D+/- Receive C+/- Transmit C+/- Receive D+/- Transmit D+/- Receive D+/- Transmit C+/- Receive C+/- LSI Corporation 61 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 54. Absolute Maximum Ratings Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V/2.5 V digital) Supply Voltage (1.0 V digital) ESD Protection Storage Temperature Symbol Min Max Unit AVDDH AVDDL DVDDIO VDD VESD TSTORE -- -- -- -- -- -40 4.2 1.2 4.2 1.2 2000 125 V V V V V C Recommended Operating Conditions Table 55. ET1011C Recommended Operating Conditions Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog)1 Supply Voltage (3.3 V digital)2 Supply Voltage (2.5 V digital)2 Supply Voltage (1.0 V digital)1 Ambient Operating Temperature--Commercial Ambient Operating Temperature--Industrial Maximum Junction Temperature Thermal Characteristics, 128 TQFP (JDEC 3 in. x 4.5 in. 4-layer PCB): 0 m/s airflow 1 m/s airflow 2.5 m/s airflow Thermal Characteristics, 84-pin MLCC and 68-pin MLCC (JDEC 3 in. x 4.5 in. 4-layer PCB): 0 m/s Airflow 1 m/s Airflow 2.5 m/s Airflow Symbol Min Typ Max Unit AVDDH AVDDL DVDDIO DVDDIO VDD TA TA 2.38 0.95 3.14 2.38 0.95 0 -40 2.5 1.0 or 1.1 3.3 2.5 1.0 or 1.1 -- -- 2.62 1.15 3.46 2.62 1.15 70 85 V V V V V C C TJ 0 -- 125 C C/W TJB TJC JT TJA TJA TJA -- -- -- -- -- -- 29 33 1 37 32 30 -- -- -- -- -- -- TJB TJC JT TJA TJA TJA -- -- -- -- -- -- 10 3 1 24 23 21 -- -- -- -- C/W -- 1. For the 128-pin TQFP package operating over the industrial temperature range, the maximum voltage is reduced from 1.15 V to 1.05. V. The center tap voltage range is changed to 1.8V only. 2. The part can operate at either 3.3 V (typically for an GMII interface) or 2.5 V (typically for an RGMII interface). 62 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications (continued) Device Electrical Characteristics Device electrical characteristics refer to the behavior of the device under specified conditions imposed on the user for proper operation of the device. Unless otherwise noted, the parameters below are valid for the conditions described in the previous section, Recommended Operating Conditions. Table 56. Device Characteristics--3.3 V Digital I/O Supply (DVDDIO) Symbol Min Typ Max Unit Input Leakage1 (digital pins without pull-up or pull-down) IILeak -10 -- 10 uA Input Leakage (digital pins with pull-up or pull-down) IILeak -100 -- 100 uA Input Low Voltage VIL -0.3 -- 0.8 V Input High Voltage Parameter VIH 2.0 -- 3.6 V Output Low Voltage2 VOL -- -- 0.4 V Output High Voltage3 VOH 2.4 -- -- V Differential Output Voltage (analog MDI pins 1000Base-T) VODIFF 0.67 0.75 0.82 V Differential Output Voltage (analog MDI pins 100Base-TX) VODIFF 0.95 1.0 1.05 V Differential Output Voltage (analog MDI pins 10Base-T) VODIFF 2.2 2.5 2.8 V Symbol Min Typ Max Unit Input Leakage (digital pins without pull-up or pull-down) IIL -10 -- 10 uA Input Leakage (digital pins with pull-up or pull-down) IIL -100 -- 100 uA Input Low Voltage VIL -0.3 -- 0.7 V Input High Voltage Table 57. Device Characteristics--2.5 V Digital I/O Supply (DVDDIO) Parameter VIH 1.7 -- 2.8 V Voltage2 VOL -- -- 0.4 V 3 VOH 2.0 -- -- V Differential Output Voltage (analog MDI pins 1000Base-T) VODIFF 0.67 0.75 0.82 V Differential Output Voltage (analog MDI pins 100Base-TX) VODIFF 0.95 1.0 1.05 V Differential Output Voltage (analog MDI pins 10Base-T) VODIFF 2.2 2.5 2.8 V Output Low Output High Voltage 1. RESET_N pin IILeak max=1mA when DVVDIO is more than 0.8V above the AVDDH supply. 2. All pins tested with IOL=4mA except for the following pins: RXD[3:0]=3mA in MII mode only; MDINT_N and MDIO=9mA, TDO=14mA. 3. All pins tested iwth IOH=3mA except for the following pins: RXD[3:0]=2mA in MII mode; MDINT_N and MDIO=6mA with VOHmin=1.95V, TDO=8mA with VOHmin=1.95V. PHYAD0 and PHYAD1 =5ma with VOHmin=1.95V. LSI Corporation 63 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications (continued) Device Electrical Characteristics (continued) Table 58. ET1011C Current Consumption 1000Base-T Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Tx/Rx random data -- 62 -- mA Supply Voltage (1.0 V analog) IAVDDL Tx/Rx random data -- 205 -- mA Supply Voltage (3.3 V digital - GMII mode) or (2.5 V digital - RGMII mode) IDVDDIO Tx/Rx random data -- -- 30 20 -- -- mA mA Supply Voltage (1.0 V digital) IVDD Tx/Rx random data -- 131 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Tx/Rx random data -- 183 -- mA Table 59. ET1011C Current Consumption 100Base-TX Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Tx/Rx random data -- 20 -- mA Supply Voltage (1.0 V analog) IAVDDL Tx/Rx random data -- 55 -- mA Supply Voltage (3.3 V digital - MII mode) or (2.5 V digital - RGMII mode) IDVDDIO Tx/Rx random data -- -- 22 14 -- -- mA mA Supply Voltage (1.0 V digital) IVDD Tx/Rx random data -- 23 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Tx/Rx random data -- 40 -- mA Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Tx/Rx random data -- 20 -- mA Supply Voltage (1.0 V analog) IAVDDL Tx/Rx random data -- 55 -- mA Supply Voltage (3.3 V digital - MII mode) or (2.5 V digital - RGMII mode) IDVDDIO Tx/Rx random data -- -- 20 14 -- -- mA mA Supply Voltage (1.0 V digital) IVDD Tx/Rx random data -- 11 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Tx/Rx random data -- 60 -- mA Table 60. ET1011C Current Consumption 10Base-T 64 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications (continued) Device Electrical Characteristics (continued) Table 61. ET1011C Current Consumption 10Base-T Idle Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Idle -- 20 -- mA Supply Voltage (1.0 V analog) IAVDDL Idle -- 55 -- mA Supply Voltage (3.3 V digital - MII mode) or (2.5V digital - RGMII mode) IDVDDIO Idle -- -- 16 10 -- -- mA mA Supply Voltage (1.0 V digital) IVDD Idle -- 11 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Idle -- 1 -- mA Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Hardware Powerdown -- 2 -- mA Supply Voltage (1.0 V analog) IAVDDL Hardware Powerdown -- 6 -- mA Supply Voltage (3.3 V or 2.5 V digital) IDVDDIO Hardware Powerdown -- 7 -- mA Supply Voltage (1.0 V digital) IVDD Hardware Powerdown -- 3 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Hardware Powerdown -- 0 -- mA Table 62. ET1011C Current Consumption Hardware Powerdown Parameter Table 63. ET1011C Current Consumption Low Power Energy Detect (LPED) Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH LPED -- 4 -- mA Supply Voltage (1.0 V analog) IAVDDL LPED -- 6 -- mA Supply Voltage (3.3 V or 2.5 V digital) IDVDDIO LPED -- 7 -- mA Supply Voltage (1.0 V digital) IVDD LPED -- 3 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP LPED -- 0 -- mA LSI Corporation 65 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications (continued) Device Electrical Characteristics (continued) Table 64. ET1011C Current Consumption Standby Powerdown and Standby Powerdown with LPED Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Standby Powerdown Mode with LPED -- 5 -- mA Supply Voltage (1.0 V analog) IAVDDL Standby Powerdown Mode with LPED -- 20 -- mA Supply Voltage (3.3 V or 2.5 V digital) IDVDDIO Standby Powerdown Mode with LPED -- 12 -- mA Supply Voltage (1.0 V digital) IVDD Standby Powerdown Mode with LPED -- 13 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Standby Powerdown Mode with LPED -- 0 -- mA Table 65. ET1011C Current Consumption Software Powerdown Parameter Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) IAVDDH Software Powerdown -- 20 -- mA Supply Voltage (1.0 V analog) IAVDDL Software Powerdown -- 59 -- mA Supply Voltage (3.3V or 2.5 V digital) IDVDDIO Software Powerdown -- 11 -- mA Supply Voltage (1.0 V digital) IVDD Software Powerdown -- 11 -- mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP Software Powerdown -- 0 -- mA 66 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specification GMII 1000Base-T Transmit Timing (128-Pin TQFP and 84-Pin MLCC Only) GTX_CLKCYCLE GTX_CLKLOW GTX_CLKHIGH GTX_CLK GTX_CLKFALL GTX_CLKRISE TXD[7:0] TX_EN TX_ER GTX_CLKHOLD GTX_CLKSU Figure 15. GMII 1000Base-T Transmit Timing Table 66. GMII 1000Base-T Transmit Timing Symbol Parameter Min Typ Max Unit GTX_CLKCYCLE GTX_CLK Cycle Time 7.5 -- 8.5 ns GTX_CLKHIGH GTX_CLK High Time 2.5 -- -- ns GTX_CLKLOW GTX_CLK Low Time 2.5 -- -- ns GTX_CLKRISE GTX_CLK Rise Time -- -- 1.0 ns GTX_CLKFALL GTX_CLK Fall Time -- -- 1.0 ns GTX_CLKSU GMII Input Signal Setup Time to GTX_CLK 2.0 -- -- ns GTX_CLKHOLD GMII Input Signal Hold Time to GTX_CLK 0.0 -- -- ns LSI Corporation 67 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) GMII 1000Base-T Receive Timing (128-Pin TQFP and 84-Pin MLCC Only) RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RX_CLK RX_CLKFALL RX_CLKRISE RXD[7:0] RX_EN RX_ER RX_CLKHOLD RX_CLKSU Figure 16. GMII 1000Base-T Receive Timing Table 67. GMII 1000Base-T Receive Timing Symbol RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RTX_CLKRISE RX_CLKFALL RX_CLKSU RX_CLKHOLD 68 Parameter RX_CLK Cycle Time RX_CLK High Time RX_CLK Low Time RX_CLK Rise Time RX_CLK Fall Time GMII Output Signal Setup Time to RX_CLK GMII Output Signal Hold Time to RX_CLK Min Typ Max Unit 7.5 2.5 2.5 -- -- 2.5 0.5 8.0 -- -- -- -- -- -- -- -- -- 1.0 1.0 -- -- ns ns ns ns ns ns ns LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) RGMII 1000Base-T Transmit Timing Trace Delay TXC GTX_CLK (TXC) TX_CLK ATtransmitter) TRANSMITTER (at AT TRANSMITTER TskewT TSKEWT TXD[8:5][3:0] TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[3:0] TXD[7:4][3:0] TXD[8:5] TXD[8:5] TXD[7:4] TXD[7:4] TSKEWR TXD[4] TXD[4] TXEN TX_EN TX_CTL (TX_CTL) TX_EN TXD[9] TXERRTXD[9] TX_ER TskewR TX_CLK TXC GTX_CLK (TXC) AT RECEIVER AT RECEIVER (at receiver) Figure 17. RGMII 1000Base-T Transmit Timing--Trace Delay Table 68. RGMII 1000Base-T Transmit Timing Symbol TskewT TskewR Tcyc Duty_G Duty_T Tr/Tf Parameter Data to Clock Output Skew (at transmitter)--Trace Delay1 Data to Clock Input Skew (at receiver)--Trace Clock Cycle Duration2 Delay1 Min Typ Max Unit -500 0 500 ps 1 1.8 2.6 ns 7.2 8 8.8 ns Duty Cycle for Gigabit3 45 50 55 % Duty Cycle for 10Base-T/100Base-TX3 40 50 60 % -- -- 0.75 ns Rise/Fall Time (20%--80%) 1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see MII register 22 bits 2:0. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. LSI Corporation 69 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) Internal Delay TXC GTX_CLK (TXC) TXC TXC WITH with internal INTERNAL delay DELAY added ADDED ATtransmitter) TRANSMITTER (at TX_CLK AT TRANSMITTER TSKEWT TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5] TXD[7:4] TsetupT TXD[8:5] TXD[7:4] TholdT TSKEWR TX_EN (TX_CTL) TXD[4] TXEN TX_CTL TXD[9] TXERR TXD[4] TX_EN TXD[9] TX_ER GTX_CLK (TXC) TXC TX_CLK TholdR (at ATreceiver) RECEIVER AT RECEIVER TsetupR Figure 18. RGMII 1000Base-T Transmit Timing--Internal Delay Table 69. RGMII 1000Base-T Transmit Timing Symbol Parameter Min Typ Max Unit TsetupT Data to Clock Output Setup (at transmitter--integrated delay)1 1.2 2.0 -- ns TholdT Clock to Data Output Hold (at transmitter--integrated delay)1 TsetupR TholdR Tcyc Duty_G Duty_T Tr/Tf 1.2 2.0 -- ns delay)1 1.0 2.0 -- ns delay)1 1.0 2.0 -- ns Data to Clock Input Setup (at receiver--integrated Data to Clock Input Hold (at receiver--integrated Duration2 7.2 8 8.8 ns Duty Cycle for Gigabit3 45 50 55 % Duty Cycle for 10Base-T/100Base-TX3 40 50 60 % -- -- 0.75 ns Clock Cycle Rise/Fall Time (20%--80%) 1. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. 70 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) RGMII 1000Base-T Receive Timing Trace Delay RXC RX_CLK (RXC) RX_CLK AT TRANSMITTER (at transmitter) AT TRANSMITTER TskewT TSKEWT RXD[8:5][3:0] RXD[3:0] RXD[7:4][3:0] RXD[3:0] RXD[7:4] RXD[8:5] RXD[3:0] RXD[7:4] TSKEWR RX_EN RX_CTL (RX_CTL) RXD[4] TX_EN RX_DV RXD[9] RX_ER RXERR TskewR RX_CLK RXC RX_CLK (RXC) AT RECEIVER ATreceiver) RECEIVER (at Figure 19. RGMII 1000Base-T Receive Timing--Trace Delay Table 70. RGMII 1000Base-T Receive Timing Symbol TskewT TskewR Tcyc Duty_G Duty_T Tr/Tf Parameter Data to Clock Output Skew (at transmitter)--Trace Delay1 Data to Clock Input Skew (at receiver)--Trace Delay Clock Cycle Duration2 1 Min Typ Max Unit -500 0 500 ps 1 1.8 2.6 ns 7.2 8 8.8 ns Duty Cycle for Gigabit3 45 50 55 % Duty Cycle for 10Base-T/100Base-TX3 40 50 60 % -- -- 0.75 ns Rise/Fall Time (20%--80%) 1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see MII register 22 bits 2:0. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. LSI Corporation 71 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) Internal Delay RXC WITH RXC with INTERNAL internal delay DELAY added ADDED RX_CLK (RXC) RXC (at ATtransmitter) TRANSMITTER RX_CLK AT TRANSMITTER TSKEWT RXD[8:5][3:0] RXD[8:5][3:0] rXD[7:4][3:0] RXD[7:4][3:0] RXD[3:0] RXD[3:0] RXD[7:4] RXD[8:5] RXD[7:4] TsetupT RXD[3:0] TholdT TSKEWR RX_EN (RX_CTL) RX_CTL RXD[4] RX_DV TX_EN RXD[9] RXERR RX_ER RXC RX_CLK (RXC) RX_CLK ATreceiver) RECEIVER (at TholdR AT RECEIVER TsetupR Figure 20. RGMII 1000Base-T Receive Timing--Internal Delay Table 71. RGMII 1000Base-T Receive Timing Symbol TsetupT TholdT TsetupR TholdR Tcyc Duty_G Duty_T Tr/Tf Parameter Data to Clock Output Setup (at transmitter--integrated delay)1 Clock to Data Output Hold (at transmitter--integrated delay)1 Data to Clock Input Setup (at receiver--integrated delay)1 Data to Clock Input Hold (at receiver--integrated delay)1 Clock Cycle Duration2 Duty Cycle for Gigabit3 Duty Cycle for 10Base-T/100Base-TX3 Rise/Fall Time (20%--80%) Min Typ Max Unit 1.2 2.0 -- ns 1.2 2.0 -- ns 1.0 1.0 7.2 45 40 -- 2.0 2.0 8 50 50 -- -- -- 8.8 55 60 0.75 ns ns ns % % ns 1. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. 72 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) MII 100Base-TX Transmit Timing TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW TX_CLK TX_CLKFALL TX_CLKRISE TXD[3:0] TX_EN TX_ER1 TX_CLKHOLD TX_CLKSU 1. TX_ER is not available on the 68-pin MLCC. Figure 21. MII 100Base-TX Transmit Timing Table 72. MII 100Base-TX Transmit Timing Symbol TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW TX_CLKRISE TX_CLKFALL TX_CLKSU TX_CLKHOLD LSI Corporation Parameter TX_CLK Cycle Time TX_CLK High Time TX_CLK Low Time TX_CLK Rise Time TX_CLK Fall Time MII Input Signal Setup Time to TX_CLK MII Input Signal Hold Time to TX_CLK Min Typ Max Unit -- -- -- -- -- 15 0 40 20 20 -- -- -- -- -- -- -- 5 5 -- -- ns ns ns ns ns ns ns 73 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) MII 100Base-TX Receive Timing RX_CLKCYCLE RX_CLKLOW RX_CLKHIGH RX_CLK RX_CLKFALL RX_CLKRISE RXD[3:0] RX_EN RX_ER RX_CLKHOLD RX_CLKSU Figure 22. MII 100Base-TX Receive Timing Table 73. MII 100Base-TX Receive Timing Symbol RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RTX_CLKRISE RX_CLKFALL RX_CLKSU RX_CLKHOLD 74 Parameter RX_CLK Cycle Time RX_CLK High Time RX_CLK Low Time RX_CLK Rise Time RX_CLK Fall Time MII Output Signal Setup Time to RX_CLK MII Output Signal Hold Time to RX_CLK Min Typ Max Unit -- -- -- -- -- 10 10 40 20 20 1 1 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) MII 10Base-T Transmit Timing TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW TX_CLK TX_CLKFALL TX_CLKRISE TXD[3:0] TX_EN TX_ER TX_CLKHOLD TX_CLKSU Figure 23. MII 10Base-T Transmit Timing Table 74. MII 10Base-T Transmit Timing Symbol TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW TX_CLKRISE TX_CLKFALL TX_CLKSU TX_CLKHOLD LSI Corporation Parameter TX_CLK Cycle Time TX_CLK High Time TX_CLK Low Time TX_CLK Rise Time TX_CLK Fall Time MII Input Signal Setup Time to TX_CLK MII Input Signal Hold Time to TX_CLK Min Typ Max Unit -- -- -- -- -- 15 0 400 200 200 1 1 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns 75 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) MII 10Base-T Receive Timing RX_CLKCYCLE RX_CLKLOW RX_CLKHIGH RX_CLK RX_CLKFALL RX_CLKRISE RXD[3:0] RX_EN RX_ER RX_CLKHOLD RX_CLKSU Figure 24. MII 10Base-T Receive Timing Table 75. MII 10Base-T Receive Timing Symbol RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RTX_CLKRISE RX_CLKFALL RX_CLKSU RX_CLKHOLD 76 Parameter RX_CLK Cycle Time RX_CLK High Time RX_CLK Low Time RX_CLK Rise Time RX_CLK Fall Time MII Output Signal Setup Time to RX_CLK MII Output Signal Hold Time to RX_CLK Min Typ Max Unit -- -- -- -- -- 10 10 400 200 200 1 1 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) Serial Management Interface Timing MDCCYCLE MDCHIGH MDCLOW MDC MDCRISE MDIO (INPUT) MDCHOLD MDCSU MDC MDIO (OUTPUT) MDCDELAY Figure 25. Serial Management Interface Timing Table 76. Serial Management Interface Timing Symbol MDCCYCLE MDCHIGH MDCLOW MDCRISE MDCFALL MDCSU MDCHOLD MDCDELAY LSI Corporation Parameter MDC Cycle Time MDC High Time MDC Low Time MDC Rise Time MDC Fall Time MDIO Signal Setup Time to MDC MDIO Signal Hold Time to MDC MDIO Delay Time from MDC Min Typ Max Unit 100 40 40 -- -- 10 10 -- -- -- -- -- -- -- -- -- -- -- -- 5 5 -- -- 80 ns ns ns ns ns ns ns ns 77 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) Reset Timing RESETPULSE_LEN RESETCFG_READ RESET_N RESETRISE LED_xx LED pins are Inputs LED pins are Outputs SYS_CLK SYSCLK COMAPULSE_LEN COMACFG_READ COMA COMAFALL LED_xx LED pins are Inputs LED pins are Outputs SYS_CLK SYSCLK to_SYS_CLK COMATO_SYSCLK COMATO_SYSCLK_VALID to_SYS_CLK_Valid Figure 26. Reset Timing Table 77. Reset Timing Symbol RESETPULSE_LEN RESETRISE RESETCFG_READ COMAPULSE_LEN COMAFALL COMATO_SYS_CLK COMATO_SYS_CLK_VALID COMACFG_READ 78 Parameter RESET_N Pulse Length RESET_N Rise Time RESET_N Deassertion to Configuration Read COMA Pulse Length COMA Fall Time COMA Deassertion to SYS_CLK COMA Deassertion to SYS_CLK Valid COMA Deassertion to Configuration Read Min Typ Max Unit 20 -- -- 20 -- -- -- -- -- 1.0 -- -- 1.0 1.0 -- -- -- -- 5.0 -- -- -- 4.2 5.0 s ns ms s ns s ms ms LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) Clock Timing XTAL_1CYCLE XTAL_1LOW XTAL_1HIGH XTAL_1 XTAL_1FALL XTAL_1RISE Figure 27. Clock Timing Table 78. Clock Timing Symbol XTAL_1CYCLE XTAL_1HIGH XTAL_1LOW XTAL_1RISE XTAL_1FALL -- -- -- LSI Corporation Parameter XTAL_1 Cycle Time XTAL_1 High Time XTAL_1 Low Time XTAL_1 Rise Time XTAL_1 Fall Time XTAL_1 Input Clock Jitter (RMS) XTAL_1 Input Clock Frequency XTAL_1 Input Clock Accuracy Min Typ Max Unit 39.998 15 15 -- -- -- -- -- 40 20 20 -- -- -- 25 -- 40.002 25 25 3 3 20 -- 50 ns ns ns ns ns ps MHz ppm 79 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) JTAG Timing TCKCYCLE TCKHIGH TCKLOW TCK TCKFALL TCKRISE TDI TMS TCKHOLD TCKSU TDO TCKDELAY Figure 28. JTAG Timing Table 79. JTAG Timing Symbol TCKCYCLE TCKHIGH TCKLOW TCKRISE TCKFALL TCKSU TCKHOLD TCKDELAY 80 Parameter TCK Cycle Time TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDI, TMS Setup Time to TCK TDI, TMS Hold Time to TCK TDO Delay Time from TCK Min Typ Max Unit 20 10 10 -- -- 2.7 0.8 -- -- -- -- 1 1 -- -- -- -- -- -- -- -- -- -- 8.1 ns ns ns ns ns ns ns ns LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Package Diagram, 128-Pin TQFP (Dimensions are in millimeters.) Note: Package outlines are unofficial and for reference only. 16.00 0.20 14.00 0.20 PIN #1 IDENTIFIER ZONE 128 103 1 102 20.00 0.20 22.00 0.20 38 65 39 64 DETAIL A DETAIL B 1.40 0.05 1.60 MAX SEATING PLANE 0.50 TYP 0.05/0.15 0.08 1.00 REF 0.25 0.106/0.200 GAGE PLANE SEATING PLANE 0.45/0.75 0.19/0.27 0.08 M DETAIL A LSI Corporation 81 82 0.40 PIN #1 IDENTIFIER 4.87 9.75 10.00 5.00 0.40 9.75 10.00 4.87 5.00 0.23 0.65 0.85 0.42 0.01 0.20 REF 0.01 0.60 0.42 0.23 0.40 2.55 Agere Systems Microelectronics (Thai) Ltd. Document Control Center UNCONTROLLED COPY January 2, 2003 8.00 5.10 2.55 5.10 8.00 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Package Diagram, 84-Pin MLCC (Dimensions are in millimeters.) Note: Package outlines are unofficial and for reference only. LSI Corporation LSI Corporation 0.50 PIN #1 IDENTIFIER 4.87 9.75 10.00 5.00 0.50 9.75 10.00 4.87 5.00 0.23 0.65 0.80 0.42 0.01 0.20 REF 0.01 0.55 0.42 0.23 0.50 2.90 Agere Systems Microelectronics (Thai) Ltd. Document Control Center UNCONTROLLED COPY January 2, 2003 8.00 5.80 2.90 5.80 Data Sheet September 2007 TruePHY ET1011C Gigabit Ethernet Transceiver Package Diagram, 68-Pin MLCC (Dimensions are in millimeters.) Note: Package outlines are unofficial and for reference only. 83 TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Ordering Information Table 80. Ordering Information Device/Package ET1011C 84-pin MLCC ET1011C 68-pin MLCC ET1011C 128-pin TQFP2 Part Number1 Description Comcode Commercial GbE Transceiver, Lead-Free L-ET1011C2-C-D 711017464 Commercial GbE Transceiver, Lead-Free L-ET1011C2-C-DT 711017465 Industrial GbE Transceiver, Lead-Free L-ET1011C2-CI-D 711017462 Industrial GbE Transceiver, Lead-Free L-ET1011C2-CI-DT 711017463 Commercial GbE Transceiver, Lead-Free L-ET1011C2-M-D 711017468 Commercial GbE Transceiver, Lead-Free L-ET1011C2-M-DT 711017469 Industrial GbE Transceiver, Lead-Free L-ET1011C2-MI-D 711017466 Industrial GbE Transceiver, Lead-Free L-ET1011C2-MI-DT 711017467 Commercial GbE Transceiver, Lead-Free L-ET1011N1C-T-DB 711010940 1. L- = lead-free, -DT = Tape and Reel. 2. This is revision 3, "C" silicon (not revision 4, "C2" ) and is not recommended for new designs. 84 LSI Corporation TruePHY ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc. Magic Packet is a registered trademark of Advanced Micro Devices, Inc. For additional information, contact your LSI Account Manager or the following: INTERNET: Home: http://www.lsi.com E-MAIL: docmaster@agere.com N. AMERICA: LSI Corporation, Coporate Headquarters, 1621 Barber Lane, Mipitas, CA, 95035 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen), (86) 10-65391096 (Beijing) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 865 900 LSI Corporation reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. LSI and the LSI logo are trademarks of LSI Corporation. All other brand and product names may be trademarks of their respective companies. TruePHY is a trademark of Agere Systems Inc.. Copyright (c) 2007 LSI Corporation All Rights Reserved September 2007 DS06-161GPHY-4 (Replaces DS06-161PHY-3, DS06-161GPHY-2, DS06-161GPHY-1 and DS05058GPHY)