TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS * Input Voltage: Supports 2.5-V Rail and 3.3-V Rail * VLDOIN Voltage Range: 1.1 V to 3.5 V * Sink/Source Termination Regulator Includes Droop Compensation * Requires Minimum Output Capacitance of 20-F (typically 3 x 10-F MLCCs) for Memory Termination Applications (DDR) * PGOOD to Monitor Output Regulation * EN Input * REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider * Remote Sensing (VOSNS) * 10-mA Buffered Reference (REFOUT) * Built-in Soft Start, UVLO and OCL * Thermal Shutdown * Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications * SON-10 PowerPADTMPackage * 1 2 * * Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 Notebook/Desktop/Server Telecom/Datacom, GSM Base Station, LCD-TV/PDP-TV, Copier/Printer, Set-Top Box DESCRIPTION The TPS51200 is a sink/source Double Data Rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration. The TPS51200 maintains a fast transient response and only requires a minimum output capacitance of 20 F. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3/DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications. The TPS51200 is available in the thermally-efficient SON-10 PowerPAD package, and is rated both Green and Pb-free. It is specified from -40C to +85C. STANDARD DDR APPLICATION TPS51200 VIN 10 VDDQ 1 REFIN VLDOIN 2 VLDOIN PGOOD 9 VTT 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 3.3 VIN PGOOD SLP_S3 VTTREF 0.1 mF UDG-08025 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008, Texas Instruments Incorporated TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE DEVICE NUMBER -40C to 85C DRC Plastic Small Outline TPS51200DRCT TPS51200DRCR PINS MEDIUM MINIMUM QUANTITY 10 Tape and Reel 250 3000 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE Input voltage range (2) Output voltage range (2) Tstg (1) (2) VIN, VLDOIN, VOSNS, REFIN -0.3 to 3.6 EN -0.3 to 6.5 PGND to GND -0.3 to 0.3 VO, REFOUT -0.3 to 3.6 PGOOD -0.3 to 6.5 Storage temperature UNIT V V C -55 to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. DISSIPATION RATINGS TABLE (1) (1) PACKAGE TA = 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 85C POWER RATING 10-Pin SON 1.92 W 19 mW/C 0.79 W PowerPAD size: 3.0 x 1.9 mm, 4 standard thermal vias. Based on the above environment, junction to thermal pad resistance JP is 10.24C/W. Junction to ambient thermal resistance JA is 52.06C/W. RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltages VIN TYP MAX 2.375 3.500 -0.1 3.5 0.5 1.8 VO, PGOOD -0.1 3.5 REFOUT -0.1 1.8 PGND -0.1 0.1 -40 85 EN, VLDOIN, VOSNS REFIN Voltage range MIN Operating free-air temperature, TA 2 UNIT V C Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 x 10 F and circuit shown in Section 1. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IIN Supply current TA = 25 C, VEN = 3.3 V, No Load 0.7 1 TA = 25 C, VEN = 0 V, VREFIN = 0, No Load 65 80 200 400 1 50 A 0.1 50 A 1 A 15 mV 15 mV -15 15 mV -25 25 mV 3 4.5 A 3.5 5.5 A 18 25 IIN(SDN) Shutdown current ILDOIN Supply current ofVLDOIN TA = 25 C, VEN = 3.3 V, No Load ILDOIN(SDN) Shutdown current of VLDOIN TA = 25 C, VEN = 0 V, No Load Input current, REFIN VEN = 3.3 V TA = 25 C, VEN = 0 V, VREFIN > 0.4 V, No Load mA A INPUT CURRENT IREFIN VO OUTPUT VREFOUT = 1.25 V (DDR1), IO = 0 A VVOSNS Output DC voltage, VO VREFOUT = 0.9 V (DDR2), IO = 0 A VLDOIN = 1.5 V, VREFOUT = 0.75 V (DDR3), IO = 0 A VVOTOL Output voltage tolerance to REFOUT -2A < IVO < 2A IVOSRCL VO source vurrent Limit With reference to REFOUT, VOSNS = 90% x VREFOUT IVOSNCL VO sink current Limit With reference to REFOUT, VOSNS = 110% x VREFOUT IDSCHRG Discharge current, VO VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA = 25C 1.25 -15 V 0.9 -15 V 0.75 V POWERGOOD COMPARATOR VTH(PG) VO PGOOD threshold PGOOD window lower threshold with respect to REFOUT -23.5% -20% -17.5% PGOOD window upper threshold with respect to REFOUT 17.5% 20% 23.5% PGOOD hysteresis TPGSTUPDLY PGOOD startup delay Startup rising edge, VOSNS within 15% of REFOUT VPGOODLOW Output low voltage ISINK = 4 mA TPBADDLY PGOOD bad delay VOSNS is outside of the 20% PGOOD window IPGOODLK Leakage current (1) VOSNS = VREFIN (PGOOD high impedance), PGOOD = VIN + 0.2 V 5% 2 ms 0.4 V s 10 1 A REFIN AND REFOUT VREFIN REFIN voltage range VREFINUVLO REFIN undervoltage lockout VREFINUVHYS REFIN undervoltage lockout hysteresis VREFOUT REFOUT voltage 0.5 REFIN rising 360 390 1.8 V 420 mV 20 mV REFIN V -10 mA < IREFOUT < 10 mA, VREFIN = 1.25 V -15 15 -10 mA < IREFOUT < 10 mA, VVREFIN = 0.9 V -15 15 -10 mA < IREFOUT < 10 mA, VREFIN = 0.75V -15 15 -10 mA < IREFOUT < 10 mA, VREFIN = 0.6 V -15 mV VREFOUTTOL REFOUT voltage tolerance to VREFIN IREFOUTSRCL REFOUT source current limit VREFOUT = 0 V 10 40 mA IREFOUTSNCL REFOUT sink current limit VREFOUT = 0 V 10 40 mA (1) 15 Ensured by design. Not production tested. 3 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 x 10 F and circuit shown in Section 1. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.2 2.3 2.375 UNIT UVLO / EN LOGIC THRESHOLD Wake up, TA = 25C VVINUVVIN UVLO threshold VENIH High-level input voltage Enable VENIL Low-level input voltage Enable VENYST Hysteresis voltage Enable IENLEAK Logic input leakage current EN, TA = 25C Hysteresis 50 V mV 1.7 0.3 V 1 A 0.5 -1 THERMAL SHUTDOWN TSON (2) Thermal shutdown threshold (2) Shutdown temperature Hysteresis 150 25 C Ensured by design. Not production tested. 4 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 DEVICE INFORMATION DRC PACKAGE TPS51200 (Bottom View) VOSNS 5 PGND 4 VO 3 VLDOIN 2 REFIN 1 6 REFOUT 7 EN 8 GND 9 PGOOD 10 VIN TERMINAL FUNCTIONS TERMINAL NAME NO. I/O EN 7 I For DDR VTT application, connect EN to SLP_S3. For any other application(s), use EN as the ON/OFF function. DESCRIPTION GND 8 - Ground.Signal ground. Connect to negative terminal of the output capacitor. PGND 4 - Power ground output for the LDO PGOOD 9 O PGOOD output. Indicates regulation. REFIN 1 I Reference input REFOUT 6 O Reference output. Connect to GND through 0.1-F ceramic capacitor. VIN 10 I 2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-F and 4.7-F is required. VLDOIN 2 I Supply voltage for the LDO VO 3 O Power output for the LDO VOSNS 5 I Voltage sense output for the LDO. Connect to positive terminal of the output capacitor or the load. 5 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 FUNCTIONAL BLOCK DIAGRAM REFIN + 1 2.3 V VIN 10 VOSNS 2 VLDOIN 6 REFOUT 3 VO 4 PGND 9 PGOOD UVLO + Gm DchgREF 5 + 7 GND 8 ENVTT DchgVTT Gm REFINOK + + + EN Startup Delay + UDG-08019 6 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 DETAILED DESCRIPTION VO SINK/SOURCE REGULATOR The TPS51200 is a sink/source tracking termination regulator specifically designed for low input voltage, low-cost, and low external component count systems where space is a key application parameter. The TPS51200 integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, VOSNS, should be connected to the positive terminal of the output capacitor(s) as a separate trace from the high current path from VO. REFERENCE INPUT (REFIN) The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The TPS51200 supports REFIN voltage from 0.5 V to 1.8 V, making it versatile and ideal for many types of low-power LDO applications. REFERENCE OUTPUT (REFOUT) When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT becomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT is less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-k MOSFET. REFOUT is independent of the EN pin state. SOFT-START The soft-start function of the VO pin is achieved via a current clamp. The current clamp allows the output capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL) level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. The soft-start function is completely symmetrical; it works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage. EN CONTROL (EN) When EN is driven high, the TPS51200 VO regulator begins normal operation. When EN is driven low, VO is discharges to GND through an internal 18- MOSFET. REFOUT remains on when EN is driven low. POWERGOOD FUNCTION (PGOOD) The TPS51200 provides an open-drain PGOOD output that goes high when the VO output is within 20% of REFOUT. PGOOD de-asserts within 10 s after the output exceeds the size of the powergood window. During initial VO startup, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD is an open-drain output, a 100-k, pull-up resistor between PGOOD and a stable active supply voltage rail is required. VO CURRENT PROTECTION The LDO has a constant overcurrent limit (OCL). Note that the OCL level reduces by one-half when the output voltage is not within the powergood window. This reduction is a non-latch protection. VIN UVLO PROTECTION For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is a non-latch protection. 7 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 THERMAL SHUTDOWN The TPS51200 monitors the its junction temperature. If the device junction temperature exceeds its threshold value, (typically 150C), the VO and REFOUT regulators are both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection. 8 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 APPLICATION INFORMATION VIN CAPACITOR Add a ceramic capacitor, with a value between 1.0-F and 4.7-F, placed close to the VIN pin, to stabilize the bias supply (2.5- V rail or 3.3- V rail) from any parasitic impedance from the supply. VLDO INPUT CAPACITOR Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-F (or greater) ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at VO. In general, use one-half of the COUT value for input. OUTPUT CAPACITOR For stable operation, the total capacitance of the VO output terminal must be greater than 20 F. Attach three, 10-F ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). If the ESR is greater than 2 m, insert an R-C filter between the output and the VOSNS input to achieve loop stability. The R-C filter time constant should be almost the same as or slightly lower than the time constant of the output capacitor and its ESR. Low VIN Applications TPS51200 can be used in an application system where either a 2.5-V rail or a 3.3-V rail is available. If only a 5-V rail is available, TPS51100 can be used instead. The TPS51200 minimum input voltage requirement is 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between -5% and 5% accuracy, or better. S3 and Pseudo-S5 Support The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and the REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4/S5 state). Figure 1 shows a typical startup and shutdown timing diagram for an application that uses S3 and pseudo-S5 support. Tracking Startup and Shutdown The TPS51200 also supports tracking startup and shutdown when EN is tied directly to the system bus and not used to turn on or turn off the device. During tracking startup, VO follows REFOUT once REFIN voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail via a voltage divider. The typical soft-start time for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The SS time of the VO output no longer depends on the OCL setting, but it is a function of the SS time of the VDDQ rail. PGOOD is asserted 2 ms after VO is within 20% of REFOUT. During tracking shutdown, VO falls following REFOUT until REFOUT reaches 0.37 V. Once REFOUT falls below 0.37 V, the internal discharge MOSFETs are turned on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted once VO is beyond the 20% range of REFOUT. Figure 2 shows the typical timing diagram for an application that uses tracking startup and shutdown. 9 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 3.3VIN VVDDQ = 1.5 V 0.390 V 0.370 V VLDOIN REFIN REFOUT (VTTREF) EN (S3_SLP) VVO = 0.75 V Tss VO TSS = PGOOD CO x VO IOOCL 2 ms UDG-08021 Figure 1. Typical Timing Diagram for S3 and pseudo-S5 Support 3.3VIN EN VLDOIN REFIN REFOUT (VTTREF) VO tSS determined by the SS time of VLDOIN VVO = 0.75 V PGOOD UDG-08020 2ms Figure 2. Typical Timing Diagram of Tracking Startup and Shutdown 10 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Output Tolerance Consideration for VTT DIMM Applications The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 3). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 4 for typical characteristics for a single memory cell. Vtt SPD DQ CA Vdd Vtt Vdd CA Vdd DQ DDR3 240 Pin Socket VO 10 mF 10 mF TPS51200 10 mF UDG-08022 Figure 3. Typical Application Diagram for DDR3 VTT DIMM using TPS51200 VDDQ VTT Q1 25 W RS 20 W Ouput Buffer (Driver) Receiver Q2 VOUT VIN VSS UDG-08023 Figure 4. DDR Physical Signal System Bi-Directional SSTL Signaling In Figure 4, when Q1 is on and Q2 is off: * Current flows from VDDQ via the termination resistor to VTT * VTT sinks current In Figure 4, when Q2 is on and Q1 is off: * * Current flows from VTT via the termination resistor to GND VTT sources current 11 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003). VTTREF - 40 mV < VTT < VTTREF + 40 mV, for both dc and ac conditions The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning. The TPS51200 ensures the regulator output voltage to be: VTTREF -25 mV < VTT < VTTREF + 25mV, for both DC and AC conditions and -2 A < IVTT < 2 A The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to DDR, DDR2, DDR3 and Low Power DDR3/DDR4 applications (see Table 1 for detailed information). To meet the stability requirement, a minimum output capacitance of 20 F is needed. Considering the actual tolerance on the MLCC capacitors, three 10-F ceramic capacitors are sufficient to meet the above requirement. Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology and Their Differences DDR FSB Data Rates 200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz Motherboard termination to VTT for all signals Termination Termination Current Demand Max source/sink transient currents of up to 2.6A to 2.9A 2.5V Core and I/O 1.25V VTT Voltage Level DDR2 DR3 Low Power DDR3 800, 1066, 1330 and 1600 MHz Same as DDR3 On-die termination for data group. VTT termination for address, command and control signals On-die termination for data group. VTT termination for address, command and control signals Same as DDR3 Not as demanding Not as demanding Same as DDR3 Only 34 signals (address, * command, control) tied to VTT Only 34 signals (address, * command, control) tied to VTT * ODT handles data signals * ODT handles data signals Less than 1A of burst current Less than 1A of burst current 1.8V Core and I/O 0.9V VTT 1.5V Core and I/O 0.75V VTT 1.2V Core and I/O 0.6V VTT The TPS51200 is designed as a Gm driven LDO. The voltage droop between the reference input and the output regulator is determined by the transconductance and output current of the device. The typical Gm is 250 S at 2 A and changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see Equation 1) . FUGBW = Gm 2 p COUT (1) where * * * FUGBW is the unity gain bandwidth Gm is transconductance COUT is the output capacitance There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. In order to maintain stablility, the zero location contributed by the ESR of the output capacitors should be greater than the -3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to prevent the gain peaking effect around the Gm -3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO trace. 12 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Figure 5. Bode Plot for a Typical DDR3 Configuration Figure 5 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200, where: * * * * * * * VIN = 3.3 V VVLDOIN = 1.5 V VVO = 0.75 V IIO = 2 A 3 x 10-F capacitors included ESR = 2.5 m ESL = 800 pH The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52. The 0-dB level is crossed, the gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB. Figure 6 shows the load regulation and Figure 7 shows the transient response for a typical DDR3 configuration. When the regulator is subjected to 1.5-A load step and release, the output voltage measurement shows no difference between the dc and ac conditions. 13 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 OUTPUT VOLTAGE vs OUTPUT CURRENT 790 VOUT - Output Voltage - mV VIN = 3.3 V 0C 780 25C 770 760 -40C 750 740 730 720 710 700 -3 DDR3 -40C 0C 25C 85C -2 85C -1 0 1 IOUT - Output Current - A 2 3 Figure 6. DC Regulaltion Figure 7. Transient LDO Design Guidelines The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage Gm-driven to drive a certain load. For TPS51200, a minimum of 300 mV (VLDOINMIIN - VOMAX) is needed in order to support a Gm driven sourcing current of 2 A based on a design of VIN = 3.3 V and COUT = 3 x 10F. Because the TPS51200 is essentially a Gm driven LDO, its impedance characteristics are both a function of the 1/Gm and RDS(on) of the sourcing MOSFET (see Figure 8). The current inflection point of the design is between 2 A and 3 A. When ISRC is less than the inflection point, the LDO is considered to be operating in the Gm region; when ISRC is greater than the inflection point but less than the overcurrent limit point, the LDO is operating in the RDS(on) region. The maximum sourcing RDS(on) is 0.144 with VIN = 3.0 V and TJ = 125C. 14 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com VVO - Output Voltage - V SLUS812 - FEBRUARY 2008 1/Gm Inflection Point (between 2 A and 3 A) 1/RDS(on) Overcurrent Limit ISRC - Source Current - A UDG-08026 Figure 8. TPS51200 Impedance Characteristics 15 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 THERMAL DESIGN Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2. PDISS _ SRC = (VVLDOIN - VVO ) x IO _ SRC (2) In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power dissipation, PDISS_SNK can be calculated by Equation 3. PDISS _ SNK = VVO IO _ SNK (3) Because the device does not sink and source current at the same time and the IO current may vary rapidly with time, the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system. Another source of power consumption is the current used for the internal current control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less during normal operatiing conditions. This power must be effectively dissipated from the package. Maximum power dissipation allowed by the package is calculated by Equation 4. PPKG = [TJ(MAX) - TA(MAX)]/ JA PPKG = (TJ(max) TA(max) ) qJA (4) where * * * TJ(MAX) is +125C TA(MAX) is the maximum ambient temperature in the system JA is the thermal resistance from junction to ambient The thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200 is housed in a thermally-enhanced PowerPADTM package that has an exposed die pad underneath the body. For improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, JA, 52.06C/W, is achieved based on a land pattern of 3 mm x 1.9 mm with four vias (0.33-mm via diameter, the standard thermal via size) without air flow (see Figure 9). Land Pad 3 mm x 1.9 mm Exposed Thermal Die Pad, 2.48 mm x 1.74 mm UDG-08018 Figure 9. Recommend Land Pad Pattern for TPS51200 To further improve the thermal performance of this device, using a larger than recommended thermal land as well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical thermal resistance from junction to thermal pad, JP, is 10.24C/W (based on the recommend land pad and four standard thermal vias). 16 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 For further information regarding the PowerPADTM package and the recommended board layout, refer to the PowerPADTM package application note (SLMA002). This document is available at www.ti.com. LAYOUT CONSIDERATIONS Consider the following points before starting the TPS51200 layout design. * The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide connections. * The output capacitor for VO should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL trace inductance. * VOSNS should be connected to the positive node of VO output capacitor(s) as a separate trace from the high current power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If sensing the voltage at the point of the load is required, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between the GND pin and the output capacitor(s). * Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitor(s) is larger than 2 m. * REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of REFOUT. Avoid any noise-generating lines. * The negative node of the VO output capacitor(s) and the REFOUT capacitor should be tied together by avoiding common impedance to the high current path of the VO source/sink current. * The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias connecting to the internal system ground planes (for better result, use at least two internal ground planes). Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane. Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point. * In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the package's thermal pad. The wide traces of the component and the side copper connected to the thermal land pad help to dissipate heat. Numerous vias 0,33 mm in diameter connected from the thermal land to the internal/solder side ground plane(s) should also be used to help dissipation. * Please consult the TPS51200-EVM User's Guide (SLUUxxx) for detailed layout recommendations. 17 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 TYPICAL CHARACTERISTICS For Figure 10 through Figure 24, 3 x 10-F MLCCs (0805) are used on the output. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 940 1.30 VIN = 3.3 V 930 VOUT - Output Voltage - mV VOUT- Output Voltage - V 1.28 1.26 -40C 0C 1.24 1.22 DDR -40C 0C 25C 85C 1.20 920 910 -40C 0C 900 890 DDR2 -40C 0C 25C 85C 880 85C 1.18 85C 870 -3 -2 -1 0 1 IOUT - Output Current - A 2 -3 3 Figure 11. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 85C VIN = 3.3 V 0C VOUT - Output Voltage - mV 760 -40C 750 740 730 700 -3 2 3 DDR3 -40C 0C 25C 85C VIN = 3.3 V 650 25C 770 710 -1 0 1 IOUT - Output Current - A 670 780 720 -2 Figure 10. 790 VOUT - Output Voltage - mV VIN = 3.3 V 25C 25C 85C 25C 630 610 0C -40C 590 DDR3 -40C 0C 25C 85C 570 550 -2 -1 0 1 IOUT - Output Current - A 2 3 -3 Figure 12. -2 -1 0 1 IOUT - Output Current - A 2 3 Figure 13. 18 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 x 10-F MLCCs (0805) are used on the output. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT CURRENT vs OUTPUT VOLTAGE 1.30 1.00 VIN = 2.5 V VIN = 2.5 V 1.25 1.20 VOUT - Output Voltage - V VOUT- Output Voltage - V 0.95 1.15 25C 1.10 1.05 1.00 DDR 85C -40C 0C 25C 85C 0.95 -40C -40C 0.90 0.85 0.80 85C DDR2 0.75 0C 0.90 25C & 0C -40C 0C 25C 85C 0.70 -3 -2 -1 0 1 IOUT - Output Current - A 2 3 -3 -2 -1 0 1 IOUT - Output Current - A Figure 14. Figure 15. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 2 3 750 800 VIN = 2.5 V VIN = 2.5 V 85C 85C VOUT - Output Voltage - mV VOUT- Output Voltage - V 700 750 -40C 0C 25C 700 DDR3 -40C 0C 25C 85C -2 25C 600 -40C LP DDR3 550 -40C 0C 25C 85C 0C 500 650 -3 650 -1 0 1 IOUT - Output Current - A 2 3 -3 Figure 16. -2 -1 0 1 IOUT - Output Current - A 2 3 Figure 17. 19 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 x 10-F MLCCs (0805) are used on the output. REFOUT VOLTAGE vs REFOUT CURRENT REFOUT VOLTAGE vs REFOUT CURRENT 1.255 905 1.254 25C 904 VREFOUT - Output Voltage - mV VREFOUT - Output Voltage - V 25C 1.253 1.252 1.251 1.250 -40C 1.249 DDR 1.248 1.247 -15 -40C 25C 85C -5 0 5 10 IREFOUT - Output Current - mA 15 899 LP DDR3 -40C 25C 85C -10 85C -5 0 5 10 IREFOUT - Output Current - mA REFOUT VOLTAGE vs REFOUT CURRENT REFOUT VOLTAGE vs REFOUT CURRENT 15 605 25C 752 -40C 750 749 DDR3 -10 603 602 601 -40C 600 599 LP DDR3 598 -40C 25C 85C 85C -5 25C 604 VREFOUT - Output Voltage - mV VREFOUT - Output Voltage - mV 900 Figure 19. 753 747 -15 -40C Figure 18. 754 748 901 897 -15 755 751 902 898 85C -10 903 0 5 IREFOUT - Output Current - mA 598 -15 Figure 20. -40C 25C 85C -10 85C -5 0 5 10 IREFOUT - Output Current - mA 15 Figure 21. 20 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 x 10-F MLCCs (0805) are used on the output. DROPOUT VOLTAGE vs OUTPUT CURRENT GAIN AND PHASE vs FREQUENCY 1.25 V 1.6 60 Phase 150 50 1.4 100 0.90 V 1.2 0.6 V 1.0 0.8 0.75 V 30 50 20 0 10 Gain -50 Phase - Degrees 40 Gain - dB VDRPOUT - Output Voltage - V 200 70 1.8 0 0.6 -100 -10 VOUT(V) 0.60 0.75 0.90 1.25 0.4 0.2 -20 -30 1k 0 0 0.5 1.0 1.5 2.0 2.5 IOUT - Output Current - A 3.0 DDR2 Gain Phase 10 k 3.5 -150 100 k f - Frequency - Hz Figure 22. 1M -200 10 M Figure 23. GAIN AND PHASE vs FREQUENCY 200 60 50 Phase 40 150 100 30 Gain - dB 50 20 0 10 Gain -50 0 -100 -10 -20 -30 1k DDR3 Gain Phase 10 k -150 100 k f - Frequency - Hz 1M -200 10 M Figure 24. 21 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 DESIGN EXAMPLES Design Example 1 This design example describes a 3.3-VIN, DDR2 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.8 V R2 10 kW VVLDOIN = VVDDQ = 1.8 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.9 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08028 Figure 25. 3.3-VIN, DDR2 Configuration Design Example 1 List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor SPECIFICATION GRM21BR70J106KE76L Murata 100 k 10 F, 6.3 V C4 1000 pF Capacitor MANUFACTURER 10 k C1, C2, C3 C5 PART NUMBER 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 22 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Design Example 2 This design example describes a 3.3-VIN, DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08029 Figure 26. 3.3-VIN, DDR3 Configuration Design Example 2 List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor SPECIFICATION GRM21BR70J106KE76L Murata 100 k 10 F, 6.3 V C4 1000 pF Capacitor MANUFACTURER 10 k C1, C2, C3 C5 PART NUMBER 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 23 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Design Example 3 This design example describes a 2.5-VIN, DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 2.5 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08030 Figure 27. 2.5-VIN, DDR3 Configuration Design Example 3 List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor SPECIFICATION GRM21BR70J106KE76L Murata 100 k 10 F, 6.3 V C4 1000 pF Capacitor MANUFACTURER 10 k C1, C2, C3 C5 PART NUMBER 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 24 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Design Example 4 This design example describes a 3.3-VIN, LP DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.2 V R2 10 kW VVLDOIN = VVDDQ = 1.2 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.6 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08031 Figure 28. 3.3-VIN, LP DDR3 Configuration Design Example 4 List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor SPECIFICATION GRM21BR70J106KE76L Murata 100 k 10 F, 6.3 V C4 1000 pF Capacitor MANUFACTURER 10 k C1, C2, C3 C5 PART NUMBER 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 25 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Design Example 5 This design example describes a 3.3-VIN, DDR3 Tracking Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF VTTREF C5 0.1 mF UDG-08032 Figure 29. 3.3-VIN, DDR3 Tracking Configuration Design Example 5 List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor SPECIFICATION GRM21BR70J106KE76L Murata 100 k 10 F, 6.3 V C4 1000 pF Capacitor MANUFACTURER 10 k C1, C2, C3 C5 PART NUMBER 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 26 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Design Example 6 This design example describes a 3.3-VIN, LDO Configuration. R1 10 kW TPS51200 2.5 V 1 R2 3.86 kW VVLDOIN = VVLDOREF = 2.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVLDO = 1.8 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF ENABLE REFOUT C5 0.1 mF UDG-08033 Figure 30. 3.3-VIN, LDO Configuration Design Example 6 List of Materials REFERENCE DESIGNATOR DESCRIPTION R1 R2 SPECIFICATION MANUFACTURER GRM21BR70J106KE76L Murata 10 k Resistor 3.86 k R3 100 k C1, C2, C3 10 F, 6.3 V C4 C5 PART NUMBER 1000 pF Capacitor 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 27 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 TPS51200 www.ti.com SLUS812 - FEBRUARY 2008 Design Example 7 This design example describes a 3.3-VIN, DDR3 Configuration with LFP. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VIN 10 REFIN C4 1000 pF R3 100 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF 3.3 VIN 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V R4(1) C1 10 mF C2 10 mF C3 10 mF SLP_S3 VTTREF C5 0.1 mF C9(1) UDG-08034 Figure 31. 3.3-VIN, DDR3 Configuration with LFP Design Example 7 List of Materials REFERENCE DESIGNATOR DESCRIPTION R1, R2 R3 R4 SPECIFICATION PART NUMBER MANUFACTURER GRM21BR70J106KE76L Murata 4.7 F, 6.3 V GRM21BR60J475KA11L Murata 10 F, 6.3 V GRM21BR70J106KE76L Murata 10 k Resistor 100 k (1) C1, C2, C3 10 F, 6.3 V C4 1000 pF C5 Capacitor C6 C7, C8 C9 (1) 0.1 F (1) The values of R4 and C9 should be chosen to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output capacitors (ESR and ESL). 28 Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51200 PACKAGE OPTION ADDENDUM www.ti.com 24-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS51200DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51200DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51200DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51200DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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